Heated Phase Change Memory Cell

Abstract

In an embodiment of the present invention, a method for forming a phase-change memory device is provided. The method includes forming a bottom electrode on a support structure; sequentially forming a first blanket dielectric layer, a phase-change material layer, a second blanket dielectric layer, and a hard mask on the bottom electrode; forming an internal spacer in the opening in the hard mask to modify the opening; extending the opening into the second blanket dielectric layer to provide an extended opening; filling the extended opening with a heating element; etching the second blanket dielectric layer, the phase-change material layer, and the first blanket dielectric layer to provide a second dielectric layer, a phase-change element, and a first dielectric layer, respectively; forming a conductive liner surrounding the phase-change element; and forming a top electrode on the heating element. A structure formed thereby is also provided.

Description

[Background technology]

[0001] This application relates to semiconductor integrated circuit manufacturing, and more particularly to a phase change memory device with a heating element and a method for manufacturing the same.

[0002] Phase change memory has recently emerged as a viable technology for memory applications and analog computing. In a typical phase change memory (PCM) device, such as a cross-point PCM device, each memory cell includes a storage element and a selector. The storage element is a PCM cell, which can be written by melting, quenching, and / or recrystallization. A heater or heating element is typically used during the PCM cell writing process.

[0003] In currently existing technology, the PCM cell is typically located above a lower heater or heating element. In conventional lateral PCM cell integration processes, the upper PCM cell and the lower heater or heating element are typically patterned at different times. Due to unavoidable overlay errors or misalignment between the lower heater patterning process and the upper PCM cell (especially the phase-change element layer), and when the PCM cell is circular, the heater is not necessarily located at the center of the PCM cell. In other words, the heater and PCM cell may not be formed concentrically. Non-concentric placement of the heating element and PCM cell can result in, among other defects, non-uniform distribution of the write current, which can result in degradation and potentially unpredictable behavior of the PCM device. Furthermore, this conventional integration process introduces cell-to-cell variability in the PCM device. U.S. Patent No. 7,463,512 by Lung provides several perspectives on PCM cells based on a conventional lateral PCM cell integration process. Summary of the Invention

[0004] In an embodiment of the present invention, a phase-change memory (PCM) device is provided. The PCM device includes a bottom electrode; a first dielectric layer overlying the bottom electrode; a phase-change element overlying the first dielectric layer; a heating element overlying the phase-change element; an top electrode overlying the heating element; and a conductive liner surrounding at least the phase-change element. Here, the heating element is approximately at the center of the phase-change element and has a uniform horizontal distance to the conductive liner surrounding the phase-change element. The uniform horizontal distance from the heating element to the edge of the phase-change element provides approximately uniform conductivity, and therefore a uniform distribution of write current, during operation of the PCM device.

[0005] In one embodiment, the heating element is surrounded by a second dielectric layer and a third dielectric layer, the third dielectric layer being above the second dielectric layer and being materially different from the second dielectric layer.

[0006] In another embodiment, the second and third dielectric layers have respective exterior sidewalls that are aligned with each other and generally aligned with the phase change element.

[0007] In yet another embodiment, the conductive liner covers at least a lower portion of the outer sidewall of the second dielectric layer.

[0008] In one embodiment, the PCM device further includes a resistive liner overlying the phase change element, the resistive liner underlying the heating element and the second dielectric layer and surrounded by the conductive liner. During the "reset" state, the resistive liner provides a low resistance path for a read current when at least a portion of the phase change element is in a high resistance state due to its amorphous form, or may be experiencing resistance drift.

[0009] In another embodiment, the bottom electrode is part of metal layer M and the top electrode is part of metal layer M+1 in a back-end-of-line (BEOL) structure, where metal layer M and metal layer M+1 are two adjacent metal layers.

[0010]

[0009] The present invention also provides a method for forming a phase-change memory device, comprising the steps of: forming a bottom electrode on a support structure; sequentially forming a first blanket dielectric layer, a phase-change material layer, a second blanket dielectric layer, and a hard mask on the bottom electrode, the hard mask having an opening exposing a portion of the second blanket dielectric layer; forming an internal spacer in the opening to form a modified opening; extending the modified opening into the second blanket dielectric layer to form an extended opening; filling the extended opening with a heating element; etching the second blanket dielectric layer, the phase-change material layer, and the first blanket dielectric layer to form a second dielectric layer, a phase-change element, and a first dielectric layer, respectively; forming a conductive liner surrounding at least the phase-change element; and forming a top electrode on the heating element. By forming the heating element in the extended opening created by or arising from the internal spacer, the heating element has approximately the same distance to an outer edge or sidewall of the internal spacer.

[0011] In one embodiment, etching the second blanket dielectric layer, the phase change material layer, and the first blanket dielectric layer includes removing a hard mask surrounding the internal spacer; and etching the second blanket dielectric layer, the phase change material layer, and the first blanket dielectric layer in an anisotropic etching process using the internal spacer and the heating element as an etch mask to expose the bottom electrode. Using the internal spacer as an etch mask ensures that the heating element has approximately the same distance to the outer edge or sidewall of the phase change element and to the conductive liner surrounding the phase change element.

[0012] In another embodiment, extending the modified opening into the second blanket dielectric layer includes etching the second blanket dielectric layer with an anisotropic etching process using the interior spacer as an etch mask.

[0013] In one embodiment, the method further includes forming a resistive liner layer over the phase change material layer before forming the second blanket dielectric layer, such that the resistive liner layer is between the phase change material layer and the second blanket dielectric layer.

[0014] In another embodiment, forming the interior spacers includes depositing a conformal spacer layer covering the top surface of the hard mask and the sidewalls of the opening in the hard mask; and subsequently removing horizontal portions of the conformal spacer layer with an anisotropic etching process.

[0015] In yet another embodiment, forming the conductive liner includes forming a conductive liner layer covering the top surface of the heating element, the top surface of the internal spacer, the sidewalls of the internal spacer, the sidewalls of the second dielectric layer, the sidewalls of the phase change element, the sidewalls of the first dielectric layer, and the top surface of the lower electrode; removing horizontal portions of the conductive liner layer by an anisotropic etching process; and removing at least a portion of the conductive liner layer covering the sidewalls of the internal spacer. [Brief explanation of the drawings]

[0016] The present invention will be more fully understood and appreciated from the following detailed description of the embodiments thereof when taken in conjunction with the accompanying drawings, in which:

[0017] [Figure 1] 1A-1C are cross-sectional illustrations of a PCM device at different stages in its manufacture according to one embodiment of the present invention.

[0018] [Figure 2] 2A-2C are cross-sectional illustrations of a PCM device at a stage of fabricating the device following the process illustrated in FIG. 1, according to one embodiment of the present invention.

[0019] [Figure 3]3A-3C are cross-sectional illustrations of a PCM device at a stage of fabricating the device following the process illustrated in FIG. 2, according to one embodiment of the present invention.

[0020] [Figure 4] 4A-4C are cross-sectional illustrations of a PCM device at a stage of fabricating the device following the process illustrated in FIG. 3, according to one embodiment of the present invention.

[0021] [Figure 5] 5A-5C are cross-sectional illustrations of a PCM device at a stage of fabricating the device following the process illustrated in FIG. 4, according to one embodiment of the present invention.

[0022] [Figure 6] 6A-6C are cross-sectional illustrations of a PCM device at a stage of fabricating the device following the process illustrated in FIG. 5, according to one embodiment of the present invention.

[0023] [Figure 7] 7A-7C are cross-sectional illustrations of a PCM device at a stage of fabricating the device following the process illustrated in FIG. 6, according to one embodiment of the present invention.

[0024] [Figure 8] 8A-8C are cross-sectional illustrations of a PCM device at a stage of fabricating the device following the process illustrated in FIG. 7, according to one embodiment of the present invention.

[0025] [Figure 9] 9A-9C are cross-sectional illustrations of a PCM device at a stage of fabricating the device following the process illustrated in FIG. 8, according to one embodiment of the present invention.

[0026] [Figure 10] 10A-10C are cross-sectional illustrations of a PCM device at a stage of fabricating the device following the process illustrated in FIG. 9, according to one embodiment of the present invention.

[0027] [Figure 11] 11A-11C are cross-sectional illustrations of a PCM device at a stage of fabricating the device following the process illustrated in FIG. 10, according to one embodiment of the present invention.

[0028] [Figure 12] 12A-12C are cross-sectional illustrations of a PCM device at a stage of fabricating the device following the process illustrated in FIG. 11, according to one embodiment of the present invention.

[0029] [Figure 13] 13A-13C are cross-sectional illustrations of a PCM device at a stage of fabrication following the process illustrated in FIG. 12, according to one embodiment of the present invention.

[0030] [Figure 14A] 1 is a cross-sectional view of an exemplary PCM device in a "set" state according to one embodiment of the present invention; [Figure 14B] 1 is a cross-sectional view of an exemplary PCM device in a "reset" state according to one embodiment of the present invention;

[0031] [Figure 15] 1 is an exemplary diagram illustrating a flowchart of a method for manufacturing a PCM device according to an embodiment of the present invention.

[0032] It will be understood that for simplicity and clarity, elements shown in the figures have not necessarily been drawn to scale. Further, where applicable, in the various functional block diagrams, two connected devices and / or elements may not necessarily be illustrated as connected. In some other instances, certain elements in the functional block diagrams may be grouped together for illustrative purposes only, but this may not necessarily imply that these elements belong to or are embodied in a single physical entity. DETAILED DESCRIPTION OF THE INVENTION

[0033] In the following detailed description and the accompanying drawings, it should be understood that the various layers, structures, and regions illustrated in the drawings are intended to be both illustrative and schematic, and are not drawn to scale. Furthermore, for ease of explanation, one or more layers, structures, and regions of a type commonly used in forming semiconductor devices or structures may not be explicitly shown in a particular description or drawing. This is not to suggest that any of the layers, structures, and regions not explicitly shown are omitted from an actual semiconductor structure. Furthermore, it should be understood that the embodiments discussed herein are not limited to the specific materials, features, and processing steps shown and described herein. In particular, with respect to semiconductor processing steps, it should be emphasized that the descriptions provided herein are not intended to be exhaustive of all processing steps that may be required to form a functional semiconductor integrated circuit device. Rather, certain processing steps commonly used in forming semiconductor devices, such as wet cleaning and annealing steps, have been intentionally not described herein for the sake of simplicity.

[0034] The terms "about" or "substantially" used herein in connection with thickness, width, ratio, range, etc., are intended to indicate close or approximately so, but should be understood to not be exact. For example, the terms "about" or "substantially" used herein mean that a small range of error may exist, such as 1% or less of the stated quantity. Similarly, the terms "on," "over," or "on top of," used herein to describe the positional relationship between two layers or structures, are intended to be interpreted broadly and should not be construed to exclude the presence of one or more intervening layers or structures.

[0035] An XYZ Cartesian coordinate system may be provided in some of the figures to provide spatial context for various structural orientations of semiconductor structures shown in the figures. As used herein, the terms "vertical" or "vertical direction" or "vertical height" refer to the Z direction of the Cartesian coordinate system shown in the figures, and the terms "horizontal" or "horizontal direction" or "lateral direction" as used herein refer to the X and / or Y directions of the Cartesian coordinate system shown in the figures.

[0036] Furthermore, although different reference numbers may be used throughout different drawings, the same or similar reference numbers are used throughout the drawings to indicate the same or similar features, elements, or structures. Therefore, to simplify the description, detailed descriptions of the same or similar features, elements, or structures may not be repeated in each drawing. In some drawings, labels for the same or similar elements may be omitted to avoid cluttering the drawings.

[0037] 1 is an illustrative cross-sectional view of a PCM device at one stage in the fabrication of the device according to one embodiment of the present invention. More particularly, in fabricating a PCM device 10 (see FIG. 13 for more detail), an embodiment of the present invention provides for receiving a support structure 101, e.g., a semiconductor substrate or back-end interconnect (BEOL) structures on a semiconductor substrate. Other active and / or passive semiconductor devices, such as, e.g., transistors, isolation structures, and / or contacts, may be formed on or within the support structure (not shown for simplicity).

[0038] Embodiments of the present invention further provide for forming a bottom electrode layer 201 on the support structure 101, for example, by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process. The bottom electrode layer 201 may be, for example, a layer of titanium nitride and may be formed to have a thickness ranging from about 50 nm to about 100 nm, although the bottom electrode layer 201 may be made of other suitable materials and / or thicknesses depending on the particular application of the PCM device 10. For example, the bottom electrode layer 201 may be formed of one or more layers of materials such as tungsten (W), aluminum (Al), copper (Cu), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), doped polysilicon, cobalt silicide (CoSi), tungsten silicide (WSi), and other materials.

[0039] FIG. 2 is an exemplary cross-sectional view of a PCM device at a stage of fabricating the device following the process illustrated in FIG. 1 , according to one embodiment of the present invention. More specifically, the present invention provides a step of patterning a bottom electrode layer 201 into a bottom electrode 202. The bottom electrode 202 may be surrounded by or embedded in a dielectric material layer. In one embodiment, the bottom electrode 202 may be formed on a metal layer (e.g., an M2 or M3 layer), or the bottom electrode itself may be part of a metal layer (e.g., an M2 or M3 layer) of a BEOL structure. When the metal layer itself is part of a metal layer, such as an M2 or M3 layer, it may hereinafter be referred to as part of the PCM device 10 for ease of reference only. As exemplarily shown in FIG. 2 , the bottom electrode 202 may extend, for example, from left to right, and a dielectric material layer surrounding the bottom electrode 202 is not shown in FIG. 2 because it may be present behind and in front of the bottom electrode 202.

[0040] Embodiments of the present invention further provide forming a first blanket dielectric layer 301 on bottom electrode 202 (and the dielectric material layer surrounding it), a phase change material layer 401 on first blanket dielectric layer 301, a resistive liner layer 501 on phase change material layer 401, and a second blanket dielectric layer 601 on resistive liner layer 501. Resistive liner layer 501 may be optional, and if not used, second blanket dielectric layer 601 may be formed directly on phase change material layer 401. Formation of first blanket dielectric layer 301, phase change material layer 401, resistive liner layer 501, and second blanket dielectric layer 601 may be performed by, for example, CVD, PVD, or ALD processes.

[0041] In one embodiment, the first blanket dielectric layer 301 and the second blanket dielectric layer 601 may be any suitable dielectric material, such as, for example, silicon nitride (SiN), boron nitride (SiB), silicon oxynitride (SiON), silicon boron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN), silicon oxycarbide (SiCO), or combinations thereof. The first blanket dielectric layer 301 and the second blanket dielectric layer 601 may be individually formed to have individual thicknesses ranging from about 10 nm to about 30 nm, without limitation.

[0042] In another embodiment, the phase change material layer 401 may be a layer of material such as germanium-antimony-tellurium (GST), gallium-antimony-tellurium (GaST), or silver-indium-antimony-tellurium (AIST), although other suitable materials may also be used. Examples of other suitable phase change materials include, but are not limited to, germanium-tellurium compound materials (GeTe), silicon-antimony-tellurium (Si—Sb—Te) alloys, gallium-antimony-tellurium (Ga—Sb—Te) alloys, germanium-bismuth-tellurium (Ge—Bi—Te) alloys, indium-tellurium (In—Se) alloys, arsenic-antimony-tellurium (As—Sb—Te) alloys, silver-indium-antimony-tellurium (Ag—In—Sb—Te) alloys, Ge—In—Sb—Te alloys, Ge—Sb alloys, Sb—Te alloys, Si—Sb alloys, Ge—Te alloys, and combinations thereof. Phase change material layer 401 can be undoped or doped with, for example, one or more elements, such as, for example, oxygen (O), nitrogen (N), silicon (Si), titanium (Ti), etc.

[0043] Embodiments of the present invention provide for forming a thin layer of conformally deposited phase change material. For example, the phase change material layer 401 may be formed to have a thickness in the range of about 5 nm to about 30 nm, thinner than that of conventional PCM devices, although other thicknesses may be possible. Using a thin layer of phase change material reduces the volume of phase change material that needs to be heated by a heating element (later formed thereon), thereby reducing the time and / or energy required to transition the phase change material from a high-resistivity amorphous phase or amorphous atomic structure to a low-resistivity crystalline phase or crystalline atomic structure during operation of the PCM device. In other words, a smaller volume of phase change material results in faster phase transitions because less heating and / or cooling is required to change the phase or state of the phase change material (e.g., from amorphous to crystalline phase, or vice versa). By using a heating element in conjunction with a thinner layer of phase change material, embodiments of the present invention provide PCM devices with semiconductor structures that enable faster phase change material transitions, improving functionality.

[0044] Resistive liner layer 501 can be a thin layer of resistive material, and its resistivity may be higher than that of phase change material layer 401. Suitable materials for resistive liner layer 501 may include, for example, tantalum nitride (TaN), aluminum nitride (AlN), boron nitride (BN), aluminum oxide (AlO), tungsten nitride (WN), cobalt tungsten (CoW), nickel tungsten (NiW), yttrium oxide (YO), or alloys of these materials. The electrical resistance of resistive liner layer 501 can be significantly greater (e.g., 10 to 30 times or more) than the resistance of phase change material layer 401 when the latter is in a low-resistance or crystalline state, and conversely, can be significantly lower (e.g., 5 to 20 times lower) than the resistance of phase change material layer 401 when the latter is in a high-resistance or amorphous state.

[0045] 3 is an illustrative cross-sectional view of a PCM device at a stage of fabricating the device following the process illustrated in FIG. 2 , according to one embodiment of the present invention. More specifically, the present invention provides a step of forming a hard mask 701, for example, by a lithographic patterning process. The hard mask 701 may be formed to a thickness ranging from about 30 nm to about 100 nm and patterned to have an opening 711 that exposes the top surface of the second blanket dielectric layer 601. In one embodiment, the opening 711 may have a circular shape when viewed from above. The hard mask 701 may be made of a dielectric material that may be the same as or different from the second blanket dielectric layer 601.

[0046] FIG. 4 is a cross-sectional view illustrating a PCM device at a manufacturing step following the step illustrated in FIG. 3 , according to one embodiment of the present invention. More specifically, the present invention provides a step of forming internal spacers 702 on the sidewalls of openings 711 in hard mask 701. For example, internal spacers 702 may be formed by first depositing a conformal spacer layer. The conformal spacer layer may be made of a material such as SiN, SiB, SiON, SiBCN, SiOCN, SiCN, SiCO, or other suitable material, and covers the top surface of hard mask 701 and the sidewalls of openings 711. Subsequently, horizontal portions of the conformal spacer layer may be removed by an anisotropic and directional etching process, such as a reactive-ion-etching (RIE) process, thereby forming internal spacers 702. In one embodiment, internal spacers 702 may have a donut or ring shape when viewed from above. The formation of internal spacers 702 modifies openings 711 to form modified openings 712. The horizontal thickness of the inner spacer 702 is approximately the same along the sidewalls of the opening 711 in the hard mask 701 .

[0047] 5 is an illustrative cross-sectional view of a PCM device at a stage of fabricating the device following the process illustrated in FIG. 4 according to one embodiment of the present invention. More specifically, the present invention provides a step of extending modified opening 712 into blanket second dielectric layer 601 to provide extended opening 713. Extending modified opening 712 into blanket second dielectric layer 601 may be performed, for example, by an anisotropic etching process using inner spacer 702 as an etch mask. Extended opening 713 may expose the top surface of resistive liner layer 501, or may directly expose the top surface of phase change material layer 401 if resistive layer 501 is not used.

[0048] 6 is an illustrative cross-sectional view of a PCM device at a stage of fabrication following the process illustrated in FIG. 5 , according to one embodiment of the present invention. More specifically, an embodiment of the present invention provides a step of filling the elongated opening 713 with a heating material to form a heating element 703. The heating element 703 may be formed by a conformal deposition process and may include one material, such as TiN, or multiple materials, such as TaN / TiN / TaN. The heating element 703 is in direct contact with the underlying resistive liner layer 501 and / or the phase change material layer 401.

[0049] 7 is an illustrative cross-sectional view of a PCM device at a stage of fabricating the device following the process illustrated in FIG. 6 according to one embodiment of the present invention. More specifically, the present invention provides removing hard mask 701 surrounding interior spacers 702 to expose blanket second dielectric layer 601 underneath. The present invention may further include etching blanket second dielectric layer 601 to second dielectric layer 602, resistive liner layer 501 underneath to resistive liner 502, phase change material layer 401 underneath to phase change element 402, and blanket first dielectric layer 301 underneath to first dielectric layer 302, thereby forming PCM stack 410. The etching uses interior spacers 702 and heating element 703 as an etch mask. PCM stack 410 includes the outer sidewalls of internal spacer 702 and second dielectric layer 602, as well as the outer sidewalls of resistive liner 502, phase change element 402, and first dielectric layer 302, which are substantially aligned with each other and with the outer sidewalls of internal spacer 702 and second dielectric layer 602. Using the uniformly thick internal spacer 702 and heating element 703 as an etch mask ensures that the outer and inner sidewalls of second dielectric layer 602 are concentric. Therefore, heating element 703 can have a substantially uniform horizontal distance to the outer sidewall of second dielectric layer 602 and the sidewall of phase change element 402. In other words, heating element 703 can be approximately centered on phase change element 402 and formed to have a uniform horizontal distance to later-formed conductive liner 803. Surrounding phase change element 402 is a conductive liner, which is described in more detail below with reference to FIG.

[0050] FIG. 8 is an illustrative cross-sectional view of a PCM device at a stage of fabrication following the process illustrated in FIG. 7 , according to one embodiment of the present invention. More specifically, embodiments of the present invention provide a step of forming a conformal liner layer 801 overlying PCM stack 410. For example, conformal liner layer 801 covers heating element 703, inner spacer 702, second dielectric layer 602, resistive liner 502, phase change element 402, first dielectric layer 302, and bottom electrode 202. Conformal liner layer 801 may be a conductive liner layer, such as a metallic liner layer of TiN or other suitable conductive material. Conformal liner layer 801 may be formed to a thickness ranging from about 5 nm to about 20 nm, but is not limited to these thicknesses.

[0051] 9 is an illustrative cross-sectional view of a PCM device at a stage of fabrication following the process illustrated in FIG. 8 , according to one embodiment of the present invention. More specifically, the present invention provides for removing horizontal portions of the conformal liner layer 801 by an anisotropic etching process, such as a reactive ion etching (RIE) process. The anisotropic etching process is a directional etching process that removes portions of the conformal liner layer that cover the top surface of the PCM stack 410 (including the top surface of the heating element 703 and the top surface of the inner spacer 702) and that cover the top surface of the bottom electrode 202. The anisotropic etching process leaves vertical portions 802 of the conformal liner layer 801 on the sidewalls of the PCM stack 410, including the sidewalls of the inner spacer 702, the second dielectric layer 602, the resistive liner 502, the phase change element 402, and the first dielectric layer 302. In one embodiment, the anisotropic etching process etches into the bottom electrode 202 and may also remove the top portion of the bottom electrode 202 .

[0052] 10 is an illustrative cross-sectional view of a PCM device at a stage of fabricating the device following the process illustrated in FIG. 9 , according to one embodiment of the present invention. More specifically, an embodiment of the present invention provides a step of depositing a sacrificial layer 811 over the structure. The sacrificial layer 811 may be formed over the bottom electrode 202 and cover at least a portion of the vertical portion 802 of the conformal liner layer 801. For example, in one embodiment, an organic planarization layer (OPL) may first be deposited over the entire PCM stack 410 and also over the bottom electrode 202. In other words, the OPL may cover the top surfaces of the heating element 703 and the inner spacer 702, as well as the vertical portion 802 of the conformal liner layer 801. The OPL may then be planarized by a chemical-mechanical-polishing (CMP) process to form a flat top surface, and subsequently recessed below the inner spacer 702 to form the sacrificial layer 811. In one embodiment, the height of sacrificial layer 811 may be lower than inner spacers 702 but higher than phase change element 402 and resistive liner 502 .

[0053] 11 is an illustrative cross-sectional view of a PCM device at a stage of fabricating the device following the process illustrated in FIG. 10 , according to one embodiment of the present invention. More specifically, the present invention provides for covering and protecting the remainder of vertical portion 802 of conformal liner layer 801 with sacrificial layer 811, and removing the portion of vertical portion 802 of conformal liner layer 801 above sacrificial layer 811. Removal of the portion of vertical portion 802 of conformal liner layer 801 may be performed by a selective etching process, such as using an SC2 chemistry containing a strong acid, such as hydrochloric acid, and hydrogen peroxide, resulting in conductive liner 803 being formed from the remaining portion of conformal liner layer 801. Conductive liner 803 covers first dielectric layer 302, phase change element 402, resistive liner 502, and at least a portion of second dielectric layer 602. After removal, an embodiment of the present invention provides for selective removal of the sacrificial layer 811 surrounding the conductive liner 803 .

[0054] 12 is an illustrative cross-sectional view of a PCM device at a stage of fabricating the device following the process illustrated in FIG. 11 , according to one embodiment of the present invention. More specifically, the present invention provides a step of depositing a fourth dielectric layer 821 overlying the PCM stack 410. For example, the fourth dielectric layer 821 may be formed adjacent to the sidewalls of the inner spacer 702, a portion of the sidewalls of the second dielectric layer 602, and the conductive liner 803. In one embodiment, the top surface of the fourth dielectric layer 821 may be planarized to be flush with the top surfaces of the heating element 703 and the inner spacer 702.

[0055] 13 is an illustrative cross-sectional view of a PCM device at a stage of fabricating the device following the process illustrated in FIG. 12 , according to one embodiment of the present invention. More specifically, an embodiment of the present invention provides for forming a top electrode 831 over the heating element 703. For example, in one embodiment, a fifth dielectric layer 832 may be deposited over the PCM stack 410 and the fourth dielectric layer 821. An opening may be provided in the fifth dielectric layer 832 to expose the top surface of the heating element 703, and then the top electrode 831 may be deposited in the opening over the heating element 703. In another embodiment, a conductive material may first be deposited over the PCM stack 410 and then patterned to form the top electrode 831. A dielectric layer may then be deposited to form the fifth dielectric layer 832 surrounding the top electrode 831.

[0056] In one embodiment, bottom electrode 202 and top electrode 831 can be two adjacent metal layers in a BEOL structure. For example, bottom electrode 202 can be metal layer M, and top electrode 831 can be metal layer M+1. Metal layers M and M+1 can extend perpendicular to each other, such that bottom electrode 202 (metal layer M) can extend from left to right, and top electrode 831 (metal layer M+1) can extend into and / or out of the page in a direction perpendicular to the left-to-right direction. Here, M can be a number such as 2, 3, 4, etc. that designates a metal layer.

[0057] 14A and 14B are cross-sectional illustrations of an exemplary PCM device operating in a "set" state and a "reset" state, respectively, according to various embodiments of the present invention. More specifically, PCM device 10 may include a resistive liner 502, which may be deposited to a thickness of about a few nanometers to tens of nanometers, as described above. Resistive liner 502 may be formed to improve the electrical function of phase change element 402 (e.g., reduce resistance drift).

[0058] Resistance drift refers to the phenomenon in which the resistance of phase change element 402 of PCM device 10 does not stabilize to a constant value after writing, especially after a "reset" operation. At this time, at least switch region 840 of phase change element 402 is set to an amorphous state or amorphous phase. Therefore, the resistance of phase change element 402 changes depending on the elapsed time after writing.

[0059] 14A , read current 841 from heating element 703 can flow directly through resistive liner 502 to phase change element 402 because the electrical resistance of resistive liner 502 is significantly higher than that of phase change element 402 in the crystalline or low-resistance state. Read current 841 can continue laterally through phase change element 402, through conductive liner 803, and ultimately to bottom electrode 202.

[0060] 14B, at least a portion of phase change element 402 may change to an amorphous state, such as the portion under heating element 703. As a result, phase change element 402 may exhibit resistance drift over time, and in the absence of resistive liner 502, read current 842 may pass through phase change element 402 in an amorphous state whose electrical resistance may vary, which may adversely affect the performance of the PCM device.

[0061] According to one embodiment of the present invention, resistive liner 502 can mitigate this resistance drift because resistive liner 502 shunts read current 842 away from switch region 840 of phase change element 402 in its amorphous state. With resistive liner 502, read current 842 can flow laterally through resistive liner 502 over the amorphous portion of phase change element 402 because the amorphous portion overlying the crystalline portion of phase change element 402 has significantly higher electrical resistance than resistive liner 502. In other words, read current 842 bypasses switch region 840 (in its amorphous state) of phase change element 402 through resistive liner 502, resulting in stable electrical performance.

[0062] 15 is an exemplary diagram illustrating a flow chart of a method for fabricating a PCM device according to an embodiment of the present invention. The method includes the steps of: (910) forming a bottom electrode on a support structure, such as a substrate or a back-end electronics structure on a substrate; (920) forming a stack of layers on the bottom electrode, including, from bottom to top, a first blanket dielectric layer, a phase change material layer, a second blanket dielectric layer, an optional resistive liner, and a hard mask, the hard mask having an opening; (930) forming an internal spacer on a sidewall of the opening in the hard mask to modify the opening, thereby providing a modified opening; and (940) disposing the modified opening in the second blanket dielectric layer. (950) filling the extended opening with a heating material to form a heating element surrounded by a second blanket dielectric layer and an inner spacer; (960) removing the hard mask and etching the second blanket dielectric layer, the phase change material layer, and the first blanket dielectric layer to form a PCM stack as the second dielectric layer, the phase change element, and the first dielectric layer; (970) forming a conductive liner surrounding at least the phase change element; and (980) forming a top electrode on the heating element.

[0063] It should be understood that the exemplary methods discussed herein can be readily integrated with other semiconductor process flows, semiconductor devices, and integrated circuits comprising various analog and digital or mixed-signal circuits. In particular, integrated circuit dies can be fabricated with various devices, such as field-effect transistors, bipolar transistors, metal-oxide-semiconductor transistors, diodes, capacitors, inductors, and the like. Integrated circuits according to the present invention may be utilized in applications, hardware, and / or electronic systems. Hardware and systems suitable for implementing the present invention may include, but are not limited to, personal computers, communications networks, electronic commerce systems, portable communications devices (e.g., mobile phones), solid-state media storage devices, functional circuits, and the like. Systems and hardware incorporating such integrated circuits are considered part of the embodiments described herein. Given the teachings of the present invention provided herein, those skilled in the art will be able to conceive of other implementations and applications of the techniques of the present invention.

[0064] Thus, at least a portion of one or more of the semiconductor structures described herein may be implemented in an integrated circuit. The resulting integrated circuit chips may be sold by manufacturers in raw wafer form (i.e., as a single wafer with multiple unpackaged chips) or in packaged form as bare die. In the latter case, the chip may be mounted in a single-chip package (such as a plastic carrier with leads attached to a motherboard or other upper carrier) or in a multi-chip package (such as a ceramic carrier with surface and / or buried interconnects). In either case, the chip may then be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate or final product, such as a motherboard. The final product may be anything that includes the integrated circuit chip, from toys and other low-cost applications to advanced computer products with displays, input devices such as keyboards, and central processing units.

[0065] While descriptions of various embodiments of the present invention have been presented for illustrative purposes, these embodiments are not intended to be exhaustive, and the present invention is not limited to the disclosed embodiments. The terms used herein have been selected so as to best explain the principles of the embodiments, their practical applications or technical improvements over existing technology, and to enable others skilled in the art to understand the embodiments disclosed herein. Numerous modifications, substitutions, changes, and equivalents will occur to those skilled in the art. Such modifications, variations, and / or alternative embodiments may be made without departing from the scope of the present invention, and all are contemplated and contemplated within the scope of the present invention. It is therefore to be understood that the appended claims are intended to encompass all such modifications and variations as fall within the scope of the present invention.

Claims

1. Lower electrode; a first dielectric layer overlying the bottom electrode; a phase change element overlying the first dielectric layer; a heating element overlying the phase change element; an upper electrode overlying the heating element; and a conductive liner surrounding at least the phase change element; Equipped with the heating element is approximately centered about the phase change element and has a uniform horizontal distance to the conductive liner surrounding the phase change element; Phase change memory (PCM) devices.

2. 2. The PCM device of claim 1, wherein the heating element is surrounded by a second dielectric layer and a third dielectric layer, the third dielectric layer being above the second dielectric layer and materially different from the second dielectric layer.

3. 3. The PCM device of claim 2, wherein the second dielectric layer and the third dielectric layer have respective exterior sidewalls, the exterior sidewalls being aligned with each other and generally aligned with the phase change element.

4. The PCM device of claim 3 , wherein the conductive liner covers at least a lower portion of the outer sidewall of the second dielectric layer.

5. 10. The PCM device of claim 1 further comprising a resistive liner overlying said phase change element, said resistive liner being beneath said heating and surrounded by said conductive liner.

6. 2. The PCM device of claim 1, wherein the bottom electrode is part of metal layer M, the top electrode is part of metal layer M+1 in a back-end-of-line (BEOL) structure, and metal layer M and metal layer M+1 are two adjacent metal layers.

7. 1. A method of forming a phase change memory device, comprising: forming a bottom electrode on the support structure; Sequentially forming a first blanket dielectric layer, a phase change material layer, a second blanket dielectric layer, and a hard mask over the bottom electrode, the hard mask having an opening exposing a portion of the second blanket dielectric layer; forming an internal spacer in the opening of the hard mask to provide a modified opening; extending the modified opening into the second blanket dielectric layer to provide an extended opening; filling the elongated opening with a heating element; etching the second blanket dielectric layer, the phase change material layer, and the first blanket dielectric layer into a second dielectric layer, a phase change element, and a first dielectric layer, respectively; forming a conductive liner surrounding at least the phase change element; and forming an upper electrode on the heating element; A method for providing the above.

8. Etching the second blanket dielectric layer, the phase change material layer, and the first blanket dielectric layer includes: removing the hard mask surrounding the inner spacer; and etching the second blanket dielectric layer, the phase change material layer, and the first blanket dielectric layer in an anisotropic etching process using the interior spacers and the heating element as an etch mask to expose the bottom electrode. The method of claim 7, comprising:

9. 8. The method of claim 7, wherein extending the modified opening into the second blanket dielectric layer comprises etching the second blanket dielectric layer with an anisotropic etching process using the interior spacers as an etch mask.

10. 8. The method of claim 7, further comprising forming a resistive liner layer over the phase change material layer before forming the second blanket dielectric layer, whereby the resistive liner layer is between the phase change material layer and the second blanket dielectric layer.

11. The forming of the inner spacer includes: depositing a conformal spacer layer covering a top surface of the hard mask and sidewalls of the opening in the hard mask; and and then removing the horizontal portions of the conformal spacer layer using an anisotropic etching process. The method of claim 7, comprising:

12. The step of forming the conductive liner includes: forming a conductive liner layer covering a top surface of the heating element, a top surface of the inner spacer, a sidewall of the inner spacer, a sidewall of the second dielectric layer, a sidewall of the phase change element, a sidewall of the first dielectric layer, and a top surface of the bottom electrode; removing horizontal portions of the conductive liner layer with an anisotropic etching process; and removing at least a portion of the conductive liner layer covering the sidewalls of the inner spacer; The method of claim 7, comprising:

13. 1. A method of forming a phase change memory device, comprising: providing a bottom electrode; Sequentially forming a first blanket dielectric layer, a phase change material layer, and a second blanket dielectric layer over the bottom electrode; forming a hard mask over the second blanket dielectric layer, the hard mask having an opening exposing the second blanket dielectric layer; forming a conformal spacer layer covering a top surface of the hard mask and sidewalls of the opening in the hard mask; removing horizontal portions of the conformal spacer layer to form interior spacers on the sidewalls of the opening; etching the second blanket dielectric layer using the inner spacers as an etch mask to provide an elongated opening; and filling the elongated opening with a heating element. A method for providing

14. 14. The method of claim 13, further comprising forming a resistive liner layer over the phase change material layer before forming the second blanket dielectric layer, whereby the resistive liner layer is between the phase change material layer and the second blanket dielectric layer.

15. etching the second blanket dielectric layer, the resistive liner layer, the phase change material layer, and the first blanket dielectric layer into a second dielectric layer, a resistive liner, a phase change element, and a first dielectric layer, respectively, wherein the heating element and the interior spacer are used as an etch mask in the etching; and forming a conductive liner vertically surrounding at least the resistive liner and the phase change element; The method of claim 14 further comprising:

16. The step of forming the conductive liner includes: forming a conductive liner layer covering the heating element, the inner spacer, the second dielectric layer, the resistive liner, the phase change element, the first dielectric layer, and the bottom electrode; removing horizontal portions of the conductive liner layer; and removing at least a portion of the conductive liner layer covering the sidewalls of the second dielectric layer; 16. The method of claim 15, comprising:

17. The method of claim 16 , wherein the conductive liner is in contact with the resistive liner, the phase change element, and the bottom electrode.

18. 17. The method of claim 16, wherein the inner spacer is a third dielectric layer, further comprising forming a fourth dielectric layer, the fourth dielectric layer surrounding the conductive liner, an outer sidewall of the third dielectric layer, and at least a portion of the sidewall of the second dielectric layer.

19. forming an electrode material layer on the support structure; and patterning the electrode material layer to form the lower electrode; The method of claim 13 further comprising:

20. The method of claim 13 , wherein the inner spacer comprises a third dielectric material different from the second dielectric layer.

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