Thin film transistor and manufacturing method thereof, display substrate and display device

Abstract

The present disclosure provides a thin film transistor, a manufacturing method thereof, a display substrate, and a display device, the thin film transistor including: a gate, an active layer, a source, and a drain provided on a substrate, wherein the active layer is located on a side of the source away from the substrate, the gate is located on a side of the active layer away from the substrate, and the source and the drain are all connected to the active layer; a buffer layer provided between the active layer and a layer in which the source is located; a gate insulating layer provided between the active layer and the layer in which the gate is located, the gate insulating layer having an openwork portion; and an adapter electrode located on a side of the active layer away from the substrate, a portion electrically connected to the active layer via the openwork portion, and another portion electrically connected to the source through a first via that penetrates at least the active layer and the buffer layer, and wherein an orthogonal projection of the adapter electrode on the substrate overlaps with an orthogonal projection of the openwork portion on the substrate.

Description

[Technical Field]

[0001] The present disclosure relates to the field of display technology, and more particularly to a thin film transistor and a method for manufacturing the same, a display substrate, and a display device. [Background technology]

[0002] Vias are required to electrically connect conductive structures on different layers of a display substrate. Vias are formed through a patterning process, and their size affects the product's resolution, frame size, transmittance, etc. Summary of the Invention [Problem to be solved by the invention]

[0003] The present disclosure provides a thin film transistor, a method for manufacturing the same, a display substrate, and a display device. [Means for solving the problem]

[0004] In a first aspect, the present disclosure provides a gate, an active layer, a source, and a drain provided on a substrate, wherein the active layer is located on a side of the source remote from the substrate, the gate is located on a side of the active layer remote from the substrate, and the source and the drain are both connected to the active layer; a buffer layer disposed between the active layer and the layer in which the source is located; a gate insulating layer disposed between the active layer and the layer including the gate, the gate insulating layer having an openwork portion; and an adapter electrode located on a side of the active layer away from the substrate, a portion of which is electrically connected to the active layer through the openwork portion, and another portion of which is electrically connected to the source through a first via that penetrates at least the active layer and the buffer layer and whose orthogonal projection on the substrate overlaps with that of the openwork portion on the substrate.

[0005] In some embodiments, the openwork portion is a second via that penetrates the gate insulating layer, an orthogonal projection of the first via onto the substrate is a first projection, and an orthogonal projection of the second via onto the substrate is a second projection; The first projection is located within the range of the second projection, or a portion of the second projection is located within the range of the first projection and another portion is located outside the range of the first projection.

[0006] In some embodiments, an orthogonal projection of the adapter electrode onto the substrate covers the second projection, hi some embodiments, the adapter electrode is disposed in the same layer as the gate.

[0007] In some embodiments, the adapter electrode and the gate are arranged along a first direction; The distance between the adapter electrode and the gate in the first direction is 1 μm to 3 μm.

[0008] In some embodiments, the thin film transistor further includes a light shield located between the active layer and the substrate, the light shield at least partially overlapping an orthogonal projection of the active layer onto the substrate.

[0009] In some embodiments, the openwork portion is a second via that penetrates the gate insulating layer; The orthogonal projection of the light blocking body onto the substrate and the orthogonal projection of the second via onto the substrate partially overlap.

[0010] In some embodiments, the orthogonal projection of the light shield onto the substrate and the orthogonal projection of the adapter electrode onto the substrate partially overlap.

[0011] In some embodiments, the light shield is located in the same layer as the source.

[0012] In some embodiments, the light shield and the source are arranged along a first direction, and the distance between the light shield and the source in the first direction is 1 μm to 3 μm.

[0013] In some embodiments, the active layer includes a first conductive portion, a second conductive portion, and a channel portion located therebetween, the first via penetrates the first conductive portion, and the second conductive portion functions as the drain.

[0014] In some embodiments, the channel portion and the second conductive portion are arranged along a first direction, and the first conductive portion is striped and extends along the first direction.

[0015] In some embodiments, the pitch in the first direction of both the orthogonal projection onto the substrate of the portion where the first conductive portion and the adapter electrode contact each other and the orthogonal projection onto the substrate of the channel portion is 1 μm to 4 μm.

[0016] In some embodiments, both a portion of the adapter electrode connected to the active layer through the openwork portion and a portion of the adapter electrode connected to the source through a first via are arranged along a first direction.

[0017] In some embodiments, the diameter of the first via near the edge of the substrate is less than 2 μm; The buffer portion has a first portion covered with the active layer and a second portion not in contact with the active layer, the first portion having a first slope facing the first via, the second portion having a second slope facing the first via, the gradient of the first slope being between 70 and 90°, and the gradient of the second slope being 60° or less.

[0018] In some embodiments, an orthogonal projection of a bottom of the first via onto the substrate is located within an area covered by an orthogonal projection of the source onto the substrate; The difference between the length of the source in the first direction and the length of the bottom of the first via in the first direction is 0.5 μm or more.

[0019] In some embodiments, a protrusion is formed on the buffer layer at a portion covering the source on a side of the active layer that is closer to the channel portion.

[0020] In some embodiments, the thickness of the protrusion in the direction perpendicular to the substrate is 1000 μm to 20000 μm.

[0021] In some embodiments, the surface of the protrusion facing away from the substrate is an arcuate surface, and the arcuate surface has a curvature of 15° to 90°.

[0022] In some embodiments, the portion of the adapter electrode located within the first via is a third portion; The surface of the third portion facing away from the substrate is a convex surface that is convex outward toward the side facing away from the substrate.

[0023] In some embodiments, the difference between the maximum thickness and the minimum thickness of the third portion in the direction perpendicular to the substrate is 0.3 μm to 0.6 μm.

[0024] In some embodiments, the openwork portion is a second via that penetrates the gate insulating layer; The difference between the gradient of the slope on the gate insulating layer toward the second via and the gradient of the same side slope on the active layer toward the first via is 0° or more and 30° or less.

[0025] In some embodiments, the active layer material comprises a metal oxide material.

[0026] In a second aspect, the present disclosure further provides a display substrate comprising the thin film transistor provided by the first aspect.

[0027] In some embodiments, the display substrate includes a plurality of gate lines extending along a first direction and a plurality of data lines extending along a second direction, the plurality of gate lines and the plurality of data lines intersecting each other to define a plurality of pixel areas, and the thin film transistor is located in the pixel area; The gate of the thin film transistor is connected to the corresponding gate line, and the source of the thin film transistor is connected to the corresponding data line; The orthogonal projection of the light shield onto the substrate does not overlap with the orthogonal projection of the gate lines onto the substrate.

[0028] In a third aspect, the present disclosure further provides a display device including a display substrate provided by the second aspect.

[0029] In a fourth aspect, the present disclosure provides a semiconductor device comprising: a source, a buffer layer, an active layer, a drain, and a gate insulating layer formed on a substrate, the drain being connected to the active layer, the gate insulating layer being located on a side of the active layer away from the substrate, and the gate insulating layer having an openwork portion; forming an adapter electrode on a side of the active layer away from the substrate, the adapter electrode having a portion electrically connected to the active layer through the openwork portion and another portion electrically connected to the source through a first via that penetrates at least the active layer and the buffer layer and whose orthogonal projection on the substrate overlaps with that of the openwork portion on the substrate; forming a gate on a side of the gate insulating layer remote from the substrate.

[0030] In some embodiments, the step of forming the gate insulating layer comprises: forming a gate insulating material layer; performing a patterning process on the gate insulating material layer to form the gate insulating layer with an openwork portion, the openwork portion being a second via penetrating the gate insulating layer, wherein an orthogonal projection of the first via onto the substrate is a first projection and an orthogonal projection of the second via onto the substrate is a second projection; The method includes a step of positioning the first projection within the range of the second projection, or positioning a portion of the second projection within the range of the first projection and another portion outside the range of the first projection.

[0031] In some embodiments, the active layer includes a first processing-ready portion, a second processing-ready portion, and a channel portion located therebetween, and a portion of the first processing-ready portion is exposed to the second via; Conducting a portion of the first processing-waiting portion exposed by the second via; The method further includes the step of making the first processing waiting section and the second processing waiting section conductive, and using the conductive second processing waiting section as the drain.

[0032] In some embodiments, the manufacturing method further comprises forming a light shield formed synchronously with the source. [Brief explanation of the drawings]

[0033] The drawings are used to provide a further understanding of the present disclosure, constitute a part of the specification, and are used to explain the present disclosure in conjunction with the following specific embodiments, but are not intended to limit the disclosure. [Figure 1A] FIG. 1 is a plan view of a thin film transistor provided in some embodiments of the present disclosure. [Figure 1B] FIG. 10 is a plan view of a thin film transistor provided in another embodiment of the present disclosure. [Figure 2A] FIG. 1B is a cross-sectional view taken along line AA′ in FIG. 1A. [Figure 2B] FIG. 1B is another cross-sectional view taken along the line AA′ in FIG. 1A. [Figure 2C] 1B is a cross-sectional view taken along line BB'. [Figure 2D] FIG. 1C is another cross-sectional view taken along the line BB′ in FIG. 1B. [Figure 2E] FIG. 1C is yet another cross-sectional view taken along line BB′ in FIG. 1B. [Figure 2F] FIG. 1C is a further cross-sectional view taken along line BB′ in FIG. 1B. [Figure 3A] 1 is a schematic diagram illustrating the locations of a first via, a second via, and an active layer provided in some embodiments of the present disclosure. [Figure 3B] FIG. 10 is a conceptual diagram showing the positions of a first via, a second via, and an active layer provided in another embodiment of the present disclosure. [Figure 3C] FIG. 10 is a conceptual diagram showing the positions of a first via, a second via, and an active layer provided in another embodiment of the present disclosure. [Figure 3D] FIG. 10 is a conceptual diagram showing the positions of a first via, a second via, and an active layer provided in another embodiment of the present disclosure. [Figure 3E] FIG. 10 is a conceptual diagram showing the positions of a first via, a second via, and an active layer provided in another embodiment of the present disclosure. [Figure 4A] 1 is a scanning electron microscope (SEM) view of a longitudinal cross section of a first via provided in some embodiments of the present disclosure. [Figure 4B] 1 is a scanning electron microscope (SEM) view of a vertical cross section of a first via and its surroundings provided in some embodiments of the present disclosure. [Figure 5] FIG. 2 is a plan view of a display substrate provided in some embodiments of the present disclosure. [Figure 6A] 1 is a cross-sectional view of a display substrate provided in some embodiments of the present disclosure. [Figure 6B] FIG. 10 is a cross-sectional view of a display substrate provided in another embodiment of the present disclosure. [Figure 7A] 1 is a conceptual diagram illustrating connections between thin film transistors, gate lines, and data lines provided in some embodiments of the present disclosure. [Figure 7B] 1 is a conceptual diagram illustrating connections between thin film transistors, gate lines, and data lines provided in some embodiments of the present disclosure. [Figure 8A] 1A to 1C are conceptual diagrams illustrating a manufacturing process of a thin film transistor provided in a first example of the present disclosure. [Figure 8B] 1A to 1C are conceptual diagrams illustrating a manufacturing process of a thin film transistor provided in a first example of the present disclosure. [Figure 8C] 1A to 1C are conceptual diagrams illustrating a manufacturing process of a thin film transistor provided in a first example of the present disclosure. [Figure 8D] 1A to 1C are conceptual diagrams illustrating a manufacturing process of a thin film transistor provided in a first example of the present disclosure. [Figure 8E] 1A to 1C are conceptual diagrams illustrating a manufacturing process of a thin film transistor provided in a first example of the present disclosure. [Figure 8F] 1A to 1C are conceptual diagrams illustrating a manufacturing process of a thin film transistor provided in a first example of the present disclosure. [Figure 8G] 1A to 1C are conceptual diagrams illustrating a manufacturing process of a thin film transistor provided in a first example of the present disclosure. [Figure 8H] 1A to 1C are conceptual diagrams illustrating a manufacturing process of a thin film transistor provided in a first example of the present disclosure. [Figure 9A] 10A to 10C are conceptual diagrams illustrating a manufacturing process of a thin film transistor provided in a third example of the present disclosure. [Figure 9B] FIG. 9B is a conceptual diagram of a method for forming a second via on a gate insulating layer in step S41 in FIG. 9A. [Figure 10] 10A and 10B are conceptual diagrams illustrating a method for manufacturing a thin film transistor provided in a fourth example of the present disclosure. [Figure 11] 10A to 10C are conceptual diagrams illustrating a manufacturing process of a thin film transistor provided in a fifth example of the present disclosure. [Figure 12] 10A to 10C are conceptual diagrams illustrating a manufacturing process of a thin film transistor provided in a sixth example of the present disclosure. [Figure 13] FIG. 10 is a conceptual diagram of a method for manufacturing a thin film transistor provided in a seventh example of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0034] Specific embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain and interpret the present disclosure, and are not used to limit the present disclosure.

[0035] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will clearly and completely describe the technical solutions of the embodiments of the present disclosure in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only some embodiments of the present disclosure, and not all embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without requiring creative work all belong to the protection scope of the present disclosure.

[0036] The terms used herein to describe embodiments of the present disclosure are not intended to limit and / or restrict the scope of the disclosure. For example, unless otherwise defined, technical or scientific terms used in this disclosure have the ordinary meaning understood by one of ordinary skill in the art to which the present disclosure belongs. It should be understood that the terms "first," "second," and similar terms used in this disclosure do not denote any order, number, or importance, but are merely used to distinguish between different components. Unless the context clearly indicates otherwise, similar words such as the singular "one" or "an" also do not denote a numerical limitation, but rather the presence of at least one. Similar words such as "comprise" mean that the element or object currently preceding "comprise" encompasses the element or object exemplified after the current "comprise" and equivalents, and do not exclude other elements or objects. Terms such as "connected" or "coupled" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "top," "bottom," "left," "right," and the like are used only to denote relative positional relationships, and if the absolute position of the described object changes, such relative positional relationships may change accordingly.

[0037] On a display substrate, the electrical connections between the conductive structures on different layers must be made through vias, which are formed by a patterning process. If the via area is large, the area occupied by the entire thin film transistor will increase, which will affect the product's resolution, frame size, transmittance, etc.

[0038] FIG. 1A is a plan view of a thin film transistor provided in some embodiments of the present disclosure, FIG. 1B is a plan view of a thin film transistor provided in another embodiment of the present disclosure, FIG. 2A is a cross-sectional view along line AA′ in FIG. 1A, FIG. 2B is another cross-sectional view along line AA′ in FIG. 1A, FIG. 2C is a cross-sectional view along line BB′ in FIG. 1B, FIG. 2D is another cross-sectional view along line BB′ in FIG. 1B, FIG. 2E is yet another cross-sectional view along line BB′ in FIG. 1B, and FIG. 2F is a further cross-sectional view along line BB′ in FIG. 1B.

[0039] As shown in Figures 1A to 2F, the thin film transistor 10 includes a gate 11, an active layer 12, a source 13, and a drain 14 provided on a substrate 20, where the active layer 12 is located on the side of the source 13 away from the substrate 20, the gate 11 is located on the side of the active layer 12 away from the substrate 20, and the source 13 and the drain 14 are both connected to the active layer 12.

[0040] 2A to 2F, the thin film transistor 10 further includes a buffer layer BFL, a gate insulating layer GI, and an adapter electrode 15. The buffer layer BFL is disposed on a substrate 20 and is located between the active layer 12 and a layer including the source 13. The buffer layer BFL can be used to prevent or reduce the diffusion of metal atoms and / or impurities from the substrate 20 to the active layer 12. The material of the buffer layer BFL can include one or more of silicon nitride, silicon oxide, and silicon nitride. The thickness of the buffer layer BFL is between 100 nm and 700 nm.

[0041] The gate insulating layer GI is disposed between the active layer 12 and the layer containing the gate 11, and the gate insulating layer GI has an openwork portion VL, which may be a via or an openwork portion between the gate insulating layers GI of adjacent thin film transistors 10. The gate insulating layer GI may include an inorganic material such as silicon oxide, silicon nitride, and / or silicon nitride, and may be formed as a multilayer or single layer.

[0042] The adapter electrode 15 is located on the side of the active layer 12 away from the substrate 20, and is electrically connected to the active layer 12 and to the source 13 through a first via V1, where the first via V1 penetrates at least the active layer 12 and the buffer layer BFL, and there is an overlap between the orthogonal projection of the first via V1 onto the substrate 20 and the orthogonal projection of the openwork portion onto the substrate 20. For example, the gate insulating layers GI of adjacent thin film transistors 10 are connected in an integral structure, and for example, as shown in FIGS. 2A and 2C to 2F, a second via V2 is formed on the integral structure, and there is an overlap between the orthogonal projection of the second via V2 and the first via V1 onto the substrate 20; or, as shown in FIG. 2B, the gate insulating layers GI of different thin film transistors 10 form independent blocking film layers, and there is an overlap between the orthogonal projection of the first via V1 onto the substrate 20 and the openwork portion around the blocking film layer.

[0043] In some embodiments, the material of the active layer 12 includes a metal oxide material, such as IGZO, IGTO, IGZTO, IGZYO, or ITZO. Both the adapter electrode 15 and the source 13 can be made of metal. If the active layer 12 is made of a metal oxide, connecting the active layer 12 directly to the source 13 through a via can easily generate oxide at the contact interface between the active layer 12 and the source 13, increasing the contact resistance between the active layer 12 and the source 13. In contrast, embodiments of the present disclosure rely on an adapter electrode 15, which is located on the side of the active layer 12 away from the substrate 20 and is electrically connected to the active layer 12 and the source 13. In this case, after the active layer 12 is formed, the surface of the active layer 12 corresponding to the adapter electrode 15 can be treated to prevent oxide from forming at the interface between the active layer 12 and the adapter electrode 15. This reduces the contact resistance between the active layer 12 and the adapter electrode 15, thereby ensuring the contact reliability between the active layer 12 and the source 13. Furthermore, in the embodiment of the present disclosure, there is an overlap between the first via V1 and the openwork portion VL of the gate insulating layer GI projected onto the substrate 20, which reduces the overall area occupied by the openwork portion VL and the first via V1, which is advantageous for improving resolution, reducing the frame width, and increasing light transmittance.

[0044] In some embodiments, as shown in FIGS. 2C-2F, the orthogonal projection of the adapter electrode 15 onto the substrate 20 covers the orthogonal projection of the second via V2 onto the substrate 20.

[0045] In some embodiments, the first via V1 simultaneously penetrates the gate insulating layer GI, the active layer 12, and the buffer layer BFL, and the openwork portion is a second via V2 penetrating the gate insulating layer GI. FIG. 3A is a schematic diagram of the locations of the first via, the second via, and the active layer provided in some embodiments of the present disclosure. FIG. 3B is a schematic diagram of the locations of the first via, the second via, and the active layer provided in another embodiment of the present disclosure. FIG. 3C is a schematic diagram of the locations of the first via, the second via, and the active layer provided in another embodiment of the present disclosure. FIG. 3D is a schematic diagram of the locations of the first via, the second via, and the active layer provided in another embodiment of the present disclosure. FIG. 3E is a schematic diagram of the locations of the first via, the second via, and the active layer provided in another embodiment of the present disclosure. As shown in Figures 3A to 3E, the orthogonal projection of the first via V1 onto the substrate 20 is the first projection, and the orthogonal projection of the second via V2 onto the substrate 20 is the second projection. The first and second projections overlap, and as shown in Figure 3A, the first projection is located within the range of the second projection. Alternatively, as shown in Figures 3B to 3E, a portion of the second projection is located within the range of the first projection, and another portion is located outside the range of the first projection. Also, as shown in Figures 3A and 3B, the first projection can be located within the range of the orthogonal projection of the active layer 12 onto the substrate 20, and can be spaced apart from the interface of the orthogonal projection of the active layer 12 onto the substrate 20. Alternatively, as shown in Figures 3C to 3E, the first projection can be located at a corner position of the orthogonal projection of the active layer 12 onto the substrate 20.

[0046] The embodiments of the present disclosure do not particularly limit the shapes of the first via V1 and the second via V2, and for example, the orthogonal projection of the first via V1 onto the substrate 20 may be circular, rectangular, semicircular, or any other irregular shape. Furthermore, the orthogonal projection of the first via V1 onto the substrate 20 may be located within the range of the orthogonal projection of the active layer 12 onto the substrate 20, or may exceed the orthogonal projection of the active layer 12 onto the substrate 20.

[0047] 1A and 1B, the adapter electrode 15 is disposed in the same layer as the gate 11. Note that "disposed in the same layer" in the embodiments of the present disclosure means that the two structures are formed from the same material layer through a patterning process, and therefore the two are in the same layer in terms of stacking relationship, but this does not necessarily mean that the distance between the two and the substrate 20 is the same.

[0048] 1A to 2F, the thin-film transistor 10 further includes a light shield 16 located between the active layer 12 and the substrate 20, the orthogonal projection of which onto the substrate 20 at least partially overlaps with the orthogonal projection of the active layer 12 onto the substrate 20. For example, the active layer 12 includes a first conductive portion 121, a second conductive portion 122, and a channel portion 120 located therebetween, and the orthogonal projection of the light shield 16 onto the substrate 20 covers at least the orthogonal projection of the channel portion 120 onto the substrate 20. The light shield 16 can prevent the channel portion 120 of the active layer 12 from generating a large amount of leakage current due to light irradiation, thereby preventing the characteristics of the thin-film transistor 10 from being affected.

[0049] As shown in FIGS. 1A and 1B, the adapter electrode 15 is connected to the first conductive portion 121 in the active layer 12 through the second via V2, and is connected to the source 13 through the first via V1.

[0050] In the manufacturing process, when the second via V2 is formed by directly patterning the gate insulating layer GI, the active layer 12 below the second via V2 may be dry-etched during the etching process due to the thinness of the active layer 12, which may damage the active layer 12 and the underlying buffer layer BFL. In this case, if the distance between the light shield 16 and the source 13 is small, the first via V1 / second via V2 may communicate with the light shield 16, and after the adapter electrode 15 is formed in the via, a short circuit may occur between the adapter electrode 15 / source 13 and the light shield 16.

[0051] The light shield 16 is placed as far away as possible from the second via V2 to avoid damaging the active layer 12 when forming the second via V2 and to avoid the via extending into the light shield and causing a short circuit between the light shield and the adapter electrode / drain.

[0052] As shown in FIG. 1A , the positions of the light shield 16 and the second via V2 are offset, i.e., the orthogonal projection of the light shield 16 onto the substrate 20 does not overlap with the orthogonal projection of the second via V2 onto the substrate 20. Based on this, when the adapter electrode 15 is installed in the second via V2, the adapter electrode 15 and the light shield 16 do not overlap in the direction perpendicular to the substrate. Furthermore, in the thin film transistor according to the embodiment of the present disclosure, the gate insulating layer GI is patterned using a half-tone mask process to form the second via V2, which can avoid damage to the active layer 12. Therefore, in the thin film transistor shown in FIG. 1A , the light shield and the second via are offset, while the half-tone mask process is used to form the second via, thereby avoiding product defects.

[0053] In some embodiments, the orthogonal projection of the light shield 16 onto the substrate 20 partially overlaps with the orthogonal projection of the second via V2 onto the substrate 20. Furthermore, the orthogonal projection of the light shield 16 onto the substrate 20 partially overlaps with the orthogonal projection of the adapter electrode 15 onto the substrate 20.

[0054] In the thin-film transistor according to the embodiment of the present disclosure, the second via is formed by manufacturing using a half-tone mask process (the specific manufacturing method will be described in the following embodiment and will not be described here), so even if the thickness of the active layer 12 is small, the active layer 12 is not damaged, and further, the buffer layer BFL located on the side of the active layer 12 closer to the substrate 20 is not damaged either. Based on this, even if the orthogonal projection of the light shield 16 onto the substrate 20 and the orthogonal projection of the second via V2 onto the substrate 20 partially overlap, the overlap between them is only in the thickness direction of the substrate 20, and as shown in FIG. 2C , there is a gap between the active layer 12 and the buffer layer BFL, and there is an insulating gap between the adapter electrode 15 formed on the second via V2 and the light shield 16, so that a short circuit phenomenon can be avoided.

[0055] In some embodiments, as shown in Figure 2C, both the portion of the adapter electrode 15 connected to the active layer through the openwork / second via V2 and the portion of the adapter electrode 15 connected to the source through the first via V1 are arranged along the first direction X. That is, as shown in Figures 3A-3E, the first via V1 is located on the side of the openwork / second via V2 away from the gate 11 / light shield 16 in the first direction, further avoiding the risk of a short circuit caused by the adapter electrode 15 contacting the light shield 16 through the first via V1.

[0056] In addition, the connection method between the adapter electrode 15 and the source 13 in the first via V1 can be flexibly set, and as shown in Figure 2D, the adapter electrode 15 and the source 13 can be electrically connected in a fully covered manner, or as shown in Figures 2E to 2F, the electrical connection can also be achieved in a half-wrapped manner, and the embodiments of the present disclosure are not limited to this.

[0057] In some embodiments, the adapter electrode 15 may be formed only in a partial area of ​​the second via V2, or may completely fill the second via V2. As shown in Figure 2A, the orthogonal projection of the adapter electrode 15 onto the substrate 20 partially overlaps with the orthogonal projection of the second via V2 onto the substrate 20. Preferably, as shown in Figures 2C to 2F, the orthogonal projection of the adapter electrode 15 onto the substrate 20 covers the orthogonal projection of the second via V2 onto the substrate 20.

[0058] 1A to 2F, the light shield 16 is disposed in the same layer as the source 13. In one example, the light shield 16 and the source 13 may both employ a metal stack of Mo / Al / Al, or a metal stack of MoNB / Cu, or a metal stack of MTD / Cu, or a metal stack of MoNB / Cu / MTD. The thickness of the light shield 16 and the source 13 may both be between 1000 Å and 10000 Å.

[0059] In some embodiments, as shown in FIGS. 1B and 2C to 2F, the light shielding body 16 and the source 13 are arranged along a first direction X, and the distance d1 between the light shielding body 16 and the source 13 in the first direction X is 1 μm to 3 μm, for example, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, etc., and is not limited to this in the embodiments of the present disclosure.

[0060] In some embodiments, as shown in FIGS. 1B and 2C to 2F, the adapter electrode 15 is disposed in the same layer as the gate 11, and they are arranged along the first direction X. The distance d2 between the adapter electrode 15 and the gate 11 in the first direction X is 1 μm to 3 μm, for example, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, etc., and is not limited to this in the embodiments of the present disclosure.

[0061] In the thin film transistor provided by the embodiment of the present disclosure, the formation of the second via V2 does not damage the underlying active layer, and if the diameter of the first via V1 is smaller than the diameter of the second via V2, the via penetrating the gate insulating layer GI, the active layer 12, and the buffer layer BFL does not communicate with the light shield 16. Furthermore, the pitch between the light shield 16 and the source 13 can be set small, and accordingly, the pitch between the adapter electrode 15 connected to the source 13 and the gate 11 located opposite the channel portion 120 shielded by the light shield 16 can also be set small. This reduces the area occupied by the entire thin film transistor, which is advantageous for further improving resolution, reducing the frame width, and improving light transmittance.

[0062] In some embodiments, both the first conductive portion 121 and the second conductive portion 122 of the active layer 12 are formed by doping a semiconductor material. A first via V1 passes through the first conductive portion 121, and the second conductive portion 122 is used as the drain 14.

[0063] As shown in FIG. 1A, by displacing the light shielding body 16 and the adapter electrode 15, the adapter electrode 15 penetrates the first conductive portion 121 on the active layer 12, and the light shielding body 16 and the channel portion 120 on the active layer are directly opposite each other. In other words, the first conductive portion 121 and the channel portion 120 of the active layer are also disposed so as to intersect, and therefore the active layer diagram in FIG. 1A is L-shaped.

[0064] In addition, the active layer 12 forms a first active conductor between the portion connected to the source 13 via the adapter electrode 15 and the channel portion 120, and forms a second active conductor between the portion of the active layer 12 that functions as the drain 14, i.e., the second conductive portion 122 and the channel portion 120, thereby conducting the source 13 and the drain 14 when forming a carrier path in the channel portion 120 of the active layer 12.

[0065] 1A, the source 13 of the thin film transistor is connected to the corresponding data line, and therefore the adapter electrode 15 is connected to the source 13 through the second via V2 / first via V1. The second via V2 and the light shield 16 do not intersect with the substrate 20 in the vertical direction, and the light shield 16 faces the channel portion 120 on the active layer 12, so the first active conductive wire connecting the source 13 and the channel portion 120 is L-shaped. Furthermore, since the source 13 is connected to the data line, the first active conductive wire is also electrically connected to the data line. If the first active conductive wire is too long, the load loss on the data line will increase.

[0066] Based on this, as shown in Figures 1B and 2C to 2F, the channel section 120 and the second conductive section 122 in the active layer are arranged along the first direction X, and the first conductive section 121 is striped and extends along the first direction X.

[0067] In some embodiments, as shown in Figures 1B and 2C to 2F, the orthogonal projection onto the substrate 20 of the portion where the first conductive portion 121 and the adapter electrode 15 contact each other and the orthogonal projection onto the substrate 20 of the channel portion 120 have a pitch d3 in the first direction X of 1 μm to 4 μm, i.e., the length of the first active conductor portion is 1 μm to 4 μm, for example, 1 μm, 1.5 μm, 2 μm, 2.5 μm, 3 μm, 3.5 μm, 4 μm, etc., and is not limited to this in the embodiments of the present disclosure.

[0068] That is, the light shields 16 and the sources 13 are arranged along the first direction X, and after the pitch between the light shields 16 and the sources 13 is shortened, the first conductive portions 121 and the channel portions 120 on the active layer 12 are also arranged along the first direction X, and the first conductive portions 121 have a stripe shape. Furthermore, the length of a portion of the first active conductive wire is within 4 μm, which is beneficial to reducing the load loss on the data line and reducing the area occupied by the entire thin film transistor, thereby beneficial to improving the resolution.

[0069] 4A is a scanning electron microscope (SEM) image of a vertical cross section of a first via provided in some embodiments of the present disclosure, and FIG. 4B is a scanning electron microscope (SEM) image of a vertical cross section of a first via and its surroundings provided in some embodiments of the present disclosure. In FIG. 4A and FIG. 4B, the orthogonal projection of the first via V1 onto the substrate 20 is located at the orthogonal projection of the active layer 12 onto the substrate 20. As shown in FIG. 4A, the buffer layer BFL has a first portion BFL1 covered by the active layer 12 and a second portion BFL2 not in contact with the active layer 12. The first portion has a first slope toward the first via V1, and the gradient α of the first slope is between 70° and 90°. The second portion BFL2 has a second slope toward the first via V1, and the gradient angle β of the second slope is 60° or less. When etching the first via V1, the upper part of the second portion BFL2 is covered with resist and the upper part of the first portion BFL1 is covered with the active layer 12, so that the shape of the first via V1 that is finally formed exhibits the different slope angles as described above. The diameter d of the end of the first via V1 close to the substrate 20 is less than 2 μm, for example, the diameter d is between 1.6 μm and 1.8 μm, for example, the diameter d is 1.65 μm.

[0070] In some embodiments, the orthogonal projection of the bottom of the first via V1 onto the substrate is located within an area covered by the orthogonal projection of the source onto the substrate, and the difference between the length of the source in the first direction and the length of the bottom of the first via V1 in the first direction is 0.5 μm or more.

[0071] In some embodiments, a protrusion R is formed on the buffer layer BFL in a portion covering the side of the source active layer 12 that is closer to the channel portion.

[0072] In some embodiments, the thickness of the protrusion R in the direction perpendicular to the substrate is 1000 μm to 20000 μm.

[0073] In some embodiments, the surface of the protrusion R facing away from the substrate is an arcuate surface, and the arcuate angle is 15° to 90°.

[0074] In some embodiments, the portion of the adapter electrode 15 located within the first via V1 is the third portion 15a, and the surface of the third portion 15a facing away from the substrate is a convex surface that protrudes outward toward the substrate. The thickness of the portion of the third portion 15a near the edge of the first via is relatively thin, and the thickness of the portion of the third portion 15a near the center of the first via is relatively thick.

[0075] In some embodiments, the difference between the maximum thickness and the minimum thickness of the third portion 15a in the direction perpendicular to the substrate is 0.3 μm to 0.6 μm, and preferably 0.35 μm to 0.55 μm.

[0076] In some embodiments, the openwork portion is a second via V2 that penetrates the gate insulating layer GI, and the difference between the gradient of the slope on the gate insulating layer GI toward the second via V2 and the gradient of the same side slope toward the first via V1 on the active layer 12 is 0° or more and 30° or less. For example, the difference between the two is 2° to 10°.

[0077] For example, the gradient of the slope on the gate insulating layer GI toward the second via V2 is 30° to 90°, and the gradient of the same slope on the active layer 12 toward the first via V1 is 30° to 90°.

[0078] The embodiments of the present disclosure further provide a display substrate, and FIG. 5 is a plan view of a display substrate provided in some embodiments of the present disclosure, FIG. 6A is a cross-sectional view of a display substrate provided in some embodiments of the present disclosure, FIG. 6B is a cross-sectional view of a display substrate provided in another embodiment of the present disclosure, FIG. 7A is a conceptual diagram of a connection between a thin film transistor and a gate line and a data line provided in some embodiments of the present disclosure, and FIG. 7B is a conceptual diagram of a connection between a thin film transistor and a gate line and a data line provided in some embodiments of the present disclosure, and as shown in FIGS. 5 to 7B, the display substrate includes the thin film transistor 10 in the above embodiment.

[0079] In a first example, the display substrate can be used in a liquid crystal display panel, and the display substrate includes a plurality of gate lines GL extending along a first direction X and a plurality of data lines DL extending along a second direction Y, which are disposed on a substrate 20. The plurality of gate lines GL and the plurality of data lines DL are disposed intersecting each other to define a plurality of pixel regions P, and each pixel region P is provided with a thin film transistor 10 according to the above embodiment. Here, the gate 11 of each thin film transistor 10 is connected to a corresponding gate line GL, the source 13 is connected to a corresponding data line DL, and the drain 14 is connected to a pixel electrode 30 in the corresponding pixel region P. In some embodiments, as shown in FIGS. 6A and 7A , the gate 11 and the gate line GL of each thin film transistor 10 are integrally formed, and the gate 11 and the gate line GL extend in the same direction, and the source 13 of each thin film transistor 10 and the data line DL are integrally formed.

[0080] In another embodiment, as shown in Figures 6B and 7B, the gate 11 of the thin film transistor 10 is formed integrally with the gate line GL, the gate line GL extends along the first direction X, and the gate 11 is a stripe-shaped electrode extending along the second direction Y, and the orthogonal projection of the light shielding body 16 onto the substrate 20 does not overlap with the orthogonal projection of the gate line GL onto the substrate 20.

[0081] 6B and 7B, the light shields 16 and the sources 13 are arranged along the first direction X with a reduced pitch, and the gates 11 and the adapter electrodes 15 are arranged along the first direction X with a reduced pitch, which is advantageous for reducing the length of the active layers 12 and reducing the load loss of the data lines. In the embodiments of the present disclosure, the reduction in the area occupied by the thin film transistors on the display substrate is further advantageous for improving resolution, reducing the frame width, and increasing light transmittance.

[0082] In some embodiments, a passivation layer PVX and a planarization layer PLN are further disposed on the side of the gate 11 of the thin film transistor 10 away from the substrate 20. The planarization layer PLN is located on the side of the passivation layer PVX away from the substrate 20. The material of the passivation layer PVX may include one or more of silicon oxide, silicon nitride, and silicon nitride, and the thickness may be between 200 and 400 nm. The thickness of the planarization layer PLN may be between 2 and 3 μm, and the material may be an organic material. The pixel electrode 30 is located on the side of the planarization layer PLN away from the substrate 20 and is connected to the drain 14 through a third via V3 that penetrates at least the planarization layer PLN and the passivation layer PVX. The pixel electrode 30 may be made of a transparent conductive material such as IGZO or IZO, and the thickness may be between 400 and 1000 Å.

[0083] In some embodiments, the display substrate further includes an insulating spacer layer (not shown) and a common electrode (not shown). The insulating spacer layer is located on the side of the pixel electrode 30 away from the substrate 20 and may include at least one of silicon nitride, silicon oxide, and silicon nitride as its material and may have a thickness between 1000 and 3000 Å. The common electrode is located on the side of the insulating spacer layer away from the substrate 20 and may include a transparent conductive material such as ITO or IZO as its material and may have a thickness of 40 nm or 135 nm.

[0084] The present disclosure also provides a display device including the display substrate of the above embodiment, which may be a product or component having a display function, such as a mobile phone, a tablet, a navigation system, an electronic paper, or an OLED panel.

[0085] An embodiment of the present disclosure further provides a method for manufacturing the above thin film transistor, including:

[0086] S11: A source, a buffer layer, an active layer, a drain, and a gate insulating layer are formed on a substrate, where the source and drain are electrically connected to the active layer.

[0087] S12, forming an adapter electrode located on a side of the active layer away from the substrate, electrically connected to the active layer, and electrically connected to the source through a first via that at least penetrates the active layer and the buffer layer, wherein at least a portion of the first via is exposed at the gate insulating layer.

[0088] S13, forming a gate on the side of the gate insulating layer away from the substrate.

[0089] In some embodiments, forming the gate insulating layer includes forming a gate insulating material layer and then performing a patterning process on the gate insulating material layer to form the gate insulating layer, wherein the gate insulating layer has a second via, and the adapter electrode is connected to the active layer through the second via, and an orthogonal projection of the first via onto the substrate is a first projection, and an orthogonal projection of the second via onto the substrate is a second projection, and the second projection is located within the range of the first projection, or a portion of the second projection is located within the range of the first projection and another portion is located outside the range of the first projection.

[0090] In some embodiments, the active layer includes a first processing-awaiting portion, a second processing-awaiting portion, and a channel portion located therebetween, and a portion of the first processing-awaiting portion is exposed to the second via. The manufacturing method further includes the steps of: conductively converting the portion of the first processing-awaiting portion exposed by the second via; and conductively converting the first processing-awaiting portion and the second processing-awaiting portion into conductive materials, and using the conductive second processing-awaiting portion as the drain.

[0091] In some embodiments, the manufacturing method further comprises forming a light shield formed synchronously with the source.

[0092] 8A to 8H are conceptual diagrams of a manufacturing process of a thin film transistor provided in the first example of the present disclosure. As shown in FIGS. 8A to 8H, the manufacturing method of a thin film transistor 10 includes the following.

[0093] S20, providing a substrate 20 and cleaning the substrate 20;

[0094] 8A, the source 13 and the light shielding body 16 are formed. Here, the source 13 and the light shielding body 16 can both be a metal stack of Mo / Al / Al, a metal stack of MoNB / Cu, or a metal stack of MTD / Cu. The thickness of the light shielding body 16 and the source 13 can both be between 1000 Å and 10000 Å.

[0095] As shown in FIG. 8B, a buffer layer BFL is formed. The buffer layer BFL can be formed using a chemical vapor deposition (CVD) process, and the material of the buffer layer BFL can include one or more of silicon nitride, silicon oxide, and silicon nitride. The thickness of the buffer layer BFL is between 100 nm and 700 nm.

[0096] S23, as shown in FIG. 8C, a semiconductor layer 12a is formed. The semiconductor layer 12a can be formed using a sputtering process, and its material can be IGZO, with a thickness between 10 and 80 nm.

[0097] S24, as shown in FIG. 8D, a gate insulating layer GI is formed, which can be formed by CVD or atomic layer deposition (ALD). The material of the gate insulating layer GI can include one or more of silicon nitride, silicon oxide, and silicon nitride, and the thickness is between 600 Å and 2000 Å.

[0098] S25, as shown in FIG. 8E, a patterning process is performed on the gate insulating layer GI to form a second via V2 penetrating the gate insulating layer GI, and the second via V2 exposes the semiconductor layer 12a.

[0099] In S26, the semiconductor layer 12a is subjected to a conductive treatment, and the portion of the semiconductor layer 12a exposed to the second via V2 is formed as a conductor.

[0100] In S27, as shown in FIG. 8F, a first via V1 is formed, and the first via V1 penetrates at least the semiconductor layer 12a and the buffer layer BFL to expose at least a portion of the source 13.

[0101] In step S28, as shown in FIG. 8G, a MoNB / Cu stack, or an MTD / Cu stack, or an MoNB / Cu / MTD stack is formed to a thickness of 200 to 1200 nm, and a patterning process is then performed on the stack to form an adapter electrode 15 and a gate 11. The adapter electrode 15 is connected to the semiconductor layer 12a through the second via V2 and to the source 13 through the first via V1.

[0102] In S29, a conductive treatment is performed on the semiconductor layer 12a to form an active layer 12. As shown in FIG. 8H, the active layer 12 includes a first conductive portion 121, a second conductive portion 122, and a channel portion 120 located between the first conductive portion 121 and the second conductive portion 122, where the first conductive portion 121 is connected to the adapter electrode 15, and the second conductive portion 122 functions as the drain 14.

[0103] In a second example, the method for manufacturing the thin film transistor 10 further includes S30 after the above steps S20 to S29, in which the gate insulating layer GI is etched, and the etched gate insulating layer GI does not contact the adapter electrode 15, and the orthogonal projection of the gate insulating layer GI onto the substrate 20 may coincide with the orthogonal projection of the gate 11 onto the substrate 20 or may slightly exceed the orthogonal projection of the gate 11 onto the substrate 20.

[0104] FIG. 9A is a conceptual diagram of a manufacturing process of a thin film transistor provided in a third example of the present disclosure. As shown in FIG. 9A, the manufacturing method of the thin film transistor 10 further includes the following steps after the above steps S20 to S24.

[0105] In step S41, the first via V1 and the second via V2 are formed synchronously. Specifically, a resist layer is first formed on the gate insulating layer GI, and then a half-tone mask is used to expose and develop the resist layer, thereby removing the resist in the first region, partially removing the resist in the second region, and retaining the resist in the third region. Here, the first region is the region corresponding to the first via V1, and the second region is the region of the second via V2 excluding the first via V1. The third region is the portion other than the first and second regions. Then, a first etching is performed to form the first via V1. Furthermore, the resist layer is ashed to remove the resist in the second region. Then, a second etching is performed to form the second via V2 penetrating the gate insulating layer GI.

[0106] In step S42, the semiconductor layer is subjected to a conductive treatment using the resist layer as a mask, thereby converting the portion of the semiconductor layer exposed in the second via V2 into a conductive material.

[0107] In S43, a MoNB / Cu stack, or an MTD / Cu stack, or an MoNB / Cu / MTD stack is formed to a thickness of 200 to 1200 nm, and a patterning process is performed on the stack to form an adapter electrode 15 and a gate 11. The adapter electrode 15 is connected to the semiconductor layer through a second via V2 and to the source 13 through a first via V1.

[0108] S44: Conductive treatment is performed on the semiconductor layer to form an active layer 12 including a first conductive portion 121, a second conductive portion 122, and a channel portion 120 located between the first and second conductive portions, where the first conductive portion 121 is the portion connected to the adapter electrode 15, and the second conductive portion 122 functions as the drain 14.

[0109] FIG. 9B is a conceptual diagram of a method for forming a second via on a gate insulating layer in step S41 in FIG. 9A. As shown in FIG. 9B, step S41 may include steps S411 to S414, which are specifically as follows:

[0110] In step S411, a resist layer is formed on the gate insulating layer GI, and then the resist layer is exposed and developed using a half-tone mask to remove the resist in the first region a1, partially remove the resist in the second region a2, and retain the resist in the third region a3. Here, the first region a1 is the region corresponding to the first via V1, the second region a2 is the region where the second via V2 is located but excluding the first via V1, and the third region a3 is the portion other than the first region a1 and the second region a2.

[0111] S412: A first etching is performed to form a first via V1.

[0112] S413: ashing the resist layer to remove the resist in the second region.

[0113] S414: A second etching is performed to form a second via V2 penetrating the gate insulating layer GI.

[0114] FIG. 10 is a conceptual diagram of a method for manufacturing a thin film transistor provided in a fourth example of the present disclosure. As shown in FIG. 10, the method for manufacturing a thin film transistor 10 includes the above steps S20 to S24, and then further includes the following steps.

[0115] In step S51, the first via V1 and the second via V2 are formed synchronously. For details, refer to the description of step S41 above, and no further description will be given here.

[0116] In step S52, the semiconductor layer is subjected to a conductive treatment using the resist layer as a mask, thereby making the portion of the semiconductor layer exposed by the second via V2 conductive.

[0117] In step S53, a MoNB / Cu stack, or an MTD / Cu stack, or an MoNB / Cu / MTD stack, having a thickness of 200 to 1200 nm is formed. A patterning process is performed on the stack to form an adapter electrode 15 and a gate 11. The adapter electrode 15 is connected to the semiconductor layer 12a through a second via V2 and to the source 13 through a first via V1.

[0118] S54: Conductive treatment is performed on the semiconductor layer 12a to form an active layer 12 including a first conductive portion 121, a second conductive portion 122, and a channel portion 120 located between the first and second conductive portions, where the first conductive portion 121 is the portion connected to the adapter electrode 15, and the second conductive portion 122 functions as the drain 14.

[0119] S55: Etching the gate insulating layer GI, where the gate insulating layer GI after etching does not contact the adapter electrode 15, and the orthogonal projection of the gate insulating layer GI onto the substrate 20 may coincide with the orthogonal projection of the gate 11 onto the substrate 20, or may slightly exceed the orthogonal projection of the gate 11 onto the substrate 20.

[0120] FIG. 11 is a conceptual diagram of a manufacturing process of a thin film transistor provided in a fifth example of the present disclosure. As shown in FIG. 11, the manufacturing method of the thin film transistor 10 includes the above steps S20 to S24, and then further includes the following steps.

[0121] In step S61, a position of the gate insulating layer GI corresponding to the source 13 is etched to form a second via V2 penetrating the gate insulating layer GI, and then etching is continued to form a first via V1 penetrating the semiconductor layer 12a and the buffer layer BFL at the position of the second via V2. Because the etching rates of the semiconductor layer 12a and the gate insulating layer GI are different, the hole diameter of the first via V1 formed by etching is smaller than the hole diameter of the second via V2. A portion of the semiconductor layer 12a is exposed by the second via V2.

[0122] In step S62, the mask plate used in forming the first via V1 and the second via V2 is used as a mask to conduct the portion of the semiconductor layer 12a exposed by the second via V2.

[0123] In S63, a MoNB / Cu stack, or an MTD / Cu stack, or an MoNB / Cu / MTD stack is formed to a thickness of 200 to 1200 nm. A patterning process is performed on the stack to form an adapter electrode 15 and a gate 11. The adapter electrode 15 is connected to the semiconductor layer through a second via V2 and to the source 13 through a first via V1.

[0124] S64: Conductive treatment is performed on the semiconductor layer to form an active layer 12 including a first conductive portion 121, a second conductive portion 122, and a channel portion 120 located between the first and second conductive portions, where the first conductive portion 121 is the portion connected to the adapter electrode 15, and the second conductive portion 122 functions as the drain 14.

[0125] FIG. 12 is a conceptual diagram of a manufacturing process of a thin film transistor provided in the sixth example of the present disclosure. As shown in FIG. 12, the manufacturing method of the thin film transistor 10 includes the above steps S20 to S24 and S61 to S63, and then further includes the following steps:

[0126] S71: Conductive treatment is performed on the semiconductor layer to form an active layer 12 including a first conductive portion 121, a second conductive portion 122, and a channel portion 120 located between the first and second conductive portions, and the first conductive portion 121 is the portion connected to the adapter electrode 15, and the second conductive portion 122 functions as the drain 14.

[0127] S72: Etching the gate insulating layer GI, where the gate insulating layer GI after etching does not contact the adapter electrode 15, and the orthogonal projection of the gate insulating layer GI onto the substrate 20 may coincide with the orthogonal projection of the gate 11 onto the substrate 20, or may slightly exceed the orthogonal projection of the gate 11 onto the substrate 20.

[0128] FIG. 13 is a conceptual diagram of a method for manufacturing a thin film transistor provided in a seventh example of the present disclosure. As shown in FIG. 13, the method for manufacturing a thin film transistor 10 includes the above steps S20 to S22, and then further includes the following steps.

[0129] S81: Etching is performed on the buffer layer BFL to form a first sub-via.

[0130] S82, forming a semiconductor layer 12a having a second sub-via, the semiconductor layer 12a can be formed by adopting a sputtering method, its material can be IGZO, and its thickness is between 10 and 80 nm.

[0131] S83: Form a gate insulating layer GI (see step S24 above, which will not be described further here). Then, etch the gate insulating layer GI to form a second via V2 penetrating the gate insulating layer GI. The second via V2 includes a third sub-via overlapping the first sub-via, and the third sub-via communicates with the second sub-via and the first sub-via to form a first via V1.

[0132] In S84, a MoNB / Cu stack, or an MTD / Cu stack, or an MoNB / Cu / MTD stack is formed to a thickness of 200 to 1200 nm. A patterning process is performed on the stack to form an adapter electrode 15 and a gate 11. The adapter electrode 15 is connected to the semiconductor layer through a second via V2 and to the source 13 through a first via V1.

[0133] In S85, a conductive treatment is performed on the semiconductor layer 12a to form an active layer 12 including a first conductive portion 121, a second conductive portion 122, and a channel portion 120 located between the first and second conductive portions, and the first conductive portion 121 is the portion connected to the adapter electrode 15, and the second conductive portion 122 functions as the drain 14.

[0134] The above-described embodiments are merely exemplary embodiments adopted to explain the principles of the present disclosure, and the present disclosure is not limited thereto. It is obvious that those skilled in the art can make modifications and improvements to the embodiments without departing from the spirit and gist of the present disclosure, and such modifications and improvements are also included in the scope of protection of the present disclosure.

Claims

1. a gate, an active layer, a source, and a drain provided on a substrate, the active layer being located on a side of the source away from the substrate, the gate being located on a side of the active layer away from the substrate, and the source and the drain being all connected to the active layer; a buffer layer disposed between the active layer and the layer in which the source is located; a gate insulating layer disposed between the active layer and the layer including the gate, the gate insulating layer having an openwork portion; an adapter electrode located on a side of the active layer away from the substrate, a portion of which is electrically connected to the active layer through the openwork portion, and another portion of which is electrically connected to the source through a first via that penetrates at least the active layer and the buffer layer, and whose orthogonal projection on the substrate overlaps with that of the openwork portion on the substrate; Thin film transistor.

2. the openwork portion is a second via that penetrates the gate insulating layer, an orthogonal projection of the first via onto the substrate is a first projection, and an orthogonal projection of the second via onto the substrate is a second projection; The first projection is located within the range of the second projection, or a portion of the second projection is located within the range of the first projection and another portion is located outside the range of the first projection. The thin film transistor of claim 1 .

3. an orthogonal projection of the adapter electrode onto the substrate overlaying the second projection; The thin film transistor according to claim 2 .

4. The adapter electrode is disposed in the same layer as the gate. The thin film transistor according to any one of claims 1 to 3.

5. the adapter electrode and the gate are arranged along a first direction; a distance between the adapter electrode and the gate in the first direction of 1 μm to 3 μm; The thin film transistor according to claim 4 .

6. the thin film transistor further includes a light shield located between the active layer and the substrate, the orthogonal projection of the light shield onto the substrate at least partially overlapping with the orthogonal projection of the active layer onto the substrate; The thin film transistor according to any one of claims 1 to 5.

7. the openwork portion is a second via that penetrates the gate insulating layer; an orthogonal projection of the light blocking body onto the substrate and an orthogonal projection of the second via onto the substrate partially overlap; The thin film transistor according to claim 6 .

8. an orthogonal projection of the light shield onto the substrate and an orthogonal projection of the adapter electrode onto the substrate partially overlap; 8. The thin film transistor according to claim 6 or 7.

9. The light shielding body is disposed in the same layer as the source. The thin film transistor according to any one of claims 6 to 8.

10. the light shield and the source are arranged along a first direction; a distance between the light shield and the source in the first direction of 1 μm to 3 μm; The thin film transistor of claim 9 .

11. the active layer includes a first conductive portion, a second conductive portion, and a channel portion located therebetween, the first via penetrates the first conductive portion, and the second conductive portion functions as the drain. The thin film transistor according to any one of claims 1 to 10.

12. the channel portion and the second conductive portion are arranged along a first direction, and the first conductive portion is striped and extends along the first direction; The thin film transistor of claim 11.

13. a pitch in the first direction of both an orthogonal projection onto the substrate of a portion where the first conductive portion and the adapter electrode contact each other and an orthogonal projection onto the substrate of the channel portion is 1 μm to 4 μm; 13. The thin film transistor according to claim 11 or 12.

14. a portion of the adapter electrode connected to the active layer through the openwork portion and a portion of the adapter electrode connected to the source through a first via are both arranged along a first direction; The thin film transistor according to any one of claims 11 to 13.

15. the diameter of the first via near the end of the substrate is less than 2 μm; the buffer section has a first portion covered with the active layer and a second portion not in contact with the active layer, the first portion having a first slope facing the first via, the second portion having a second slope facing the first via, the gradient of the first slope being between 70 and 90 degrees, and the gradient of the second slope being 60 degrees or less; The thin film transistor according to any one of claims 1 to 14.

16. an orthogonal projection of a bottom of the first via onto the substrate is located within an area covered by an orthogonal projection of the source onto the substrate; a difference between a length of the source in the first direction and a length of a bottom of the first via in the first direction is 0.5 μm or more; The thin film transistor according to any one of claims 1 to 15.

17. a protrusion is formed on the buffer layer at a portion covering the source on a side of the active layer that is close to a channel portion; The thin film transistor according to any one of claims 1 to 16.

18. The thickness of the protrusion in a direction perpendicular to the substrate is 1000 μm to 20000 μm.

18. The thin film transistor of claim 17.

19. The surface of the protrusion facing away from the substrate is an arcuate surface, and the arcuate surface has an angle of 15° to 90°.

19. The thin film transistor according to claim 17 or 18.

20. a portion of the adapter electrode located within the first via is a third portion; a surface of the third portion facing away from the substrate is a convex surface that is convex outward toward the side facing away from the substrate; The thin film transistor according to any one of claims 1 to 19.

21. a difference between a maximum thickness and a minimum thickness of the third portion in a direction perpendicular to the substrate is 0.3 μm to 0.6 μm; 21. The thin film transistor of claim 20.

22. the openwork portion is a second via that penetrates the gate insulating layer; a difference between a gradient of a slope on the gate insulating layer toward the second via and a gradient of a slope on the same side on the active layer toward the first via is 0° or more and 30° or less; The thin film transistor according to any one of claims 1 to 21.

23. the material of the active layer comprises a metal oxide material; The thin film transistor according to any one of claims 1 to 15.

24. A thin film transistor according to any one of claims 1 to 23, Display board.

25. a plurality of gate lines extending along a first direction and a plurality of data lines extending along a second direction, the plurality of gate lines and the plurality of data lines intersecting each other to define a plurality of pixel regions, the thin film transistors being located in the pixel regions; The gate of the thin film transistor is connected to the corresponding gate line, and the source of the thin film transistor is connected to the corresponding data line; an orthogonal projection of the light shielding body onto the substrate does not overlap with an orthogonal projection of the gate lines onto the substrate; The display substrate according to claim 24.

26. 26. A display substrate comprising the display substrate of claim 24 or 25. Display device.

27. forming a source, a buffer layer, an active layer, a drain, and a gate insulating layer on a substrate, the drain being connected to the active layer, the gate insulating layer being located on a side of the active layer away from the substrate, and the gate insulating layer having an openwork portion; forming an adapter electrode on a side of the active layer away from the substrate, the adapter electrode having a portion electrically connected to the active layer through the openwork portion and another portion electrically connected to the source through a first via that penetrates at least the active layer and the buffer layer and whose orthogonal projection on the substrate overlaps with that of the openwork portion on the substrate; forming a gate on a side of the gate insulating layer away from the substrate; The method for manufacturing a thin film transistor according to any one of claims 1 to 23.

28. The step of forming the gate insulating layer includes: forming a gate insulating material layer; performing a patterning process on the gate insulating material layer to form the gate insulating layer with an openwork portion, the openwork portion being a second via penetrating the gate insulating layer, wherein an orthogonal projection of the first via onto the substrate is a first projection and an orthogonal projection of the second via onto the substrate is a second projection; and positioning the first projection within the range of the second projection, or positioning a portion of the second projection within the range of the first projection and another portion outside the range of the first projection. The method for manufacturing a thin film transistor according to claim 27.

29. the active layer includes a first processing-awaiting portion, a second processing-awaiting portion, and a channel portion located therebetween, a portion of the first processing-awaiting portion being exposed to the second via; The manufacturing method includes: Conducting a portion of the first processing-waiting portion exposed by the second via; and further comprising a step of connecting the first processing waiting unit and the second processing waiting unit to a conductive unit, and using the conductive second processing waiting unit as the drain.

29. The method for manufacturing a thin film transistor according to claim 28.

30. further comprising forming a light shield formed synchronously with the source; The method for manufacturing a thin film transistor according to claim 27.

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