Heterostructures, devices and methods for forming heterostructures

Abstract

A method for forming a heterostructure is provided. A method for forming a heterostructure includes providing a substrate, forming a template layer of the heterostructure such that the template layer is supported by the substrate, and performing a non-sputter epitaxial growth procedure to form a polar semiconductor layer of the heterostructure. The polar semiconductor layer is supported by and in contact with the template layer. The non-sputter epitaxial growth procedure is configured so that the polar semiconductor layer is single crystalline. The non-sputter epitaxial growth procedure is performed at a growth temperature of less than about 400 degrees Celsius.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of U.S. Provisional Application No. 63 / 418,951, filed October 24, 2020, entitled "Low Temperature Epitaxy of Polar Semiconductors," the entire disclosure of which is expressly incorporated herein by reference. [Technical Field]

[0002] The present invention relates generally to epitaxial growth of semiconductors. [Background technology]

[0003] Due to their widely tunable direct band gap, high electron mobility, large breakdown field, strong piezoelectric and spontaneous polarization, and large exciton binding energy, III-nitride semiconductors, such as InN, GaN, and AlN, and their heterostructures, nanostructures, and alloys with IIIB elements such as Sc, have attracted increasing interest and fostered a wealth of applications in optoelectronics, electronics, acoustics, green energy, and quantum devices and systems. Furthermore, as nitride-based devices surpass discrete devices, there is growing interest in integrating nitride devices and circuits with state-of-the-art silicon complementary metal-oxide-semiconductor (CMOS) technology or even all-nitride CMOS technology to reduce latency and cost and enable increased multifunctionality in hybrid integrated circuits. All of these pose significant challenges to conventional epitaxial growth of III-nitride semiconductors.

[0004] To date, molecular beam epitaxy (MBE) and metalorganic chemical vapor deposition (MOCVD) have dominated the epitaxial growth of III-nitride semiconductors, demonstrating the ability to produce high-quality III-nitrides with precise doping, composition, and thickness control. To produce high-quality materials with smooth surfaces and interfaces, the universal adsorption-transfer-epitaxy thermodynamic process is used at the growth front in both methods, during which the substrate temperature and elemental ratio, i.e., the III / V ratio, are adjusted to ensure sufficient adatom migration during growth. In this regard, the growth temperatures of III-nitrides in both methods have been limited to above 400°C, e.g., approximately 500°C for InN, approximately 800°C for GaN, and approximately 1000°C for AlN. However, these high growth temperatures are not CMOS-compatible, preventing the seamless integration of III-nitride materials and devices with advanced processing techniques and mainstream semiconductor technologies such as CMOS. Other growth techniques such as atomic layer deposition, sputtering, and pulsed laser deposition generally result in polycrystalline materials of very limited quality, or even amorphous materials. Summary of the Invention

[0005] According to one aspect of the present disclosure, a method for forming a heterostructure includes providing a substrate, forming a template layer of the heterostructure such that the template layer is supported by the substrate, and performing a non-sputter epitaxial growth procedure to form a polar semiconductor layer of the heterostructure. The polar semiconductor layer is supported by and in contact with the template layer. The non-sputter epitaxial growth procedure is configured so that the polar semiconductor layer is single crystalline. The non-sputter epitaxial growth procedure is performed at a growth temperature of less than about 400 degrees Celsius.

[0006] According to another aspect of the present disclosure, a method of fabricating a device includes forming a metal structure of a complementary metal oxide semiconductor (CMOS) component of the device, the metal structure being supported by a substrate, and, after forming the metal structure, performing a non-sputter epitaxial growth procedure to form a polar semiconductor layer of a heterostructure of the device, the polar semiconductor layer being supported by the substrate, The non-sputter epitaxial growth procedure is configured so that the polar semiconductor layer is single crystalline.

[0007] In yet another aspect of the present disclosure, a heterostructure includes a substrate and a polar semiconductor layer supported by the substrate, the polar semiconductor layer having a single-crystalline wurtzite crystal structure, and the polar semiconductor layer includes a plurality of columnar domains.

[0008] In yet another aspect of the present disclosure, a device includes a substrate and a complementary metal-oxide semiconductor (CMOS) component supported by the substrate, the CMOS transistor including a structure and a polar semiconductor layer supported by the structure, the polar semiconductor layer having a single-crystalline wurtzite crystal structure.

[0009] According to yet another aspect of the present disclosure, a method for forming a heterostructure includes providing a substrate, forming a metal layer of the heterostructure such that the metal layer is supported by the substrate and includes aluminum, and performing a non-sputter epitaxial growth procedure to form a polar semiconductor layer of the heterostructure. The polar semiconductor layer is supported by and in contact with the metal layer. The non-sputter epitaxial growth procedure is configured so that the polar semiconductor layer is single crystalline. The steps of forming the metal layer and performing the non-sputter epitaxial growth procedure are performed in the same chamber, thereby preventing the heterostructure from being exposed to the environment between the steps of forming the metal layer and performing the non-sputter epitaxial growth procedure.

[0010] According to yet another aspect of the present disclosure, a method for forming a heterostructure includes providing a substrate, forming a metal layer of the heterostructure such that the metal layer is supported by the substrate and includes molybdenum, and performing a non-sputter epitaxial growth procedure to form a polar semiconductor layer of the heterostructure. The polar semiconductor layer is supported by and in contact with the metal layer. The non-sputter epitaxial growth procedure is configured so that the polar semiconductor layer is single crystalline. The steps of forming the metal layer and performing the non-sputter epitaxial growth procedure are performed in the same chamber so that the heterostructure is not exposed to the environment between the steps of forming the metal layer and performing the non-sputter epitaxial growth procedure.

[0011] In relation to any one of the aforementioned aspects, the devices and / or methods described herein may alternatively or additionally include or involve any combination of one or more of the following aspects or features: The non-sputtered epitaxial growth procedure is performed under nitrogen-rich conditions; Forming the template layer and performing the non-sputtered epitaxial growth procedure are performed in the same chamber such that the heterostructure is not exposed to the ambient between forming the template layer and performing the non-sputtered epitaxial growth procedure; Forming the template layer includes performing a surface treatment procedure to remove oxide from the surface of the template layer; The growth temperature is less than about 300°C; The growth temperature is greater than about 20°C; The growth temperature is on the order of 20°C to 100°C.

[0012] The polar semiconductor layer comprises a III-nitride material or an alloy thereof. The polar semiconductor layer comprises AlN or an alloy thereof. The template layer comprises a metal compatible with complementary metal oxide semiconductor (CMOS) fabrication. The template layer comprises GaN. The polar semiconductor layer comprises AlN or an alloy thereof. The non-sputter epitaxial growth procedure is performed at a growth temperature below 400°C. The non-sputter epitaxial growth procedure is performed under nitrogen-rich conditions. The non-sputter epitaxial growth procedure is configured such that the polar semiconductor layer is in contact with the metal structure. The steps of forming the metal structure and performing the non-sputter epitaxial growth procedure are performed in the same chamber such that the heterostructure is not exposed to the ambient between the steps of forming the metal structure and performing the non-sputter epitaxial growth procedure. Forming the metal structure includes performing a surface treatment procedure to remove oxides from the surface of the metal structure. The method further includes forming a heterostructure template layer before performing the non-sputter epitaxial growth procedure, such that the polar semiconductor layer contacts the template layer. The structure includes a metal. The polar semiconductor layer includes a plurality of columnar domains. The surface of the polar semiconductor layer in contact with the structure has an atomically smooth surface. The non-sputter epitaxial growth procedure is configured to be performed at a growth temperature that is compatible with complementary metal-oxide semiconductor (CMOS) fabrication.

[0013] For a more complete understanding of the present disclosure, reference should be made to the following detailed description and the accompanying drawings, in which like reference numerals identify like elements throughout the drawings. [Brief explanation of the drawings]

[0014] [Figure 1]1A and 1B show low-temperature epitaxy of ScAlN on a GaN template. (a) is a schematic diagram of a heterostructure having a III-nitride-based layer (e.g., an ScAlN film) grown on a GaN template according to an example; (b) is an SEM image of the example heterostructure; (c) is a graphical plot of the XRDX 2θ-ω scan of the (002) plane of the example heterostructure; and (d) is a graphical plot of the XRC·FWHM of the (0002) and (101*2) planes of a ScAlN film grown on a GaN template. The "1*" represents a bar 1 with a horizontal line over it. [Figure 2] Figure 1 shows microstructural analysis of ScAlN films grown at different temperatures on GaN templates. (a) HAADF-STEM image of the ScAlN / GaN interface of an example of ScAlN grown at 700 °C. (b) ABF-STEM image of the ScAlN region of an example of ScAlN grown at 700 °C. (c) HAADF-STEM image of the ScAlN / GaN interface of an example of ScAlN grown at 100 °C. (d) ABF-STEM image of the ScAlN region of an example of ScAlN grown at 100 °C. Shaded balls for the Sc / Al and N atoms are embedded in parts b and d to better visualize the atomic stacking sequence. [Figure 3] 1A and 1B show low-temperature epitaxy of heterostructures having ScAlN films on Al / Si templates (e.g., Al templates combined with Si substrates) according to an example, where (a) is a schematic diagram of the example heterostructure, (b) is an SEM image of the example heterostructure, and (c, d) are graphical plots of XRD 2θ-ω scans of the (0002) plane of example heterostructures having ScAlN grown on Al / Si templates with various Sc contents and various film thicknesses. [Figure 4]Figure 1 shows microstructural analysis of an exemplary heterostructure with a ScAlN layer grown at 100 °C on an Al / Si template. (a) is a cross-sectional HAADF-STEM image of the ScAlN / Al / Si heterostructure; (b, c) are HAADF-STEM images of the Al / Si and ScAlN / Al interfaces; and (d) is an ABF-STEM image acquired from the ScAlN region. Shaded balls are embedded in part (d) for the Sc / Al and N atoms to better visualize the atomic stacking sequence. [Figure 5] Figure 1 shows low-temperature epitaxy of an exemplary heterostructure with an AlN layer on an Al / Si template. (a) is an AFM image (RMS=0.69 nm), (b) is a graphical plot of the XRD 2θ-ω scan of AlN grown on the Al / Si template at 100 °C, and (c) is a HAAD-STEM (left) and ABF-STEM (right) image of AlN grown on the Al / Si template at 100 °C. Shaded balls for the Al and N atoms are embedded in the ABF-STEM image to better visualize the atomic stacking sequence. [Figure 6] 1 is a flow diagram of a method for fabricating a device having a heterostructure with a polar semiconductor layer grown at low temperature, according to an example. [Figure 7] 1A-1C show exemplary heterostructures with III-nitride-based layers grown via low-temperature epitaxy: (a) is a schematic diagram of an AlGaN / AlN bilayer heterostructure grown on an Al / Si template; (b) is a schematic diagram of an ScAlN / AlN bilayer heterostructure grown on a Mo / Si template; and (c) is a schematic diagram of an AlN / ScAlN / AlN trilayer heterostructure grown on a Mo / Si template; (d-f) are corresponding SEM images of the surface morphology of the multilayer heterostructure shown in section (a-c) grown at 100° C. [Figure 8] Examples of (a) Ga-polar and (b) N-polar Al(Ga,In)N / GaN HEMTs using low-temperature in situ epitaxially grown AlN as a high-k gate dielectric layer are shown. [Figure 9]Figure 1 shows exemplary transistor structures using low-temperature grown polar semiconductor Al(Sc)N as the dielectric layer and 2D material as the channel: (a) global (back) gate structure and (b) local (top) gate structure. [Figure 10] FIG. 1 illustrates an exemplary low-temperature grown AlN transistor. [Figure 11] FIG. 1 shows an exemplary high-power Al(Ga)N p-in diode, where the p- and n-Al(Ga) layers can be grown under low or high temperature, while the i-Al(Ga)N layer is grown at low temperature, and the low-temperature i-Al(Ga)N layer results in an improved breakdown voltage of the diode. [Figure 12] FIG. 1 illustrates an exemplary high-power Al(Ga)N Schottky diode, where the n-Al(Ga)N layer is grown at low temperature, while the n-Al(Ga) layer can be grown under low or high temperature, with the low-temperature n-Al(Ga)N layer resulting in an improved breakdown voltage of the diode. [Figure 13] FIG. 1 illustrates an exemplary high-power Al(Ga)N bipolar transistor in which n- and p-Al(Ga) layers can be grown at low temperatures, resulting in improved breakdown voltage of the transistor. [Figure 14] FIG. 1 illustrates a ferroelectric transistor random access memory cell having a metal low-temperature grown ferroelectric ScAlN-metal capacitor and a silicon or GaN based write-read transistor, according to an example. [Figure 15] 1A and 1B show exemplary deep-ultraviolet LED structures based on low-temperature epitaxially grown semiconductor heterostructures: (a) a conventional Al(Ga)N-based DUV-LED structure grown on a low-temperature grown Al(Ga)N buffer; and (b) a low-temperature grown Al(Ga)-based DUV-LED structure, which may be useful in connection with some substrates or applications. [Figure 16] FIG. 1 illustrates an exemplary self-powered photodetector that uses low-temperature epitaxially grown polar semiconductor Al(Ga,In,Sc)N as a light-absorbing layer. [Figure 17]Figure 1 shows three examples of thin-film acoustic wave resonator structures using low-temperature grown polar semiconductor Al(Sc)N as the piezoelectric layer: (a) bulk resonator, (b) free-standing resonator based on surface micromachining, and (c) free-standing resonator based on bulk micromachining. DETAILED DESCRIPTION OF THE INVENTION

[0015] Embodiments of the disclosed devices and methods may assume a variety of forms. Specific embodiments are shown in the drawings and described below, with the understanding that the disclosure is intended to be illustrative. The disclosure is not intended to limit the invention to the specific embodiments described and illustrated herein.

[0016] Fabrication methods are described that include low-temperature epitaxy. In some cases, epitaxy may be performed at ultra-low temperatures. Devices fabricated by the disclosed methods are also described. As described herein, the disclosed methods can be useful for fabricating devices with highly reactive III-nitride or other polar semiconductor layers.

[0017] The disclosed method involves low-temperature epitaxial growth (e.g., growth at CMOS-compatible temperatures, such as below 400°C) of single-crystalline III-nitride semiconductor layers. While there has been some previous work using sputtering, these are not single-crystalline and are not epitaxially grown. In some cases, III-nitride semiconductor layers or other polar semiconductor layers are grown on a metal template and / or substrate, such as Al. The growth / epitaxy of the III-nitride semiconductor layer and the metal can be performed in the same reaction chamber, which can avoid the formation of surface oxides and the incorporation of interface impurities. An additional metal layer can be deposited on the III-nitride semiconductor layer to form, for example, a top electrode.

[0018] The low-temperature growth of III-nitrides of the disclosed method may be used to fabricate a wide range of devices, including, for example, transistors, memory, acoustic resonators / filters, and MEMS devices. For example, devices may include multilayer structures having stacks of metal / III-nitride layers, AlN / ScAlN layers, and / or other layer combinations. In some cases, the multilayer structures may include AlN / ScAlN stacks with opposite polarities. Ferroelectric layers or materials may also be epitaxially grown directly on metal substrates at low temperatures.

[0019] Although described with reference to an MBE-based example, other epitaxial growth processes can be used, including, for example, MOCVD, atomic layer epitaxy, and pulsed laser deposition.

[0020] Although described herein with reference to III-nitride-based examples (e.g., Al-based examples), other polar semiconductors may be used and / or formed via the low-temperature epitaxy techniques described herein, including, for example, ZnO, Ga2O3, GaAs, and BaTiO3. Thus, the disclosed methods and devices are not limited to III-nitrides and their alloys (e.g., AlN and ScAlN).

[0021] The disclosed method and device utilize a previously unexplored growth regime for achieving crystalline nitride semiconductors, with growth temperatures below 400 °C, making them CMOS-compatible. This low-temperature growth has several potential advantages: i) it frees up constraints on processing conditions before and after film deposition, providing better compatibility with different material platforms and semiconductor technologies, such as silicon CMOS technology; ii) in high-temperature growth regimes, adatom migration leads to a "jump-over" effect near surface defects such as nanogaps / dots, whereas low-temperature growth provides better surface coverage, rapid coalescence, and uniform thickness; iii) the nucleation process is easier at low temperatures, favoring heteroepitaxy of III-nitride semiconductors on dissimilar materials, such as metal substrates; iv) following ii) and iii) above, this type of "on-site" growth enabled by low temperatures is not affected by surface thermodynamics and can therefore be performed over a very wide growth window, i.e., a wide temperature and II / V ratio window. v) Low-temperature growth tends to produce multi-domain films, potentially blocking the dislocation threading that is unavoidable during high-temperature growth, which is useful for improving the fracture strength of the material. However, compared to conventional high-temperature growth, low-temperature growth tends to result in insufficient adatom mobility and lower-quality material. In principle, this can be largely addressed by using high-quality substrates or templates and optimal growth rates.

[0022] Examples of low-temperature, CMOS-compatible epitaxy of polar nitride semiconductors are described. The epitaxial growth of single-crystalline wurtzite-phase ScAlN, AlN, and AlGaN with high crystalline quality and atomically sharp interfaces has been demonstrated over a wide growth temperature range (approximately 700 to approximately 20 °C), which was previously unattainable. To explain the epitaxy of crystalline materials at such low growth temperatures, an on-site growth mechanism is presented, which is explained by a polar surface-controlled adsorption-epitaxy process, compared to the conventional adsorption-transfer-epitaxy process for epitaxy at high temperatures. Furthermore, the epitaxial growth of wurtzite-phase ScAlN with various Sc contents and film thicknesses, as well as AlN on CMOS-compatible aluminum metal electrodes, was achieved using the proposed low-temperature on-site growth method. Such a significant expansion of the growth window for polar III-nitrides enables the full epitaxial integration of nitride architectures with various other semiconductor platforms and technologies.

[0023] Using ScAlN and AlN as examples, the disclosed method and device establish that low-temperature growth of III-nitride semiconductors can maintain the wurtzite crystal structure and provide reasonable crystal quality, interface, and chemical composition control comparable to conventional high-temperature growth, but with better compatibility with different substrates and processing techniques. ScAlN thin films and AlN films with various thicknesses and Sc contents were grown at low temperatures (below 100°C) on GaN and metal substrates. The ScAlN films exhibit excellent wurtzite atomic stacking order with sharp interfaces and atomically smooth surfaces on both GaN and metal (Al, Mo) substrates. These results pave the way for growing high-quality III-nitride semiconductors at low temperatures for advanced hybrid and emerging integrated circuits across different technology and material platforms.

[0024] The examples described herein were grown using a Veeco GENxplor MBE system equipped with a dual-filament SUMO Knudsen cell for the Al source (6N5 purity) and Ga source (7N purity), a high-temperature Knudsen cell for the Sc source (5N purity), and a Veeco Unibulb radio frequency (RF) plasma source. The N source was operated with a N gas (6N purity) flow rate of 0.35 sccm and an RF power of 350 W. Meanwhile, the total metal flux was controlled to maintain N-rich growth conditions with an III / V ratio of approximately 0.8. The GaN template and Si substrate were cleaned with acetone, methanol, and deionized water before loading into the MBE system. They were then degassed for 2 h at 200 °C and 600 °C in the MBE load-lock chamber and preparation chamber, respectively.

[0025] Examples include low-temperature epitaxy of ScAlN on GaN As shown in part a of Figure 1, ScAlN films with Sc content of about 18% were grown on GaN templates. As described herein, the GaN templates can comprise layers or structures of CMOS components of devices. In this set of examples, 100 nm thick Si-doped GaN films were grown on GaN templates. + GaN was first grown on a GaN template to obtain an atomically smooth and clean surface. The excess Ga adatoms on the surface were then re-evaporated, followed by in-situ surface nitridation to obtain a Ga-free surface. Subsequently, 100-nm-thick ScAlN films were grown at varying growth temperatures. The growth temperature ranged from a commonly used high temperature (700 °C) to an unexplored low temperature (20 °C). Part b of Figure 1 shows a typical scanning electron microscope image of an ScAlN / GaN film grown at 100 °C, revealing a granular surface, consistent with previous reports on ScAlN grown under N-rich conditions. Meanwhile, the surface morphology was found to be insensitive to the growth temperature. All examples showed similar granular surfaces, although the grain size was slightly larger at higher growth temperatures.

[0026] Part c of Figure 1 shows XRD 2θ-ω scans of the (0002) plane of ScAlN films grown at various temperatures. All examples have a clear, strong, characteristic diffraction peak at 36° for wurtzite ScAlN. Furthermore, in long-range scans (20-100°), no other peaks originating from either the cubic phase or misoriented structures are observed, indicating the single-crystalline wurtzite crystal structure of these ScAlN films. To the applicant's knowledge, this is the first demonstration of epitaxial growth of single-crystalline wurtzite nitride semiconductors at such unexplored low growth temperatures (even lower than room temperature). For comparison, previous reports have always shown polycrystalline structures when growing AlN at room temperature.

[0027] The evolution of crystalline quality with growth temperature has been characterized using XRD rocking curves (XRC). As shown in part d of Figure 1, the (0002) and (101 * 2) The full width at half maximum XRC of both planes gradually increases with decreasing growth temperature. * " indicates a "1 superscript horizontal line." The FWHM of the (0002) XRC of ScAlN grown at 20°C (330 arcsec) increased by only 22% compared to ScAlN grown at 700°C (270 arcsec). However, after lowering the growth temperature to 20°C, the (101 * 2) The FWHM of the face XRC increased by 137%, indicating an increase in edge dislocation density with decreasing growth temperature. Overall, lower growth temperatures do not significantly degrade the crystal quality.

[0028] The crystalline structure of the examples was further characterized using high-angle annular dark-field (HAADF) and annular bright-field (ABF) scanning transmission electron microscopy (STEM). Parts a and c of Figure 2 show HAADF-STEM images acquired from the ScAlN / GaN interface where the ScAlN epilayers were grown at 700°C and 100°C, respectively. Atomically smooth, clean, and sharp ScAlN / GaN interfaces were observed for both ScAlN films. The wurtzite atomic stacking order (ABAB) was well maintained along the growth direction, and no clear intercalation or non-intercalation planes were observed.

[0029] Furthermore, we confirmed the lattice polarity using ABF-STEM, as shown in parts b and d of Figure 2. In the ABF-STEM image, the darkest contrast corresponds to the heaviest atoms. Therefore, the process can be explained by the atomic stacking sequence of Sc / Al and N atoms embedded in parts b and d of Figure 2. Comparing the atomic model of the wurtzite crystal structure with the experimental results, we can easily confirm that the initial metal (M) polarity lattice of the GaN template was completely inherited by the ScAlN films, i.e., the ScAlN films grown at 700 °C and 100 °C have an M-polarity lattice. Due to the N-rich growth conditions and low growth temperature, the ScAlN exhibits columnar-like growth with slightly misoriented domains (less than 1°). However, no inverted domains with nitrogen (N) polarity were observed in the ScAlN films, suggesting that all films have a highly uniform M-polarity lattice. This is in contrast to polycrystalline or mixed-phase materials deposited by sputtering in the same temperature range.

[0030] Polar surface controlled on-site epitaxy Based on the above analysis and examples, we demonstrate that epitaxial growth of nitride alloys containing highly reactive atoms such as Sc and Al is not limited to the conventional narrow growth window, i.e., relatively high growth temperatures. Single-crystalline wurtzite-phase nitrides can also be grown or achieved at low growth temperatures without significant degradation of crystalline quality. These results contrast with earlier reports in which polycrystalline nitrides were often observed when growth temperatures were below 300°C.

[0031] The successful growth of wurtzite nitrides at low temperatures is attributed to a polar surface-controlled on-site epitaxy mechanism or process. Decreasing the growth temperature dramatically suppresses the adatom diffusion capacity and negligible desorption rates. Therefore, the conventional adsorption-transfer-epitaxy process is simplified to an adsorption-epitaxy process. At low growth temperatures, the kinetic energy of impinging atoms can support short-range diffusion of adatoms to neighboring sites with the lowest surface potential energy. However, the long-range diffusion typically observed in conventional high-temperature growth regimes does not occur. The strong polarization of wurtzite nitrides leads to strong electrostatic potential fluctuations on the surface. In addition to the polar lattice-induced surface potential, lattice kinks and vacancy sites can generate additional electrostatic potential fluctuations on the surface. At conventional high growth temperatures, adatoms migrate to the sites with the lowest energy and have enough energy to participate in growth. The diffusion length is generally between hundreds of nanometers and tens of micrometers. At low temperatures, adatoms cannot achieve long-range diffusion due to the continuity of the lattice, but low-potential sites still exist near the atomic landing sites, which are within a short diffusion length. Therefore, as long as adatoms can diffuse to those sites, the wurtzite lattice is maintained and growth can continue. Considering that the diffusion length at low temperatures (nanometer or subnanometer scale) is much shorter than that of conventional high-temperature growth, it can be considered as on-site growth, with negligible surface diffusion.

[0032] Nitride alloys containing highly reactive atoms such as Al and Sc were grown at low temperatures while maintaining the single-crystalline wurtzite phase. This phenomenon suggests that bond strength also contributes to the proposed on-site growth mechanism; that is, greater bond strength favors low-temperature epitaxy. Furthermore, a clean, crystalline surface would be useful for avoiding misoriented nucleation at the start and initiating such growth at low temperatures. This achievement provides a viable path for the fully epitaxial integration of III-nitride architectures in special application scenarios, such as nitrides grown on CMOS-compatible metal electrodes.

[0033] Low-temperature epitaxy of ScAlN on aluminum. Aluminum (Al) is a commonly used metal electrode in CMOS technology. However, Al's relatively low melting point (approximately 660 °C) makes it unable to withstand high-temperature processes. Therefore, epitaxial growth of III-nitrides on Al electrodes has not previously been achievable due to the limitations of the widely used high growth temperatures. To further explore the scalability of the low-temperature epitaxy approach, examples of ScAlN films with various Sc contents and thicknesses were also grown on crystalline Al / Si templates, as shown schematically in part a of Figure 3. As described herein, the Al / Si templates can constitute layers or structures of CMOS components in devices. For example, the Al structures may correspond to electrodes or contacts of CMOS components. In these examples, a 100-nm-thick layer of Al was first deposited on a Si(111) substrate at 100 °C, followed by growth of ScAlN at the same temperature. The surface morphology of ScAlN grown on Al / Si exhibits a granular surface (Figure 3, part b), which is similar to that of ScAlN grown on GaN under the same conditions (Figure 1, part b). XRD 2θ-ω scans of these ScAlN films are shown in part c of Figure 3. The XRD 2θ-ω scans of the Al / Si template show a characteristic diffraction peak at 38.5°, suggesting a cubic structure for the MBE-grown Al film. After ScAlN growth, a characteristic peak of the wurtzite phase was observed at 36°, and long-range scans revealed no other peaks from either the cubic phase or misoriented domains, confirming the single-crystalline wurtzite crystal structure of this ScAlN film. Furthermore, ScAlN films with varying Sc content up to 0.4 were also successfully grown on such Al / Si templates. In the XRD 2θ-ω scans, the diffraction peaks of ScAlN gradually shift to higher angles. This trend is similar to previous reports on ScAlN grown by MBE at high temperatures (700°C). Meanwhile, the effect of film thickness on such low-temperature epitaxy of ScAlN on Al / Si templates was also analyzed. ScAlN films with thicknesses of 30, 100, and 150 nm were grown. 0.3 Al 0.7The N layer was grown on the same Al / Si template. Similar diffraction peaks for the wurtzite phase were clearly observed in these three samples, as shown in part d of Figure 3. Cracks were observed on the ScAlN surface with a thickness of over 200 nm due to the in-plane strain induced by the lattice mismatch between Al and ScAlN.

[0034] The microstructure of ScAlN grown on Al / Si at a low temperature of 100 °C was characterized using HAADF-STEM and ABF-STEM. Figure 4, part a, shows a cross-sectional HAADF-STEM image of 50 nm-thick ScAlN grown on 100 nm-thick Al / Si. A sharp and distinct interface was observed for the ScAlN / Al / Si heterostructure. The ScAlN layer exhibited fluctuations in diffraction contrast, indicating that the ScAlN domains had a columnar structure. Each domain had a diameter of approximately 10 nm, which is consistent with the granular surface morphology (Figure 3, part b). The columnar domain formation is primarily due to the N-rich growth conditions and low growth temperature, which dramatically limit the diffusion length of impinging atoms. Figure 4, part b, shows a HAADF-STEM image of the Al / Si interface, demonstrating the distinct cubic structure of the MBE-grown Al template. The ScAlN / Al interface is shown in Figure 4, part c. A clear lattice transition from cubic Al to wurtzite ScAlN is observed, with the interface thickness being only a few monolayers. The ScAlN layer has a highly ordered wurtzite stacking sequence (ABABAB). The in-plane rotation of the domains is less than 1° during STEM measurements. Based on the atomic stacking order at the interface, the epitaxial relationship in the ScAlN / Al / Si heterostructure is

[0001] (112 * 0) ScAlN ||

[0111] (1 * 10) Al ||

[0111] (1 * 10) SiPart d of Figure 4 shows an ABF-STEM image captured from the ScAlN layer. Sc / Al and N atoms are embedded inside to visualize the atomic stacking arrangement. Comparing with the atomic structure of wurtzite III-nitrides, it is easy to confirm that the ScAlN grown on the Al / Si template has an M-polar lattice. This is in contrast to ScAlN deposited by sputtering, where a similar but lower growth temperature was used, but the ScAlN layer prefers an N-polar lattice. The lack of a buffer layer in a fully epitaxial process may play an important role in maintaining the M-polar lattice.

[0035] Low-temperature epitaxy of ScAlN on molybdenum.

[0036] Epitaxial growth of wurtzite ScAlN at low temperatures can be achieved on molybdenum (Mo) substrates. Mo is not only a desirable metal electrode for CMOS technology, but also a useful bottom electrode for filters and resonators due to its high acoustic velocity. Thus, epitaxially grown ScAlN on Mo offers a viable route to achieving both CMOS-compatible ferroelectric nitrides and a new class of low-loss ultra-high-frequency acoustoelectronic devices.

[0037] Low-temperature epitaxy of AlN and AlGaN. Low-temperature epitaxial growth of AlN and AlGaN films was also analyzed. Due to its ultrawide bandgap, AlN has been widely used as an in-situ surface passivation layer to improve device performance. However, partially amorphous AlN was achieved at growth temperatures below 250 °C. Low-temperature epitaxy of AlN on Al / Si templates was investigated. Part a of Figure 5 shows an atomic force microscope (AFM) image of as-grown AlN on an Al / Si template, measuring 3 × 3 μm. 2The root-mean-square (RMS) roughness of 0.69 nm for the scanned area of ​​100 μm is shown. Even using N-rich growth conditions during the low-temperature growth of AlN, a reasonably atomically smooth surface was achieved, which is even smoother than AlN grown at a higher growth temperature under the same N-rich conditions. This is mainly due to the suppressed diffusion process under the lower growth temperature, thus avoiding the typical three-dimensional (3D) growth induced by surface diffusion at high growth temperatures.

[0038] Part b of Figure 5 shows the long-range XRD 2θ-ω scan of the AlN / Al / Si heterostructure. <0002> Only characteristic diffraction peaks of the α-plane were observed, confirming the single-crystalline wurtzite crystal structure of this AlN film. Part c of Figure 5 shows the HAADF-STEM image and the corresponding ABF-STEM image captured from the near-surface region. The well-ordered wurtzite atomic stacking arrangement (ABABAB) is well maintained all the way to the top surface, indicating that the proposed low-temperature on-site growth mechanism does not degrade the crystal structure. As shown in part c of Figure 5, the stacking arrangements of Al and N atoms are labeled with blue and red balls, respectively, in the ABF-STEM image. Compared with the crystal structure of wurtzite AlN, a uniform M-polarity lattice is confirmed for the as-grown AlN on the Al / Si template. Furthermore, epitaxial growth of AlGaN can be achieved even at low growth temperatures (≤100 °C). Therefore, low-temperature growth of AlN is not limited to metal substrates (Al and Mo). Low-temperature growth can also be achieved on GaN or AlN templates. These results provide low-temperature growth of AlN and AlGaN alloys, which can be used not only as in situ high-quality passivation layers but also for hybrid integration with other material platforms.

[0039] FIG. 6 illustrates a method 600 for fabricating a heterostructure having a monocrystalline polar semiconductor layer grown at low temperature, according to one example. As described herein, method 600 is configured to allow III-nitride based or other polar semiconductor layers to be grown on a metal or other template at low temperatures, e.g., temperatures low enough for compatibility with CMOS fabrication. The polar semiconductor layer may or may not exhibit piezoelectric or ferroelectric behavior. Method 600 can be used to fabricate devices, heterostructures, and other structures having polar semiconductor films or layers described herein, and / or other devices, heterostructures, or structures.

[0040] Method 600 may begin at act 602, where a substrate is prepared and / or otherwise provided. In some cases, operation 602 includes providing a silicon substrate in operation 604. The silicon substrate may have a (111) orientation. The substrate may be patterned or otherwise treated to configure the substrate to reduce defect formation in subsequently grown layers of the heterostructure and / or otherwise improve material quality therein. Such treatment may also facilitate the formation of different regions of the heterostructure.

[0041] Alternative or additional substrate materials may be used, including, for example, sapphire, bulk GaN, bulk AlN, or other semiconductor materials. Still other materials may be used, including, for example, silicon carbide. In still other cases, a metal substrate may be used. For example, the metal substrate may be composed of or otherwise include Al, Pt, and / or Mo.

[0042] The substrate may be cleaned in act 606. Optionally, a native oxide layer or other oxide layers may be removed from the substrate surface in act 608. Oxide removal may include multiple steps including, for example, an etching step and an annealing step.

[0043] In other cases, additional or alternative processing may be performed, including, for example, doping or deposition procedures. Thus, the substrate may or may not have a uniform composition. The substrate may be a uniform or composite structure. Any number of layers or structures may be deposited on the substrate prior to performing the acts described below.

[0044] Method 600 may include act 610, in which one or more template or other layers are formed or otherwise provided. In some cases, the template layer is composed of or otherwise includes a metal such as Al or Mo. In other cases, the template layer is composed of or otherwise includes a III-nitride layer (e.g., GaN) or other semiconductor layer. The template layer is supported by a substrate. In some cases, the template layer is in contact with the substrate. In other cases, one or more buffers or other layers or structures (e.g., CMOS component structures) are disposed between the template layer and the substrate.

[0045] In some cases, operation 610 is part of a CMOS fabrication procedure directed to fabricating CMOS components of a device (e.g., CMOS transistors, diodes, etc.). For example, several layers or other structures, including various types of electrodes, contacts, and other structures, may be formed during the CMOS fabrication procedure. In some cases, one of the structures of the CMOS component may be configured as or function as a template layer.

[0046] 6, operation 610 includes operation 612 in which a template layer is deposited. A wide variety of deposition procedures can be used. Optionally, the template layer is patterned in act 614.

[0047] Operation 610 may include deposition or other formation of one or more other metal layers or structures. For example, a bottom contact may be formed in operation 616. Operation 616 may be performed in parallel with (e.g., as part of) operation 612. The number and other characteristics of the metal layers or structures may vary depending on the configuration of the device (e.g., the number of terminals).

[0048] As described herein, the metal layer or structure may be part of a CMOS component of the fabricated device, for example, the metal layer or structure may be an electrode of a CMOS transistor, a CMOS diode, or other CMOS component.

[0049] As described herein, in some cases, the metal layer or structure is formed in a chamber that is also used to perform the epitaxial growth procedure to form the polar semiconductor layer. That is, the same chamber is used to form the metal layer or structure and to grow the polar semiconductor layer. As a result, the metal layer (or other layers or portions of the heterostructure being formed) is not exposed to the ambient between the formation of the metal structure and the performance of the non-sputter epitaxial growth procedure.

[0050] Alternatively, method 600 includes act 618, in which a surface treatment procedure is performed to remove oxide from the surface of the metal layer. In some cases, act 618 includes annealing the polycrystalline metal layer in a vacuum at act 620. The annealing temperature can vary, for example, depending on the composition of the metal layer and / or other structures of the device (e.g., CMOS component structures). For example, MoO3 has a relatively low melting point (795°C), in which case annealing above the melting point, e.g., at about 900°C, can be used. Annealing can also improve the surface roughness of the metal layer. In one example involving annealing at 900°C for 10 minutes, a smooth surface was observed on each domain, except for the domain boundaries. Furthermore, after the high-temperature anneal, the domain boundaries were more uniform, and misoriented clusters were significantly reduced. Oxides may be removed by additional or alternative methods to achieve a highly ordered, atomically smooth surface. For example, the oxide can be removed by an etching procedure using an acidic solution such as, for example, hydrochloric acid (HCl) or buffered hydrofluoric acid (BHF).

[0051] After forming the metal structure or other template, in operation 622, a non-sputter epitaxial growth procedure is performed to form a monocrystalline polar semiconductor layer supported by and in contact with the template layer. As described above, the monocrystalline polar semiconductor layer may be composed of or otherwise include a III-nitride based material (e.g., an alloy of III-nitride materials). Other polar semiconductors (e.g., ZnO) may also be grown.

[0052] The polar semiconductor layer may or may not be ferroelectric or piezoelectric. As described herein, the polar semiconductor layer may have a wurtzite structure. For example, the polar semiconductor material may be AlN. Additional or alternative III-nitride materials may be used, including, for example, gallium nitride (GaN), indium nitride (InN), and alloys thereof.

[0053] The epitaxial growth procedure may be configured to incorporate scandium and / or another Group IIIB element into an alloy of III-nitride materials. Thus, the alloy may be, for example, ScAlN or YAIN. In some cases, operation 622 includes operation 624, in which an MBE procedure is performed. In other cases, an MOCVD or other non-sputter epitaxial growth procedure is performed in act 626.

[0054] The surface treatment of act 618 can be performed before (e.g., in preparation for) performing an epitaxial growth procedure in which a wurtzite structure is formed. This can form a wurtzite structure on the metal layer. The metal layer can therefore act as a template for the wurtzite structure and / or other elements of the heterostructure. In some cases, operation 612 can include operation 628, growing a monocrystalline semiconductor layer in the chamber in which the template layer is formed. For example, the same chamber can be used to form a metal template layer (e.g., a Mo or Al template layer) and grow a polar semiconductor layer. As a result, the substrate can remain in the epitaxial growth chamber between forming the metal layer and growing the monocrystalline semiconductor layer, e.g., not be removed from the epitaxial growth chamber. Thus, exposure to the ambient is avoided.

[0055] As described herein, the epitaxial growth procedure can be performed at low temperatures. In some cases, the growth temperature may be less than about 400°C or other temperatures compatible with CMOS. For example, the growth temperature may be about 300°C or less. As with the examples described herein, the growth temperature may be within a range of about 20°C to about 100°C. The growth temperature may correspond to a temperature measured with a thermocouple in the growth chamber. The growth temperature at the epitaxial surface may vary slightly. Therefore, the growth temperature is approximated via the thermocouple temperature measurement. The upper and / or lower limits of the growth temperature range may vary depending on the polar semiconductor material and / or epitaxial growth technique.

[0056] At each level within the preferred growth temperature range, the resulting wurtzite structure is single crystalline to a degree that is unattainable, for example, by sputtering-based procedures for forming ScAlN layers. Such procedures can only produce structures with X-ray diffraction rocking curve linewidths of a few degrees at best. In contrast, structures grown by the disclosed method exhibit X-ray diffraction rocking curve linewidths on the order of hundreds of arc-seconds or less, which is well above one order of magnitude. In this way, in the case of ferroelectrics, leakage current paths can be minimized or otherwise sufficiently reduced so that the resulting wurtzite structure has an appropriately high breakdown field strength level, e.g., a breakdown field strength level significantly greater than the coercive field of the ferroelectric.

[0057] The difference in crystalline quality evidenced by X-ray diffraction rocking curve linewidth can be used to distinguish between single-crystalline and polycrystalline structures. As used herein, the term "polycrystalline" refers to a structure having an X-ray diffraction rocking curve linewidth on the order of a few degrees or more. As used herein, the term "single-crystalline" refers to a structure having an X-ray diffraction rocking curve linewidth at least an order of magnitude smaller than a few degrees.

[0058] Additional or alternative differences in crystalline quality may be used to distinguish between single-crystal and polycrystalline structures. As used herein, the term "polycrystalline" refers to a structure having multiple crystal grains. As described and used herein, the term "single-crystal" may refer to a structure having multiple domains.

[0059] In some cases, the epitaxial growth procedure is performed under nitrogen-rich conditions. For example, a nitrogen-to-metal flux ratio can be set in operation 630 in which the nitrogen flow is controlled. In some cases, the non-equilibrium flux ratio can be set to highly or extremely nitrogen (N)-rich conditions, such as an N-to-metal flux ratio of 2 to 1 or greater.

[0060] Controlling the flux ratio between the metal and nitrogen sources can be useful for improving the material quality of III-nitride or other polar semiconductor layers. For example, N-rich growth conditions can be useful in the growth of ScAlN to avoid Sc-Al intermetallic compounds, ScAlN perovskite phase formation, and / or other defects.

[0061] Optionally, the single-crystalline polar semiconductor layer may then be annealed in act 632. The annealing may be performed at a temperature higher than the growth temperature. In some cases, the annealing temperature is in the range of about 700° C. to about 1500° C. In other cases, the polar semiconductor layer is not annealed at such a high temperature to maintain compatibility with the CMOS components of the fabricated device.

[0062] Such post-growth high-temperature annealing of ScAlN can be performed in situ in the same growth chamber (e.g., the same MBE chamber) in act 634. In other cases, the annealing is performed ex situ in a chamber dedicated to the annealing procedure. The annealing process can be performed under high vacuum (e.g., in situ in the growth chamber) in act 636. In other cases, the annealing can be performed using nitrogen plasma irradiation or under nitrogen gas flow in act 638.

[0063] Method 600 may include act 640, in which one or more layers (e.g., semiconductor layers) are formed after growth of the wurtzite structure. As a result, the layers may be in contact with the wurtzite structure. For example, in act 642, one or more III-nitride (e.g., GaN or AlGaN) or other semiconductor layers may be epitaxially grown. Act 642 may be performed in the same epitaxial growth chamber used to grow the wurtzite structure. As a result, the substrate (and heterostructure) is not removed from the epitaxial growth chamber between performing acts 622 and 640.

[0064] Alternatively or additionally, operation 640 includes operation 644, in which one or more metal or other conductive layers or structures are formed. For example, a metal layer may be deposited on a polar semiconductor layer, where the polar semiconductor layer is disposed between and in contact with two metal layers. The layers or structures may be deposited or otherwise formed. In some cases, the conductive structure is configured as a top or top contact. For example, the conductive structure may be a gate.

[0065] In some cases, method 600 includes act 646, in which the substrate is removed. The substrate may be partially or completely removed. Once the substrate is completely removed, the heterostructure is freestanding. In some cases, act 646 includes performing an etching procedure, such as a wet or dry etching procedure. Alternatively or additionally, the substrate is mechanically removed. Thus, the manner in which the substrate is removed may vary accordingly.

[0066] Method 600 may include fewer, additional, or alternative acts. For example, one or more acts may be directed to forming other structures or regions of a device that includes a heterostructure. The nature of the regions or structures may vary according to the nature of the device. In another example, method 600 does not include act 618, in which an oxide layer is removed from a metal layer or structure, for example, because the heterostructure is not exposed to the ambient between the formation of the metal layer and the growth of the polar semiconductor layer.

[0067] The order of operations in method 600 may differ from the example shown in Figure 6. For example, contacts and / or other structures formed in operation 610 may be performed after the growth of the ferroelectric layer.

[0068] A wide variety of devices can be fabricated by the method 600 of Figure 6 and / or other methods of fabricating heterostructures with polar semiconductor layers described herein. For example, ferroelectric ScAlN or other alloys of III-nitride materials may be useful in various types of nonvolatile memory devices (e.g., FeRAM, FeFET, FTJ, and FeSFET devices), various types of reconfigurable electronic and other devices (e.g., Fe-HEMT, Fe-capacitor, and SAW devices), various types of photodetection, photovoltaic, and optoelectronic devices (e.g., self-powered photodetectors and solar cell devices), and various homojunction devices (e.g., devices that use laterally distributed charge plates to tune the Fermi levels of adjacent layers). Still other types of devices can be fabricated, including, for example, Fe-based thin film bulk acoustic wave resonator (FBAR) devices.

[0069] Some exemplary devices are described below. In some cases, the devices include CMOS components (e.g., CMOS transistors or diodes). As described herein, the CMOS components can include structures supporting polar semiconductor layers.

[0070] Figure 7 shows some exemplary heterostructures with polar semiconductor layers grown by low-temperature epitaxy. In these cases, the multilayer nitride heterostructures are grown on metal electrodes, although Si or other substrates / templates may be used in other cases (e.g., examples involving multimode, high-frequency, and low-loss acoustic resonators and filters, memory electronics, MEMS / NEMS, and various flexible nitride devices). As described herein, the metal electrodes serve as templates for the polar semiconductor layers, which may correspond to layers or structures of the CMOS components of the device. The quasi-three-dimensional growth at low temperatures (e.g., under N-rich conditions) described herein relieves stress within the multilayer structure. Three exemplary heterostructures include an AlGaN / AlN heterostructure bilayer grown on an Al / Si template, an ScAlN / AlN bilayer heterostructure grown on a Mo / Si template, and an AlN / ScAlN / AlN trilayer heterostructure grown on a Mo / Si template.

[0071] Parts d and f in Figure 7 show the surface morphologies of three multilayer structures grown at 100°C. No obvious cracks were observed in any of the examples, indicating that the stress between each layer was released. Meanwhile, except for the RHEED pattern of the wurtzite structure, no other high-energy electron diffraction (RHEED) patterns were observed at the end of growth for all examples. This indicates that all low-temperature grown multilayers maintain a distinct wurtzite crystal structure, which was also confirmed by XRD measurements. Therefore, low-temperature epitaxy is useful for growing single-crystalline multilayer nitride heterostructures.

[0072] Additionally, in the structure shown in part c of Figure 7, the ScAlN layer can be made ferroelectric. Therefore, the polarity of the ScAlN layer can be polarized (changing from metal polarity to nitrogen polarity, or vice versa) while the polarity of the AlN layer remains the same. Such unique designs enable the design and development of reconfigurable electronic, acoustic, and photonic devices. Multilayer structures can also include many stacks of AlN / ScAlN, metal / ScAlN, metal / AlN, GaN / AlN, GaN / ScAlN, 2D TMD / ScAlN, or other periodic structures containing rare-earth-doped III-nitrides. While rare-earth-doped III-nitrides are often designed to be ferroelectric, in other cases, enhanced piezoelectric and / or optical properties can be utilized in multilayer structures. Furthermore, the thickness of the multilayer structure can vary. For example, for acoustic filter / resonator-related applications, the thickness can be in the range of approximately 100 nm, while for memory and / or quantum-related applications, the thickness can be on the nanometer scale.

[0073] Figure 8 shows examples of (a) Ga-polar and (b) N-polar Al(Ga,In)N / GaN high electron mobility transistor (HEMT) devices with polar semiconductor layers grown using low growth temperatures. In these examples, the polar semiconductor layers are made of AlN. The AlN layers can be grown in situ (e.g., in the same growth chamber used to grow the underlying layers) as described herein. In these examples, the polar semiconductor layers are configured as high-k gate dielectric layers for the HEMT devices.

[0074] Figure 9 shows examples of transistor structures that use low-temperature-grown polar semiconductor layers as dielectric layers. In these examples, the polar semiconductor layers are composed of AlN or ScAlN. The dielectric layer is disposed adjacent to a channel layer that is composed of or otherwise includes a two-dimensional (2D) material, such as hexagonal BN (hBN). These and other aspects of the transistor structure can vary. For example, the example shown in Figure 9(a) is a global (back) gate structure, while the example shown in Figure 9(b) is a local (top) gate structure.

[0075] Figure 10 shows an example of an AlN-based transistor device having one or more low-temperature-grown AlN-based layers. In this case, the transistor includes source and drain contacts spaced from an n-type AlN body region by respective polarization-graded AlGaN layers. Each AlGaN layer can be grown as described herein.

[0076] Figure 11 shows an example of a high-power Al(Ga)N PIN diode with one or more low-temperature-grown AlN-based layers. In this case, the p- and n-Al(Ga) layers can be grown at low or high temperatures, and the intrinsic (i)-Al(Ga)N layer is grown at low temperature. Growing the i-Al(Ga)N layer at low temperature as described herein helps improve the breakdown voltage of the diode for the reasons discussed above.

[0077] Figure 12 shows an example of a high-power Al(Ga)N Schottky diode with one or more low-temperature grown AlN-based layers. The diode can be grown at low or high temperatures. + The n-type Al(Ga)N layer includes a doped Al(Ga)N layer, and the n-type Al(Ga)N layer is grown at low temperature. Growing the n-type Al(Ga)N layer at low temperature as described herein helps improve the breakdown voltage of the diode for the reasons discussed above.

[0078] An example of a high-power Al(Ga)N bipolar transistor with multiple low-temperature-grown AlN-based layers is shown in Figure 13. This device includes n-type and p-type Al(Ga) layers grown at low temperatures, which improves the breakdown voltage of the transistor for the reasons discussed above.

[0079] Figure 14 shows an example of a ferroelectric transistor random access memory cell device with a low-temperature-grown AlN-based layer. In this example, the device includes a capacitor with a low-temperature-grown ferroelectric ScAlN layer disposed between two metal layers. The device also includes a silicon or GaN-based write-read transistor.

[0080] Figure 15 shows examples of deep ultraviolet LED devices with one or more low-temperature epitaxially grown III-nitride layers. The example shown in part a of Figure 15 is an Al(Ga)N-based DUV-LED device with a low-temperature grown Al(Ga)N buffer layer. The example shown in part b of Figure 15 has a low-temperature grown Al(Ga)N-based DUV-LED structure.

[0081] 16 shows an example of a self-powered photodetector with low-temperature epitaxially grown III-nitride layers. In this example, the III-nitride layers are Al(Ga,In,Sc)N layers configured to function as light absorption layers.

[0082] Figure 17 shows three examples of thin-film acoustic wave resonator devices with low-temperature-grown III-nitride layers. In these cases, the III-nitride layers are composed of Al(Sc)N and configured to function as piezoelectric layers. a) is a bulk resonator, b) is a surface-micromachined freestanding resonator, and c) is a bulk-micromachined freestanding resonator.

[0083] The above-described examples demonstrate the low-temperature epitaxy of single-crystalline wurtzite nitrides on both GaN and CMOS-compatible Al metal electrodes using MBE. Highly ordered wurtzite atomic stacking arrangements and atomically sharp interfaces were achieved at growth temperatures as low as 100 °C. The polar surface-controlled on-site growth mechanism explains the successful epitaxy of single-crystalline polar nitrides at low temperatures. Furthermore, the growth of wurtzite ScAlN with Sc contents up to 0.4 and AlN films on CMOS-compatible Al metal electrodes was achieved using the proposed on-site epitaxy method. The examples demonstrate the epitaxy of polar nitride semiconductors in an unexplored low-temperature regime, which also supports integration with CMOS technology and advanced hybrid and integrated circuits across a wide variety of technology and material platforms.

[0084] As used herein, the terms "atomically smooth" or "atomically smooth surface" may be used herein in reference to a layer of a heterostructure to indicate that the layer has a surface roughness (e.g., root mean square, or RMS roughness) of less than or about 1 nm. In some cases, the RMS roughness of such an atomically smooth layer is less than 1% of the layer thickness. Surface roughness may vary according to growth conditions, parameters, and other aspects of the fabrication processes and / or other processes described and / or referenced herein.

[0085] The term "about" is used herein to include deviations from a specified value that would be understood by one of ordinary skill in the art to be substantially the same as the specified value, e.g., due to the absence of any appreciable, detectable, or otherwise significant difference in the operation, results, properties, or other aspects of the disclosed methods and devices.

[0086] Although the present disclosure has been described with reference to particular embodiments, these embodiments are merely illustrative and do not limit the present disclosure. Modifications, additions, and / or deletions can be made to the embodiments without departing from the spirit and scope of the present disclosure.

[0087] The foregoing description is given for clarity of understanding only, and no unnecessary limitations should be understood therefrom.

Claims

1. 1. A method for forming a heterostructure, comprising: providing a substrate; forming a template layer of the heterostructure supported on the substrate; performing a non-sputter epitaxial growth procedure to form a polar semiconductor layer of the heterostructure supported by and in contact with the template layer; the non-sputter epitaxial growth procedure is configured such that the polar semiconductor layer is monocrystalline; The method, wherein the non-sputter epitaxial growth procedure is performed at a growth temperature of less than about 400 degrees Celsius.

2. The method of claim 1 , wherein the non-sputter epitaxial growth procedure is performed under nitrogen-rich conditions.

3. 10. The method of claim 1, wherein forming the template layer and performing the non-sputter epitaxial growth procedure are performed in the same chamber such that the heterostructure is not exposed to the ambient between forming the template layer and performing the non-sputter epitaxial growth procedure.

4. The method of claim 1 , wherein forming the template layer includes performing a surface treatment procedure to remove oxides from a surface of the template layer.

5. The method of claim 1 , wherein the growth temperature is less than about 300° C.

6. The method of claim 1 , wherein the growth temperature is greater than about 20° C.

7. The method of claim 1 , wherein the growth temperature is between about 20° C. and about 100° C.

8. The method of claim 1 , wherein the polar semiconductor layer comprises a III-nitride material or an alloy thereof.

9. The method of claim 1 , wherein the polar semiconductor layer comprises AlN or an alloy thereof.

10. The method of claim 1 , wherein the template layer comprises a metal compatible with complementary metal oxide semiconductor (CMOS) fabrication.

11. the template layer comprises GaN; The method of claim 1 , wherein the polar semiconductor layer comprises AlN or an alloy thereof.

12. 1. A method of manufacturing a device, comprising: forming a metal structure for a complementary metal oxide semiconductor (CMOS) component of the device, the metal structure being supported by a substrate; after forming the metal structure, performing a non-sputter epitaxial growth procedure to form a polar semiconductor layer of a heterostructure of the device, the polar semiconductor layer being supported by the substrate; The method, wherein the non-sputter epitaxial growth procedure is configured such that the polar semiconductor layer is single crystalline.

13. 13. The method of claim 12, wherein the non-sputter epitaxial growth procedure is performed at a growth temperature of less than about 400 degrees Celsius.

14. The method of claim 12 , wherein the non-sputter epitaxial growth procedure is performed under nitrogen-rich conditions.

15. The method of claim 12 , wherein the non-sputter epitaxial growth procedure is configured to configure the polar semiconductor layer so that the polar semiconductor layer is in contact with the metal structure.

16. 13. The method of claim 12, wherein forming the metal structure and performing the non-sputter epitaxial growth procedure are performed in the same chamber such that the heterostructure is not exposed to the ambient between forming the metal structure and performing the non-sputter epitaxial growth procedure.

17. The method of claim 12 , wherein forming the metal structure includes performing a surface treatment procedure to remove oxides from the surface of the metal structure.

18. 13. The method of claim 12, further comprising forming a template layer of the heterostructure before performing the non-sputter epitaxial growth procedure such that the polar semiconductor layer is in contact with the template layer.

19. A heterostructure, A substrate; a polar semiconductor layer supported on the substrate; the polar semiconductor layer has a single-crystal wurtzite crystal structure; The polar semiconductor layer comprises a plurality of columnar domains.

20. 20. The heterostructure of claim 19, wherein the polar semiconductor layer comprises AlN or an alloy thereof.

21. 20. The heterostructure of claim 19, wherein said polar semiconductor layer comprises an AlN alloy, said AlN alloy comprising a Group IIIB element.

22. 20. The heterostructure of claim 19, wherein said polar semiconductor layer is piezoelectric.

23. 20. The heterostructure of claim 19, wherein said polar semiconductor layer is ferroelectric.

24. 20. The heterostructure of claim 19, further comprising a template layer disposed between said substrate and said polar semiconductor layer, said polar semiconductor layer in contact with said template layer.

25. 25. The heterostructure of claim 24, wherein said template layer and said polar semiconductor layer have opposite polarities.

26. 25. The heterostructure of claim 24 wherein the template layer comprises a metal.

27. 25. The heterostructure of claim 24, wherein the surface of the polar semiconductor layer at the interface with the template layer has an atomically smooth surface.

28. A device, A substrate; a complementary metal oxide semiconductor (CMOS) component supported by a substrate, the CMOS transistor comprising a structure; a polar semiconductor layer supported by the structure; the polar semiconductor layer has a single-crystalline wurtzite crystal structure.

29. 30. The device of claim 28, wherein the structure comprises a metal.

30. 30. The device of claim 28, wherein the polar semiconductor layer comprises a plurality of columnar domains.

31. 30. The device of claim 28, wherein the surface of the polar semiconductor layer in contact with the structure has an atomically smooth surface.

32. 1. A method for forming a heterostructure, comprising: providing a substrate; forming a metal layer of the heterostructure such that the metal layer is supported by the substrate, the metal layer comprising aluminum; performing a non-sputter epitaxial growth procedure to form a polar semiconductor layer of the heterostructure, the polar semiconductor layer being supported by and in contact with the metal layer; the non-sputter epitaxial growth procedure is configured such that the polar semiconductor layer is monocrystalline; The method of claim 1, wherein the step of forming the metal layer and the step of performing the non-sputter epitaxial growth procedure are performed in the same chamber such that the heterostructure is not exposed to the ambient between the steps of forming the metal layer and performing the non-sputter epitaxial growth procedure.

33. 33. The method of claim 32, wherein the non-sputter epitaxial growth procedure is configured to be performed at a growth temperature where the polar semiconductor layer is compatible with complementary metal oxide semiconductor (CMOS) fabrication.

34. 1. A method for forming a heterostructure, comprising: providing a substrate; forming a metal layer of the heterostructure such that the metal layer is supported by the substrate, the metal layer comprising molybdenum; performing a non-sputter epitaxial growth procedure to form a polar semiconductor layer of the heterostructure supported by and in contact with the metal layer; the non-sputter epitaxial growth procedure is configured such that the polar semiconductor layer is monocrystalline; The method of claim 1, wherein the step of forming the metal layer and the step of performing the non-sputter epitaxial growth procedure are performed in the same chamber such that the heterostructure is not exposed to the ambient between the steps of forming the metal layer and performing the non-sputter epitaxial growth procedure.

35. 35. The method of claim 34, wherein the non-sputter epitaxial growth procedure is configured to be performed at a growth temperature where the polar semiconductor layer is compatible with complementary metal oxide semiconductor (CMOS) fabrication.

Images