Transistors with selectively landed gate arrays

Abstract

The semiconductor device may include a plurality of transistors (110), wherein a first array (204, 206) of low-resistivity material is formed in a first dielectric layer (216), a gate subset (204) of the first array is formed on a plurality of gate electrodes (202) of the transistors, and a source subset (206) of the first array is formed on a plurality of source regions (212) of the transistors. A second array (205, 207) of low-resistivity material may be formed in a second dielectric layer (220), wherein the gate subset (205) of the second array is formed on the gate subset (204) of the first array, thereby electrically connecting to the plurality of gate electrodes (202), and the source subset (207) of the second array is formed on the source subset (206) of the first array, thereby electrically connecting to the plurality of source regions (212).

Description

[Technical Field]

[0001] The present specification relates to semiconductor devices. [Background technology]

[0002] Semiconductor devices are typically formed on a portion of a wafer, such as a silicon (Si) wafer, a silicon carbide (SiC) wafer, or a gallium nitride (GaN) wafer. The area of ​​the wafer where the devices are formed is sometimes called the active area.

[0003] In semiconductor devices, electrical connections are typically provided, for example, so that the semiconductor device can be controlled or operated by an external device. For example, the gate of a transistor may need to be electrically connected to a power source to turn the transistor on or off. Often, multiple devices (e.g., transistors) are formed on a wafer and may be controlled by a common electrical connection, such as when a gate pad is connected to an external power source and a gate runner connects the gate pad to multiple gates / transistors.

[0004] To ensure reliable and consistent connectivity of various devices, it may be desirable to make such electrical connections relatively large, where feasible. However, electrical connections may consume valuable surface area of ​​the wafer that could otherwise be used to increase device density. Thus, the wafer surface area used by electrical connections is sometimes referred to as dead zone. Thus, a conflict exists between establishing reliable electrical connections of semiconductor devices and avoiding dead zones on the wafer.

[0005] Attempts to resolve this conflict can further complicate the design and implementation of semiconductor devices. For example, routing a metal track for a gate connection may require interrupting metal routing for other transistor connections, such as source metal routing for a vertical field-effect transistor (FET) and / or emitter metal routing for an insulated gate bipolar transistor (IGBT). Such interruptions in metal routing may increase associated resistance and / or may make it difficult to form electrical connections when packing associated semiconductor die. Summary of the Invention

[0006] According to one general aspect, a semiconductor device may include a plurality of transistors including a plurality of source regions and a plurality of gate electrodes, and a first dielectric layer formed on the plurality of source regions and the plurality of gate electrodes. The semiconductor device may include a first array of low-resistivity material formed in the first dielectric layer, with a subset of gates of the first array formed on the plurality of gate electrodes and a subset of sources of the first array formed on the plurality of source regions, and a second dielectric layer formed on the first dielectric layer and on the first array. The semiconductor device may include a second array of low-resistivity material formed in the second dielectric layer, with a subset of gates of the second array formed on the subset of gates of the first array and thereby electrically connected to the plurality of gate electrodes, and a subset of sources of the second array formed on the subset of sources of the first array and thereby electrically connected to the plurality of source regions. The semiconductor device may include a gate pad metal formed on the second dielectric layer and electrically connected to a subset of gates in the second array, and a source pad metal formed on the second dielectric layer and electrically connected to a subset of sources in the second array.

[0007] According to another general aspect, a semiconductor device may include a plurality of transistors including a plurality of source regions and a plurality of gate electrodes; and a first array of low-resistance plug material formed in a first plug layer over the plurality of transistors, with a subset of gates of the first array formed over the plurality of gate electrodes and a subset of sources of the first array formed over the plurality of source regions. The semiconductor device may include a second array of low-resistance plug material formed in a second plug layer over the first plug layer, with a subset of gates of the second array formed over the subset of gates of the first array and thereby electrically connected to the plurality of gate electrodes, and a subset of sources of the second array formed over the subset of sources of the first array and thereby electrically connected to the plurality of source regions. The semiconductor device may include a gate pad metal formed in a first metal layer over the second plug layer and electrically connected to the subset of gates of the second array, and a source pad metal formed in the first metal layer and electrically connected to the subset of sources of the second array.

[0008] According to another general aspect, a method of fabricating a semiconductor device may include forming a plurality of transistors in a substrate, the plurality of transistors including a plurality of source regions and a plurality of gate electrodes, and forming a first dielectric layer over the plurality of source regions and the plurality of gate electrodes. The method may include forming a first array of low-resistivity material in the first dielectric layer, wherein a subset of gates of the first array are formed over the plurality of gate electrodes and a subset of sources of the first array are formed over the plurality of source regions, and forming a second dielectric layer over the first dielectric layer and the first array. The method may include forming a second array of low-resistivity material in the second dielectric layer, wherein a subset of gates of the second array are formed over the subset of gates of the first array, thereby electrically connected to the plurality of gate electrodes, and a subset of sources of the second array are formed over the subset of sources of the first array, thereby electrically connected to the plurality of source regions. The method may include forming a gate pad metal on the second dielectric layer, the gate pad metal electrically connected to a subset of gates in the second array, and forming a source pad metal on the second dielectric layer, the source pad metal electrically connected to a subset of sources in the second array.

[0009] The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features will be apparent from the description and drawings, and from the claims. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram illustrating a top view of a semiconductor device including a selectively landed gate array. [Figure 2] 2 illustrates a cross-sectional view of an exemplary implementation of the semiconductor device of FIG. 1. [Figure 3] 2A-2C illustrate additional cross-sectional views of exemplary implementations of the semiconductor device of FIG. 1. [Figure 4] 2A-2C illustrate additional cross-sectional views of exemplary implementations of the semiconductor device of FIG. 1. [Figure 5]2A-2C illustrate additional cross-sectional views of exemplary implementations of the semiconductor device of FIG. 1. [Figure 6] 2 illustrates exemplary current flows and internal resistances that may be implemented using the semiconductor device of FIG. 1. [Figure 7] 2 illustrates an exemplary top view of a first metal layer of the semiconductor device of FIG. 1. [Figure 8] 2 illustrates an exemplary top view of a second metal layer of the semiconductor device of FIG. 1. [Figure 9A] FIG. 1 illustrates a first cross-sectional view of a first exemplary stage of a manufacturing process for a semiconductor device including a selectively landed gate array. [Figure 9B] FIG. 1 illustrates a second cross-sectional view of a first exemplary stage of a manufacturing process for a semiconductor device including a selectively landed gate array. [Figure 10A] FIG. 1 illustrates a first cross-sectional view of a second exemplary stage of a manufacturing process for a semiconductor device including a selectively landed gate array. [Figure 10B] FIG. 10 illustrates a second cross-sectional view of a second exemplary stage of a manufacturing process for a semiconductor device including a selectively landed gate array. [Figure 11A] FIG. 10 illustrates a first cross-sectional view of a third exemplary stage of a manufacturing process for a semiconductor device including a selectively landed gate array. [Figure 11B] FIG. 10 illustrates a second cross-sectional view of a third exemplary stage of a manufacturing process for a semiconductor device including a selectively landed gate array. [Figure 12A] FIG. 10 illustrates a first cross-sectional view of a fourth exemplary stage of a manufacturing process for a semiconductor device including a selectively landed gate array. [Figure 12B] FIG. 10 illustrates a second cross-sectional view of a fourth exemplary stage of a manufacturing process for a semiconductor device including a selectively landed gate array. [Figure 13] FIG. 10 is a schematic diagram illustrating a top view of an alternative example of a semiconductor device including a selectively landed gate array. [Figure 14]14 is a flowchart illustrating an exemplary process flow for fabricating the device of FIGS. 1-13. DETAILED DESCRIPTION OF THE INVENTION

[0011] The described technique overcomes the above difficulties by enabling desired distribution of transistor control signals, such as gate signals, using, for example, a metal redistribution layer. A double plug process is used in which a first array of low-resistance plug material (e.g., first tungsten (W) plugs) is disposed in a first plug layer, with a first subset of the first array forming a first transistor connection type, such as gate connections, and a second subset of the first array forming a second transistor connection type, such as source connections.

[0012] A second array of low-resistance plug material (e.g., second tungsten (W) plugs) is disposed in the second plug layer, with a first subset of the second array contacting the first subset of the first array, thereby continuing, for example, the gate connection. A second subset of the second array may then contact a second subset of the first array, thereby continuing, for example, the source connection. The first subset of the second array may then connect to a first connection pad, such as a gate pad, in the first metal layer, and the second subset of the second array may connect to a second connection pad, such as a source pad, in the second metal layer.

[0013] More specifically, the described configurations enable selective contact between electrodes and their corresponding connections in an overlying (first) metal layer. For example, a first subset of the first array may be disposed on a gate electrode and partially covered with a dielectric material so as to be electrically isolated from an overlying source pad, but also partially covered with a first subset of the second array so as to be electrically connected to a gate metal, such as a gate pad or gate runner. Similarly, a second subset of the first array may be disposed on a source region or source electrode and partially covered with a dielectric material so as to be electrically isolated from an overlying gate pad or gate runner, but also partially covered with a second subset of the second array so as to be electrically connected to a source pad.

[0014] In a more specific example, described in more detail below, a semiconductor device may include a plurality of vertical transistors, with an array of linear gate electrodes interdigitated with and parallel to an array of linear source electrodes. A first array of low-resistivity material may then have a first subset thereof formed on (e.g., landed directly on) the gate electrodes and a second subset thereof formed on (e.g., landed directly on) the source electrodes. Thus, a first subset of the first array (sometimes referred to as a gate subset) interdigitates with a second subset of the first array (sometimes referred to as a source subset) in a first plug layer above the substrate of the semiconductor device of FIG. 1.

[0015] A second array of low-resistance plug material may then be selectively formed in a second plug layer above the first plug layer, with a first subset (sometimes referred to as a gate subset) of the second array selectively formed on the first subset (or gate subset) of the first array (and thereby into gate electrodes). A second subset (sometimes referred to as a source subset) of the second array may be selectively formed on the second subset (or source subset) of the first array (and thereby into source electrodes). As noted above, if the second array of low-resistance plug material is not disposed on the first array of low-resistance plug material, a dielectric material may be provided (e.g., in the second plug layer above the first plug layer) to selectively insulate the first array in the first plug layer from undesired connections to pads or runner metal in a first metal layer above the second plug layer.

[0016] Thus, the active area of ​​the associated transistor can be increased compared to the available semiconductor die area to 100 percent or nearly 100 percent of the available semiconductor die area. Such advantages can be obtained while still allowing metal tracks or runners to be used to carry electrical signals, such as gate control signals, for the power transistors because such tracks or runners can be provided in a first metal layer above the active area of ​​the device (e.g., above the second plug layer).

[0017] In some implementations, the available semiconductor die area may be semiconductor area within an isolation region or termination region of a corresponding semiconductor die. Such isolation or termination regions may be disposed around at least a portion of the periphery of the corresponding semiconductor die and may help regulate the breakdown voltage of an associated power transistor. For example, such isolation regions may prevent breakdown below the rated voltage of the transistor by, for example, terminating high electric fields during transistor operation.

[0018] Additionally, signal metal for other connections to the transistor, such as source and / or emitter connections, may be continuous. That is, in the implementations described herein, breaks in the signal metal to accommodate routing of the metal tracks / runners are avoided because such metal tracks / runners are provided in a first metal layer above the active area of ​​the device. This allows the associated area of ​​the source and / or emitter signal metal to be increased, which in turn can improve the performance of the associated transistor, e.g., increasing the current carrying capability for the same die size as conventional implementations, and can simplify electrical connections to the signal metal, such as electrical clips or wirebond connections, when the device is packaged for use.

[0019] The techniques described herein may also provide other advantages. For example, in some implementations, the resistance of a gate connection within an associated semiconductor may be easily adjusted or tuned, with precision ranging from the milliohm range to hundreds of ohms. Such adjustment may be achieved as a result of forming slots in at least a portion of a first subset of a first array of low-resistivity plug materials formed on the gate electrode. By providing such slots, current may be pushed out of the low-resistivity plug material and into a relatively high-resistivity gate electrode material (e.g., doped polysilicon), as described in more detail below.

[0020] By locating such slots in specific locations, for example, adjacent to a gate pad connected to an external power source, all gate current can be forced to flow through the gate electrode material below the slot. In this way, the gate current of the entire semiconductor device can be given a desired resistance using only a desired local area within the active area of ​​the device. Desired resistance parameters can then be obtained by adjusting the size and spacing of the slots. For example, the resistance value can be adjusted, and local heat dissipation that may be associated with high-speed switching can be controlled.

[0021] FIG. 1 is a diagram that schematically illustrates a top view of a semiconductor device including a selectively landed gate array. In the example of FIG. 1, the semiconductor device includes an active area 110 and an isolation or termination region 120. In the example of FIG. 1, termination region 120 surrounds active area 110. That is, termination region 120 defines the periphery of active area 110. In some implementations, termination region 120 may include implants and / or trench structures for terminating electric fields associated with operation of transistors implemented within active area 110 of the semiconductor device of FIG. 1.

[0022] As shown in Figure 1, semiconductor device 100 includes an array 130 of low-resistivity plug material. That is, as described above, array 130 can include a first array in a first plug layer and a second array in a second plug layer disposed at least partially on the first plug layer. From the top view of Figure 1, the first plug layer is indistinguishable from the second plug layer, but the first and second plug layers are visible in the following examples, for example, in Figures 2-5.

[0023] In the example of FIG. 1, array 130 includes regularly spaced rows of conductive material and may be implemented using tungsten or other metallic material. That is, in the implementations of FIGS. 2-12, array 130 may be implemented as a linear array of low-resistance plug material. As discussed with respect to FIG. 13, in other implementations, array 130 may also include a matrix or grid of rows and / or columns of conductive material. For example, the rows and / or columns may be irregularly spaced or segmented. In other examples, array 130 may define a hexagonal (or other shaped) grid. Thus, the particular configuration of array 130 will depend on the particular implementation desired.

[0024] 1, array 130 may extend across all or nearly all of active area 110, being appropriately spaced from active area 110 for associated semiconductor processing. The configuration of array 130 allows for low resistance connections from array 130 to the gate and source electrodes of transistors disposed below array 130 in active area 110. For example, as described above, array 130 may be implemented using tungsten, which has approximately 100 times less resistance than doped polysilicon for the gate electrodes.

[0025] Semiconductor device 100 also has a gate pad area 140 and a gate pad connection area 140a. As shown in Figure 1, gate pad connection area 140a may have a smaller area than gate pad area 140. Gate runner 150, gate runner 160, and gate pad contact runner 170 may be part of a signal distribution layer in a first metal layer of the semiconductor device of Figure 1.

[0026] 7, the source pad may be disposed in the first metal layer (suitably spaced from gate runner 150, gate runner 160, and gate pad contact runner 170, and from termination region 120), but is omitted in the example of FIG. 1 so that array 130 can be viewed. Similarly, in the simplified example of FIG. 1, various dielectric layers are omitted so that array 130 can be viewed.

[0027] Gate runners 150, gate runners 160, and gate pad contact runners 170 may be selectively electrically coupled to a first subset (e.g., a subset of gates) of array 130. For example, gate runners 150, gate runners 160, and gate pad contact runners 170 in a first metal layer may all be selectively connected to (e.g., disposed above) a first subset (of gates) of a second array in a second plug layer below the first metal layer. The subset of gates of the second array may then be connected to the subset of gates below the first array in the first plug layer, thereby connecting to the gate electrodes of transistors in active area 110.

[0028] Similarly, source pads (which, as just mentioned, are not shown in FIG. 1 ) can be selectively electrically coupled to a second (e.g., source) subset of the second array in a second plug layer below the first metal layer. The source subset of the second array can then be connected to the source subset underlying the first array in the first plug layer, and thereby connected to the source electrodes of the transistors in the active area 110.

[0029] 1, where array 130 is formed as a linear array, gate subsets of array 130 may be interdigitated with source subsets of array 130. For example, in FIG. 1, the gate subsets and source subsets may be alternated such that odd rows are included in the gate subsets and even rows are included in the source subsets.

[0030] In the example of FIG. 1 , the entire active area 110 of the semiconductor device 100, appropriately spaced from the termination region 120, can contain active transistor segments. Accordingly, areas previously used to implement metal gate tracks, contacts, or runners can be omitted or used for active transistor area. Thus, semiconductor devices having transistor active areas equal to those of semiconductor devices constructed using conventional or existing techniques can be fabricated using semiconductor dies having smaller areas. That is, areas traditionally used to implement gate metal can be omitted, and the corresponding die size can be reduced by the amount of area used to implement such gate metal (e.g., up to 15% of the associated active area). Stated differently, in some implementations, arrays 130, such as the exemplary implementations described herein, can avoid reducing the active area within the active area of ​​corresponding semiconductor devices, such as the transistors described herein.

[0031] 1, slots 180 are formed within active area 110 by simply forming (e.g., removing or not forming) slots in a portion of the low-resistance plug material of a gate subset of a first array of arrays 130 in the first plug layer, thereby resulting in increased internal gate resistance. By so forming the slots, for example, as described and illustrated in more detail below with respect to FIG. 3, gate current can be forced to traverse the doped polysilicon of the gate electrodes of transistors in active area 110 rather than the low-resistance plug material. In other words, in FIG. 1, slots 180 can be understood to reveal or indicate doped polysilicon underlying the gate electrodes that would otherwise be obscured by array 130 in FIG. 1.

[0032] This allows for the provision of gate resistance without the need for an external gate resistor. The value or degree of gate resistance (and associated effects, such as heat dissipation) may be adjusted or tuned simply by controlling the number, size, or spacing of slots 180 (which may therefore also be referred to as resistors 180). Furthermore, the internal gate resistance provided by slots 180 may be determined independently of the die size of the semiconductor device of FIG. 1. Additional examples of resistors 180, as well as related features and advantages, are provided below, for example, with respect to FIGS. 3, 6, and 13.

[0033] Figure 2 is a diagram illustrating a cross-sectional view of an exemplary implementation of the semiconductor device of Figure 1. In the example of Figure 2, a doped polysilicon gate electrode 202 is interdigitated with a source electrode (also called a source contact or source metal) 203.

[0034] The first array of low resistance plug material formed in the first plug layer includes a first array subset of gates 204 and a first array subset of sources 206. The second array of low resistance plug material formed in the second plug layer includes a second array subset of gates 205 (visible in cross section 200a, as described below) and a second array subset of sources 207.

[0035] 2, the first plug layer refers to the layer in which the first arrays 204, 206 are formed. The first plug layer is above the substrate 212 and below the second plug layer in which the second arrays 205, 207 of low-resistivity plug material are formed. As shown and described in more detail below, the gate subsets 204 and source subsets 206 (sometimes referred to as gate plugs and source plugs, respectively) may have different lengths in the vertical, i.e., Y, direction because each gate plug of a gate subset 204 is formed on an underlying gate electrode 202.

[0036] 2, dielectric material 210 is shown as being disposed around gate subsets 204, 205 and source subsets 206, 207, as well as around gate electrode 202. Dielectric material 210 may include multiple layers and / or multiple types of dielectric materials, as described in more detail below.

[0037] Gate metal 250 may be disposed in a first metal layer over dielectric material 210. For example, gate metal 250 may conceptually correspond to, for example, gate runner 150, gate runner 160, or gate pad contact runner 170 of FIG.

[0038] Figure 2 further shows a first cross section 200a along gate runner 250. Figure 2 also shows a second cross section 200b along multiple gate electrodes 202, gate subsets 204 / 205, and source subsets 206 / 207.

[0039] In cross sections 200a and 200b, substrate 212 is shown as including, for example, an epitaxial layer, which may be an n-type epitaxial layer having a doping concentration that is lower than the doping concentration of an underlying portion (not shown in FIG. 2) of substrate 212. Such a substrate may be, for example, a heavily doped n-type substrate, such as a silicon carbide (SiC) substrate, or another semiconductor substrate.

[0040] 2, a gate oxide is formed on substrate 212 and below gate electrode 202. Dielectric material 210 is shown as including dielectric layer 216, which may be, for example, borophosphosilicate glass (BPSG) or other suitable dielectric. Dielectric material 210 is shown as including dielectric layer 220, which may be, for example, a suitable silicon oxide, nitride, or other suitable dielectric. Buffer layer 218 may be disposed between dielectric layers 216 and 220.

[0041] A cladding or barrier metal 222 may be disposed between the plugs of the first plug layer and the plugs of the second layer. The barrier metal 222 may be used to avoid reflections during photolithography processing, and because the barrier metal 222 is wider than the adjacent plugs (e.g., gate plugs 204 / 205 or source plugs 206 / 207), it may be useful in maintaining electrical connection between the first and second plug layers in the event of any undesired misalignment that may occur during processing.

[0042] 2, as described above with respect to FIG. 1, the first plug layer is shown as including plugs 204, 206 (as well as gate electrode 202), the second plug layer is shown as including plugs 205, 207, and the first metal layer is shown as including gate metal 250. Also, as noted above, and as described in more detail below with respect to, for example, FIG. 3 and FIG. 7, the first metal layer may also include source pads that contact source subsets 207 of the second plug layer, as well as any dielectric material necessary to maintain isolation between gate metal 250 and such source pads.

[0043] In Figure 2, dielectric region 224 corresponds to slot 180 in Figure 1 and is used to provide an internal gate resistance for the semiconductor device of Figure 2. As can be seen in Figure 3 (which may represent, for example, cross section AA of Figure 1), current 302 is therefore forced through gate metal 250, plug 205 in the second plug layer, plug 204a in the first plug layer, around plug slot 224 in the dielectric material, through gate electrode 202, and into plug 204b in the first plug layer.

[0044] 3 also shows a source pad 304 in the first metal layer. As shown, the source pad 304 may be separated and electrically isolated from the gate metal 250 by a dielectric layer 306.

[0045] Figure 4 illustrates an additional cross-sectional view of an exemplary implementation of the semiconductor device of Figure 1. Figure 4 illustrates a more detailed view of cross-sectional view 200b of Figure 2, including source pad metal 304.

[0046] Figure 5 illustrates an additional cross-sectional view of an exemplary implementation of the semiconductor device of Figure 1. Figure 5 illustrates a more detailed view of cross-sectional view 200a of Figure 2, including redistributed gate runner metal 250.

[0047] Figure 6 shows an example current flow and internal resistance that may be implemented using the semiconductor device of Figure 1. Figure 6 shows that active area 610 may include gate runner 650 (similar to gate runner 150 of Figure 1) and gate pad contact runner 670 (similar to gate pad contact runner 170 of Figure 1, shown transparently in Figure 6). Slot 680 corresponds to slot / resistor 180 of Figure 1.

[0048] As indicated by the various arrows in Figure 6, all current entering gate pad contact runner 670 traverses gate runner 650 (and a similar gate runner on the other side of active area 610, not shown in Figure 6), which redistributes the current throughout the remaining transistors in active area 610.

[0049] As mentioned above, the provision of slot 680 provides an internal gate resistance Rg without requiring connection to an external resistor. Rg tunability is provided from at least the milliohm range to several hundred ohms. Exemplary Rg values ​​for SiC power devices can range from approximately 1 to 20 ohms.

[0050] Further in Figure 6, dashed lines 680a represent spaced or separated slots along the gate electrode. As discussed above, high-speed switching operation of the semiconductor device of Figure 6 can result in heat buildup, for example, within the gate electrode. As shown, spacing the slots 680a over a wider area can improve localized heat dissipation, even during high-speed switching operation.

[0051] 7 is a diagram illustrating an example top view of a first metal layer of the semiconductor device of FIG. 1. As described above, the first metal layer may include gate metals 750 and 770. The first metal layer may also include, for example, a source pad metal 704 similar to source pad metal 304 of FIG. 3. Also corresponding to FIG. 3, a dielectric 706 may be used to separate and electrically insulate source pad metal 706 from gate metals 750, 770.

[0052] Figure 8 illustrates an exemplary top view of a second metal layer of the semiconductor device of Figure 1. Such a second metal layer is typically used to facilitate external connections to the semiconductor device.

[0053] In Figure 8, source metal 804 covers essentially all portions of the active area not covered by gate metal 802. Some additional exemplary details of the second metal layer of Figure 2 are shown in Figure 12 below.

[0054] Figures 9A, 9B, 10A, 10B, 11A, 11B, 12A, and 12B are diagrams showing cross-sectional views of an exemplary manufacturing process for a semiconductor device including a selectively landed gate array according to the example of Figures 1 through 8. In each of Figures 9A, 10A, 11A, and 12A, the upper X-direction cross-section generally corresponds to the cross-sectional view of Figure 3, and in each of Figures 9B, 10B, 11B, and 12B, the lower Y-direction cross-section generally corresponds to the cross-sectional view of Figure 4.

[0055] 9A and 9B, gate oxide 214 is formed, followed by an annealing process, followed by deposition of doped polysilicon material and then etched to form gate electrode 202. A mask layer (not shown) may be used to form source contact 203. Dielectric 216 may be formed as a layer of BPSG in a reflow process.

[0056] Thus, cross section 900a shows space for gate feed lines and gate pad contacts formed on either side of BPSG dielectric 216 such that the width of BPSG dielectric 216 provides the type of slot 180 in Figure 1, e.g., 224 in Figures 2 and 3, or 680 (or 680a) in Figure 6. Cross section 900b shows the establishment of openings in BPSG dielectric 216, including openings 906 for a first array of gate subsets and openings 908 for a first array of source subsets, to form, for example, a first array of tungsten plugs in a first plug layer.

[0057] 10A and 10B show the addition of gate plug 204 and source plug 206, respectively. A layer of cladding metal 222 is added, followed by buffer layer 218. Deposition of dielectric layer 220 can then be performed.

[0058] 11A and 11B, cross sections 1100a and 1100b, respectively, illustrate etching of dielectric layer 220 and buffer layer 218 to form a second array of plugs in the second plug layer. Specifically, second array gate plugs 205 are shown as formed in cross section 1100a, and second array source plugs 207 are shown as formed in cross section 1100b.

[0059] 12A and 12B show the formation of a first metal layer including gate pad contact 250 and source pad contacts 304 and 1204, respectively. An intermetal dielectric layer 1206 and a passivation layer 1208 are then formed. A second metal layer including gate contact 1210 and source contact 1212 can then be formed.

[0060] Figure 13 is a schematic diagram illustrating a top view of an alternative example of a semiconductor device including a selectively landed gate array. In Figure 13, gate pad contact runner 1302, similar to gate pad contact runner 170 of Figure 1, may be connected by a gate plug in the second plug layer, for example, similar to gate plug 205 of Figures 2-5. The gate plug in the second plug layer is not visible in Figure 13 because it is obscured by gate pad contact runner 1302.

[0061] For example, gate plugs in the first plug layer similar to gate plugs 204 of Figures 2-5 form grid 1304 of Figure 13. That is, grid 1304 can be understood from the foregoing description to be formed on underlying gate electrodes that are not visible in Figure 13 because they are obscured by grid 1304. In the example of Figure 13, the illustrated cell design includes all of the gate electrodes interconnected such that redistributed gate runners are not required for signal propagation. In alternative implementations, the square cell layout of Figure 13 can be replaced with other layouts, such as a hexagonal layout.

[0062] The oval region 1306 represents slotting of the gate plug, i.e., grid 1304, in the first plug layer near the gate pad contact runner 1302 (and near the underlying gate plug in the second plug layer). The oval region 1306 thus represents the internal Rg section through which the gate current passes through the active gate material (e.g., a doped polysilicon gate electrode). Any shape (e.g., circular, oval, square, or rectangular) may be used. Additionally or alternatively, slotting may be performed at other locations within the grid 1304.

[0063] Figure 14 is a flowchart illustrating an exemplary process flow for fabricating the device of Figures 1-13. In the example of Figure 14, a plurality of transistors including a plurality of source regions and a plurality of gate electrodes may be formed in a substrate (1402). A first dielectric layer may be formed over the plurality of source regions and the plurality of gate electrodes (1404).

[0064] A first array of low-resistivity material can be formed in the first dielectric layer, with a gate subset of the first array formed on the plurality of gate electrodes and a source subset of the first array formed on the plurality of source regions 1406. For example, a first plug layer can be formed including a tungsten material (e.g., tungsten plugs).

[0065] A second dielectric layer can be formed on the first dielectric layer and the first array (1408). A second array of low-resistivity material can be formed in the second dielectric layer, with a second array of gate subsets formed on the first array of gate subsets, thereby electrically connecting to the plurality of gate electrodes, and a second array of source subsets formed on the first array of source subsets, thereby electrically connecting to the plurality of source regions (1410). For example, a second plug layer can be formed, including a tungsten material (e.g., tungsten plugs).

[0066] A gate pad metal and a source pad metal can be formed on the second dielectric layer 1412. For example, a gate pad metal can be formed on the second dielectric layer and electrically connected to a subset of gates in the second array, and a source pad metal can be formed on the second dielectric layer and electrically connected to a subset of sources in the second array.

[0067] In various exemplary implementations described herein and other exemplary implementations, various transistor devices may be provided as planar gate devices or trench gate devices. Depending on the specific configuration and / or doping profile of the elements of the transistor devices, such transistor devices may implement vertical field effect transistors (FETs) or insulated gate bipolar transistors (IGBTs).

[0068] In exemplary implementations described herein, the transistor device may be implemented as a vertical transistor implemented in a substrate, which may be a heavily doped n-type substrate such as a SiC substrate or another semiconductor substrate. Such a vertical transistor device may also include an epitaxial layer 302, which may be an n-type epitaxial layer having a doping concentration lower than that of the underlying substrate. For example, such a substrate may include or implement the drain terminal (or collector terminal in an IGBT implementation) of the vertical transistor. The epitaxial layer may implement the drift region of the vertical transistor. The majority carrier flow in the foregoing examples is electrons, but becomes holes when the conductivity type of the vertical transistor is reversed, switching between n-type and p-type conductivity.

[0069] A vertical transistor may include a body region, which may be a p-type well region, which may also be referred to as a bulk region. A source region (or emitter region, in the case of an IGBT implementation) may be disposed within the body region. In operation, application of an appropriate bias to the gate electrode forms a conduction channel from the source region through the body region to the epitaxial layer (e.g., to the drift region of a vertical transistor).

[0070] A first exemplary implementation, referred to as Example 1, includes a semiconductor device, the semiconductor device comprising: a plurality of transistors each including a plurality of source regions and a plurality of gate electrodes; a first dielectric layer formed on the plurality of source regions and the plurality of gate electrodes; a first array of low resistance material formed in the first dielectric layer, a gate subset of the first array formed over a plurality of gate electrodes and a source subset of the first array formed over a plurality of source regions; a second dielectric layer formed on the first dielectric layer and on the first array; a second array of low resistance material formed in the second dielectric layer, a subset of gates of the second array formed on a subset of gates of the first array, thereby electrically connecting to the plurality of gate electrodes, and a subset of sources of the second array formed on a subset of sources of the first array, thereby electrically connecting to the plurality of source regions; a gate pad metal formed on the second dielectric layer and electrically connected to a subset of gates in the second array; a source pad metal formed on the second dielectric layer and electrically connected to the source subset of the second array.

[0071] Example 2 includes the semiconductor device of Example 1, wherein the first array and the second array are linear arrays, the gate subsets of the first array and the source subsets of the first array are parallel to each other, the gate subsets of the second array land on the gate subsets of the first array, and the source subsets of the second array land on the source subsets of the first array.

[0072] Example 3 includes the semiconductor device of example 1, wherein the gate pad metal and the source pad metal are disposed in the first metal layer, and further comprising: A gate runner is disposed in the first metal layer, separate from the gate pad metal, and connected to the gate pad metal by a subset of gates in the first array and a subset of gates in the second array.

[0073] Example 4 includes the semiconductor device of Example 1, wherein at least one of the gate subsets of the first array has a slot formed above an underlying gate electrode of the plurality of gate electrodes, whereby the first dielectric layer contacts the underlying gate electrode within the slot, such that a gate current through at least one of the gate subsets is directed below the slot and through the underlying gate electrode during operation of the semiconductor device.

[0074] Example 5 includes the semiconductor device of example 4, wherein each of the subset of gates in the first array connected to the gate pad metal by a corresponding one of the subset of gates in the second array has a slot formed above the underlying gate electrode such that all of the gate current through the gate pad metal traverses the underlying gate electrode during operation of the semiconductor device.

[0075] Example 6 includes the semiconductor device of example 1; the first array and the second array comprise tungsten; The plurality of gate electrodes include doped polysilicon.

[0076] Example 7 includes the semiconductor device of example 1, wherein the plurality of transistors are included in a silicon carbide (SiC) semiconductor region.

[0077] Example 8 includes the semiconductor device of example 7; The plurality of transistors includes vertical field effect transistors (FETs), and the SiC semiconductor region includes a drift region of the vertical FET and a drain region of the vertical FET.

[0078] Example 9 includes the semiconductor device of example 7; The plurality of transistors include vertical insulated gate bipolar transistors (IGBTs), the plurality of source regions include emitter regions of the vertical IGBTs, and the SiC semiconductor region includes a drift region of the vertical IGBTs and a collector region of the vertical IGBTs.

[0079] A tenth exemplary implementation, referred to as Example 10, includes a semiconductor device, the semiconductor device comprising: a plurality of transistors each including a plurality of source regions and a plurality of gate electrodes; a first array of low resistance plug material formed in the first plug layer over the plurality of transistors, a gate subset of the first array formed over the plurality of gate electrodes and a source subset of the first array formed over the plurality of source regions; a second array of low resistance plug material formed in a second plug layer on the first plug layer, a subset of gates of the second array formed on the subset of gates of the first array, thereby electrically connecting to the plurality of gate electrodes, and a subset of sources of the second array formed on the subset of sources of the first array, thereby electrically connecting to the plurality of source regions; a gate pad metal formed in the first metal layer over the second plug layer and electrically connected to a subset of gates in the second array; a source pad metal formed in the first metal layer and electrically connected to the source subset of the second array.

[0080] Example 11 includes the semiconductor device of example 10, wherein the first array and the second array are linear arrays, the gate subsets of the first array and the source subsets of the first array are parallel to each other, the gate subsets of the second array land on the gate subsets of the first array, and the source subsets of the second array land on the source subsets of the first array.

[0081] Example 12 includes the semiconductor device of example 10, wherein the semiconductor device comprises: The semiconductor device further comprises a gate runner disposed in the first metal layer, separate from the gate pad metal, and connected to the gate pad metal by a subset of gates in the first array and a subset of gates in the second array.

[0082] Example 13 includes the semiconductor device of example 10, wherein at least one of the gate subsets of the first array has a slot formed above an underlying gate electrode of the plurality of gate electrodes, whereby the first dielectric layer contacts the underlying gate electrode within the slot, such that a gate current through at least one of the gate subsets is directed below the slot to pass through the underlying gate electrode during operation of the semiconductor device.

[0083] Example 14 includes the semiconductor device of example 13, wherein each of the subset of gates in the first array connected to the gate pad metal by a corresponding one of the subset of gates in the second array has a slot formed above the underlying gate electrode such that all of the gate current through the gate pad metal traverses the underlying gate electrode during operation of the semiconductor device.

[0084] Example 15 includes the semiconductor device of example 10; the first array and the second array comprise tungsten; The plurality of gate electrodes include doped polysilicon.

[0085] Example 16 includes the semiconductor device of example 10, wherein the plurality of transistors are included in a silicon carbide (SiC) semiconductor region.

[0086] A seventeenth example, herein referred to as Example 17, includes a method of fabricating a semiconductor device, the method comprising: forming a plurality of transistors in a substrate, each transistor including a plurality of source regions and a plurality of gate electrodes; forming a first dielectric layer over the plurality of source regions and the plurality of gate electrodes; forming a first array of low resistance material in the first dielectric layer, a gate subset of the first array formed over the plurality of gate electrodes and a source subset of the first array formed over the plurality of source regions; forming a second dielectric layer over the first dielectric layer and over the first array; forming a second array of low resistance material in the second dielectric layer, a subset of gates of the second array formed on the subset of gates of the first array and thereby electrically connected to the plurality of gate electrodes, and a subset of sources of the second array formed on the subset of sources of the first array and thereby electrically connected to the plurality of source regions; forming a gate pad metal on the second dielectric layer and electrically connecting to the subset of gates in the second array; forming a source pad metal on the second dielectric layer and electrically connecting to the source subset of the second array;

[0087] Example 18 includes the method of example 17, further comprising: forming the first array and the second array as linear arrays, wherein the gate subset of the first array and the source subset of the first array are parallel to one another; landing a subset of gates of a second array on a subset of gates of a first array; and landing the source subset of the second array on the source subset of the first array.

[0088] Example 19 includes the method of example 17, wherein the gate pad metal and the source pad metal are disposed in the first metal layer, further comprising: Further comprising providing a gate runner in the first metal layer separate from the gate pad metal and connected to the gate pad metal by a subset of gates in the first array and a subset of gates in the second array.

[0089] Example 20 includes the method of example 17, further comprising: further including forming a slot above an underlying gate electrode of the plurality of gate electrodes in at least one of the gate subsets of the first array, whereby the first dielectric layer contacts the underlying gate electrode within the slot, such that a gate current through at least one of the gate subsets is directed through the underlying gate electrode below the slot during operation of the semiconductor device.

[0090] In the foregoing description, when an element, such as a layer, region, substrate, or component, is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled with another element, it will be understood that it can be directly disposed on, connected to, or coupled with the other element, or that one or more intervening elements may be present. Conversely, when an element is referred to as being directly on, directly connected to, or directly coupled with another element or layer, no intervening elements or layers are present. Throughout the detailed description of the present invention, the terms direct, directly connected, or directly coupled may not be used, but elements shown as being directly on, directly connected, or directly coupled may be referred to as such. The claims of this application (if included) may be amended to describe the exemplary relationships described herein or shown in the drawings.

[0091] As used in this specification and claims, the singular can include the plural unless the context clearly dictates otherwise. Spatially relative terms (e.g., throughout, above, above, below, lower, underneath, below, etc.) are intended to encompass different orientations of the device during use or operation in addition to the orientation depicted in the drawings. In some implementations, the relative terms above and below can include vertically above and vertically below, respectively. In some implementations, the term adjacent can include laterally adjacent or horizontally adjacent.

[0092] Some implementations may be implemented using various semiconductor processing and / or packaging technologies, such as, but not limited to, silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), and / or other types of semiconductor processing technologies associated with semiconductor substrates.

[0093] While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. It will therefore be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. These have been presented by way of example only, and not limitation, and it will be understood that various changes in form and detail may be made. Any portion of the apparatus and / or methods described herein may be combined in any combination except mutually exclusive combinations. The implementations described herein may include various combinations and / or subcombinations of functions, components, and / or features of the different implementations described.

[0094] While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents will now occur to those of ordinary skill in the art. It is therefore to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the embodiments.

Claims

1. A semiconductor device comprising: a plurality of transistors (110) including a plurality of source regions (212) and a plurality of gate electrodes (202); a first dielectric layer (216) formed on the plurality of source regions (212) and the plurality of gate electrodes (202); a first array (204, 206) of low resistance material formed in the first dielectric layer, a gate subset (204) of the first array formed on the plurality of gate electrodes and a source subset (206) of the first array formed on the plurality of source regions; a second dielectric layer (220) formed on the first dielectric layer (216) and on the first array (204, 206); a second array (205, 207) of low-resistivity material formed in the second dielectric layer, wherein a gate subset (205) of the second array is formed on the gate subset (204) of the first array, thereby electrically connecting to the plurality of gate electrodes (202), and a source subset (207) of the second array is formed on the source subset (206) of the first array, thereby electrically connecting to the plurality of source regions (212); a gate pad metal (140) formed on the second dielectric layer (220) and electrically connected to the gate subset (205) of the second array; a source pad metal (304) formed on the second dielectric layer (220) and electrically connected to the source subset (207) of the second array.

2. 2. The semiconductor device of claim 1, wherein the first array (204, 206) and the second array (205, 207) are linear arrays, the gate subset (204) of the first array and the source subset (206) of the first array are parallel to each other, the gate subset (205) of the second array lands on the gate subset (204) of the first array, and the source subset (207) of the second array lands on the source subset (206) of the first array.

3. the gate pad metal (250) and the source pad metal (304) are disposed in a first metal layer; 2. The semiconductor device of claim 1, further comprising a gate runner (150, 160, 170, 250) disposed within the first metal layer, separate from the gate pad metal (140), and connected to the gate pad metal by the subset of gates (204) of the first array and the subset of gates (205) of the second array.

4. 2. The semiconductor device of claim 1, wherein at least one of the gate subsets of the first array has a slot formed above an underlying gate electrode of the plurality of gate electrodes, whereby the first dielectric layer contacts the underlying gate electrode within the slot, such that a gate current through the at least one of the gate subsets is directed below the slot through the underlying gate electrode during operation of the semiconductor device.

5. 5. The semiconductor device of claim 4, wherein each of the gate subsets (204) of the first array connected to the gate pad metal by a corresponding one of the gate subsets (205) of the second array is slotted above an underlying gate electrode such that all of the gate current through the gate pad metal (140) traverses the underlying gate electrode during operation of the semiconductor device.

6. the first array (204, 206) and the second array (205, 207) comprise tungsten; the plurality of gate electrodes (202) comprise doped polysilicon; The semiconductor device of claim 1 .

7. The semiconductor device of claim 1 , wherein the plurality of transistors are included in a silicon carbide (SiC) semiconductor region.

8. The plurality of transistors include vertical field effect transistors (FETs), and the SiC semiconductor region includes a drift region of the vertical FET, a drain region of the vertical FET, and 8. The semiconductor device of claim 7, comprising:

9. the plurality of transistors include vertical insulated gate bipolar transistors (IGBTs), the plurality of source regions include emitter regions of the vertical IGBTs, and the SiC semiconductor region includes a drift region of the vertical IGBT and a collector region of the vertical IGBT; 8. The semiconductor device of claim 7, comprising:

10. A semiconductor device comprising: a plurality of transistors (110) including a plurality of source regions (212) and a plurality of gate electrodes (202); a first array (204, 206) of low resistance plug material formed in a first plug layer over the plurality of transistors, a gate subset (204) of the first array formed over the plurality of gate electrodes (202) and a source subset (206) of the first array formed over the plurality of source regions (212); a second array (205, 207) of low resistance plug material formed in a second plug layer on the first plug layer, wherein a gate subset (205) of the second array is formed on the gate subset (204) of the first array, thereby electrically connecting to the plurality of gate electrodes (202), and a source subset (207) of the second array is formed on the source subset (206) of the first array, thereby electrically connecting to the plurality of source regions (212); a gate pad metal (140) formed in a first metal layer over the second plug layer and electrically connected to the subset of gates in the second array; a source pad metal (304) formed in the first metal layer and electrically connected to the source subset of the second array.

11. 11. The semiconductor device of claim 10, wherein the first array (204, 206) and the second array (205, 207) are linear arrays, the gate subset (204) of the first array and the source subset (206) of the first array are parallel to each other, the gate subset (205) of the second array lands on the gate subset (204) of the first array, and the source subset (207) of the second array lands on the source subset (206) of the first array.

12. a gate runner (150, 160, 170, 250) disposed within the first metal layer, separate from the gate pad metal (140), and connected to the gate pad metal by the gate subset (204) of the first array and the gate subset (205) of the second array; The semiconductor device of claim 10 further comprising:

13. 11. The semiconductor device of claim 10, wherein at least one of the gate subsets of the first array has a slot formed above an underlying gate electrode of the plurality of gate electrodes, whereby the first dielectric layer contacts the underlying gate electrode within the slot, such that a gate current through the at least one of the gate subsets is directed below the slot and through the underlying gate electrode during operation of the semiconductor device.

14. 14. The semiconductor device of claim 13, wherein each of the gate subsets (204) of the first array connected to the gate pad metal by a corresponding one of the gate subsets (205) of the second array is slotted above an underlying gate electrode such that all of the gate current passing through the gate pad metal (140) traverses the underlying gate electrode during operation of the semiconductor device.

15. the first array (204, 206) and the second array (205, 207) comprise tungsten; the plurality of gate electrodes (202) comprise doped polysilicon; The semiconductor device of claim 10.

16. The semiconductor device of claim 10 , wherein the plurality of transistors are included in a silicon carbide (SiC) semiconductor region.

17. 1. A method of fabricating a semiconductor device, comprising: forming (1402) a plurality of transistors (110) in a substrate, the plurality of transistors including a plurality of source regions (212) and a plurality of gate electrodes (202); forming a first dielectric layer (216) formed on the plurality of source regions (212) and the plurality of gate electrodes (202); forming (1406) a first array (204, 206) of low resistance material formed in the first dielectric layer, wherein a gate subset (204) of the first array is formed on the plurality of gate electrodes and a source subset (206) of the first array is formed on the plurality of source regions; forming (1408) a second dielectric layer (220) formed on the first dielectric layer (216) and on the first array (204, 206); forming (1410) a second array (205, 207) of low resistance material formed in the second dielectric layer, wherein a gate subset (205) of the second array is formed on the gate subset (204) of the first array, thereby electrically connecting to the plurality of gate electrodes (202), and a source subset (207) of the second array is formed on the source subset (206) of the first array, thereby electrically connecting to the plurality of source regions (212); forming (1412) a gate pad metal (140) formed on the second dielectric layer (220) and electrically connected to the gate subset (205) of the second array; forming (1412) a source pad metal (304) formed on the second dielectric layer (220) and electrically connected to the source subset (207) of the second array.

18. forming the first array (204, 206) and the second array (205, 207) as linear arrays, wherein the gate subset (204) of the first array and the source subset (206) of the first array are parallel to each other; Landing the gate subset (205) of the second array on the gate subset (204) of the first array; landing the source subset (207) of the second array on the source subset (206) of the first array; 20. The method of claim 17, further comprising:

19. the gate pad metal and the source pad metal are disposed in a first metal layer; 18. The method of claim 17, further comprising providing a gate runner (150, 160, 170, 250) in the first metal layer that is separate from the gate pad metal (140) and connected to the gate pad metal (140) by the gate subset (204) of the first array and the gate subset (205) of the second array.

20. forming a slot (224) above an underlying gate electrode (202) of the plurality of gate electrodes in at least one of the gate subsets (204) of the first array, whereby the first dielectric layer (216) is in contact with the underlying gate electrode within the slot (224), such that a gate current through the at least one of the gate subsets is directed below the slot and through the underlying gate electrode during operation of the semiconductor device; 20. The method of claim 17, further comprising:

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