Electrical Connection Test

Abstract

A method for testing an array of devices, each device having an electrical connection between two electrodes controllable by a signal applied to a control element, the method comprising: applying a reference potential to a first of the two electrodes of each device; directing a charged particle beam onto a second of the two electrodes of each device; varying the signal applied to the control element of each device; and monitoring a signal charged particle from the second electrode of each device for each applied signal.

Description

[Technical Field]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to European Patent Application No. 22201818.6, filed October 17, 2022, which is incorporated herein by reference in its entirety.

[0002]

[0002] Embodiments provided herein disclose a method for testing an array of devices, a charged particle optical apparatus for testing an array of devices, a substrate including a two-dimensional array of logic transistors within a test area, and a non-transitory computer-readable medium. [Background technology]

[0003]

[0003] In the integrated circuit (IC) manufacturing process, unfinished or completed circuit components are inspected to ensure they are manufactured according to design and free of defects. Inspection systems can be employed that utilize optical microscopes, such as scanning electron microscopes (SEMs), or charged particle (e.g., electron) beam microscopes. As the physical size of IC components continues to shrink and their structures become more complex, the accuracy and throughput of defect detection and inspection become even more important. Overall image quality depends, among other things, on a combination of high detection efficiency for secondary electron signals and backscattered electron signals. Because backscattered electrons have high emission energies upon escaping from deep layers of a sample, their detection can be desirable in imaging complex structures such as buried layers, nodes, and high-aspect-ratio trenches or holes in 3D NAND devices. In applications such as overlay metrology, it can be desirable to simultaneously obtain high-quality imaging and efficient collection of surface information from secondary electrons and buried layer information from backscattered electrons, highlighting the need for using multiple electron detectors in SEMs. Although multiple electron detectors of various structural arrangements can be used to maximize the collection and detection efficiency of secondary and backscattered electrons individually, the overall detection efficiency remains low and therefore the achieved image quality may be insufficient for high-precision and high-throughput defect inspection and metrology of two-dimensional and three-dimensional structures. Summary of the Invention

[0004]

[0004] One embodiment of the present disclosure provides a method for testing an array of devices, each device having an electrical connection between two electrodes controllable by a signal applied to a control element, the method including applying a reference potential to a first of the two electrodes of each device, directing a charged particle beam onto a second of the two electrodes of each device, varying the signal applied to the control element of each device, and monitoring the signal charged particle from the second electrode of each device for each applied signal.

[0005]

[0005] One embodiment of the present disclosure provides a charged particle optical apparatus for testing an array of devices, each device having an electrical connection between two electrodes controllable by a signal applied to a control element, and an electron optical apparatus including a reference voltage source configured to supply a reference potential to a first of the two electrodes of each device, a charged particle optical device configured to direct a charged particle beam onto a second of the two electrodes of each device, a signal source configured to vary the signal applied to the control element of each device, and a detector for monitoring a signal charged particle from the second electrode of each device for each applied signal.

[0006]

[0006] One embodiment of the present disclosure provides a substrate including an array of devices within a test area, each device having an electrical connection between a source electrode and a drain electrode that is controllable by a potential applied to a gate electrode, wherein either the source electrode or the drain electrode is connected to a common reference junction, and the source electrode and the drain electrode that is not connected to the common reference junction are electrically coupled to respective electrode contacts exposed on the surface of the substrate.

[0007]

[0007] One embodiment of the present disclosure provides a non-transitory computer-readable medium storing instructions for a processor of a controller to execute a method for testing an array of devices, each device having an electrical connection between two electrodes controllable by a signal applied to a control element, the method including controlling the application of a reference potential to a first of the two electrodes of each device, controlling the direction of a charged particle beam onto a second of the two electrodes of each device, controlling variation of the signal applied to the control element of each device, and controlling monitoring of a signal charged particle from the second electrode of each device for each applied signal.

[0008]

[0008] Other advantages of the embodiments of the present disclosure will become apparent from the following description, taken in conjunction with the accompanying drawings, in which specific embodiments of the invention are shown by way of illustration and example.

[0009]

[0009] The above and other aspects of the present disclosure will become more apparent from the following description of exemplary embodiments taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a schematic diagram illustrating an exemplary electron beam inspection (EBI) system consistent with an embodiment of the present disclosure. [Figure 2A]

[0011] 2 is a schematic diagram illustrating an example electron beam tool that may be part of the example electron beam inspection system of FIG. 1, consistent with an embodiment of the present disclosure. [Figure 2B] FIG. 2 is a schematic diagram illustrating an example electron beam tool that may be part of the example electron beam inspection system of FIG. 1, consistent with an embodiment of the present disclosure. [Figure 2C] FIG. 2 is a schematic diagram illustrating an example electron beam tool that may be part of the example electron beam inspection system of FIG. 1, consistent with an embodiment of the present disclosure. [Figure 3]

[0012] FIG. 1 is a diagram of an array of logic transistors for testing electrical connections. [Figure 4]

[0013] 10 is a graph showing the relationship between the gate voltage of a logic transistor and signal electrons detected from a drain electrode. [Figure 5]

[0014] FIG. 1 is a diagram of an array of DRAM structures for testing electrical connections. [Figure 6]

[0015] FIG. 1 is a diagram of an array of devices under test (DUTs) with various structures across the array for testing electrical connections. [Figure 7]

[0016] FIG. 1 is a diagram of an array of logic transistors for testing electrical connections. [Figure 8]

[0017] FIG. 8 shows how the logic transistors of FIG. 7 are electrically connected to the surface of the substrate. [Figure 9]

[0018] 1 is a diagram of an alternative arrangement of devices such as logic transistors. [Figure 10]

[0019] 1 is a diagram of an array of different types of DUTs. [Figure 11]

[0020] FIG. 10 illustrates an alternative arrangement of logic transistors for testing electrical connections. [Figure 12]

[0021] FIG. 1 illustrates a typical implementation of device measurement using a charged particle beam. DETAILED DESCRIPTION OF THE INVENTION

[0011]

[0022] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which, unless otherwise stated, like numbers in different drawings represent the same or similar elements. The implementations described in the following description of exemplary embodiments do not represent all implementations. Instead, the implementations are merely examples of apparatus and methods consistent with aspects related to the disclosed embodiments as recited in the appended claims. For example, while some embodiments are described in the context of utilizing electron beams, the disclosure is not so limited. Other types of charged particle beams may be applied as well.

[0012]

[0023] Electronic devices are built with circuits formed on a piece of silicon called a substrate. Many circuits may be formed together on the same piece of silicon, called an integrated circuit, or IC. The size of these circuits has decreased dramatically, allowing more circuits to fit on a substrate. For example, an IC chip in a smartphone can be about the size of a thumbnail yet contain over 2 billion transistors, each less than 1 / 1000 the thickness of a human hair.

[0013]

[0024] Characterization of transistors during the manufacturing process can be done with electrical tests performed by physical probes and metal pads. These test structures require a large area. Realistically, only a few transistors of a given type can be tested per substrate. Embodiments of the present disclosure enable characterization of transistors based on scanning a large number of transistors with, for example, an SEM and detecting secondary electron and backscattered electron signals. The detected signals indicate the extent to which each transistor is switched on. This allows for testing a much larger number of transistors (or other devices capable of switching current flow).

[0014]

[0025] The relative dimensions of components in the drawings may be exaggerated for clarity. Within the following description of the drawings, the same or similar reference numbers refer to the same or similar components or entities, and only the differences with respect to individual embodiments are described. As used herein, unless otherwise stated, the term "or" encompasses all possible combinations unless infeasible. For example, if a component is stated to include A or B, the component may include A, or B, or A and B, unless otherwise stated or infeasible. As a second example, if a component is stated to include A, B, or C, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A, B, and C, unless otherwise stated or infeasible.

[0015]

[0026] Referring now to FIG. 1 , FIG. 1 illustrates an exemplary EBI system 10 that may include a detector consistent with embodiments of the present disclosure. The EBI system 10 can be used for imaging. As shown in FIG. 1 , the EBI system 10 includes a main chamber 11, a load / lock chamber 20, an electron beam tool 100, and an equipment front-end module (EFEM) 30. The electron beam tool 100 is located within the main chamber 11. The EFEM 30 includes a first load port 30 a and a second load port 30 b. The EFEM 30 may include additional load ports. The first load port 30 a and the second load port 30 b receive wafers (e.g., semiconductor wafers or wafers made of other materials) or wafer front-opening integrated pods (FOUPs) containing samples to be inspected (the wafers and samples may be collectively referred to herein as “samples”).

[0016]

[0027] One or more robot arms (not shown) of the EFEM 30 can transfer wafers to the load / lock chamber 20. The load / lock chamber 20 is connected to a load / lock vacuum pumping system (not shown) that removes gas molecules from the load / lock chamber 20 to reach a first pressure below atmospheric pressure. After the first pressure is reached, one or more robot arms (not shown) can transfer the wafers from the load / lock chamber 20 to the main chamber 11. The main chamber 11 is connected to a main chamber vacuum pumping system (not shown) that removes gas molecules from the main chamber 11 to reach a second pressure below the first pressure. After the second pressure is reached, the wafers are subjected to inspection by the electron beam tool 100. The electron beam tool 100 can be a single-beam system or a multi-beam system. A controller 109 is electronically connected to the electron beam tool 100 and can be electronically connected to other components as well. The controller 109 can be a computer configured to perform various controls of the EBI system 10. In FIG. 1, the controller 109 is shown as being external to the structure including the main chamber 11, the load / lock chamber 20 and the EFEM 30, but it is understood that the controller 109 may also be part of the structure.

[0017]

[0028] FIG. 2A illustrates a charged particle beam device in which the inspection system may include a multi-beam inspection tool that uses multiple primary electron beamlets to simultaneously scan multiple locations on a sample.

[0018]

[0029] As shown in FIG. 2A , the electron beam tool 100A (also referred to herein as an electron beam apparatus 100A or an electron optical device) may include an electron source 202, a gun aperture 204, a condenser lens 206, a primary electron beam 210 emitted from the electron source 202, a source conversion unit 212, multiple beamlets 214, 216, and 218 of the primary electron beam 210, a primary projection optics 220, a wafer stage (not shown in FIG. 2A ), multiple secondary electron beams 236, 238, and 240, a secondary optics 242, and an electron detection device 244. The electron source 202 may generate primary particles, such as electrons in the primary electron beam 210. A controller, an image processing system, and the like may be coupled to the electron detection device 244. The primary projection optics 220 may include a beam separator 222, a deflection scanning unit 226, and an objective lens 228. The electronic detection device 244 may include detection sub-regions 246 , 248 , 250 .

[0019]

[0030] The electron source 202, gun aperture 204, condenser lens 206, source conversion unit 212, beam separator 222, deflection scanning unit 226, and objective lens 228 can be aligned with a primary optical axis 260 of the electron beam device 100A. The secondary optics 242 and electron detection device 244 can be aligned with a secondary optical axis 252 of the electron beam device 100A.

[0020]

[0031] The electron source 202 may include a cathode, extractor, or anode, and primary electrons may be emitted from the cathode and extracted or accelerated to form a primary electron beam 210 with a crossover (virtual or real) 208. The primary electron beam 210 may be visualized as being emitted from the crossover 208. The gun aperture 204 may block peripheral electrons of the primary electron beam 210 to reduce the size of the probe spots 270, 272, 274.

[0021]

[0032] The source conversion unit 212 may include an image-forming element array (not shown in FIG. 2A ) and a beam-limiting aperture array (not shown in FIG. 2A ). Examples of the source conversion unit 212 are described in U.S. Pat. No. 9,691,586, U.S. Patent Application Publication No. 2017 / 0025243, and International Patent Application No. PCT / EP2017 / 084429, all of which are incorporated herein by reference in their entireties. The image-forming element array may include an array of micro-deflectors or micro-lenses. The image-forming element array may form multiple parallel images (virtual or real) of the crossover 208 with multiple beamlets 214, 216, and 218 of the primary electron beam 210. The beam-limiting aperture array may limit the multiple beamlets 214, 216, and 218.

[0022]

[0033] The condenser lens 206 can focus the primary electron beam 210. The current of the beamlets 214, 216, and 218 downstream of the source conversion unit 212 can be varied by adjusting the focusing power of the condenser lens 206 or by changing the radial size of the corresponding beam-limiting aperture in the beam-limiting aperture array. The condenser lens 206 can be a movable condenser lens that can be configured to have a movable first principal plane. The movable condenser lens can be configured to be magnetic, so that the off-axis beamlets 216 and 218 land on the beamlet-limiting aperture at a rotation angle. The rotation angle varies with the focusing power and the position of the first principal plane of the movable condenser lens. In some embodiments, the movable condenser lens can be a movable anti-rotation condenser lens that includes an anti-rotation lens having a movable first principal plane. Movable condenser lenses are further described in U.S. Patent Application Publication No. 2017 / 0025241, which is incorporated herein by reference in its entirety.

[0023]

[0034] The objective lens 228 can focus the beamlets 214 , 216 , 218 onto a wafer 230 (ie, a sample) for inspection, and can form multiple probe spots 270 , 272 , 274 on the surface of the wafer 230 .

[0024]

[0035] The beam separator 222 may be a Wien filter-type beam separator that generates an electrostatic dipole field and a magnetic dipole field. In some embodiments, when these fields are applied, the force exerted on the electrons of the beamlets 214, 216, and 218 by the electrostatic dipole field may be equal in magnitude and opposite in direction to the force exerted on the electrons by the magnetic dipole field. Thus, the beamlets 214, 216, and 218 may pass straight through the beam separator 222 with zero deflection angle. However, the total dispersion of the beamlets 214, 216, and 218 generated by the beam separator 222 may be non-zero. The beam separator 222 may separate the secondary electron beams 236, 238, and 240 from the beamlets 214, 216, and 218 and direct the secondary electron beams 236, 238, and 240 toward the secondary optics 242.

[0025]

[0036] The deflection scanning unit 226 can deflect the beamlets 214, 216, 218 to scan the probe spots 270, 272, 274 across the surface area of ​​the wafer 230. In response to the beamlets 214, 216, 218 impinging on the probe spots 270, 272, 274, secondary electron beams 236, 238, 240 can be emitted from the wafer 230. The secondary electron beams 236, 238, 240 can include electrons having an energy distribution, including secondary electrons and backscattered electrons. The secondary optics 242 can focus the secondary electron beams 236, 238, 240 onto detection subregions 246, 248, 250 of the electron detection device 244. The detection subregions 246, 248, 250 can be configured to detect the corresponding secondary electron beams 236, 238, 240 and generate corresponding signals used to reconstruct an image of the surface area of ​​the wafer 230.

[0026]

[0037] 2A shows an example of electron beam tool 100 as a multi-beam tool using multiple beamlets, embodiments of the present disclosure are not so limited. For example, electron beam tool 100 may be a single-beam tool that uses only one primary electron beam to scan locations on the wafer one at a time.

[0027]

[0038] As shown in FIG. 2B , electron beam tool 100B (also referred to herein as electron beam apparatus 100B) can be a single-beam inspection tool used in EBI system 10. Electron beam apparatus 100B includes an electron optical device configured to project electrons toward a sample location (i.e., where a wafer is located) and a wafer holder 136 supported by a motorized stage 134 for holding a wafer 150 (i.e., the sample) to be inspected. Electron beam tool 100B includes an electron emitter, which can include a cathode 103, an anode 121, and a gun aperture 122. Electron beam tool 100B further includes a beam-limiting aperture 125, a condenser lens 126, a column aperture 135, an objective lens assembly 132, and a detector 144. In some embodiments, the objective lens assembly 132 may be a modified SORIL lens and includes a pole piece 132a, a control electrode 132b, a deflector 132c, and an excitation coil 132d. During the imaging process, an electron beam 161 emanating from the tip of the cathode 103 is accelerated by the anode 121 voltage, passes through the gun aperture 122, the beam-limiting aperture 125, and the condenser lens 126, and is focused by the modified SORIL lens to a probe spot 170, which can impinge on the surface of the wafer 150. The probe spot 170 can be scanned across the surface of the wafer 150 by a deflector, such as deflector 132c or another deflector in a SORIL lens. Secondary or scattered primary particles, such as secondary electrons or scattered primary electrons emanating from the wafer surface, can be collected by a detector 144 to determine the beam intensity, allowing an image of the area of ​​interest on the wafer 150 to be reconstructed.

[0028]

[0039] An image processing system 199 may also be provided, including the image acquirer 120, the storage 130, and the controller 109. The image acquirer 120 may include one or more processors. For example, the image acquirer 120 may include a computer, a server, a mainframe host, a terminal, a personal computer, any type of mobile computing device, and the like, or a combination thereof. The image acquirer 120 may be connected to the detector 144 of the electron beam tool 100B through a medium such as an electrical conductor, a fiber optic cable, a portable storage medium, IR, Bluetooth, the Internet, a wireless network, wireless radio, or a combination thereof. The image acquirer 120 may receive signals from the detector 144 and construct an image. Thus, the image acquirer 120 may acquire an image of the wafer 150. The image acquirer 120 may also perform various post-processing functions, such as generating contours, overlaying indicators on the acquired image, and the like. The image acquirer 120 may be configured to perform adjustments, such as brightness and contrast, of the acquired image. The storage 130 may be a storage medium such as a hard disk, random access memory (RAM), cloud storage, other types of computer-readable memory, and the like. The storage 130 may be coupled to the image acquirer 120 and may be used to store raw scanned image data as original images or to store post-processed images. The image acquirer 120 and the storage 130 may be connected to the controller 109. In some embodiments, the image acquirer 120, the storage 130, and the controller 109 may be integrated together as one electronic control unit.

[0029]

[0040] In some embodiments, the image acquirer 120 can acquire one or more images of the sample based on an imaging signal received from the detector 144. The imaging signal can correspond to a scanning motion for performing charged particle imaging. The acquired image can be a single image including multiple imaging areas that can include various features of the wafer 150. The single image can be stored in the storage 130. The imaging can be performed based on imaging frames.

[0030]

[0041] The condenser and illumination optics of an electron beam tool may include or be supplemented by electromagnetic quadrupole electron lenses. For example, as shown in FIG. 2B, electron beam tool 100B may include a first quadrupole lens 148 and a second quadrupole lens 158. In some embodiments, the quadrupole lenses are used to control the electron beam. For example, first quadrupole lens 148 may be controlled to adjust the beam current, and second quadrupole lens 158 may be controlled to adjust the beam spot size and beam shape.

[0031]

[0042] FIG. 2B illustrates a charged particle beam device in which the inspection system can use a single primary beam that can be configured to generate secondary electrons by interacting with the wafer 150. As in the embodiment shown in FIG. 2B, the detector 144 can be positioned along the optical axis 105. The primary electron beam can be configured to travel along the optical axis 105. Accordingly, the detector 144 can include a hole in its center to allow the primary electron beam to pass through and reach the wafer 150. However, some embodiments can use a detector that is positioned off-axis with respect to the optical axis along which the primary electron beam travels. For example, as in the embodiment shown in FIG. 2A, a beam separator 222 can be provided to direct the secondary electron beam toward the off-axis detector. The beam separator 222 can be configured to redirect the secondary electron beam by an angle α.

[0032]

[0043] Another example of a charged particle beam device will now be discussed with reference to Figure 2C. The electron beam tool 100C (also referred to herein as electron beam device 100C or electron optical device) may be an example of an electron beam tool 100 and may be similar to the electron beam tool 100A shown in Figure 2A.

[0033]

[0044] As shown in FIG. 2C , beam separator 222 can be a Wien filter-type beam separator that generates electrostatic and magnetic dipole fields. In some embodiments, when these fields are applied, the force exerted on electrons in beamlets 214, 216, and 218 by the electrostatic dipole field can be equal in magnitude and opposite in direction to the force exerted on electrons by the magnetic dipole field. Thus, beamlets 214, 216, and 218 can pass straight through beam separator 222 with zero deflection angle. However, the total dispersion of beamlets 214, 216, and 218 generated by beam separator 222 can be non-zero. With respect to the dispersion plane 224 of beam separator 222, FIG. 2C illustrates the dispersion of beamlet 214, having a nominal energy V and energy width ΔV, into beamlet portion 262 corresponding to energy V, beamlet portion 264 corresponding to energy V+ΔV / 2, and beamlet portion 266 corresponding to energy V−ΔV / 2. The total force exerted by the beam separator 222 on the electrons in the secondary electron beams 236, 238, 240 may be non-zero. The beam separator 222 may separate the secondary electron beams 236, 238, 240 from the beamlets 214, 216, 218 and direct the secondary electron beams 236, 238, 240 towards the secondary optics 242.

[0034]

[0045] A semiconductor electron detector (sometimes referred to as a "PIN detector") can be used in the apparatus 100 of the EBI system 10. The EBI system 10 can be a high-speed wafer imaging SEM including an image processor. The electron beam generated by the EBI system 10 can illuminate the surface of a sample or pass through the sample. The EBI system 10 can be used to image surface or subsurface structures of a sample, such as to analyze layer alignment. In some embodiments, the EBI system 10 can detect and report process defects associated with semiconductor wafer manufacturing, for example, by comparing an SEM image to a device layout pattern or to an SEM image of the same pattern elsewhere on the wafer being inspected. The PIN detector can include a silicon PIN diode that can be operated with a negative bias. The PIN detector can be configured so that incident electrons generate a relatively large and well-defined detection signal. In some embodiments, the PIN detector can be configured so that incident electrons generate multiple electron-hole pairs, while photons generate only one electron-hole pair. PIN detectors used for electron counting can have many differences compared to photodiodes used for photon detection, as discussed below.

[0035]

[0046] In one embodiment, a detector (e.g., the electronic detection device 244 shown in FIG. 2A or 2C or the detector 144 shown in FIG. 2B) includes multiple detector elements (e.g., detection subregions 246, 248, 250). The detector elements can be connected to one or more circuit layers. The detector's circuit layers can include circuits with amplification and / or digitization functions, such as amplifier circuits. The circuit layers can include one or more transimpedance amplifiers (TIAs) and one or more ADCs. The detector elements and associated feedback resistors can be connected to the TIAs and ADCs. One or more digital signal lines can be connected from the ADCs to, for example, the image acquirer 120 shown in FIG. 2B, for transferring digital signals.

[0036]

[0047] In some embodiments, the detector can communicate with a controller that controls the charged particle beam system. The controller can instruct components of the charged particle beam system to perform various functions, such as controlling a charged particle source to generate a charged particle beam and controlling a deflector to scan the charged particle beam. The controller can also perform various other functions, such as adjusting the sampling rate of the detector, resetting the sensing elements, or performing image processing. In one embodiment, the controller is configured to control the settings of the ADC. The controller can include storage, which can be a storage medium such as a hard disk, random access memory (RAM), other types of computer-readable memory, and the like. The storage can be used to save raw scanned image data as original images or post-processed images. A non-transitory computer-readable medium can be provided that stores instructions for a processor of the controller 109 to perform charged particle beam detection, sampling period determination, image processing, or other functions and methods consistent with the present disclosure. Common forms of non-transitory media include, for example, floppy disks, flexible disks, hard disks, solid state drives, magnetic tape or any other magnetic data storage media, CD-ROMs, any other optical data storage media, any physical media with a pattern of holes, ROMs, PROMs and EPROMs, flash EPROMs or any other flash memory, NVRAMs, caches, registers, any other memory chips or cartridges, and network-attached versions thereof.

[0037]

[0048] The block diagrams in the figures may illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer hardware / software products according to various exemplary embodiments of the present disclosure. In this regard, each block in the schematic diagrams may represent a specific arithmetic or logical operation that may be implemented using hardware, such as electronic circuits. The blocks may also represent modules, segments, or portions of code that include one or more executable instructions for implementing the specified logical function(s). It should be understood that in some alternative implementations, the functions shown in the blocks may occur in a different order than that depicted in the figures. For example, depending on the functionality involved, two blocks shown in succession may be executed or performed substantially simultaneously, or the two blocks may be executed in the reverse order. Some blocks may be omitted. It should also be understood that each block of the block diagrams, and combinations of blocks, may be implemented by a dedicated hardware-based system that performs the specified functions or acts, or by a combination of dedicated hardware and computer instructions.

[0038]

[0049] A method for testing electrical connections is disclosed. In one embodiment, the method is for characterizing a device, such as a transistor, on a substrate. Characterizing the device may include determining one or more properties of the device. For example, if the device is a transistor, the transistor may be characterized by one or more of its threshold voltage (on / off gate voltage), its leakage current at zero gate voltage, and its subthreshold IV slope (which determines how sharp the on / off transition is).

[0039]

[0050] Embodiments of the method are described below primarily in terms of testing logic transistors, i.e., transistors used in logic circuits. Such logic transistors may be for binary or analog purposes. However, the method can be applied to testing other devices, particularly devices having an electrical connection between two electrodes that is controllable by a signal applied to a control element (e.g., the gate electrode of a transistor). For example, the device may be a DRAM structure or a photodiode.

[0040]

[0051] FIG. 3 shows a schematic diagram of an array 50 of devices. In the example shown in FIG. 3, the devices are transistors 51. As shown in FIG. 3, in one embodiment, the array 50 is a two-dimensional array. In one embodiment, the transistors 51 are arranged in a regular pattern to form the array 50. In one embodiment, the transistors 51 are arranged in grid columns and rows in the array 50. It is not necessary for the transistors 51 to be arranged in a regular pattern. The transistors 51 may also be arranged in an irregular pattern. A regular pattern facilitates a high density arrangement of the transistors 51 within the array 50.

[0041]

[0052] In one embodiment, array 50 is a test structure for use in characterizing transistors 51. The test structure may not be used in a functional portion of the substrate (e.g., a functional portion of an IC). In one embodiment, the test structure is located in a scribe lane of the substrate. The test structure may be separated when the chips are separated from the substrate.

[0042]

[0053] In one embodiment, the transistors are formed in a particularly dense pattern. For example, in one embodiment, the transistors 51 are arranged at a pitch of at most 500 nm, optionally at most 200 nm, optionally at most 100 nm, optionally at most 50 nm. In one embodiment, the pitch is applicable to both the rows and columns of the grid of the array 50.

[0043]

[0054] In one embodiment, all of the transistors 51 in the array 50 are of the same type. This means that all of the transistors 51 are manufactured to have the same intended characteristics. For example, the transistors 51 may be designed to have the same threshold voltages as one another. Of course, there may be some variation in the actual properties of the transistors 51. It may be desirable to test the array 50 of transistors 51 to determine the actual transistor 51 characteristics. For example, the average (e.g., mean) and / or spread (e.g., standard deviation) of the threshold voltages across the transistors 51 in the array 50 may be determined.

[0044]

[0055] 3, in one embodiment, each device includes two electrodes between which an electrical connection may be made. In the example of transistor 51, the two electrodes may be source electrode 52 and drain electrode 53. When the transistor is switched on, a substantial or significant current may flow between source electrode 52 and drain electrode 53. When transistor 51 is switched off, a sufficiently small current (or no current) may flow between source electrode 52 and drain electrode 53.

[0045]

[0056] In one embodiment, the method includes applying a reference potential to a first of the two electrodes 52, 53 of each device. For example, in the arrangement shown in Figure 3, the reference potential is applied to the source electrode 52 of each transistor 51. In an alternative embodiment, the reference potential may be applied to the drain electrode 53 of each transistor 51.

[0046]

[0057] 3 , in one embodiment, first electrodes (e.g., source electrodes 52) of transistors 51 are connected to a common reference potential to apply a reference potential. For example, all of the source electrodes 52 can be electrically connected to a common reference junction 57. The common reference junction 57 can be a terminal such as a pad. The voltage of the common reference junction 57 can be controlled, thereby controlling the reference potential applied to the source electrodes 52 of the transistors 51. Connecting the transistors 51 to a common reference potential can make it easier to apply a reference potential to each transistor 51. Providing a single common reference junction 57 can reduce the space occupied by the entire test structure.

[0047]

[0058] In one embodiment, the reference potential is ground. For example, ground may be the reference ground potential of an electron optical device such as the electron beam tool 100. Alternatively, a different reference potential may be used.

[0048]

[0059] In one embodiment, the method includes directing (e.g., projecting) a charged particle beam (e.g., electron beam 55) onto a second of two electrodes of each device (e.g., transistor 51). The second electrode is an electrode to which no reference potential is applied. From the perspective of transistor 51, the second electrode is one of source electrode 52 and drain electrode 53. In the example shown in FIG. 3, the second electrode is drain electrode 53. Alternatively, a reference potential may be applied to drain electrode 53, and the charged particle beam may be directed onto source electrode 52.

[0049]

[0060] In one embodiment, the electron beam is projected by an electron optical device of an electron optical apparatus (e.g., electron beam tool 100). In one embodiment, the electron beam is projected simultaneously onto all of the drain electrodes 52. Alternatively, the electron beam may be scanned across the array 50 such that the electron beam is projected sequentially onto the drain electrodes 53.

[0050]

[0061] In one embodiment, the controller 109 is configured to control the landing energy of the electron beam, which is the energy of the electrons at the sample location. In one embodiment, the controller 109 is configured to control the landing energy of the electron beam depending on the type of transistors 51 in the array 50.

[0051]

[0062] For example, if transistor 51 is a PMOS transistor, the landing energy may be controlled to at least 1 keV, optionally at least 2 keV, optionally at least 5 keV, and optionally at least 10 keV. Such landing energies may result in a negative charge on the PMOS transistor such that the pn junction beneath the illuminated drain electrode 53 is reverse biased. The reverse bias means that electrons from the beam do not flow from the exposed drain electrode 53 to the silicon beneath it. Instead, charge can only flow through the channel if it is open, or accumulate on the drain electrode 53 if it is closed.

[0052]

[0063] If transistor 51 is an NMOS transistor, controller 109 may control the landing energy to be at most 1 keV, optionally at most 500 eV, and / or to be at least 100 eV, optionally at least 200 eV, optionally at least 500 eV. Such landing energies may result in a positive charge in the NMOS transistor such that the pn junction under the illuminated drain electrode 53 is reverse biased.

[0053]

[0064] In one embodiment, the method includes varying a signal applied to a control element of each device (e.g., transistor 51). In the example of a device, transistor 51, the control element may be gate electrode 54 of transistor 51. The signal may be an electrical potential. When a voltage above a threshold voltage is applied to gate electrode 54, a substantial or appreciable current may flow between source electrode 52 and drain electrode 53. When a voltage below the threshold voltage is applied to gate electrode 54, no current may flow between source electrode 52 and drain electrode 53.

[0054]

[0065] As shown in FIG. 3 , in one embodiment, the control elements of multiple devices are connected to a common control electrode 59 for applying varying electrical potentials. FIG. 3 shows all of the gate electrodes 54 of the transistors 51 electrically connected to the common control electrode 59. By providing the common control electrode 59, a known electrical potential can be applied to the gate electrodes 54 across the transistors 51 of the array 50. It may be easier to apply and vary electrical potentials to the gate electrodes 54. By providing a common control electrode 59 for multiple transistors 51, the total amount of space occupied by the test structure can be reduced. In particular, it may not be necessary to provide separate pads to apply gate voltages to each transistor individually.

[0055]

[0066] In one embodiment, the signal applied to the control element of each device (e.g., transistor 51) is gradually increased or decreased. For example, if the signal is a potential, the potential applied to the control element can be gradually increased. In one embodiment, the signal is varied by sweeping the signal over a range. In one embodiment, the lower end of the range is a value below the device's threshold signal such that each device is switched off and a dark voltage contrast signal is obtained due to the transistor's high effective resistance. Transistors with threshold voltages lower than the applied gate voltage provide a voltage contrast signal with a first intensity, while transistors with threshold voltages higher than the applied gate voltage provide a voltage contrast signal with a second intensity, the second voltage contrast signal being weaker than the first voltage contrast signal. Note that when the applied gate voltage is lower than the threshold voltage, the transistor current decreases exponentially; therefore, the voltage contrast signal, which depends on the current through the transistor, also decreases dramatically as the applied gate voltage drops below the threshold voltage. In one embodiment, the upper end of the range is a value above the device's signal threshold such that the device is switched on and current flows between the two electrodes. As the signal gradually increases, the device with the lowest threshold signal will turn on. This can be detected as described in more detail below. As the signal increases, more and more devices will turn on. At the high end of the range, all devices will be switched on. Of course, there may be one or more defective devices that never switch on.

[0056]

[0067] In one embodiment, the method includes monitoring signal charged particles (e.g., signal electrons) from the second electrode of each device for each applied signal. For example, when a signal (e.g., a particular potential) is applied to the control element (e.g., gate electrode 54) of each device (e.g., transistor 51), the detector 144 of the electron beam tool 100 detects signal electrons, such as backscattered electrons and secondary electrons, from each transistor 51. The detected signal electron data can be recorded for a given signal applied to the device's control element. The signal applied to the device's control element can then be varied (e.g., increased in steps) and the signal electrons resulting from the electron beam projected onto the drain electrode 53 can be monitored for the new applied signal. This monitoring step can be performed sequentially for each varied signal. As a result, signal electrons are detected for each device in the array 50 for a given potential applied to the gate electrode 54.

[0057]

[0068] FIG. 4 is a graph showing the relationship between the potential applied to the gate electrode 54 and the current of signal electrons detected as coming from that transistor 51. In FIG. 4, the X-axis represents the potential applied to the gate electrode 54 of a given transistor 51. The Y-axis represents the current of signal electrons detected from that transistor 51. This is sometimes referred to as the voltage contrast signal. FIG. 4 shows multiple curves 41 of signal electrons versus gate voltage. Each curve 41 may correspond to a respective transistor 51 in the array 50.

[0058]

[0069] As shown in Figure 4, the curves 41 may generally have similar shapes to one another. However, the curves may have spread. It is desirable to measure the extent to which the curves spread. This may be an indication of the manufacturing tolerances of the parameters of a given type of transistor 51.

[0059]

[0070] In one embodiment, an electron beam 55 is projected onto vias or contact metal associated with the transistors 51. In one embodiment, the electron beam 55 induces a current into the drain electrode 53 of each transistor 51 through the exposed vias or contact metal. The current of signal electrons from each via or contact metal depends on the threshold voltage of the associated transistor 51 and the potential applied to the gate electrode 54. The threshold voltages of the transistors 51 may vary across the array 50, even if all transistors 51 are nominally of the same type (e.g., have the same intended threshold voltage). As shown in FIG. 4, the output may be a family of curves 51 showing the voltage contrast signal of each transistor 51 plotted against the gate voltage. This plot may be sufficient to measure the distribution of threshold voltages. Further information may also be derived from this data. FIG. 4 illustrates a threshold range 42 of values ​​over which the threshold voltages of different transistors 51 in the array 50 may vary.

[0060]

[0071] The current of signal electrons detected from the via or contact metal of the transistor 51 depends on the extent to which the transistor 51 is switched on, i.e., the extent to which current can flow between the source electrode 52 and the drain electrode 53. If there is a sufficiently small current (or no current) flowing between the source electrode 52 and the drain electrode 53, charge can accumulate on the drain electrode 53.

[0061]

[0072] Depending on the type of transistor 51, positive charge may accumulate. The accumulated positive charge may reduce the likelihood of secondary electrons reaching the detector. This may reduce the number of secondary electrons reaching the detector 144. This may result in, for example, dark spots in any SEM images generated. In contrast, if current is allowed to flow freely between the source electrode 52 and the drain electrode 53, secondary electrons may be able to more freely reach the detector 144 of the electron beam tool 100. This may result in, for example, a higher voltage contrast signal and a thinner spot in any SEM images generated.

[0062]

[0073] An embodiment of the present disclosure is expected to reduce the area required for a test structure to test a given number of devices. In particular, known test structures require a large area because metal pads can occupy an area of ​​several micrometers. Such an area is required for each individual transistor to be tested. An embodiment of the present disclosure is expected to enable testing of, for example, an order of magnitude more transistors 51 for a given area.

[0063]

[0074] An embodiment of the present disclosure is expected to increase the number of statistics that can be measured for a given type of device. Using known techniques, only tens to hundreds of transistors of a given type can be measured using electrical testing of the entire substrate. This limits the number of statistics. An embodiment of the present disclosure is expected to significantly increase the number of transistors of a given type that can be measured, thereby improving the statistics (e.g., characteristics) that can be measured. Such statistics can help manufacturers determine the possible range of structural design features for a device to ensure that the device has desired characteristics / properties. For example, if it is known that a transistor requires a given average threshold voltage and a given standard deviation of that threshold voltage, the dimensions of the electrodes needed to meet these requirements can be determined.

[0064]

[0075] An embodiment of the present disclosure is expected to provide improved failure analysis. With known test structures, measured information does not facilitate failure analysis. One reason for this is that the measured information may not be specifically localized to each transistor. This is due to the limited number of transistors that can realistically be tested on a given substrate. An embodiment of the present disclosure is expected to be able to test more transistors (or other devices) across the entire substrate. This allows the measured information to be localized to each transistor, facilitating failure analysis.

[0065]

[0076] In one embodiment, the signals applied to the control elements of each device are applied by test probes. For example, nanoprobes can be used to apply and vary a voltage to a common control electrode 59. The voltage applied to the common control electrode 59 is applied to the gate electrodes 54 of all transistors 51 in the array 50. In one embodiment, the test probes are used in parallel with voltage contrast measurements. In one embodiment, the electron beam tool 100 is configured to support nanoprobes in parallel with voltage contrast measurements.

[0066]

[0077] A signal may be applied to the device's control element simultaneously with scanning the electron beam 55 across the array 50 to detect signal electrons from the transistors 51. However, it is not necessary to apply a potential to the gate electrode 54 simultaneously with scanning. In an alternative embodiment, the potential to the gate electrode 54 may be applied first. Then, application of the potential may be suppressed (e.g., stopped) during scanning. The potential already applied to the gate electrode 54 may be stable during scanning. If the potential is stable during scanning, it may not be necessary to actively apply a voltage to the gate electrode 54 during scanning.

[0067]

[0078] It is not necessary to apply signals to the control elements of the device by test probes, and alternative methods of applying signals such as gate voltages are described below.

[0068]

[0079] In one embodiment, the signal applied to the control element of each device is applied by directing (e.g., projecting) an additional charged particle beam onto a common control contact connected to multiple switches. For example, a second electron beam can be used to provide a gate voltage. In one embodiment, the electron beam tool 100 is configured to project multiple electron beams. One of the multiple electron beams can be used to provide a gate voltage, for example, by projecting the electron beam onto the common control contact 59. One or more other electron beams 55 can be projected onto vias connected to drain electrodes 53 of transistors 51 in the array. This can allow gate voltages to be applied simultaneously as scanning of the array 50 is performed.

[0069]

[0080] In one embodiment, common control contact 59 is at least 500 nm, optionally at least 1 μm, optionally at least 2 μm, optionally at least 5 μm, and optionally at least 10 μm away from transistor 51. Increasing the distance between common control contact 59 and transistor 51 may make it easier to distinguish between signal electrons coming from the electron beam on common control contact 59 and signal electrons coming from electron beam 55 projected onto transistor 51.

[0070]

[0081] In an alternative embodiment, the signal applied to the control element of each device is applied by projecting the charged particle beam onto a common control contact 59 connected to multiple control elements before projecting the charged particle beam onto the second electrode of each device. The common control contact 59 has a capacitance such that the signal applied to the control element of each device is maintained while monitoring the signal charged particle from the second electrode of each device. The electron beam tool 100 may not need to project multiple electron beams. In one embodiment, the electron beam tool 100 is configured to project a single beam. The common control contact 59 can have a capacitance large enough to be charged by the electron beam and to stably hold the desired voltage during a voltage contrast scan of the transistor 51.

[0071]

[0082] In an alternative embodiment, light can be used to provide an effective gate voltage to the transistors 51. For example, in one embodiment, the electron beam tool 100 can include a light source configured to project photons onto the array 50. The photons can, for example, strike all of the transistors 51 and generate electron-hole pairs in the transistor channel. The light can induce a conductive path between the source electrode 52 and the drain electrode 53 of each transistor 51. In one embodiment, the light source is configured to illuminate simultaneously with the scanning of the device by the electron beam 55.

[0072]

[0083] FIG. 12 illustrates a typical implementation of transistor measurements using an electron beam 55. As shown in FIG. 12, a transistor 51 is connected to a control contact 59 and a reference contact 57. The drain electrode 53 (or the source electrode 52 in an alternative implementation) is exposed and scanned with the electron beam 55. The arrangement shown in FIG. 12 can be repeated, arranged, and connected in various ways, for example, as shown in FIG. 3. FIG. 3 illustrates a two-dimensional array in which the transistors 51 are in an array 50 and share a common control contact 59 and a common reference contact 57. Another possibility is to arrange the transistors 51 more irregularly around the periphery of the electronic structure, for example, as described with reference to FIG. 7. In a further alternative, multiple transistors are electrically coupled to different control contacts instead of a common control contact.

[0073]

[0084] As discussed above and shown in Figure 3, in one embodiment the device is a transistor 51. However, it is not necessary that the device be a transistor. In an alternative embodiment, the device is a DRAM structure 61.

[0074]

[0085] FIG. 5 is a diagram of an array 50 of DRAM structures 61. As shown in FIG. 5, in one embodiment, the DRAM structures 61 are arranged in a two-dimensional grid. The DRAM structures 61 may be arranged in a regular pattern. The DRAM structures 61 may be arranged in multiple columns and rows of the grid. The array 50 of DRAM structures 61 may have two uses. The array 50 may be used both for testing devices and as a functional part of a circuit (e.g., for use as a memory).

[0075]

[0086] In one embodiment, each DRAM structure 61 includes a source electrode 52, a drain electrode 53, and a gate electrode 54. Some of the features of the arrangement shown in Figure 5 may be the same as those shown in Figure 3. For example, a common control contact 59 may be connected to all of the gate electrodes 54 of the DRAM structures 61. A common reference contact 57 may be electrically connected to the source electrodes 52 of all of the DRAM structures 61.

[0076]

[0087] The difference between the array 50 of DRAM structures 61 and the array 50 of logic transistors 51 is that the drain electrode 53 of the array 50 of DRAM structures 61 is connected to a capacitor 62. In contrast, logic transistors do not have such a capacitor. Each DRAM structure 61 includes a respective capacitor 62 connected to its drain electrode 53. The capacitor 62 may be electrically disposed between the drain electrode 53 and a terminal 63 connected to a via exposed at the surface of the substrate. In such a setup, readout is performed by an electron beam 55, which induces a current through the exposed via into the capacitor 62 of each DRAM structure 61.

[0077]

[0088] When electron beam 55 is incident on DRAM structure 61, capacitor 62 charges if the potential applied to gate electrode 54 is such that the transistor is switched off. In contrast, if the gate voltage is such that the transistor is switched on, capacitor 62 does not charge. Plotting the voltage contrast signal of capacitor 62 versus gate voltage yields a set of curves similar to that of Figure 4. When the gate voltage is below the threshold voltage of DRAM structure 61, capacitor 62 charges and the voltage contrast signal is low. At larger gate voltages, no charge accumulates on capacitor 62 and the voltage contrast signal is larger.

[0078]

[0089] In alternative embodiments, the device may be another type of device having an electrical connection between two electrodes that is controllable by a signal applied to a control element. For example, in one embodiment, the device is a photodiode. The signal applied to the control element may be a photon signal, e.g., light.

[0079]

[0090] In one embodiment, the photon signal is varied by varying the intensity of light incident on the photosensitive control element of the photodiode. The light intensity can be swept, for example, from low to high. There can be a threshold intensity for each photodiode at which current begins to flow between the two electrodes of the photodiode.

[0080]

[0091] Additionally or alternatively, the wavelength of the photon signal can be swept through various wavelengths. There may be a threshold wavelength that turns on the photodiode control element or turns off the control element. By sweeping through various wavelengths, the wavelength that switches each photodiode on / off can be determined. Of course, the photon signal, e.g., the light beam, may include various wavelengths. In one embodiment, the wavelength of the photon signal is the dominant wavelength of the photon signal, e.g., the wavelength of maximum intensity.

[0081]

[0092] In one embodiment, the method includes determining at least one of a threshold signal (e.g., threshold voltage), leakage current, and subthreshold slope for each device. These values ​​may be determined from the monitored signal particles. For example, these values ​​may be determined from curve 41 shown in FIG. 4.

[0082]

[0093] The threshold voltage may be determined as the gate voltage at which the voltage contrast signal increases above a threshold level. It may not be necessary to individually determine the threshold voltage of each transistor 51. In alternative embodiments, it may be sufficient to determine the average (e.g., mean) threshold voltage across the array 50 of transistors 51. Alternatively, it may not be necessary to measure the threshold voltage at all.

[0083]

[0094] Leakage current is the current between source electrode 52 and drain electrode 53 when transistor 51 is switched off (e.g., when the potential applied to gate electrode 54 is equal to the reference potential applied to source electrode 52). Leakage current is sometimes called dark current.

[0084]

[0095] In one embodiment, the signal electrons detected by the detector 144 may include backscattered electrons and secondary electrons. The current of backscattered electrons detected by the detector 144 may be expected to remain substantially constant regardless of the potential applied to the gate electrode 54. In contrast, the current of secondary electrons may be expected to vary with the gate voltage. The constant current of backscattered electrons may be known. By measuring the detector current, the current of secondary electrons may be determined.

[0085]

[0096] Subthreshold slope refers to the shape of curve 41 below the threshold voltage shown in Figure 4. Subthreshold slope is the slope of curve 41 before the control element of transistor 51 turns on.

[0086]

[0097] To determine some properties of transistor 51, it may be necessary to calibrate the detected values. For example, it may be desirable to correlate the signal measured by electron beam tool 100 with the actual current passing through the substrate. Calibration can be done by preparing SEM images of one or many devices of known properties.

[0087]

[0098] In addition to or instead of calibration, the system may be mathematically modeled, as described below, to measure one or more properties of transistor 51.

[0088]

[0099] The voltage contrast signal may be represented by the electron beam tool 100 as a gray level value (GLV). The current I detected by the detector 144 d is related to the GLV as follows:

number

[0089]

[0100] The detector current consists of secondary electron (SE) current and backscattered electron (BSE) current as follows:

number

[0090]

[0101] The charge generated in the via follows the conservation of charge. I P +Idevice = δI p +ηI p

[0091]

[0102] The two parts on the right and the primary beam current are known or may be determined. The device current can be calculated. Scanning the electron beam over the exposed vias of the transistor creates charge that is then neutralized to some extent depending on how well the via is connected to a source of free charge. Assuming all contact charge neutralization flows out of the transistor channel, the device current is specified as the drain-source current of the transistor.

[0092]

[0103] By adding a model for the secondary electron yield emission of the metal contacts, it is possible to convert the measured SE current into a drain-source voltage for the transistor. This model for the positive charging case can be found in the literature and is as follows:

number

[0093]

[0104] In one embodiment, the method includes varying the charged particle beam current applied to the second electrode of each device while maintaining a signal applied to the control element of each device. In one embodiment, the method includes monitoring a signal charged particle from the second electrode of each device with respect to the varied current. For example, the primary beam current (i.e., the current of the electron beam 55) can be varied. This can allow for plotting the source-drain current versus the source-drain voltage at a given gate voltage. In one embodiment, the method includes determining, for each device, the relationship between the potential difference between the two electrodes and the current between the two electrodes.

[0094]

[0105] In one embodiment, a secondary electron yield model can be calibrated. To know the secondary electron yield of vias exposed at the surface of the substrate, it may be desirable to measure the secondary electron current in an uncharged state. To avoid charging, it may be desirable to ensure that sufficient charge can flow between, for example, the drain electrode 53 and the source electrode 52 of the transistor 51. The charge can then flow to the contacts for neutralization, thereby avoiding charging in the exposed vias.

[0095]

[0106] In one embodiment, the method includes applying a saturation signal to the control element of each device. For example, the potential applied to the gate electrode 54 can be set large (above the expected threshold voltage of the transistor 51). This can result in maximum current as secondary electrons from vias exposed at the surface of the substrate. Additionally or alternatively, the method can include projecting light onto each device so that the two electrodes are electrically connected in substantially all of the devices. For example, a light beam can be shone on the array 50 to control charge accumulation due to effects such as photoconductivity, photoelectric effect, or thermal effect. This can lead to saturation of signal electrons from the exposed vias. This can then determine the secondary electron yield of the metal in the exposed vias.

[0096]

[0107] In one embodiment, the method includes monitoring a signal charged particle current from the second electrode of each device while inhibiting (e.g., stopping) the projection of the charged particle beam onto the second electrode of each device. The secondary electron current can be measured in an uncharged state.

[0097]

[0108] In one embodiment, the charged particle optical apparatus is for testing an array of devices 50. The apparatus includes a reference voltage source. The reference voltage source is configured to supply a reference potential to a first electrode of each electrode of each device. For example, the reference voltage source can be electrically connected to the common reference junction 57. The reference voltage source can simply be a reference ground potential of the apparatus (e.g., electron beam tool 100).

[0098]

[0109] In one embodiment, the apparatus includes a charged particle optical device configured to project a charged particle beam onto the second of the two electrodes of each device. For example, an electron beam tool 100 such as that shown in Figure 2A, 2B, or 2C can be employed to project an electron beam onto the drain electrode 53 of the transistor 51.

[0099]

[0110] In one embodiment, the apparatus includes a signal source configured to vary a signal applied to the control element of each device. For example, the signal source may include a voltage source electrically connected to the common control contact 59. The signal source may include a test probe configured to be electrically connected to the common control contact 59 to apply a varying signal (e.g., potential).

[0100]

[0111] Alternatively, the signal source may include a controllable light source for emitting light of a controlled intensity and / or wavelength.

[0101]

[0112] In one embodiment, the apparatus includes a detector 144 for monitoring the signal charged particles from the second electrode of each device for each applied signal. The detector may be, for example, as described above in the context of Figure 2A, 2B, or 2C.

[0102]

[0113] FIG. 6 is a schematic diagram of a mark 70. As shown in FIG. 6, in one embodiment, the mark 70 includes a number of DUTs. The DUTs may be arranged in a two-dimensional grid. The grid may include columns and rows. Not all DUTs are shown in FIG. 6. As suggested by FIG. 6, the mark 70 may include a number of columns and rows of DUTs arranged in a regular pattern. Each DUT may include an array 50 of devices. For example, there may be as many as 1000 devices in each array 50 of the mark 70. The mark 70 may be provided on a substrate.

[0103]

[0114] 6, in one embodiment, a common control contact 59 is electrically connected to the control element of each device in the array 50. For example, the common control contact 59 may be connected to the gate electrodes 54 of all transistors 51 in all arrays 50 in a mark 70. The mark 70 may include an array 50 of transistors 51.

[0104]

[0115] In one embodiment, at least one structural characteristic of the device varies in a predetermined manner across the array or mark 70. For example, within each array 50 of the mark 70, all transistors 51 may be designed to be of the same type. However, there may be one or more intended structural differences between the arrays 50. For example, in one embodiment, the at least one structural characteristic that varies in a predetermined manner includes at least one of an overlay shift between layers of the device and a dimension of a component of the device.

[0105]

[0116] In one embodiment, the marks 70 include column variations 71. For example, the column variations 71 may be a programmed overlay shift between two layers of a device. In one embodiment, the marks 70 include row variations 72. For example, the row variations may be an increase in the dimension of the gate electrode 54 of the device.

[0106]

[0117] For example, by sweeping through the gate voltage as described above, it is possible to measure how the threshold voltage and / or other parameters of the device depend on the programmed variation of the device, which can help the designer identify possible values ​​of different dimensions and allowable values ​​of overlay that lead to acceptable results.

[0107]

[0118] For example, in one embodiment, in each DUT (e.g., each array 50), the number of transistors 51 that are switched on and off for each applied gate voltage can be counted. For each DUT, a yield value can be determined, which can be the ratio of transistors that are switched on to the total number of transistors. The relationship between the yield value and overlay or dimensions (e.g., critical dimensions) can be examined. Additionally or alternatively, the relationship between one or more parameters, such as threshold voltage or geometric variations in the device design, can be examined.

[0108]

[0119] Figure 7, for example, schematically illustrates an arrangement of devices that is an alternative to the arrangement shown in Figure 3. In one embodiment, the devices are arranged in an array 50. In the example shown in Figure 7, the devices are transistors 51. As shown in Figure 7, the transistors 51 may be arranged in a line. However, the transistors 51 may be arranged differently and need not be provided in a regular pattern. The transistors 51 may also be arranged irregularly.

[0109]

[0120] The transistor 51 may be placed to have a particular context. Context refers to the environment of the transistor 51. For example, the context of the transistor 51 may relate to where the transistor 51 is placed on the substrate (e.g., how far from the edge of the substrate) and / or what types of structures are located adjacent to the transistor 51. Different types of structures may have different respective manufacturing processes associated with them. Depending on the manufacturing process of the structures near the transistor 51, the manufacturing process may affect the properties of the transistor 51. It is expected that one embodiment of the present invention will enable evaluation of how the context of the transistor 51 (or other type of device) may affect its properties.

[0110]

[0121] As shown in FIG. 7 , in one embodiment, the substrate including the transistor 51 includes electrode contacts 76. In one embodiment, electrodes to which the electron beam is directed are connected to the respective electrode contacts 76. The electrode contacts 76 are exposed on the surface of the substrate. The electrode contacts 76 may be pads, for example, metal pads. In the arrangement shown in FIG. 7 , the drain electrode 53 is connected to the respective electrode contacts 76. Alternatively, the source electrode 52 may be connected to the respective electrode contacts 76, and the drain electrode 53 may be connected to a reference potential.

[0111]

[0122] As shown in FIG. 7 , the electrode contacts 76 may be spaced apart from the drain electrodes 53. As shown in FIG. 7 , in one embodiment, the electrode contacts 76 are disposed at the contact regions. The contact regions may be spaced apart from the drain electrodes 53, the source electrodes 52, and / or the gate electrodes 54. By spaced apart the electrode contacts 76 from the transistor 51, the transistor 51 is less susceptible to undesired effects from the electron beam used to charge the electrode contacts 76. The drain electrodes 53 may be indirectly charged by the electron beam. The electron beam may be directly incident on the electrode contacts 76. The electrode contacts 76 are electrically connected to their respective drain electrodes 53. The electron beam is indirectly directed to the drain electrodes 53 via the electrode contacts 76.

[0112]

[0123] By physically positioning the electrode contacts 76 away from the transistor 51, the possibility of the application of the electron beam inducing undesirable capacitive effects in the transistor is reduced. For example, the possibility of undesirable charging of the gate electrode 54 by the electron beam may be reduced. One embodiment of the present invention is expected to improve the accuracy of evaluating the transistor 51. During evaluation of the transistor 51, any undesirable disturbances occurring in the transistor 51 as a result of the electron beam may undesirably affect the accuracy of the evaluation.

[0113]

[0124] As shown in FIG. 7 , the contact area may include densely packed electrode contacts 76. For example, the electrode contacts 76 may be arranged in an array, such as a two-dimensional array. The electrode contacts 76 may be arranged in multiple rows and / or columns. The electrode contacts 76 may be arranged in a regular array. One embodiment of the present invention is expected to reduce the overall area that needs to be scanned by the electron beam to evaluate the transistor 51. By densely packing the electrode contacts 76, the required scanning range can be reduced, thereby shortening the time required for evaluation.

[0114]

[0125] 7, the substrate may include one or more electronic structures 73. The electronic structures 73 may be located near, e.g., adjacent to, the transistor 51. The electronic structures 73 may form part of the context of the transistor 51 under test. The electronic structures 73 may be an electronic product or part of an electronic product. The electronic structures may include transistors and / or memory devices such as DRAM and / or SRAM. The electronic structures 73 may include a processor for executing a process.

[0115]

[0126] By placing the transistor 51 in proximity to the electronic structure 73, the transistor 51 can better represent the device properties of the electronic structure 73. By placing the transistor 51 near a particular electronic structure 73, it is possible to evaluate the effect (sometimes called the proximity effect) that the electronic structure 73 may have on the properties of the transistor 51. One embodiment of the present invention is expected to improve the accuracy of device evaluation of electronic products or electronic structures that may be part of electronic products.

[0116]

[0127] 7, in one embodiment, the gate electrodes 54 are connected to a common control contact 59. However, it is not necessary that a common control contact 59 be provided. In alternative embodiments, the gate electrodes 54 may be connected to respective individual control contacts. In a further alternative, the gate electrodes 54 may be grouped together, with each group including multiple gate electrodes 54. All of the gate electrodes 54 of a group may be connected to a common group control contact. Multiple group control contacts may be provided for each of multiple groups of data electrodes 54.

[0117]

[0128] As shown in FIG. 7 , in one embodiment, the common control contact 59 is adjacent to the contact area where the electrode contact 76 is provided. As shown in FIG. 7 , in one embodiment, the substrate includes a scan area 75. The scan area 75 may correspond to the area of ​​the surface of the substrate that is scanned by the electron beam. As shown in FIG. 7 , the contact area of ​​the electrode contact 76 may be within the scan area 75. The electrode contact 76 is scanned during the scanning of the electron beam across the substrate. As shown in FIG. 7 , the scan area 75 may be much smaller than the overall size of the substrate. One embodiment of the present invention is expected to reduce the scan area required to access the transistor 51. For example, as shown in FIG. 7 , the electrode contact 76 may be located in a relatively small contact area.

[0118]

[0129] As shown in FIG. 7 , in one embodiment, at least a portion of the common control contact 59 is within the scan region 75. During scanning of the electron beam across the surface of the substrate, the common control contact 59 can be scanned by the electron beam. In one embodiment, the electron beam is directed onto the common control contact 59 in the same scan line as that used to scan the electrode contacts 76. As shown in FIG. 7 , in one embodiment, at least a portion of the common reference contact 57 is within the scan region 75. In one embodiment, the electron beam is directed onto the common reference contact 57. For example, in one embodiment, the electron beam can be scanned using a frame scan mode. Frame scanning involves scanning the electron beam along multiple substantially parallel lines. For example, the electron beam can be scanned horizontally along a first line from the upper left corner of the scan region 75 shown in FIG. 7 to the upper right corner of the scan region. Subsequent scan lines can be parallel to and slightly below the first scan line. The entire scan region 75 can be scanned by the electron beam by scanning the lines sequentially.

[0119]

[0130] 7, in one embodiment, each line of a frame scan includes multiple (e.g., a row) of electrode contacts 76, as well as a scanned portion of common control contact 59 and / or a portion of common reference contact 57. As shown in FIG. 7, in one embodiment, scan area 75 includes electrode contacts 76, at least a portion of common control contact 59, and at least a portion of common reference contact 57. The omitted electrons of each area can be shown in a single image.

[0120]

[0131] In one embodiment, within each scan line, the electron beam is directed onto a common control contact 59 before scanning a row of electrode contacts. In one embodiment, after the electron beam is directed onto multiple (e.g., a row) of electrode contacts 76, the electron beam is directed onto a common reference contact 57.

[0121]

[0132] 7, in one embodiment, the substrate includes a number of electrical traces 77-79. The electrical traces electrically connect the electrode contacts 76 to the respective drain electrodes 53. If sufficient space exists, the electrical traces 77-79 may be positioned adjacent to one another. The electrical traces may be located at substantially the same level within the substrate.

[0122]

[0133] Alternatively, the electrical traces 77-79 may be provided at different levels within the substrate. The electrical traces 77-79 may be disposed at different levels within the substrate to extend across the substrate. This is shown in Figure 8. As shown in Figure 8, there may be multiple levels (e.g., three) within the substrate across which the electrical traces 77-79 extend. Each electrical trace 77-79 electrically connects the drain electrode 53 to a respective electrode contact.

[0123]

[0134] 8, in one embodiment, a first electrical trace 77 is located at the lowest level of electrical traces 77-79. A second electrical trace 78 is located at a middle level within the substrate. A third electrical trace 79 is located at the highest level within the substrate. By locating the electrical traces 77-79 at different levels, the electrical traces 77-79 can occupy a smaller percentage of the space within the overall substrate.

[0124]

[0135] As shown in FIG. 7 , in one embodiment, the substrate includes a reset switch 74. The reset switch 74 may include, for example, a transistor. In one embodiment, the charge on the gate electrode of the transistor of the reset switch 74 is controlled to control whether the gate electrode 54 of the transistor 51 is connected to a reference potential. In the arrangement shown in FIG. 7 , the reset switch 74 is configured to control whether the common reference contact 59 is in electrical contact with the common control contact 59. When the electrical connection is provided, the gate electrode 54 is discharged. This allows the transistor 51 to be evaluated again (e.g., repeated testing) without a subsequent test being undesirably affected by the previous test.

[0125]

[0136] In one embodiment, the reset switch 74 is closed by directing an electron beam onto the reset switch 74, for example, onto the gate electrode or a pad connected to the gate electrode. The reset switch 74 can then be reopened by allowing charge to leak away (e.g., through gate leakage). Alternatively, the properties of the electron beam may be changed so that the electron beam is again directed onto the reset switch 74, negatively charging the gate electrode of the reset switch 74. For example, the landing energy of the electrons in the electron beam can be adjusted so that the gate electrode of the reset switch 74 is oppositely charged.

[0126]

[0137] Alternatively, the reset switch 74 can be closed by shining light onto the reset switch 74 (e.g., using light-induced conductivity). This causes the reset switch 74 to close temporarily while the light is incident on the reset switch 74. To reopen the reset switch 74, the light can be turned off. Using light can be expected to reopen the reset switch 74 more quickly than if an electron beam were used to control the reset switch 74.

[0127]

[0138] Figure 9 is a schematic diagram of an alternative arrangement of devices such as transistors 51. As shown in Figure 9, in one embodiment, transistors 51 are arranged in a number of arrays 50. However, it is not necessary that transistors 51 be arranged in arrays 50. Transistors 51 can be rearranged as needed and need not be organized in a row.

[0128]

[0139] For example, as shown in Figure 9, in one embodiment, transistors 51 are arranged around one or more electronic structures 73. In the example shown in Figure 9, one set of transistors 51 is arranged to surround one electronic structure 73, and another group of transistors 51 surrounds another electronic structure 73. The transistors 51 may be located adjacent to the electronic structures 73. The transistors 51 may have properties that more accurately represent the properties of the transistor or other device that forms part of the electronic structures 73.

[0129]

[0140] 9, in one embodiment, the scan area 75 is separate from the transistor 51. An electrode contact 76 may be provided within the scan area 75.

[0130]

[0141] The transistors 51 may be located at various different locations within the substrate. For example, different transistors 51 may be located in different contexts, such as near different types of electronic structures 73 or different types of devices having different manufacturing processes. As shown in FIG. 9 , electrical traces 77 may be provided to electrically connect electrode contacts 76 to the transistors 51. In one embodiment, the electron beam scans only one field of view, i.e., scan area 75, accessing the effects of different contexts on the electrical metrics of the transistors 51. In FIG. 9 , the electrical traces 77 between the electrode contacts and the transistors 51 are shown only schematically. In one embodiment, each transistor 51 is electrically connected to its respective electrode contact 76 by an electrical trace 77.

[0131]

[0142] Figure 10 shows a mark 70 including an array 50 of devices such as transistors. Features that are the same as the arrangement shown in Figure 6 will not be described again in detail below. For example, the common control contact 59 and common reference contact 57 may be as described elsewhere.

[0132]

[0143] 10, in one embodiment, the mark 70 includes a column variation 71. For example, the column variation 71 may be a programmed overlay shift between two layers of the device. Alternatively, the column variation may be, for example, an increase in the dimension of the gate electrode 54 of the device.

[0133]

[0144] 10, in one embodiment, mark 70 includes an arrangement of arrays 50. In one embodiment, arrays 50 include devices of different types. For example, some of arrays 50A may be arrays of transistors with relatively high threshold voltages. Another number of arrays 50B may be arrays of transistors with relatively low threshold voltages.

[0134]

[0145] 10, in one embodiment, mark 70 includes a mixture of different types of devices, such as a mixture of high and low threshold voltage transistors. As shown in FIG. 10, in one embodiment, mark 70 includes an array of arrays 50.

[0135]

[0146] Marks 70 can be used to incorporate geometric variations and proximity effects by mixing arrays 50 of different types of transistors. Although not shown in FIG. 10 , row variations may also exist in addition to the column variations 71 shown. Different types of transistors may be formed using different manufacturing processes. The manufacturing process used to manufacture high threshold voltage transistors may unintentionally affect the properties of low threshold voltage transistors. Similarly, the manufacturing process for low threshold voltage transistors may unintentionally affect the properties of high threshold voltage transistors. By placing different types of transistors near each other, the effects of the manufacturing process on nearby devices can be measured.

[0136]

[0147] By providing column variations and / or row variations, it is possible to find the best process window. For example, it is possible to determine at which overlays the properties (metrics) of transistor 51 are within specification, i.e., acceptable, and at which overlays the metrics are outside specification. This helps define the overlay window, i.e., where the manufacturing process has acceptable results.

[0137]

[0148] As shown in Figure 10, in one embodiment, one common reference contact 57 may be provided for many or all of the arrays 50. As shown in Figure 10, one common control contact 59 may be provided for many or optionally all of the arrays 50 of marks 70.

[0138]

[0149] Figure 11 is a diagram illustrating an alternative arrangement of transistors under test 51. As shown in Figure 11, in one embodiment, transistors 51 are arranged in an array 50. However, transistors 51 may also be arranged in a more irregular manner.

[0139]

[0150] Features shown in FIG. 11 that are also shown in other figures will not be described again below for the sake of brevity. For example, common reference contact 57, common control contact 59, transistor 51, and electrode contact 76 may be as described elsewhere. As shown in FIG. 11, in one embodiment, the substrate includes probe contacts 82. Probe contacts 82 are sometimes referred to as probe measurement sites. Probe contacts 82 are exposed at the surface of the substrate. In one embodiment, probe contacts 82 include pads, e.g., metal pads.

[0140]

[0151] 11 , in one embodiment, the probe contact 82 is electrically connected to one of the electrode contacts 76. For example, in one embodiment, the probe contact 82 and the connected electrode contact 76 may be integrally formed with one another. For example, a single metal pad may be provided to function as both the probe contact 82 and the connected electrode contact 76. Alternatively, the probe contact 82 and the connected electrode contact 76 may be provided as separate contacts that are electrically connected, for example, by electrical traces.

[0141]

[0152] 11, in one embodiment, the probe contacts 82 are larger than the electrode contacts 76. The probe contacts 82 may be large enough that a physical probe can make electrical contact with the probe contacts 82. The electrode contacts 76 may not need to be large enough to be accessible by a physical probe.

[0142]

[0153] In one embodiment, the probe contact 82 is for electrically connecting the associated electrode contact 76 to the probe. By providing the probe contact 82 as a larger pad, the physical tip of the probe can be used to connect to the probe contact 82.

[0143]

[0154] In one embodiment, the calibration method includes connecting probes to multiple probe contacts 82, a common reference contact 57, and a common control contact 59. The probes can be used to measure current and / or voltage.

[0144]

[0155] 11, in one embodiment, scan area 75 includes electrode contacts 76. Scan area 75 may include a portion of common control contact 59.

[0145]

[0156] 11, in one embodiment, the scan area 75 is scanned by the electron beam scanning multiple substantially parallel lines 80. The lines 80 may be scanned sequentially to scan the entire scan area 75.

[0146]

[0157] In one embodiment, the common control contact 59 is scanned before the electrode contacts 76 are scanned. The common control contact 59 may be charged before the electrode contacts 76 are scanned by the electron beam. In one embodiment, the scan area 75 is scanned using a frame scan mode.

[0147]

[0158] FIG. 11 illustrates an alternative scanning mode. In particular, in one embodiment, the electrode contacts 76 are scanned in a line scanning mode. In line scanning mode, the scan area 75 need not be scanned. Instead, a single scan line 81 may be scanned. The scan line may be straight, i.e., linear. In the arrangement shown in FIG. 11, one scan line 81 is shown for scanning half of the electrode contacts 76. In one embodiment, a second scan line is scanned to scan the other half of the electrode contacts 76. In one embodiment, the common control contact 59 is discharged between scanning of different scan lines 81.

[0148]

[0159] 11, in one embodiment, scan line 81 covers a portion of common control electrode 59 and multiple electrode contacts 76. In one embodiment, common control contact 59 is scanned within scan line 81 before electrode contacts 76 are scanned.

[0149]

[0160] In the arrangements described with reference to the figures, devices such as transistors 51 are typically provided with respective electrode contacts 76. However, this is not required. For example, in alternative embodiments, many or all of the drain electrodes 53 of the transistors 51 are connected to a common electrode contact (not shown), such as by electrically connecting the electrode contacts 76 shown in the figures, or by providing a large electrode contact 76 connected to many of the drain electrodes 53 of the transistors 51. In one embodiment, an individual control contact is provided for each transistor 51, for example, connected to each gate electrode 54. By providing individual control contacts, the transistors 51 may be individually addressable even though they share a common electrode contact for their drain electrodes 53.

[0150]

[0161] In one embodiment, a non-transitory computer-readable medium stores instructions for a processor of a controller (eg, controller 109) to perform a method as described above.

[0151]

[0162] Exemplary embodiments of the present disclosure are described in the following numbered clauses: 1. A method for testing an array of devices, each device having an electrical connection between two electrodes controllable by a signal applied to a control element; applying a reference potential to a first of two electrodes of each device; directing a charged particle beam onto a second of the two electrodes of each device; Varying the signal applied to the control element of each device; monitoring the signal charge particles from the second electrode of each device for each applied signal; A method comprising: 2. The method of clause 1, wherein the signal is an electric potential. 3. The method of clause 2, wherein the control elements of multiple devices are connected to a common control contact for applying varying electrical potentials. 4. A method according to any one of the preceding clauses, wherein the signals applied to the control elements of each device are applied by test probes. 5. A method according to any one of clauses 1 to 3, wherein the signal applied to the control element of each device is applied by directing a further charged particle beam to a common control contact connected to multiple control elements. 6. A method according to any one of clauses 1 to 3, wherein, prior to inducing a charged particle beam onto the second electrode of each device, the signal applied to the control element of each device is applied by inducing the charged particle beam onto a common control contact connected to a number of control elements, whereby the common control contact has a capacitance such that the signal applied to the control element of each device is maintained while monitoring the signal charged particle from the second electrode of each device. 7. The method of clause 6, further comprising directing the charged particle beam onto a common reference junction connected to the multiple first electrodes. 8. The method of clause 7, wherein after directing the charged particle beam onto the second electrodes of the multiple devices, the charged particle beam is directed onto a common reference junction. 9. The method of clause 1, wherein the signal is a photon signal and the step of varying the photon signal includes varying at least one of the intensity and wavelength of the photon signal. 10. A method according to any one of the preceding clauses, wherein the first electrodes of the multiple devices are connected to a common reference potential for applying a reference potential. 11. A method according to any one of the preceding clauses, comprising determining, for each device, at least one of a threshold signal, a leakage current, and a subthreshold slope from signal particles monitored for the varied signal. 12. Varying the current of the charged particle beam applied to the second electrode of each device while maintaining the signal applied to the control element of each device; monitoring the signal charge from the second electrode of each device with respect to the varied current; 10. The method of any one of the preceding clauses, further comprising: 13. The method of clause 12, further comprising determining, for each device, a relationship between a potential difference between the two electrodes from a signal particle monitored for the varied signal and a current between the two electrodes. 14. applying a saturation signal to the control element of each device and / or directing light onto each device such that two electrodes are electrically connected in substantially all of the devices; monitoring a signal charged particle from the second electrode of each device while suppressing the induction of the charged particle beam onto the second electrode of each device; 10. The method of any one of the preceding clauses, further comprising: 15. A method according to any one of the preceding clauses, wherein a second electrode is electrically coupled to the first electrode and a respective electrode contact located in a contact region remote from the control element. 16. The method of clause 15, wherein the charged particle beam is directed onto the second electrode by scanning the charged particle beam over the contact area such that the charged particle beam is indirectly directed onto the second electrode by directly directing the charged particle beam onto the electrode contact. 17. The method of clause 16, wherein scanning comprises scanning the charged particle beam along a number of substantially parallel lines. 18. The method of clause 17, further comprising scanning the charged particle beam along multiple substantially parallel lines across a common control contact connected to multiple control elements. 19. The method of clause 17, wherein scanning each line includes scanning the charged particle beam across a common control contact electrically coupled to multiple control elements and across multiple electrode contacts. 20. The method of clause 16, wherein scanning includes scanning the charged particle beam along at least one straight line across a common control contact connected to multiple control elements and across electrode contacts. 21. A method according to any one of clauses 18 to 20, wherein the common control contact is scanned before the electrode contacts are scanned. 22. A charged particle optical apparatus for testing an array of devices, each device having an electrical connection between two electrodes controllable by a signal applied to a control element, the electro-optical apparatus comprising: a reference voltage source configured to provide a reference potential to a first of the two electrodes of each device; a charged particle optical device configured to direct a charged particle beam onto a second of the two electrodes of each device; a signal source configured to vary the signal applied to the control element of each device; a detector for monitoring the signal charged particles from the second electrode of each device for each applied signal; A charged particle optical device comprising: 23. A charged particle optical apparatus according to clause 22, further comprising a substrate at the sample location, the substrate comprising an array of devices, each device having an electrical connection between two electrodes controllable by a signal applied to a control element. 24. A charged particle optical apparatus according to clause 23, wherein the device is a logic transistor or a DRAM structure. 25. A charged particle optical apparatus according to clause 23 or 24, wherein at least one structural characteristic of the device varies in a predetermined way across the array. 26. A charged particle optical apparatus according to any one of clauses 23 to 25, wherein the at least one characteristic comprises at least one of an overlay shift between layers of the device and a dimension of a component of the device. 27. A substrate containing an array of devices within a test area, each device having an electrical connection between its source and drain electrodes controllable by a potential applied to its gate electrode, wherein either the source or drain electrode is connected to a common reference junction, and whichever of the source and drain electrodes is not connected to the common reference junction is electrically coupled to a respective electrode contact exposed on the surface of the substrate. 28. The substrate of clause 27, wherein the arrangement comprises a two-dimensional array. 29. A substrate according to clause 27 or 28, wherein the device comprises a logic transistor or a memory structure. 30. The substrate of any one of clauses 27-29, wherein the gate electrode is electrically coupled to a common control contact. 31. The substrate of any one of clauses 27 to 30, wherein the electrode contacts comprise separate vias. 32. A substrate according to any one of clauses 27 to 31, wherein the electrode contacts are located at the contact region remote from the gate electrode and remote from whichever of the source and drain electrodes is connected to the common reference contact. 33. The substrate of clause 32, wherein the contact region is adjacent a common control contact to which the gate electrode is electrically coupled. 34. A substrate according to any one of clauses 27 to 33, wherein the electrode contacts are arranged in a two-dimensional array. 35. A substrate according to any one of clauses 27 to 34, wherein the electrode contact is disposed adjacent to the electronic structure. 36. A substrate according to any one of clauses 27 to 35, wherein the electrode contacts are arranged around the electronic structure. 37. The substrate of any one of clauses 27-36, wherein electrical traces extend between the electrode contacts and the source and drain electrodes that are not connected to the common reference contact. 38. The substrate of clause 37, wherein the electrical traces are disposed at multiple levels within the substrate so as to extend across the substrate. 39. A substrate according to any one of clauses 27 to 38, comprising an array of other devices having target properties different from the array of devices. 40. The substrate of claim 39, wherein the arrays are located adjacent to each other. 41. A substrate according to any one of clauses 27 to 40, including a probe contact connected to one of the electrode contacts for electrically connecting the electrode contact to the probe. 42. The substrate of any one of clauses 27-41, further comprising a reset switch configured to selectively couple the gate electrode to the common reference junction. 43. The substrate of any one of clauses 27 to 42, wherein the devices are arranged at a pitch of at most about 200 nm, optionally at most about 100 nm, optionally at most about 50 nm. 44. A substrate according to any one of clauses 27 to 43, wherein the array is located in a scribe lane of the substrate. 45. A non-transitory computer-readable medium storing instructions for a processor of a controller to execute a method for testing an array of devices, each device having an electrical connection between two electrodes controllable by a signal applied to a control element; controlling the application of a reference potential to a first of two electrodes of each device; controlling the direction of the charged particle beam onto a second of the two electrodes of each device; controlling the variation of the signal applied to the control element of each device; controlling the monitoring of signal charged particles from the second electrode of each device for each applied signal; 1. A non-transitory computer-readable medium, comprising:

[0152]

[0163] A non-transitory computer-readable medium may be provided that stores instructions for a processor of a controller (e.g., controller 109 of FIG. 1 ) to perform image inspection, image acquisition, activating a charged particle source, adjusting electrical excitation of an astigmatism corrector, adjusting electron landing energy, adjusting excitation of an objective lens, adjusting position and orientation of a secondary electron detector, controlling stage movement, exciting a beam separator, applying scanning deflection voltages to beam deflectors, receiving and processing data related to signal information from an electron detector, configuring electrostatic elements, detecting signal electrons, adjusting control electrode potentials, adjusting voltages applied to the electron source, extraction electrode and sample, etc. Common forms of non-transitory media include, for example, floppy disks, flexible disks, hard disks, solid state drives, magnetic tape or any other magnetic data storage medium, compact disk read-only memory (CD-ROM), any other optical data storage medium, any physical medium with a pattern of holes, random access memory (RAM), programmable read-only memory (PROM) and erasable programmable read-only memory (EPROM), flash EPROM or any other flash memory, non-volatile random access memory (NVRAM), cache, registers, any other memory chip or cartridge, and network-connected versions of these.

[0153]

[0164] It will be understood that the embodiments of the present disclosure are not limited to the exact construction described above and illustrated in the accompanying drawings, and that various modifications and changes can be made without departing from the scope thereof. While the present disclosure has been described in connection with various embodiments, other embodiments of the present invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with the true scope and spirit of the invention being indicated by the following claims.

[0154]

[0165] The above description is intended to be illustrative, not limiting. Thus, it will be apparent to one skilled in the art that modifications can be made as described without departing from the scope of the claims set out below.

Claims

1. 1. A method for testing an array of devices, each device having an electrical connection between two electrodes controllable by a signal applied to a control element; applying a reference potential to a first of the two electrodes of each device; directing a charged particle beam onto a second of the two electrodes of each device; Varying the signal applied to the control element of each device; monitoring a signal charge particle from the second electrode of each device for each applied signal; A method comprising:

2. The method of claim 1 , wherein the signal is an electrical potential.

3. The method of claim 2 wherein the control elements of multiple devices are connected to a common control contact for applying the varying potential.

4. The method of claim 1 , wherein the signals applied to the control elements of each device are applied by test probes.

5. 10. The method of claim 1, wherein the signal applied to the control element of each device is applied by directing a further charged particle beam to a common control contact connected to multiple of the control elements.

6. 2. The method of claim 1, wherein, prior to directing a charged particle beam onto the second electrode of each device, the signal applied to the control element of each device is applied by directing the charged particle beam onto a common control contact connected to a number of the control elements, whereby the common control contact has a capacitance such that the signal applied to the control element of each device is maintained while monitoring the signal charged particle beam from the second electrode of each device.

7. The method of claim 1 , wherein the signal is a photon signal, and wherein the step of altering the photon signal comprises altering at least one of an intensity and a wavelength of the photon signal.

8. The method of claim 1 , wherein the first electrodes of multiple devices are connected to a common reference potential for applying the reference potential.

9. 10. The method of claim 1, comprising determining, for each device, at least one of a threshold signal, a leakage current, and a subthreshold slope from the monitored signal particles for the varied signal.

10. Varying the charged particle beam current applied to the second electrode of each device while maintaining the signal applied to the control element of each device; monitoring a signal charge particle from the second electrode of each device in response to the varied current; The method of claim 1 , comprising:

11. 11. The method of claim 10, comprising determining, for each device, a relationship between the potential difference between the two electrodes from the monitored signal particles for the varied signal and the current between the two electrodes.

12. applying a saturation signal to the control element of each device and / or directing light onto each device such that the two electrodes are electrically connected in substantially all of the devices; monitoring a signal charged particle beam from the second electrode of each device while suppressing the directing of the charged particle beam onto the second electrode of each device; The method of claim 1 , comprising:

13. 1. A charged particle optical apparatus for testing an array of devices, each device having an electrical connection between two electrodes controllable by a signal applied to a control element, the electro-optical apparatus comprising: a reference voltage source configured to provide a reference potential to a first of the two electrodes of each device; a charged particle optical device configured to direct a charged particle beam onto a second of the two electrodes of each device; a signal source configured to vary the signal applied to the control element of each device; a detector for monitoring signal charged particles from the second electrode of each device for each applied signal; A charged particle optical device comprising:

14. 14. The charged particle optical apparatus of claim 13, further comprising a substrate at the sample location, said substrate comprising an array of devices, each device having an electrical connection between two electrodes controllable by a signal applied to a control element.

15. 15. A charged particle optical apparatus according to claim 14, wherein the device is a logic transistor or a DRAM structure.

Images