Display substrate and display device

Abstract

The present invention provides a display substrate and a display device, the display substrate comprising a driving transistor and a storage capacitor, the storage capacitor including a first plate and a second plate, the second plate being disposed in the same layer as the channel of the driving transistor, the second plate being closer to the base substrate than the first plate, the orthogonal projection of the second plate on the base substrate overlaps with the orthogonal projection of the pixel aperture on the base substrate, the display substrate satisfying the relationship that (W*L+S2)*M1 / M2 is in the range of [0.014, 0.133] and S2 / (W*L) is in the range of [2.82, 28.85], and where W is the channel width of the driving transistor, L is the channel length of the driving transistor, S2 is the facing area between the second plate and the first plate, M1 is the number of pixel openings on the display substrate, and M2 is the area of ​​the display substrate, which increases the facing area of ​​the storage capacitor plate, improves the capacitance, enhances the capacitance retention ability, and increases the area ratio of the storage capacitor to the pixel opening, thereby improving the area occupancy rate of the storage capacitor and improving display quality.

Description

[Technical Field]

[0001] The embodiments of the present disclosure relate to a display substrate and a display device. [Background technology]

[0002] With the rapid development of science and technology, display media has become an important part of people's lives. Organic light-emitting diode (OLED) display media is self-luminous, which means it has excellent color and image quality. Summary of the Invention [Problem to be solved by the invention]

[0003] The embodiments of the present disclosure provide a display substrate and a display device to improve display quality and / or reduce power consumption. [Means for solving the problem]

[0004] An embodiment of the present disclosure provides a display substrate, comprising: a base substrate; and a plurality of sub-pixels disposed on the base substrate, each of the sub-pixels including a pixel circuit including a driving transistor and a storage capacitor, the storage capacitor including a first plate and a second plate, the first plate of the storage capacitor being connected to a gate of the driving transistor; and a light-emitting element electrically connected to the pixel circuit, the pixel circuit being configured to drive the light-emitting element, the sub-pixels including a pixel aperture configured to define a light-emitting area of ​​the sub-pixel, wherein an orthogonal projection of the storage capacitor on the base substrate defines an emissive area of ​​the pixel aperture. the orthogonal projection of the channel of the driving transistor on the base substrate overlaps with the orthogonal projection of the pixel opening on the base substrate, and the display substrate satisfies the relationship that (W*L+S2)*M1 / M2 has a value range of [0.014, 0.133] and S2 / (W*L) has a value range of [2.82, 28.85], where W is the channel width of the driving transistor, L is the channel length of the driving transistor, S2 is the opposing area of ​​the second electrode plate and the first electrode plate, M1 is the number of pixel openings on the display substrate, and M2 is the area of ​​the display substrate.

[0005] For example, the second plate of the storage capacitor is connected to the first electrode of the driving transistor, the storage capacitor further includes a third plate, the third plate and the second plate are connected to each other, and the third plate and the second plate are respectively installed on both sides of the first plate.

[0006] For example, the second electrode plate includes a first plate-shaped portion, and the first plate-shaped portion and the channel of the driving transistor are integral with each other.

[0007] For example, the second electrode plate further includes a second plate-shaped portion, the first plate-shaped portion and the second plate-shaped portion are separated from each other, the area of ​​the first plate-shaped portion is larger than the area of ​​the second plate-shaped portion, or both the first plate-shaped portion and the second plate-shaped portion are connected to the channel of the driving transistor.

[0008] For example, the channel of the drive transistor is a semiconductor material, and the material of the second plate is a conductor made of the same semiconductor material as the channel of the drive transistor that has been doped.

[0009] For example, the channel of the driving transistor extends along a first direction, the pixel opening has a central axis extending along the first direction, the maximum dimension of the pixel opening along a second direction is W0, the first direction and the second direction intersect, the distance from the channel of the driving transistor to the central axis is D1, and the value range of 2*D1 / W0 is [0.2, 0.4] or [0.6, 0.8].

[0010] For example, the display substrate further includes a plurality of signal lines located on one side of the storage capacitor, the signal lines extending along the second direction, orthogonal projections of the plurality of signal lines on the base substrate overlap with orthogonal projections of the pixel opening on the base substrate, a dimension of the pixel opening along the first direction is H0, a distance in the first direction between the farthest edges of the plurality of signal lines is Hs, and a value range of L / (H0-Hs) is [0.16, 0.61].

[0011] For example, the display substrate further includes a data line, a first gate line, a second gate line, and a first initialization line, the pixel circuit further includes a data write transistor and a first reset transistor, a first pole of the data write transistor is connected to the data line, a gate of the drive transistor is connected to a second pole of the data write transistor, a gate of the data write transistor is connected to the first gate line, a first pole of the first reset transistor is connected to the first initialization line, a second pole of the first reset transistor is connected to the gate of the drive transistor, and a gate of the first reset transistor is connected to the second gate line, and the multiple signal lines include the first gate line, the second gate line, and the first initialization line.

[0012] For example, the area of ​​the pixel aperture is S0, the sum of the opposing area of ​​the second electrode plate and the first electrode plate and the area of ​​the channel of the driving transistor is Ss, the relationship between Ss and S0 satisfies Ss=A*S0+B, the value range of A is [0.42, 0.82], and the value range of B is [-2700, -3100].

[0013] For example, an orthogonal projection of the pixel opening on the base substrate overlaps with an orthogonal projection of the third plate on the base substrate, the third plate includes a first edge extending along a first direction and a second edge extending along the first direction, the pixel opening includes a first edge extending along the first direction and a second edge extending along the first direction, the first edge of the third plate is closer to the first edge of the pixel opening than the second edge of the third plate, and the second edge of the third plate is closer to the second edge of the pixel opening than the first edge of the third plate, and the sub-pixel is △ The formula U=|U02-U01| is satisfied, U01 is the coordinate distance between the chromaticity coordinate point at the first view angle and the chromaticity coordinate point at the 0-degree view angle, U02 is the coordinate distance between the chromaticity coordinate point at the second view angle and the 0-degree view angle, △U is the absolute value of the difference between U02 and U01, the chromaticity coordinate point at the 0-degree view angle is the chromaticity coordinate point on the normal line at the center of the display substrate, the first view angle and the second view angle are located on opposite sides of the normal line, and the numerical values ​​of the included angles with the normal line are equal, and △U≦0.0020.

[0014] For example, the display substrate further includes a first power supply line, the first power supply line being configured to supply a first voltage signal to the pixel circuit, the first power supply line including a first power supply connecting line extending along a first direction and a first power supply signal line extending along a second direction, an orthogonal projection of the first power supply connecting line on the base substrate overlaps with an orthogonal projection of the pixel opening on the base substrate, a facing area between the third electrode plate and the first electrode plate is Sc1, an overlapping area between the orthogonal projection of the third electrode plate on the base substrate and the orthogonal projection of the pixel opening on the base substrate is Sc2, Sc2 / Sc1≧0.9, a width of the first power supply connecting line is W1, an overlapping width between the first power supply connecting line and the pixel opening is W2, and W2 / W1≧0.9.

[0015] For example, the maximum dimension of the pixel opening along the second direction is W0, the value range of 2×W2 / W0 is [0.71, 0.99], and the value range of step voltage Uc / dimension Lg is [0.32, 0.74], the step voltage Uc is the step voltage of the light-emitting element, the unit of the step voltage Uc is volts, the unit of the dimension Lg is the diagonal length of the display substrate, and the unit of the dimension Lg is inches.

[0016] For example, the pixel opening has a central axis extending along the first direction, the minimum distance from the first power supply connection line to the central axis is Xd1, the minimum distance from the third electrode plate to the central axis is Xd2, and the value range of Xd1 / Xd2 is [0.9, 1.1].

[0017] For example, the display substrate further includes a plurality of signal lines located on one side of the storage capacitor, wherein the orthogonal projection of the plurality of signal lines on the base substrate overlaps with the orthogonal projection of the pixel opening on the base substrate, the plurality of signal lines are arranged along a first direction, the signal lines extend along a second direction, the first direction and the second direction intersect, the distance between the third electrode plate and the signal line closest to it is Xd3, the line width of the signal line is Xd4, and the value range of Xd3 / Xd4 is [0.9, 1.1].

[0018] For example, the display substrate further includes a first power line, the first power line configured to supply a first voltage signal to the pixel circuit, the first power line including a first power connection line extending along a first direction and a first power signal line extending along a second direction, the pixel opening has a central axis extending along the first direction, the minimum distance from the first power connection line to the central axis is Xd1, the minimum distance between the first power connection line and the third electrode plate is Xd0, DP=|Xd1-Xd0| / 2, the maximum dimension of the pixel opening along the second direction is W0, and the value range of DP / W0 is [0.01, 0.19].

[0019] For example, the display substrate further includes a first signal line, the first signal line extending along a first direction, the subpixel including a first subpixel and a second subpixel adjacent to each other in the second direction, the first signal line configured to supply a data signal to the pixel circuit of the first subpixel, the pixel opening of the first subpixel and the pixel opening of the second subpixel being spaced apart, and the first signal line being located between the pixel opening of the first subpixel and the pixel opening of the second subpixel.

[0020] For example, the minimum distances between the pixel aperture of the first subpixel and the first signal line are Xa1 and Xa2, respectively, and the value range of Xa1 / Xa2 is [0.8, 1.2].

[0021] For example, the display substrate further includes a second signal line, the second signal line extending along the first direction, the first signal line and the second signal line being located on opposite sides of the same third electrode plate, and a positive projection of the second signal line on the base substrate overlaps with a positive projection of the pixel opening of the second sub-pixel on the base substrate.

[0022] For example, the distance between the third electrode plate and the second signal line is Xa3, the distance between the third electrode plate and the first signal line is Xa4, and the value range of Xa3 / Xa4 is [0.8, 1.2].

[0023] For example, the display substrate further includes a third signal line, the third signal line extends along the first direction, a positive projection of the third signal line on the base substrate overlaps with a positive projection of the pixel opening of the first subpixel on the base substrate, a minimum distance between a third electrode plate of the first subpixel and the third signal line is Xa5, a minimum distance from the third signal line to the first signal line is Xa6, and a value range of Xa5 / Xa6 is [0.8, 1.2].

[0024] For example, the first signal line includes a data line, and at least one of the second signal line and the third signal line includes a first power supply connection line.

[0025] For example, the display substrate further includes a data line and a first power line, the data line is configured to supply a data voltage to the pixel circuit, the data line extends along a first direction, the first power line is configured to supply a first voltage signal to the pixel circuit, the first power line includes a first power connection line extending along the first direction and a first power signal line extending along a second direction, the subpixels include a first subpixel and a second subpixel adjacent to each other in the second direction, and a positive projection of the first power connection line on the base substrate overlaps with a positive projection of the pixel opening of the first subpixel on the base substrate and overlaps with a positive projection of the pixel opening of the second subpixel on the base substrate.

[0026] For example, two data lines are respectively installed on both sides of the first power supply connecting line, and the orthogonal projections of the two data lines on the base substrate respectively overlap with the orthogonal projections of the pixel openings of the first sub-pixel and the second sub-pixel on the base substrate.

[0027] For example, two data lines are respectively installed on both sides of the first power supply connecting line, and the orthogonal projections of the two data lines on the base substrate do not overlap with the orthogonal projections of the pixel openings of the first sub-pixels on the base substrate, and do not overlap with the orthogonal projections of the pixel openings of the second sub-pixels on the base substrate.

[0028] For example, the display substrate further includes a first power supply line, the first power supply line being configured to supply a first voltage signal to the pixel circuit, the first power supply line including a first power supply connecting line extending along a first direction and a first power supply signal line extending along a second direction, a vertical projection of the first power supply connecting line on the base substrate overlaps with a vertical projection of the pixel opening on the base substrate, the pixel opening has a maximum dimension along the second direction of W0, the subpixel includes a first subpixel and a second subpixel adjacent to each other in the second direction, one of the two first power supply connecting lines has a dimension in the second direction of Xb1, the other of the two first power supply connecting lines has a dimension in the second direction of Xb2, and a value range of (Xb1+Xb2) / W0 is [0.08, 0.48].

[0029] For example, the display substrate further includes a driving circuit, the driving circuit is located on one side of the display substrate, a subpixel away from the driving circuit has a first luminance L1, a subpixel close to the driving circuit has a second luminance L2, and the value range of |L1-L2| is [1, 9].

[0030] For example, the display substrate further includes two driving circuits, the two driving circuits being located on opposite sides of the display area of ​​the display substrate, a subpixel on the central axis of the display substrate has a third luminance L3, a subpixel adjacent to one of the two driving circuits has a fourth luminance L4, the extension direction of the central axis of the display substrate is the same as the extension direction of the driving circuits, and the value range of |L3-L4| is [1, 9].

[0031] For example, a first limiting portion is provided between two pixel openings adjacent in a first direction, a second limiting portion is provided between two pixel openings adjacent in a second direction, the first direction and the second direction intersect, the thickness of the first limiting portion is H1, the thickness of the second limiting portion is H2, and H1≠H2.

[0032] For example, H1 is smaller than H2.

[0033] For example, the display substrate further includes an insulating layer, a barrier dam, and a packaging layer, the light-emitting element includes a first electrode, a second electrode, and a light-emitting functional layer located between the first electrode and the second electrode, the first electrode of the light-emitting element is connected to the pixel circuit by a via that penetrates the insulating layer, the packaging layer is configured to package the light-emitting element, the packaging layer includes a laminate of an inorganic packaging film and an organic packaging film, a packaging adhesive is provided on the outside of the packaging layer, the insulating layer includes a planarization layer, the planarization layer includes a first planar portion and a second planar portion, a groove is provided between the first planar portion and the second planar portion, the barrier dam is located on the outer periphery of the display area of ​​the display substrate, and the orthogonal projection of the barrier dam on the base substrate covers the orthogonal projection of the groove on the base substrate.

[0034] For example, the display substrate further includes a data line, a first gate line, a second gate line, and a first initialization line, the pixel circuit further includes a data write transistor and a first reset transistor, a first pole of the data write transistor is connected to the data line, a gate of the drive transistor is connected to a second pole of the data write transistor, the gate of the data write transistor is connected to the first gate line, a first pole of the first reset transistor is connected to the first initialization line, a second pole of the first reset transistor is connected to the gate of the drive transistor, and the gate of the first reset transistor is connected to the second gate line, a dummy sub-pixel is provided near an edge of the display substrate, the dummy sub-pixel has a dummy drive transistor and a first dummy reset transistor, the first dummy reset transistor is connected to the gate of the dummy drive transistor, and the first dummy reset transistor is disconnected from the first initialization line.

[0035] For example, the display substrate further includes a dummy data line, the dummy data line extends along a first direction, the dummy data line and the data line are insulated from each other, the dummy subpixel includes at least two dummy subpixels adjacent to each other in a second direction, and the dummy data lines of the at least two dummy subpixels are connected to each other.

[0036] For example, the dummy data line is configured to supply a constant voltage by being connected to a constant voltage terminal.

[0037] For example, the at least two dummy subpixels include a first dummy subpixel, a second dummy subpixel, and a third dummy subpixel, and three dummy data lines of the first dummy subpixel, the second dummy subpixel, and the third dummy subpixel are connected to each other.

[0038] For example, the display substrate further includes a first power line, the pixel circuit further includes an emission control transistor, a first pole of the emission control transistor is connected to the first power line and a second pole of the emission control transistor is connected to the second pole of the driving transistor, and the dummy sub-pixel further includes a dummy emission control transistor, a first pole of the dummy emission control transistor is disconnected from the first power line and a second pole of the dummy emission control transistor is connected to the second pole of the dummy driving transistor.

[0039] For example, the display substrate further includes a pixel limiting layer, the pixel limiting layer including a limiting portion, the pixel opening being limited by the limiting portion, the light-emitting element including a first electrode and a light-emitting functional layer, the pixel limiting layer being configured to expose at least a portion of the first electrode, and the light-emitting functional layer covering a sidewall of the limiting portion.

[0040] For example, the light emitting element further includes a second electrode, the light emitting functional layer is located between the first electrode and the second electrode, and the second electrode is in contact with the top wall of the limiting portion.

[0041] For example, the display substrate further includes an insulating layer, a first electrode of the light-emitting element is connected to the pixel circuit by a via penetrating the insulating layer, the limiting portion includes a first limiting portion and a second limiting portion, a thickness of the first limiting portion is smaller than a thickness of the second limiting portion, and a positive projection of the via on the base substrate overlaps with a positive projection of the first limiting portion on the base substrate.

[0042] For example, the display substrate further includes a dummy pixel limiting layer, the dummy pixel limiting layer includes a plurality of dummy limiting portions, the extension direction of the dummy limiting portions is the same as the extension direction of the second limiting portions, and the distance between two adjacent dummy limiting portions is larger than the distance between two adjacent second limiting portions.

[0043] For example, the distance between two adjacent dummy limiting portions is 2 to 20 times the distance between two adjacent second limiting portions.

[0044] For example, the display substrate further includes a second reset transistor, a second initialization line, and an initialization bus, the initialization bus being provided outside the display area of ​​the display substrate, a first pole of the second reset transistor being connected to the initialization bus by the second initialization line, a second pole of the second reset transistor being connected to the light-emitting element by the driving transistor, the second reset transistor being connected to sub-pixels in one row, and the number of the second reset transistors for sub-pixels in the same row being less than the number of the sub-pixels.

[0045] For example, the display substrate further includes a light-emitting control transistor, a first power line, and a first power bus, the first power line being configured to supply a first voltage signal to the pixel circuit, the first power line being connected to the first power bus, a first pole of the light-emitting control transistor being connected to the first power line, and a second pole of the light-emitting control transistor being connected to the second pole of the driving transistor, and the number of light-emitting control transistors in one row of sub-pixels being less than the number of sub-pixels in the row.

[0046] For example, the number of light-emission control transistors in one row of sub-pixels is greater than the number of second reset transistors.

[0047] For example, the second electrode plate is installed in the same layer as the channel of the driving transistor, the second electrode plate is closer to the base substrate than the first electrode plate, and the orthogonal projection of the second electrode plate on the base substrate overlaps with the orthogonal projection of the pixel opening on the base substrate.

[0048] An embodiment of the present disclosure further provides a display substrate, comprising: a base substrate; and a plurality of sub-pixels disposed on the base substrate, each sub-pixel including a driving transistor and a storage capacitor, the storage capacitor having a first plate and a second plate, the first plate of the storage capacitor being connected to a gate of the driving transistor and the second plate of the storage capacitor being connected to a first electrode of the driving transistor; and a light-emitting element electrically connected to the pixel circuit, the pixel circuit being configured to drive the light-emitting element, the sub-pixels including pixel apertures configured to define a light-emitting area of ​​the sub-pixels, an orthogonal projection of the storage capacitor on the base substrate overlaps with an orthogonal projection of the pixel aperture on the base substrate, and a channel of the driving transistor overlaps with the base substrate of the pixel aperture. the orthogonal projection on the plate overlaps with the orthogonal projection of the pixel opening on the base substrate; the second plate is disposed on the same layer as the channel of the driving transistor, and is closer to the base substrate than the first plate; the display substrate satisfies the relationship (W*L+S2)*M1 / M2, which has a value range of [0.014, 0.133], and P=k0*(W / L)*Uc, where k0 has a value range of [2.8*E-07, 5.8*E-06], where W is the channel width of the driving transistor, L is the channel length of the driving transistor, S2 is the facing area between the second plate and the first plate, M1 is the number of pixel openings on the display substrate, M2 is the area of ​​the display substrate, Uc is the step voltage of the light-emitting element, and P is the power consumption of the sub-pixel.

[0049] An embodiment of the present disclosure further provides a display substrate, comprising: a base substrate; and a plurality of sub-pixels disposed on the base substrate, each sub-pixel including a driving transistor and a storage capacitor, the storage capacitor having a first plate and a second plate, the first plate of the storage capacitor being connected to a gate of the driving transistor and the second plate of the storage capacitor being connected to a first electrode of the driving transistor; and a light-emitting element electrically connected to the pixel circuit, the pixel circuit being configured to drive the light-emitting element, the sub-pixels including pixel apertures configured to define a light-emitting area of ​​the sub-pixels, an orthogonal projection of the storage capacitor on the base substrate overlaps with an orthogonal projection of the pixel aperture on the base substrate, and the orthogonal projection of the channel of the driving transistor overlaps with an orthogonal projection of the pixel aperture on the base substrate, the orthogonal projection on the base substrate overlaps with the orthogonal projection of the pixel opening on the base substrate; the second electrode plate is disposed in the same layer as the channel of the driving transistor; the second electrode plate is closer to the base substrate than the first electrode plate; a first limiting portion is disposed between two pixel openings adjacent to each other in a first direction; a second limiting portion is disposed between two pixel openings adjacent to each other in a second direction; the first direction and the second direction intersect; a thickness of the first limiting portion is H1, a thickness of the second limiting portion is H2, and H1≠H2; and the display substrate satisfies a relationship in which the value range of S2 / (W*L) is [2.82, 28.85], where W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and S2 is the facing area of ​​the second electrode plate and the first electrode plate.

[0050] An embodiment of the present disclosure further provides a display substrate, comprising: a base substrate; and a plurality of sub-pixels disposed on the base substrate, each sub-pixel including a driving transistor and a storage capacitor, the storage capacitor including a first plate and a second plate, the first plate of the storage capacitor being connected to a gate of the driving transistor and the second plate of the storage capacitor being connected to a first electrode of the driving transistor; and a light-emitting element electrically connected to the pixel circuit, the pixel circuit being configured to drive the light-emitting element, each sub-pixel including a pixel aperture configured to limit a light-emitting area of ​​the sub-pixel, an orthogonal projection of the storage capacitor on the base substrate overlaps with an orthogonal projection of the pixel aperture on the base substrate, an orthogonal projection of a channel of the driving transistor on the base substrate overlaps with an orthogonal projection of the pixel aperture on the base substrate, the second plate being disposed in the same layer as the channel of the driving transistor, the second plate being closer to the base substrate than the first plate; and the display substrate is formed of an insulating layer, a barrier dam, and a pattern the first electrode of the light-emitting element is connected to the pixel circuit by a via that penetrates the insulating layer; the packaging layer is configured to package the light-emitting element, the packaging layer including a laminate of an inorganic packaging film and an organic packaging film, and a packaging adhesive is provided on the outer side of the packaging layer; the insulating layer includes a planarization layer, the planarization layer including a first planar portion and a second planar portion, and a groove is provided between the first planar portion and the second planar portion; the barrier dam is located on the outer periphery of the display area of ​​the display substrate, and an orthogonal projection of the barrier dam on the base substrate covers an orthogonal projection of the groove on the base substrate; and the display substrate satisfies a relationship in which the value range of S2 / (W*L) is [2.82, 28.85], where W is the channel width of the driving transistor, L is the channel length of the driving transistor, and S2 is the facing area between the second electrode plate and the first electrode plate.

[0051] An embodiment of the present disclosure further provides a display substrate, comprising: a base substrate; and a plurality of sub-pixels disposed on the base substrate, each of the sub-pixels including a driving transistor and a storage capacitor, the storage capacitor having a first plate and a second plate, the first plate of the storage capacitor being connected to a gate of the driving transistor and the second plate of the storage capacitor being connected to a first electrode of the driving transistor; and a light-emitting element electrically connected to the pixel circuit, the pixel circuit being configured to drive the light-emitting element, the sub-pixels including a pixel aperture configured to define a light-emitting area of ​​the sub-pixel; The orthogonal projection of the capacitor on the base substrate overlaps with the orthogonal projection of the pixel opening on the base substrate, the orthogonal projection of the channel of the driving transistor on the base substrate overlaps with the orthogonal projection of the pixel opening on the base substrate, the second plate is installed in the same layer as the channel of the driving transistor, and the second plate is closer to the base substrate than the first plate, and the display substrate satisfies a relationship in which the value range of S2 / (W*L) is [2.82, 28.85], where W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and S2 is the facing area of ​​the second plate and the first plate.

[0052] An embodiment of the present disclosure further provides a display substrate, comprising: a base substrate; and a plurality of sub-pixels disposed on the base substrate, each sub-pixel comprising a driving transistor and a storage capacitor, the storage capacitor having a first plate and a second plate, a pixel circuit, the first plate of the storage capacitor being connected to a gate of the driving transistor and the second plate of the storage capacitor being connected to a first electrode of the driving transistor; and a light-emitting element electrically connected to the pixel circuit, the pixel circuit being configured to drive the light-emitting element, each sub-pixel comprising a pixel aperture configured to limit a light-emitting area of ​​the sub-pixel, an orthogonal projection of the storage capacitor on the base substrate overlaps with an orthogonal projection of the pixel aperture on the base substrate, an orthogonal projection of the channel of the driving transistor on the base substrate overlaps with an orthogonal projection of the pixel aperture on the base substrate, the second plate being disposed in the same layer as the channel of the driving transistor, the second plate being closer to the base substrate than the first plate; the display substrate further comprises a data line, a first gate line, a second gate line, and a first initialization line; a first electrode of the data write transistor connected to the data line, a gate of the drive transistor connected to a second electrode of the data write transistor, a gate of the data write transistor connected to the first gate line, a first electrode of the first reset transistor connected to the first initialization line, a second electrode of the first reset transistor connected to the gate of the drive transistor, and a gate of the first reset transistor connected to the second gate line; dummy sub-pixels are provided near the edges of the display substrate, each dummy sub-pixel having a dummy drive transistor and a first dummy reset transistor, the first dummy reset transistor being connected to the gate of the dummy drive transistor and isolated from the first initialization line; and the display substrate satisfies a relationship in which S2 / (W*L) is in the range of [2.82, 28.85], where W is the channel width of the drive transistor, L is the channel length of the drive transistor, and S2 is the facing area of ​​the second electrode plate and the first electrode plate.

[0053] An embodiment of the present disclosure further provides a display substrate, comprising: a base substrate; and a plurality of sub-pixels disposed on the base substrate, each sub-pixel including a driving transistor and a storage capacitor, the storage capacitor having a first plate and a second plate, the first plate of the storage capacitor being connected to a gate of the driving transistor and the second plate of the storage capacitor being connected to a first electrode of the driving transistor; and a light-emitting element electrically connected to the pixel circuit, the pixel circuit being configured to drive the light-emitting element, the sub-pixels including pixel apertures configured to define a light-emitting area of ​​the sub-pixels, an orthogonal projection of the storage capacitor on the base substrate overlaps with an orthogonal projection of the pixel aperture on the base substrate, and a channel of the driving transistor being connected to the base substrate. the orthogonal projection of the pixel opening on the display substrate overlaps with the orthogonal projection of the pixel opening on the base substrate, the second electrode plate is disposed in the same layer as the channel of the driving transistor, and the second electrode plate is closer to the base substrate than the first electrode plate; the display substrate further comprises a pixel limiting layer, the pixel limiting layer including a limiting portion, the pixel opening being limited by the limiting portion; the light-emitting element including a first electrode and a light-emitting functional layer, the pixel limiting layer being configured to expose at least a portion of the first electrode, and the light-emitting functional layer covering a sidewall of the limiting portion; and the display substrate satisfies a relationship in which the value range of S2 / (W*L) is [2.82, 28.85], where W is the width of the channel of the driving transistor, L is the length of the channel of the driving transistor, and S2 is the facing area of ​​the second electrode plate and the first electrode plate.

[0054] For example, any one of the above display substrates that satisfies the value range of S2 / (W*L) is [2.82, 28.85] may further satisfy the relationship that the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133], where M1 is the number of pixel openings of the display substrate and M2 is the area of ​​the display substrate.

[0055] For example, any one of the above display substrates that satisfies the value range of S2 / (W*L) is [2.82, 28.85] and / or the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133] may further satisfy the relationship P=k0*(W / L)*Uc, where k0 is in the value range of [2.8*E-07, 5.8*E-06], Uc is the step voltage of the light-emitting element, and P is the power consumption of the sub-pixel.

[0056] An embodiment of the present disclosure further provides a display device including any one of the above display substrates.

[0057] In order to more clearly describe the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments are briefly described below. Obviously, the drawings described below only relate to some embodiments of the present disclosure, and do not limit the present disclosure. [Brief explanation of the drawings]

[0058] [Figure 1] FIG. 1 is a schematic diagram of a pixel array on a display substrate. [Figure 2] FIG. 2 is a schematic diagram showing how pixel circuits in a display substrate according to an embodiment of the present disclosure drive light-emitting elements to emit light. [Figure 3] FIG. 3 is a circuit schematic diagram of a display substrate according to another embodiment of the present disclosure. [Figure 4] FIG. 4 is a circuit schematic diagram of a display substrate according to another embodiment of the present disclosure. [Figure 5] FIG. 5 is a layout diagram of a display substrate according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a cross-sectional view taken along line A1-A2 in FIG. [Figure 7] 7A to 7G are plan views of a single layer of the display substrate in FIG. [Figure 8] 8A to 8E are plan views of a layered structure of a portion of the display substrate in FIG. 5, and FIG. 8F is a schematic diagram of the width and length of the channel of the drive transistor on the display substrate in FIG. [Figure 9]FIG. 9 is a layout diagram of a display substrate according to an embodiment of the present disclosure. [Figure 10] FIG. 10 is a layout diagram of a display substrate according to another embodiment of the present disclosure. [Figure 11] FIG. 11 is a layout diagram of a display substrate according to another embodiment of the present disclosure. [Figure 12] FIG. 12 is a layout diagram of a display substrate according to another embodiment of the present disclosure. [Figure 13] FIG. 13 is a layout diagram of a display substrate according to another embodiment of the present disclosure. [Figure 14] FIG. 14 is a layout diagram of a display substrate according to another embodiment of the present disclosure. [Figure 15] FIG. 15 is a stacking diagram of some of the film layers in FIG. [Figure 16] FIG. 16 is a layout diagram of a display substrate according to another embodiment of the present disclosure. [Figure 17] FIG. 17 is a stacking diagram of some of the film layers in FIG. [Figure 18] FIG. 18 is a stacking diagram of a portion of film layers of a display substrate according to one embodiment of the present disclosure. [Figure 19] FIG. 19 is a stacking diagram of a portion of film layers of a display substrate according to one embodiment of the present disclosure. [Figure 20] FIG. 20 is a stacking diagram of a portion of film layers of a display substrate according to one embodiment of the present disclosure. [Figure 21] FIG. 21 is a schematic diagram of a center pixel of a display substrate according to an embodiment of the present disclosure. [Figure 22] FIG. 22 is a cross-sectional view taken along line B1-B2 in FIG. [Figure 23] FIG. 23 is a schematic diagram of the coordinate distances of chromaticity coordinate points at two different angles of view of the display substrate. [Figure 24] FIG. 24 is a layout diagram of a display substrate according to an embodiment of the present disclosure. [Figure 25] FIG. 25 is a plan view of a display substrate according to an embodiment of the present disclosure. [Figure 26] FIG. 26 is a plan view of a display substrate according to an embodiment of the present disclosure. [Figure 27] FIG. 27 is a plan view of a display substrate according to an embodiment of the present disclosure. [Figure 28] FIG. 28 is a plan view of a display substrate according to an embodiment of the present disclosure. [Figure 29] FIG. 29 is a layout diagram of a display substrate according to an embodiment of the present disclosure. [Figure 30] FIG. 30 is a schematic diagram of a display substrate according to an embodiment of the present disclosure. [Figure 31] FIG. 31 is a schematic diagram of a display substrate according to an embodiment of the present disclosure. [Figure 32] FIG. 32 is a schematic diagram of a display substrate according to an embodiment of the present disclosure. [Figure 33A] FIG. 33A is a plan view of a pixel confining layer on a display substrate according to an embodiment of the present disclosure. [Figure 33B] FIG. 33B is a plan view of a pixel confining layer on a display substrate according to an embodiment of the present disclosure. [Figure 34] FIG. 34 is a schematic diagram of a display substrate according to an embodiment of the present disclosure. [Figure 35] FIG. 35 is an electron microscope view of a display substrate according to an embodiment of the present disclosure. [Figure 36] FIG. 36 is a schematic diagram of a display substrate according to an embodiment of the present disclosure. [Figure 37] FIG. 37 is a schematic diagram of a display substrate according to an embodiment of the present disclosure. [Figure 38] FIG. 38 is a circuit schematic diagram of a dummy sub-pixel on a display substrate according to an embodiment of the present disclosure. [Figure 39] FIG. 39 is a layout diagram of dummy pixel circuits on a display substrate according to an embodiment of the present disclosure. [Figure 40] FIG. 40 is a schematic diagram of a display substrate according to an embodiment of the present disclosure. [Figure 41A] FIG. 41A is a schematic diagram of a display substrate according to one embodiment of the present disclosure. [Figure 41B] FIG. 41B is a schematic diagram of a display substrate according to another embodiment of the present disclosure. [Figure 42]FIG. 42 is a schematic diagram of a display substrate according to an embodiment of the present disclosure. [Figure 43] FIG. 43 is a schematic diagram of a display substrate according to an embodiment of the present disclosure. [Figure 44] FIG. 44 is a circuit diagram of a display substrate according to an embodiment of the present disclosure. [Figure 45] FIG. 45 is a schematic diagram of a display substrate according to an embodiment of the present disclosure. [Figure 46] FIG. 46 is a schematic diagram of a brightness test of a display substrate according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0059] In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, but not all of the embodiments. Based on the described embodiments of the present disclosure, any other embodiments that a person skilled in the art can obtain without inventive efforts fall within the scope of protection of the present disclosure.

[0060] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meaning understood by those skilled in the art to which this disclosure belongs. The terms "first," "second," and similar terms used in this disclosure do not denote any order, number, or importance, but are merely used to distinguish different components. Similarly, similar terms such as "comprise" or "include" refer to the elements or components described before the term covering the elements or components listed after the term and their equivalents, without excluding other elements or components. Similar terms such as "connect" or "coupled" are not limited to physical or mechanical connections, but also include electrical connections, whether direct or indirect. Terms such as "top," "bottom," "left," "right," and the like only refer to relative positions, and if the absolute positions of the described objects change, the relative positions may change accordingly.

[0061] In a typical organic light-emitting diode display, the organic light-emitting layer needs to be completed by a deposition process, which imposes strict requirements on the process conditions and makes it difficult to realize a large area.

[0062] Inkjet printing to produce OLED light-emitting material layers is the optimal method for achieving low-cost OLED production and enabling OLED displays to compete in the mid- to high-end market. Inkjet printing is an efficient process, with less material waste than evaporation printing and much faster printing speed.

[0063] When forming the light-emitting functional layer of an organic light-emitting diode (OLED) using inkjet printing, organic materials are typically dissolved in a solvent to form a solution (ink), which is then spray-printed directly onto the surface of a base substrate to form light-emitting functional layers for subpixels, such as red (R), green (G), and blue (B). Compared with evaporation techniques, inkjet-printed OLED technology offers obvious technological advantages in terms of manufacturing process, yield, and cost. For example, the light-emitting functional layer may include multiple film layers, such as an emitting layer (light-emitting material layer), which may further include at least one of a hole injection layer, a hole transport layer, an electron transport layer, an electron injection layer, etc. The organic light-emitting functional layer may be selected as needed. At least one film layer in the light-emitting functional layer may be manufactured using an inkjet printing process.

[0064] Because polymers have larger molecular weights, they are mainly formed into films by solution processing, such as spin coating or printing, but inkjet printing technology is the optimal method for preparing light-emitting polymer solutions. In recent years, people have been making efforts to improve the pixel resolution and film uniformity of display screens and extend their service life, and research into the formation of photoelectric materials using inkjet printing has become increasingly active. For example, film layers such as the hole transport layer, hole injection layer, and light-emitting layer of a display screen can all be manufactured using inkjet printing technology, laying the foundation for the manufacture of display screens using a fully printed method.

[0065] When the film layer of the light-emitting functional layer is manufactured using an inkjet printing process, the flatness of the light-emitting functional layer is more demanding. The flatter the light-emitting functional layer in each subpixel, the more likely it is to reduce or avoid color cast, and the better the display effect of the display substrate. Achieving a flat light-emitting functional layer can be achieved by adjusting the structure of the display substrate. The display substrate according to the embodiment of the present disclosure can solve the color cast problem at 45-degree and 60-degree left and right viewing angles of the entire display substrate.

[0066] FIG. 1 is a schematic diagram of a pixel arrangement on a display substrate. As shown in FIG. 1, the display substrate includes a plurality of sub-pixels 100 located on a base substrate, and the plurality of sub-pixels 100 are arranged in an array. As shown in FIG. 1, the plurality of sub-pixels 100 are arranged in an array along a first direction Y and a second direction X. Although the embodiments of the present disclosure will be described using the plurality of sub-pixels 100 arranged in an array as shown in FIG. 1 as an example, the arrangement of the plurality of sub-pixels 100 is not limited to that shown in FIG. 1.

[0067] As shown in FIG. 1, the display substrate includes a plurality of pixels PX, each of which includes a plurality of subpixels 100. As shown in FIG. 1, the plurality of subpixels 100 includes a first subpixel 101, a second subpixel 102, and a third subpixel 103. As shown in FIG. 1, each pixel PX includes a first subpixel 101, a second subpixel 102, and a third subpixel 103. The first subpixel 101, the second subpixel 102, and the third subpixel 103 emit light of different colors, and subpixels in the same column emit light of the same color. A plurality of pixels PX are sequentially arranged in the subpixels in the same row. In the embodiments of the present disclosure, a case will be described in which the first direction Y is the column direction and the second direction X is the row direction. In other embodiments, the first direction Y may be the row direction and the second direction X may be the column direction.

[0068] In the embodiment of the present disclosure, a case where the first sub-pixel 101 is a red sub-pixel, the second sub-pixel 102 is a green sub-pixel, and the third sub-pixel 103 is a blue sub-pixel will be described as an example.

[0069] As shown in Fig. 1, the base substrate BS includes a display region R01 and a peripheral region R02 located on at least one side of the display region R01. Fig. 1 will be described taking as an example a case where the peripheral region R02 surrounds the display region R01.

[0070] Fig. 2 is a schematic diagram showing a pixel circuit in a display substrate according to an embodiment of the present disclosure driving a light-emitting element to emit light. Fig. 3 is a schematic circuit diagram of a display substrate according to another embodiment of the present disclosure. Fig. 4 is a schematic circuit diagram of a display substrate according to another embodiment of the present disclosure.

[0071] As shown in Figures 2 to 4, each sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a is electrically connected to the light-emitting element 100b and configured to drive the light-emitting element 100b. For example, the pixel circuit 100a is configured to drive the light-emitting element 100b to emit light. The light-emitting element 100b includes a light-emitting area. The pixel array shown in Figure 1 refers to the location of the light-emitting area of ​​the light-emitting element 100b in the sub-pixel 100.

[0072] 2 and 3 include a pixel circuit and a light emitting element in one sub-pixel. Three sub-pixels are shown in Fig. 4. The three sub-pixels in Fig. 4 are located in one row.

[0073] For example, as shown in Figures 2 to 4, in the sub-pixel 100, the pixel circuit 100a includes a data write transistor T1, a reset transistor T2, a drive transistor T3, and a storage capacitor Cst, and the light-emitting element 100b is connected to the drive transistor T3. The reset transistor T2 is configured to reset the gate T3g of the drive transistor T3. As shown in Figures 2 to 4, the storage capacitor Cst includes a first terminal C1 and a second terminal C2.

[0074] 2 to 4, the display substrate includes gate lines G1, G2, data lines DT, first power lines PL1, second power lines PL2, and an initialization line INT1. The gate line G2 may be referred to as a reset control signal line. For example, the first power line PL1 is configured to supply a constant first voltage signal VDD to the sub-pixel 100, and the second power line PL2 is configured to supply a constant second voltage signal VSS to the sub-pixel 100, with the first voltage signal VDD being greater than the second voltage signal VSS. The gate line G1 is configured to supply a scan signal SCAN to the sub-pixel 100, the gate line G2 is configured to supply a reset control signal RESET1 to the sub-pixel 100, and the data line DT is configured to supply a data signal (data voltage) DATA to the sub-pixel 100. The initialization line INT1 is configured to supply an initialization signal Vinit1 to the sub-pixel 100.

[0075] As shown in Figures 2 to 4, the driving transistor T3 is electrically connected to the light-emitting element 100b, and outputs a driving current under the control of signals such as a scanning signal SCAN, a data signal DATA, a first voltage signal VDD, and a second voltage signal VSS, thereby driving the light-emitting element 100b to emit light.

[0076] For example, the light emitting element 100b includes an organic light emitting diode (OLED), and the light emitting element 100b emits red light, green light, blue light, white light, etc. when driven by the corresponding pixel circuit 100a.

[0077] For example, as shown in Figures 2 to 4, the first electrode E1 of the light-emitting element 100b is connected to the first pole T3a of the driving transistor T3, the second electrode E2 of the light-emitting element 100b is connected to the second power line PL2, the second pole T3b of the driving transistor T3 is connected to the first power line PL1, the gate T3g of the driving transistor T3 is connected to the second pole T1b of the data write transistor T1, the first pole T1a of the data write transistor T1 is connected to the data line DT, and the gate T1g of the data write transistor T1 is connected to the gate line G1.

[0078] 2 to 4, the gate T3g of the drive transistor T3 is connected to the first terminal C1 of the storage capacitor Cst, the second terminal C2 of the storage capacitor Cst is connected to the first pole T3a of the drive transistor T3, and the first terminal C1 of the storage capacitor Cst is further connected to the second pole T1b of the data write transistor T1.

[0079] 2 to 4, the first electrode T2a of the reset transistor T2 is connected to the initialization line INT1, the second electrode T2b of the reset transistor T2 is connected to the gate T3g of the drive transistor T3, and the gate T2g of the reset transistor T2 is connected to the gate line G2. The first terminal C1 of the storage capacitor Cst is further connected to the second electrode T2b of the reset transistor T2.

[0080] For example, as shown in Figures 2 to 4, the gate T3g of the drive transistor T3, the first terminal C1 of the storage capacitor Cst, the second pole T1b of the data write transistor T1, and the second pole T2b of the reset transistor T2 are connected to each other, all connected to node N1, and are at the same potential.

[0081] For example, as shown in FIGS. 2 to 4, the second terminal C2 of the storage capacitor Cst, the first electrode E1 of the light-emitting element 100b, and the first electrode T3a of the driving transistor T3 are connected to each other, all connected to node N2, and are at the same potential.

[0082] For example, as shown in FIGS. 3 and 4, the display substrate further includes a reset transistor T4 configured to reset the first electrode E1 of the light emitting element 100b.

[0083] 3 and 4, the display substrate further includes a gate line G4, which may be referred to as a reset control signal line, configured to provide a reset control signal RESET2 to the reset transistor T4.

[0084] For example, as shown in FIGS. 3 and 4, the display substrate further includes an initialization line INT2 configured to provide an initialization signal Vinit2 to the reset transistor T4.

[0085] For example, as shown in Figures 3 and 4, the first electrode T4a of the reset transistor T4 is connected to the initialization line INT2, the second electrode T4b of the reset transistor T4 is connected to the first electrode E1 of the light-emitting element 100b, and the gate T4g of the reset transistor T4 is connected to the gate line G4.

[0086] For example, as shown in Figures 3 and 4, the second pole T4b of the reset transistor T4 is connected to the first electrode E1 of the light-emitting element 100b by the driving transistor T3, the first pole T3a of the driving transistor T3 is connected to the first electrode E1 of the light-emitting element 100b, and the second pole T3b of the driving transistor T3 is connected to the second pole T4b of the reset transistor T4.

[0087] For example, the initialization signal Vinit1 and the initialization signal Vinit2 may be constant voltage signals, and their magnitude may be between the first voltage signal VDD and the second voltage signal VSS, but this is not limited thereto. For example, the initialization signal Vinit1 and the initialization signal Vinit2 may both be equal to or less than the second voltage signal VSS.

[0088] For example, in some embodiments of the present disclosure, the initialization line INT1 and the initialization line INT2 are connected and configured to supply the same initialization signal, i.e., the initialization signal Vinit1 and the initialization signal Vinit2 are equal, but this is not limiting. In other embodiments, the initialization line INT1 and the initialization line INT2 are isolated from each other and supply different initialization signals.

[0089] For example, as shown in Fig. 2, the second electrode T3b of the driving transistor T3 is directly connected to the first power line PL1. As shown in Fig. 3 and Fig. 4, the display substrate further includes a gate line G5 and an emission control transistor T5, the gate line G5 is configured to supply an emission control signal EM to the emission control transistor T5, and the second electrode T3b of the driving transistor T3 is connected to the first power line PL1 by the emission control transistor T5.

[0090] For example, as shown in Figures 3 and 4, the first pole T5a of the light-emitting control transistor T5 is connected to the first power line PL1, the second pole T5b of the light-emitting control transistor T5 is connected to the second pole T3b of the driving transistor T3, and the gate T5g of the light-emitting control transistor T5 is connected to the gate line G5.

[0091] For example, as shown in Figures 3 and 4, the second pole T5b of the light-emitting control transistor T5, the second pole T4b of the reset transistor T4, and the second pole T3b of the driving transistor T3 are connected to each other, all connected to node N3, and are at the same potential.

[0092] 4, the plurality of sub-pixels 100 includes a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. For example, the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 are sequentially arranged along the second direction X. Of course, the sub-pixels within one pixel may be arranged in other ways.

[0093] For example, as shown in FIG. 4, the driving transistor T3 is a dual-gate transistor and includes a sub-transistor T31 and a sub-transistor T32. As shown in FIG. 4, the sub-transistor T31 and the sub-transistor T32 are connected in series. FIG. 4 illustrates an example in which the driving transistor T3 is a dual-gate transistor. In other embodiments, transistors other than the driving transistor T3 may be configured as dual-gate transistors. That is, each transistor in the pixel circuit may be configured as a single-gate transistor as needed, or as a dual-gate transistor as needed.

[0094] For example, as shown in FIGS. 3 and 4, the display substrate includes a reset signal transmission line INI, and the second pole T4b of the reset transistor T4 is connected to the second pole T3b (node ​​N3) of the drive transistor by the reset signal transmission line INI.

[0095] Fig. 5 is a layout diagram of a display substrate according to one embodiment of the present disclosure. Fig. 6 is a cross-sectional view taken along line A1-A2 in Fig. 5. Figs. 7A to 7G are plan views of a single layer of the display substrate in Fig. 5. Figs. 8A to 8E are plan views of a laminated portion of the display substrate in Fig. 5. Fig. 8F is a schematic diagram of the width and length of a channel of a driving transistor on the display substrate in Fig. 5.

[0096] For example, as shown in FIG. 6, the display substrate includes a base substrate BS, a barrier layer BR disposed on the base substrate BS, and a buffer layer BF. As shown in FIG. 6, an active layer LY0 and a gate insulating layer GI disposed on the active layer LY0 are disposed on the buffer layer BF. A first conductive pattern layer LY1 is disposed on the gate insulating layer GI, an interlayer insulating layer ILD is disposed on the first conductive pattern layer LY1, a second conductive pattern layer LY2 is disposed on the interlayer insulating layer ILD, an insulating layer ISL is disposed on the second conductive pattern layer LY2, and a first electrode layer LY3 is disposed on the insulating layer ISL. FIGS. 5 and 6 show the first terminal C1 and the second terminal C2 of the storage capacitor Cst. The first terminal C1 includes a first electrode plate Ca (shown in FIG. 7B), and the second terminal C2 includes a second electrode plate Cb (shown in FIG. 7A) and a third electrode plate Cc (shown in FIG. 7D).

[0097] For example, as shown in FIG. 6, the first conductive pattern layer LY1 is closer to the base substrate BS than the second conductive pattern layer LY2.

[0098] 5 and 6, a display substrate according to an embodiment of the present disclosure includes a base substrate BS and sub-pixels 100 disposed on the base substrate BS. A plurality of sub-pixels 100 may be disposed.

[0099] 5 and 6, the display substrate further includes a pixel confining layer PDL, and the sub-pixel 100 includes a pixel opening P0, which is configured to expose at least a portion of the first electrode E1 and to define a light-emitting area of ​​the sub-pixel 100. For example, as shown in FIG. 6, the slope angle of the portion of the pixel confining layer PDL that defines the pixel opening P0 is 40 to 65 degrees.

[0100] For example, as shown in Figures 5 and 6, the subpixel 100 includes a pixel circuit 100a and a light-emitting element 100b, the pixel circuit 100a includes a storage capacitor Cst, the second electrode plate Cb is closer to the base substrate BS than the first electrode plate Ca, the first electrode plate Ca is closer to the base substrate BS than the third electrode plate Cc, the light-emitting element 100b includes a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2, and the pixel circuit 100a is configured to drive the light-emitting element 100b.

[0101] 6 shows an example in which all the film layers of the light-emitting functional layer FL are formed by inkjet printing, that is, all the film layers of the light-emitting functional layer FL are disposed within the pixel opening P0. However, in other embodiments, some of the film layers of the light-emitting functional layer FL may be formed by inkjet printing, some of the film layers of the light-emitting functional layer FL may be formed by vapor deposition, and the film layers formed by vapor deposition may be common layers. For an embodiment in this case, see FIG. 45.

[0102] In some drawings of embodiments of the present disclosure, a first direction Y and a second direction X are shown in plan views, and a third direction Z is shown in cross-sectional views. The first direction Y and the second direction X are both parallel to the main surface of the base substrate BS. The third direction Z is perpendicular to the main surface of the base substrate BS. For example, the first direction Y and the second direction X intersect. The embodiments of the present disclosure will be described using an example in which the first direction Y and the second direction X are perpendicular. As shown in FIG. 6, the main surface of the base substrate BS is the surface on which each element on the base substrate BS is manufactured. As shown in FIG. 6, the upper surface of the base substrate BS is the main surface of the base substrate BS.

[0103] For example, as shown in Figures 5, 7B, and 7D, the first power supply line PL1 includes a first power supply signal line PL11 extending along the second direction X and a first power supply connecting line PL12 extending along the first direction Y, and the first power supply signal line PL11 is connected to the first power supply connecting line PL12.

[0104] For example, as shown in Figures 5, 7B and 7D, the data line DT extends along the first direction Y, the data line DT is formed in steps, the data line DT includes a first portion DTa, a second portion DTb and a third portion DTc, the first portion DTa and the third portion DTc are connected by the second portion DTb, the first portion DTa and the third portion DTc are located on the first conductive pattern layer LY1, and the second portion DTb is located on the second conductive pattern layer LY2.

[0105] In an embodiment of the present disclosure, elements located on the second conductive pattern layer LY2 may be connected to elements located on the first conductive pattern layer LY1 and elements located on the active layer LY0 by vias, and elements located on the first conductive pattern layer LY1 and elements located on the active layer LY0 may be connected by elements located on the second conductive pattern layer LY2.

[0106] For example, the insulating layer that a via passes through may be determined depending on the condition of the insulating layer between the two conductive pattern layers connected by the via.

[0107] 5, 7B, and 7D, in some embodiments of the display substrate of the present disclosure, a pixel circuit 100a is formed by an active layer LY0, a first conductive pattern layer LY1, and a second conductive pattern layer LY2, thereby simplifying the manufacturing process and reducing the thickness of the display substrate. The initialization line INT1 and / or the first power line PL1 may be referred to as a conductive structure 40, and the conductive structure 40 includes a signal transmission line 411 and a signal connecting line 412. The conductive structure 40 is configured to supply a voltage signal to the sub-pixel 100, the signal transmission line 411 extending along the second direction X, the signal connecting line 412 extending along the first direction Y, and the signal connecting line 412 electrically connected to the signal transmission line 411.

[0108] 5, the conductive structure 40 includes a conductive structure 400 and a conductive structure 401. As shown in FIG. 5, the first power supply line PL1 may be referred to as the conductive structure 400, and the initialization line INT1 may be referred to as the conductive structure 401.

[0109] For example, as shown in FIG. 5, the conductive structure 40 uses a mesh structure including a portion extending along the first direction Y (i.e., the signal connection line 412) and a portion extending along the second direction X (i.e., the signal transmission line 411).

[0110] For example, as shown in Figures 5, 7B, and 7D, the first power line PL1 of the pixel circuit 100a is formed by two conductive pattern layers. As shown in Figures 5, 7B, and 7D, the portions of the first power line PL1 extending in the first direction Y are all formed in a stepped manner. As shown in Figures 5 and 7D, the portions of the first power line PL1 extending in the second direction X are all located on the second conductive pattern layer LY2.

[0111] 5, 7B, and 7D, the signal connecting line 412 includes a first portion 412a, a second portion 412b, and a third portion 412c, the first portion 412a and the third portion 412c are connected by the second portion 412b, the first portion 412a and the third portion 412c are located on the first conductive pattern layer LY1, and the second portion 412b is located on the second conductive pattern layer LY2. The signal connecting line 412 includes a first power connecting line PL12.

[0112] For example, as shown in FIG. 5, the first portion PLa and the second portion PLb of the first power supply connecting line PL12 are connected by a via Va, and the second portion PLb and the third portion PLc of the first power supply connecting line PL12 are connected by a via Vb.

[0113] For example, as shown in FIG. 5, the first power supply signal line PL11 and the first power supply connecting line PL12 are connected by a via V0.

[0114] For example, as shown in FIG. 5, the first portion DTa and the second portion DTb of the data line DT are connected by a via Vc, and the second portion DTb and the third portion DTc of the data line DT are connected by a via Vd.

[0115] 7A shows the active layer LY0, which may include, but is not limited to, polycrystalline silicon.

[0116] The first conductive pattern layer LY1 is shown in Fig. 7B. As shown in Fig. 7B, the first conductive pattern layer LY1 includes a first terminal C1 (first electrode plate Ca), a connection electrode CEa, a connection electrode CEb, a connection electrode CEc, a connection electrode CEd, a connection electrode CEe, a first portion DTa of the data line DT, a third portion DTc of the data line DT, a first portion PLa of the first power supply connecting line PL12, and a third portion PLc of the first power supply connecting line PL12.

[0117] 7C shows the interlayer insulating layer ILD, and vias in the interlayer insulating layer ILD are shown in FIG. 7C. Vias V1 to V13, vias Va to Vd, and via V0 are shown in FIG.

[0118] 7D shows the second conductive pattern layer LY2. As shown in FIG. 7D, the second conductive pattern layer LY2 includes the third electrode Cc of the second terminal C2, the connection electrode CEf, the gate line G1, the gate line G2, the gate line G5, the reset signal transmission line INI, the initialization signal line INT11, and the first power signal line PL11.

[0119] 7E shows the insulating layer ISL and the vias in the insulating layer ISL. 7E shows the vias VH.

[0120] Fig. 7F shows the first electrode layer LY3 of the light-emitting element, and Fig. 7F shows the first electrode E1.

[0121] 7G shows the pixel confining layer PDL, which is indicated by a pixel opening P0 in the pixel confining layer PDL. The pixel opening P0 corresponds to the effective light-emitting area of ​​the sub-pixel. If the display substrate uses an inkjet printing process to manufacture at least one film layer in the light-emitting functional layer FL, the film layer manufactured by inkjet printing is located within the pixel opening P0 of the pixel confining layer PDL.

[0122] 5 to 8E, the first power supply signal line PL11 and the first power supply connecting line PL12 are connected by a via V0.

[0123] 5 to 8E, the connection electrode CEa is connected to the gate line G5 by a via V9, and serves as the gate of the light-emission control transistor T5.

[0124] 5 to 8E, one end of the connection electrode CEb is connected to the first power line PL1 (first power signal line PL11) by a via V11, and the other end of the connection electrode CEb is connected to the first pole T5a of the light-emission control transistor T5 by a via V10.

[0125] 5 to 8E, the connection electrode CEc is connected to the gate line G1 by a via V12, and serves as the gate of the data write transistor T1.

[0126] 5 to 8E, the data line DT is connected to the first pole T1a of the data write transistor T1 by a via V4.

[0127] 5 to 8E, the connection electrode CEd is connected to the gate line G2 by a via V6, and serves as the gate of the reset transistor T2.

[0128] 5 to 8E, one end of the connection electrode CEe is connected to the initialization line INT1 (initialization signal line INT11) by a via V7, and the other end of the connection electrode CEe is connected to the first pole T2a of the reset transistor T2 by a via V8.

[0129] 5 to 8E, one end of the connection electrode CEf is connected to the first terminal C1 (first electrode plate Ca, gate of the drive transistor T3) by a via V3, and the other end of the connection electrode CEf is connected to the first pole T1b of the data write transistor T1 (i.e., the second pole T2b of the reset transistor T2) by a via V5.

[0130] 5 to 8E, the third plate Cc of the second terminal C2 is connected to the second plate Cb of the second terminal C2 (ie, the first pole T3a of the driving transistor T3) by a via V2.

[0131] 5 to 8E, the reset signal transmission line INI is connected to the first pole T3a of the drive transistor T3 by a via V1, and the reset signal transmission line INI is connected to the second pole T5b of the light-emission control transistor T5 by a via V13.

[0132] 5 to 8E, the second electrode T5b of the light-emission control transistor T5 and the second electrode T3b of the drive transistor T3 are connected by a reset signal transmission line INI.

[0133] 7A, the first plate-shaped portion Cba and the second plate-shaped portion Cbb may both be connected to the channel T3c of the driving transistor T3, and the first plate-shaped portion Cba, the second plate-shaped portion Cbb, and the channel T3c of the driving transistor T3 may be located in the same layer. For example, the first plate-shaped portion Cba, the second plate-shaped portion Cbb, and the channel T3c of the driving transistor T3 may be integrated into one structure.

[0134] In the display substrate according to the embodiment of the present disclosure, the pattern design of the active layer LY0 is matched with the pattern design of the channel of the driving transistor and the capacitor plate located in the active layer, thereby optimizing the balance between light emission uniformity and power consumption, thereby improving the light emission uniformity of the display substrate and reducing power consumption.

[0135] 7A, the first plate-shaped portion Cba includes a first portion PR1 and a second portion PR2, the first portion PR1 extending along the first direction Y and the second portion PR2 extending along the second direction X, and the first portion PR1 and the second plate-shaped portion Cbb are arranged opposite each other and are respectively arranged on both sides of the channel T3c of the driving transistor T3 in the second direction X. In FIG. 7A, the first portion PR1, the second portion PR2, and the second plate-shaped portion Cbb are divided by dashed lines.

[0136] 5, 7A, 8B, and 8E, the second plate Cb and the channel of the driving transistor T3 may be integral and formed from the same film using the same patterning process. The channel of the driving transistor T3 is made of a semiconductor material, and the second plate Cb is a conductor made of the semiconductor material doped.

[0137] FIG. 8B shows a channel T1c of the data write transistor T1, a channel T2c of the reset transistor T2, a channel T3c of the drive transistor T3, and a channel T5c of the light-emitting control transistor T5.

[0138] Fig. 9 is a layout diagram of a display substrate according to one embodiment of the present disclosure, Fig. 10 is a layout diagram of a display substrate according to another embodiment of the present disclosure, and Fig. 11 is a layout diagram of a display substrate according to another embodiment of the present disclosure.

[0139] 9 shows two subpixels 100, namely, a first subpixel 101 and a second subpixel 102. As shown in FIG. 9, the first subpixel 101 and the second subpixel 102 are adjacent to each other and sequentially arranged along the second direction X. As shown in FIG. 9, the layout of the pixel circuit of the first subpixel 101 and the layout of the pixel circuit of the second subpixel 102 use a mirror image design. As shown in FIG. 9, the pixel circuit of the first subpixel 101 and the pixel circuit of the second subpixel 102 are axially symmetric with respect to a line extending along the first direction Y.

[0140] 9, the pixel aperture P0 (pixel aperture P01) of the first sub-pixel 101 and the pixel aperture P0 (pixel aperture P02) of the second sub-pixel 102 both overlap with the first power line PL1 (first power supply connecting line PL12). That is, the orthogonal projection of the pixel aperture P01 on the base substrate overlaps with the orthogonal projection of the first power supply line PL1 (first power supply connecting line PL12) on the base substrate, and the orthogonal projection of the pixel aperture P02 on the base substrate overlaps with the orthogonal projection of the first power supply line PL1 (first power supply connecting line PL12) on the base substrate. The portion of the first power supply line PL1 (first power supply connecting line PL12) located directly below the aperture P0 can serve as a planarization layer, further increasing the flatness of the light-emitting layer and thereby reducing color cast, for example, by reducing color cast at the horizontal angle of view, thereby further improving display quality. That is, the central axis of the third electrode plate Cc of the storage capacitor in the first direction Y is brought closer to the central axis C0 of the pixel opening P0 extending along the first direction Y, and both sides of the third electrode plate Cc in the pixel opening P0 are planarized by the signal line. Of course, the adjacent subpixels in FIG. 9 are not limited to the first subpixel 101 and the second subpixel 102, but may be other forms, such as the adjacent second subpixel 102 and the adjacent third subpixel 103, or the adjacent first subpixel 101 and the adjacent third subpixel 103. Both of the two adjacent subpixels in FIG. 9 overlap with the first power supply connecting line PL12, and the embodiments of the present disclosure include, but are not limited to, this situation. For example, in some embodiments, one of the two adjacent subpixels may overlap with the first power supply connecting line PL12, but the other of the two adjacent subpixels may not overlap with the first power supply connecting line PL12.

[0141] As shown in Fig. 10, the third electrode plate Cc and the first power connection line PL12 are respectively disposed on both sides of the central axis C0. In the display substrate shown in Fig. 10, the occupancy rate of the first power connection line PL1 (first power connection line PL12) in the width direction of the pixel opening (second direction X) is larger than , i.e., the planarization dimension of the first power connection line PL12 in the width direction of the pixel opening is larger than . As a result, the third electrode plate Cc and the first power connection line PL12 disposed on both sides of the central axis C0 both play a planarizing role, thereby increasing the planarization of the light-emitting layer and reducing color cast, for example, color cast in the horizontal field of view, thereby further improving display quality. Fig. 10 shows a case where the third sub-pixel 103 and the first sub-pixel 101 are adjacently arranged in sequence along the second direction X.

[0142] 10 , the maximum dimension W0 of the pixel aperture P03 of the third subpixel 103 along the second direction X is different from the maximum dimension W0 of the pixel aperture P01 of the first subpixel 101 along the second direction X. Correspondingly, the overlapping area between the first power supply connecting line PL12 and the pixel aperture P03 of the third subpixel 103 is different from the overlapping area between the first power supply connecting line PL12 and the pixel aperture P01 of the first subpixel 101. For example, the ratio of the overlapping area between the first power supply connecting line PL12 and the pixel aperture P03 of the third subpixel 103 to the area of ​​the pixel aperture P03 of the third subpixel 103 is equal to or approximately equal to the ratio of the overlapping area between the first power supply connecting line PL12 and the pixel aperture P01 of the first subpixel 101 to the area of ​​the pixel aperture P01 of the first subpixel 101.

[0143] 10, the maximum dimension W0 of the pixel aperture P03 of the third subpixel 103 along the second direction X is larger than the maximum dimension W0 of the pixel aperture P01 of the first subpixel 101 along the second direction X. Correspondingly, the overlapping area between the first power supply connecting line PL12 and the pixel aperture P03 of the third subpixel 103 is larger than the overlapping area between the first power supply connecting line PL12 and the pixel aperture P01 of the first subpixel 101.

[0144] As shown in FIG. 10, the overlap dimension in the second direction X between the first power supply connecting line PL12 and the pixel opening P03 of the third sub-pixel 103 is larger than the overlap dimension in the second direction X between the first power supply connecting line PL12 and the pixel opening P01 of the first sub-pixel 101.

[0145] FIG. 10 shows the maximum dimension W03 of the pixel aperture P03 of the third sub-pixel 103 along the second direction X and the maximum dimension W01 of the pixel aperture P01 of the first sub-pixel 101 along the second direction X.

[0146] 11 shows a case where one of the pixel openings P0 of two adjacent subpixels 100 overlaps with the first power supply connecting line PL12, but the other of the pixel openings P0 of the two adjacent subpixels 100 does not overlap with the first power supply connecting line PL12. That is, the first power supply connecting line PL12 serves as a planarizing element for one of the adjacent subpixels. For example, the first power supply connecting line PL12 serves as a planarizing element for at least one of the adjacent subpixels.

[0147] 3 to 11, an embodiment of the present disclosure provides a display substrate, including a base substrate BS and a plurality of sub-pixels 100 disposed on the base substrate BS. Each sub-pixel 100 includes a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a includes a driving transistor T3 and a storage capacitor Cst, the storage capacitor Cst having a first plate Ca and a second plate Cb, the first plate Ca of the storage capacitor Cst being connected to a gate T3g of the driving transistor T3 and the second plate Cb of the storage capacitor Cst being connected to a first electrode T3a of the driving transistor T3. The light-emitting element 100b is electrically connected to the pixel circuit 100a, and the pixel circuit 100a is configured to drive the light-emitting element 100b. The sub-pixel 100 includes a pixel aperture P0 configured to define a light-emitting area of ​​the sub-pixel 100.

[0148] As shown in FIG. 5, the orthogonal projection of the storage capacitor Cst on the base substrate BS overlaps with the orthogonal projection of the pixel aperture P0 on the base substrate BS.

[0149] 5, 8E, 8F, and 9 to 11, the orthogonal projection of the channel T3c of the driving transistor T3 on the base substrate BS overlaps with the orthogonal projection of the pixel opening P0 on the base substrate BS. In FIGS. 8E and 8F, the portion of the active layer LY0 indicated by the dashed cross is a semiconductor, such as polycrystalline silicon, and the remaining portion is a conductor, such as doped polycrystalline silicon. In embodiments of the present disclosure, the semiconductor may be formed into a conductor by a doping process. For example, but not limited to, the doping process may be performed before forming the first conductive pattern layer LY1.

[0150] As shown in Figures 5, 6, 7A, 7B, 8A, 8B, 8E, and 9 to 11, the second electrode plate Cb is placed in the same layer as the channel T3c (shown in Figures 7A and 8E) of the driving transistor T3, the second electrode plate Cb is closer to the base substrate BS than the first electrode plate Ca, and the orthogonal projection of the second electrode plate Cb on the base substrate BS overlaps with the orthogonal projection of the pixel opening P0 on the base substrate BS.

[0151] For example, the display substrate satisfies the relationship that the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133] and the value range of S2 / (W*L) is [2.82, 28.85].

[0152] As shown in Figures 7A, 8E, and 8F, W is the width of the channel T3c of the driving transistor T3, L is the length of the channel T3c of the driving transistor T3, and as shown in Figures 5, 6, and 9 to 11, S2 is the area of ​​the second electrode plate Cb facing the first electrode plate Ca, M1 is the number of pixel openings P0 on the display substrate, and M2 is the area of ​​the display substrate. For example, M2 is the total area of ​​the display substrate in a plan view. For example, M2 is the sum of the area of ​​the display region R01 and the area of ​​the peripheral region R02.

[0153] The display substrate according to the embodiment of the present disclosure maximizes the area occupied by the storage capacitor. The larger the area of ​​the pixel opening, the larger the area occupied by the storage capacitor. Correspondingly, the smaller the area of ​​the pixel opening, the smaller the area occupied by the storage capacitor. A display substrate that satisfies the above value ranges, i.e., the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133] and the value range of S2 / (W*L) is [2.82, 28.85], can increase the facing area of ​​the electrode plates of the storage capacitor, increase the capacitance, and improve the capacitance retention ability. It also increases the area ratio between the storage capacitor and the pixel opening, which is advantageous for improving the area occupied by the storage capacitor and improving display quality.

[0154] Of course, in other embodiments, the value range of S2 / (W*L) does not need to be limited, as long as the value range of (W*L+S2)*M1 / M2 is within [0.014, 0.133]. In this case, the facing area of ​​the storage capacitor's plates can be increased, the capacitance can be increased, and the capacitance retention ability can be improved. It is also advantageous to increase the area ratio between the storage capacitor and the pixel opening, improve the area occupancy rate of the storage capacitor, and improve display quality.

[0155] For example, the value range of (W*L+S2)*M1 / M2 may be [0.02, 0.1].

[0156] Furthermore, for example, the value range of (W*L+S2)*M1 / M2 may be [0.02, 0.05].

[0157] Furthermore, for example, the value range of (W*L+S2)*M1 / M2 may be [0.03, 0.05].

[0158] For example, the value range of S2 / (W*L) may be [5,28].

[0159] Furthermore, for example, the value range of S2 / (W*L) may be [6, 27.5].

[0160] Furthermore, for example, the value range of S2 / (W*L) may be [7, 27.5].

[0161] For example, in some embodiments, the display substrate may be a 27-inch product, W=1.5-4 micrometers, for example, W may be 2.5 micrometers, 2.6 micrometers, or 2.7 micrometers, L=10-20 micrometers, for example, L may be 13 micrometers, 14 micrometers, or 15 micrometers, M1 is the number of pixel apertures (4K multiplied by the resolution), i.e., 3840*2160=8294400, for example, M2 is in the range of 1900 square centimeters to 2100 square centimeters, for example, M2=59.8*33.6=2009.28 square centimeters, for example, S2=900-1200 square micrometers, for example, S2 may be 1020 square micrometers, 1030 square micrometers, or 1040 square micrometers.

[0162] For example, for a 27-inch product, W = 2.5 micrometers, L = 15 micrometers, M1 = 8,294,400 pieces, M2 = 2,009.28 square centimeters, S2 = 1,030 square micrometers, so the value of (W*L+S2)*M1 / M2 is 0.04 and the value of S2 / (W*L) is 27.4. When calculating, standardize the units, for example, convert square centimeters to square micrometers.

[0163] For example, in some embodiments, the display substrate may be a 65-inch product, W=1.5-4 micrometers, for example, W may be 2.5 micrometers, 2.6 micrometers, or 2.7 micrometers, L=20-30 micrometers, for example, L may be 23 micrometers, 24 micrometers, or 25 micrometers, M1 is the number of pixel apertures (8K multiplied by the resolution), i.e., 7680*4320=33177600, M2 is in the range of 11600-11700 square centimeters, for example, M2=143.9*80.94=11647.27 square centimeters, and S2=900-1200 square micrometers, for example, 1020 square micrometers, 1030 square micrometers, or 1040 square micrometers.

[0164] For example, for a 65-inch product, W = 2.7 micrometers, L = 25 micrometers, M1 = 7680 * 4320 = 33,177,600 pieces, M2 = 143.9 * 80.94 = 11,647.27 square centimeters, S2 = 1,200 square micrometers, the value of (W * L + S2) * M1 / ​​M2 is 0.036, and the value of S2 / (W * L) is 17.7.

[0165] For example, in some embodiments, the display substrate may be a 75-inch product, for example, W=1.5-4 micrometers, for example, W may be 2.5 micrometers, 2.6 micrometers or 2.7 micrometers, for example, L=35-45 micrometers, for example, L may be 39 micrometers, 40 micrometers or 41 micrometers, M1 is the number of pixel apertures (8K multiplied by resolution)=7680*4320=33177600, for example, M2 is in the range of 14400-14500 square centimeters, for example, M2=154.96*93.38=14470.16 square centimeters, and S2=900-1200 square micrometers, for example, S2 may be 1020 square micrometers, 1030 square micrometers or 1040 square micrometers.

[0166] For example, for a 75-inch product, W = 4 micrometers, L = 39 micrometers, M1 = 33,177,600 pieces, M2 = 154.96 * 93.38 = 14,470.16 square centimeters, S2 = 1,200 square micrometers, the value of (W * L + S2) * M1 / ​​M2 is 0.031, and the value of S2 / (W * L) is 7.69.

[0167] For example, referring to Figures 5, 6, 7D, 8A and 8D, and 9 to 11, the storage capacitor Cst further includes a third electrode Cc, where the third electrode Cc and the second electrode Cb are connected to each other, and the third electrode Cc and the second electrode Cb are respectively disposed on either side of the first electrode Ca. The second electrode Cb is disposed below the first electrode Ca, and the third electrode Cc is disposed above the first electrode Ca, which is advantageous for increasing the capacitance of the storage capacitor and improving display quality. Of course, the placement of the third electrode Cc may be determined by comprehensively considering the planarization design, capacitance, the position of the first electrode Ca, and the position of the second electrode Cb.

[0168] 12 is a layout diagram of a display substrate according to another embodiment of the present disclosure. Compared with the display substrate shown in FIG. 5, in the display substrate shown in FIG. 12, the connection electrode CEb is located on the active layer LY0 and is integral with the first electrode T5a of the light-emitting control transistor T5.

[0169] 13 is a layout diagram of a display substrate according to another embodiment of the present disclosure. Compared with the display substrate shown in FIG. 5, in the display substrate shown in FIG. 13, the second electrode T5b of the light-emitting control transistor T5 is directly connected to the second electrode T3b of the driving transistor T3.

[0170] Fig. 14 is a layout diagram of a display substrate according to another embodiment of the present disclosure. Fig. 15 is a stacking diagram of some of the film layers in Fig. 14. As shown in Figs. 14 and 15, the second electrode plate Cb includes a first plate-shaped portion Cba, and the first plate-shaped portion Cba and the channel of the driving transistor T3 are integral with each other.

[0171] 14 and 15, the second electrode plate Cb further includes a second plate-shaped portion Cbb, where the first plate-shaped portion Cba and the second plate-shaped portion Cbb are spaced apart, and the area of ​​the first plate-shaped portion Cba is larger than the area of ​​the second plate-shaped portion Cbb. As shown in FIGS. 14 and 15, the second plate-shaped portion Cbb and the first plate-shaped portion Cba are located in the same layer and are spaced apart. The first plate-shaped portion Cba, the second plate-shaped portion Cbb, and the channel of the driving transistor T3 are located in the same layer, and all are located in the active layer LY0.

[0172] As shown in FIGS. 14 and 15, the second plate-shaped portion Cbb is connected to the third electrode plate Cc by a via V22.

[0173] 15, the first plate-shaped portion Cba includes a first portion PR1 and a second portion PR2, the first portion PR1 extending along the first direction Y and the second portion PR2 extending along the second direction X, the first portion PR1 and the second plate-shaped portion Cbb being disposed opposite each other and being disposed on both sides of the channel T3c of the driving transistor T3 in the second direction X. For example, as shown in FIG. 15, the first portion PR1 and the second portion PR2 form a figure-7 shape. In FIG. 15, the first portion PR1 and the second portion PR2 are divided by a dashed line.

[0174] Figure 16 is a layout diagram of a display substrate according to another embodiment of the present disclosure. Figure 17 is a stacking diagram of some of the film layers in Figure 16. As shown in Figures 16 and 17, the driving transistor T3 uses a dual-gate structure. Figure 17 shows channels T3c1 and T3c2 of the driving transistor T3.

[0175] For example, the channel of the drive transistor T3 is a semiconductor material, and the material of the second plate Cb is a conductor made of the same semiconductor material as the channel of the drive transistor T3 that is doped.

[0176] 5, 9 to 14, and 16, the pixel aperture P0 has a central axis C0 extending along the first direction Y. The pixel aperture P0 is symmetrical with respect to the central axis C0.

[0177] 9 to 11, the pixel aperture P0 of the sub-pixel 100 includes a pixel aperture P01 of the first sub-pixel 101, a pixel aperture P02 of the second sub-pixel 102, and a pixel aperture P03 of the third sub-pixel 103.

[0178] 9 to 11, the central axis C0 includes the central axis C01 of the pixel aperture P0 (pixel aperture P01) of the first subpixel 101, the central axis C02 of the pixel aperture P0 (pixel aperture P02) of the second subpixel 102, and the central axis C03 of the pixel aperture P0 (pixel aperture P03) of the third subpixel 103.

[0179] 18 is a stacking diagram of a portion of a film layer of a display substrate according to one embodiment of the present disclosure. For example, as shown in FIG. 18, the channel of the driving transistor T3 extends along a first direction Y, the pixel opening P0 has a central axis C0 extending along the first direction Y, the maximum dimension of the pixel opening P0 along the second direction X (the width of the pixel opening P0) is W0, the first direction Y intersects with the second direction X, the distance from the channel T3c of the driving transistor T3 to the central axis C0 is D1, and the value range of 2*D1 / W0 is [0.2, 0.4] or [0.6, 0.8]. The larger the value of D1, the smaller the occupancy rate of the driving transistor T3 and the larger the area of ​​the storage capacitor. Having the ratio of 2*D1 / W0 within this range is advantageous for confining the position of the channel or gate of the driving transistor, thereby improving the retention capacity of the storage capacitor, and for increasing the area ratio between the storage capacitor and the pixel opening, thereby improving the area occupancy rate of the storage capacitor and display quality.

[0180] For example, for the blue subpixel, W0=50 micrometers, D1=15.3 micrometers, and the value of 2*D1 / W0 is 0.6.

[0181] For example, for the green subpixel, W0=28 micrometers, D1=3.25 micrometers, and the value of 2*D1 / W0 is 0.2.

[0182] For example, for the red subpixel, W0=28 micrometers, D1=2.55 micrometers, and the value of 2*D1 / W0 is 0.2.

[0183] The above are some examples, and the values ​​of W0 and D0 may be set as needed, as long as the value range of 2*D1 / W0 is [0.2, 0.4] or [0.6, 0.8]. For the blue subpixel, the value range of 2*D1 / W0 is [0.6, 0.8], and for the green and / or red subpixel, the value range of 2*D1 / W0 is [0.2, 0.4].

[0184] 19 is a stacking diagram of a portion of film layers of a display substrate according to an embodiment of the present disclosure. For example, as shown in FIG. 19, the display substrate further includes a plurality of signal lines SGL located on one side of the storage capacitor Cst, the signal lines SGL extending along the second direction X, the orthogonal projections of the signal lines SGL on the base substrate BS overlap with the orthogonal projections of the pixel opening P0 on the base substrate BS, the dimension of the pixel opening P0 along the first direction Y (the height of the pixel opening P0) is H0, the distance in the first direction Y between the furthest edges of the signal lines SGL is Hs, and the value range of L / (H0-Hs) is [0.59, 1.19]. The smaller the value of the length L of the channel T3c, the larger the area of ​​the storage capacitor. Having the value of L / (H0-Hs) within this range is advantageous for confining the position of the channel or gate of the driving transistor, thereby achieving a storage capacitor with a relatively large capacitance.

[0185] In some non-limiting examples, the value of L is about 10-30 μm, the value of H0 is about 50-75 μm, and the value of Hs is about 10-25 μm.

[0186] For example, L=30 μm, H0=75 μm, Hs=25 μm, and the value of L / (H0−Hs) is 0.6.

[0187] 19, the display substrate further includes a data line DT, a gate line G1, a gate line G2, and an initialization line INT1, the pixel circuit 100a further includes a data write transistor T1 and a reset transistor T2, a first pole of the data write transistor T1 is connected to the data line DT, a gate of the driving transistor T3 is connected to the second pole of the data write transistor T1, a gate of the data write transistor T1 is connected to the gate line G1, a first pole of the reset transistor T2 is connected to the initialization line INT1, a second pole of the reset transistor T2 is connected to the gate of the driving transistor T3, and a gate of the reset transistor T2 is connected to the gate line G2, and the plurality of signal lines SGL include the gate line G1, the gate line G2, and the initialization line INT1. Of course, in other embodiments, the plurality of signal lines SGL may include at least one of the gate line G1, the gate line G2, and the initialization line INT1, or may include other signal lines overlapping the pixel aperture P0.

[0188] For example, the area of ​​the pixel aperture P0 is S0, the sum of the opposing area of ​​the second electrode plate Cb and the first electrode plate Ca and the area of ​​the channel T3c of the driving transistor T3 is Ss, and the relationship between Ss and S0 satisfies Ss=A*S0+B, where A is in the range of [0.42, 0.82] and B is in the range of [-2700, -3100]. Using the above formula to realize the fitting of the design areas of the pixel aperture, storage capacitor, and driving transistor increases the area ratio of the storage capacitor to the pixel aperture, which is advantageous to improving the area occupancy rate of the storage capacitor and display quality.

[0189] For example, in some embodiments, Ss=179, S0=4524, and the units of area S0 and area Ss are both square micrometers, where A=0.686 and B=-2924.

[0190] For example, in some embodiments, Ss=2440, S0=7820, and the units of the area S0 and the area Ss are both square micrometers. In this case, A=0.686, and B=-2924.

[0191] For example, in some embodiments, Ss = 370, S0 = 4802, and the units of area S0 and area Ss are both square micrometers. In this case, A = 0.686, and B = -2924.

[0192] For example, in some embodiments, Ss=3219, S0=8955, and the units of area S0 and area Ss are both square micrometers. In this case, A=0.686, and B=-2924.

[0193] 20 is a stacking diagram of some film layers of a display substrate according to an embodiment of the present disclosure. For example, as shown in FIGS. 5, 9 to 11, and 20, the orthogonal projection of the pixel opening P0 on the base substrate BS overlaps with the orthogonal projection of the third electrode plate Cc on the base substrate BS.

[0194] For example, as shown in FIG. 20, the third electrode plate Cc includes a first edge portion CL1 extending along the first direction Y and a second edge portion CL2 extending along the first direction Y, and the pixel opening P0 includes a first edge portion KL1 extending along the first direction Y and a second edge portion KL2 extending along the first direction Y.

[0195] For example, as shown in FIG. 20, the first edge CL1 of the third plate Cc is closer to the first edge KL1 of the pixel opening P0 than the second edge CL2 of the third plate Cc, and the second edge CL2 of the third plate Cc is closer to the second edge KL2 of the pixel opening P0 than the first edge CL2 of the third plate Cc, and the subpixel 100 is △U=|U02-U01| is satisfied, U01 is the coordinate distance between the chromaticity coordinate point at the first view angle and the chromaticity coordinate point at the 0-degree view angle, U02 is the coordinate distance between the chromaticity coordinate point at the second view angle and the 0-degree view angle, △U is the absolute value of the difference between U02 and U01, the chromaticity coordinate point at the 0-degree view angle is the chromaticity coordinate point on the normal line located at the center of the display substrate, the first view angle and the second view angle are located on opposite sides of the normal line, the numerical values ​​of the included angles with the normal line are equal, and △U≦0.0020.

[0196] For example, as shown in FIG. 20, subpixel 100 has: △U=|U02-U01|≦k×|Xb-Xa| / KW, where k is a color cast coefficient, 0.009≦k≦0.03, ΔU<0.0020, Xa is the minimum distance in the second direction X between the first edge CL1 of the third electrode plate Cc and the first edge KL1 of the pixel opening P0, Xb is the minimum distance in the second direction X between the second edge CL2 of the third electrode plate Cc and the second edge KL2 of the pixel opening P0, and the first direction Y and the second direction X intersect, KW is the maximum dimension of the pixel opening P0 in the second direction X, and U U01 is the coordinate distance between the chromaticity coordinate point at the first view angle and the chromaticity coordinate point at the 0-degree view angle, U02 is the coordinate distance between the chromaticity coordinate point at the second view angle and the chromaticity coordinate point at the 0-degree view angle, △U is the absolute value of the difference between U02 and U01, the chromaticity coordinate point at the 0-degree view angle is the chromaticity coordinate point on the normal line at the center of the display substrate, the first view angle and the second view angle are located on opposite sides of the normal line, and the numerical values ​​of the included angles with the normal line are equal.

[0197] The dimension KW is the maximum dimension W0 of the pixel aperture P0 along the second direction X (the width of the pixel aperture P0).

[0198] For example, as shown in FIG. 20 , the third electrode plate Cc further includes a third edge portion CL3 extending along the second direction X and a fourth edge portion CL4 extending along the second direction X, and the pixel opening P0 includes a third edge portion KL3 extending along the second direction X and a fourth edge portion KL4 extending along the second direction X.

[0199] As shown in FIG. 20, the orthogonal projection of the third edge portion CL3 on the base substrate is located outside the orthogonal projection of the pixel aperture P0 on the base substrate.

[0200] As shown in FIG. 20, the orthogonal projection of the fourth edge portion CL4 on the base substrate is located within the orthogonal projection of the pixel aperture P0 on the base substrate.

[0201] 20, a first edge CL1 and a second edge CL2 are disposed opposite each other, and a third edge CL3 is connected to the first edge CL1 and the second edge CL2 by fillets. A third edge CL3 and a fourth edge CL4 are disposed opposite each other, and the fourth edge CL4 is connected to the first edge CL1 and the second edge CL2 by fillets. Of course, in other embodiments, adjacent edges of the opening do not have to be connected by fillets.

[0202] Fig. 21 is a schematic diagram of a center pixel of a display substrate according to an embodiment of the present disclosure. Fig. 22 is a cross-sectional view taken along line B1-B2 in Fig. 21. Fig. 23 is a schematic diagram of coordinate distances of chromaticity coordinate points at two different viewing angles of the display substrate.

[0203] The center-point pixel PXc is shown in Figure 21. For example, the center-point pixel PXc is the pixel PX located at the center of the display area R01.

[0204] For example, a non-contact spectrometer (e.g., PR630, 730, CS2000, 2000A) is used to randomly inspect the display substrate (panel) to be tested in a darkroom (illuminance of 1 lx or less) (by sampling 10 or more panels and selecting the worst data). The test point is the center pixel of the display substrate. The u' and v' coordinates of this point in the 1976 UV chromaticity coordinate system for the four colors RBGW are read. Measurements are made at nine viewing angles: 0 degrees, ±15 degrees, ±30 degrees, ±45 degrees, and ±60 degrees. The u' and v' values ​​at each angle are measured and obtained. Take the color cast at a viewing angle of -60 degrees as an example.

number

[0205] Substituting this into the formula, we obtain Δu′v′ for -60 degrees, and similarly calculate and obtain Δu′v′ for 60 degrees. By optimizing the structure of the display substrate, the difference between the two values ​​of the four colors (RGBW) can be made less than 0.0015, and the Δu′v′ value at each angle can be made less than 0.025. When the first subpixel 101 is a red subpixel, the second subpixel 102 is a green subpixel, and the third subpixel 103 is a blue subpixel and the color cast of white light is measured, the first subpixel 101, the second subpixel 102, and the third subpixel 103 at the center pixel PXc are all lit.

[0206] The uniform color space CIE1976 is converted from CIE1931XYZ.

[0207] The calculation formula for CIE1976Luv includes:

number

[0208] Note that the color cast measurement method is not limited to the above description, and the measuring device used is not limited to the listed ones. The same measuring device may be used to measure chromaticity coordinates at different angles of view, and the coordinate distance between the chromaticity coordinate point at each angle of view and the chromaticity coordinate point at a 0-degree angle of view may be obtained.

[0209] The embodiment of the present disclosure will be described as an example in which the color cast condition of the center pixel PXc is measured, but it goes without saying that the color cast conditions of each sub-pixel of other appropriate pixels may also be measured.

[0210] The coordinate distance between the chromaticity coordinate point P2 and the chromaticity coordinate point P1 is shown in Figure 23. As shown in Figure 23, x0 is the coordinate distance on the abscissa between the chromaticity coordinate point P2 and the chromaticity coordinate point P1, y0 is the coordinate distance on the ordinate between the chromaticity coordinate point P2 and the chromaticity coordinate point P1, and z0 is the coordinate distance between the chromaticity coordinate point P2 and the chromaticity coordinate point P1.

[0211] For example, the coordinate distance between chromaticity coordinate points at two angles of view refers to the square root of the sum of the square of the difference between the abscissas and the square of the difference between the ordinates of the two chromaticity coordinate points.

[0212] Fig. 22 shows a normal line L0 at the center of the display substrate, and the normal line L0 is parallel to the third direction Z. Fig. 22 also shows a first view angle VW1 and a second view angle VW2. The angle formed by the first view angle VW1 and the normal line L0 is +θ, and the angle formed by the second view angle VW2 and the normal line L0 is -θ. At a positive view angle θ, the view angle is obtained by rotating the normal line L0 clockwise by the angle θ, and at a negative view angle -θ, the view angle is obtained by rotating the normal line L0 counterclockwise by the angle θ.

[0213] Figures 21 and 22 are for measuring color cast in the horizontal angle of view, and when measuring color cast in the vertical angle of view, first angle of view VW1 and first angle of view VW2 are set on both sides of the normal line L0 in the first direction Y.

[0214] 24 is a layout diagram of a display substrate according to an embodiment of the present disclosure. Fig. 24 shows a first sub-pixel 101, a second sub-pixel 102, and a third sub-pixel 103. As shown in Fig. 24, the first sub-pixel 101, the second sub-pixel 102, and the third sub-pixel 103 are sequentially arranged along the second direction X.

[0215] As shown in Fig. 24, the initialization line INT1 includes an initialization signal line INT11 and an initialization connection line INT12, and the initialization signal line INT11 is connected to the initialization connection line INT12. As shown in Fig. 24, the initialization signal line INT11 and the initialization connection line INT12 are connected by a via Vj. As shown in Fig. 24, the initialization signal line INT11 extends along the second direction X, and the initialization connection line INT12 extends along the first direction Y.

[0216] As shown in FIG. 24, the initialization connection lines INT12 and the first power supply connection lines PL12 are alternately arranged in the second direction X at corresponding positions.

[0217] As shown in FIG. 24, the first portion INTa and the second portion INTb of the initialization connection line INT12 are connected by a via Vg, and the second portion INTb and the third portion INTc of the initialization connection line INT12 are connected by a via Vh.

[0218] 24, the initialization connection line INT12 passes through the first sub-pixel 101, and two adjacent first power supply connection lines PL1 pass through the second sub-pixel 102 and the third sub-pixel 103, respectively. That is, the initialization connection line INT12, one first power supply connection line PL12, and the other first power supply connection line PL12 are sequentially arranged along the second direction X. The initialization connection line INT12 extends along the first direction Y, and the first power supply connection line PL12 extends along the first direction Y.

[0219] 25 is a plan view of a display substrate according to an embodiment of the present disclosure. For example, the subpixel 100 shown in FIG. 25 is the third subpixel 103, which is a blue subpixel.

[0220] For example, as shown in Figures 5 and 25, the display substrate further includes a first power supply line PL1 configured to supply a first voltage signal to the pixel circuit 100a, and the first power supply line PL1 includes a first power supply connecting line PL12 extending along the first direction Y and a first power supply signal line PL11 extending along the second direction X, and the orthogonal projection of the first power supply connecting line PL12 on the base substrate BS overlaps with the orthogonal projection of the pixel opening P0 on the base substrate BS.

[0221] 5 and 25, the first power supply connecting line PL12 is formed by connecting multiple conductive parts located on two conductive pattern layers. The embodiments of the present disclosure include, but are not limited to, this. In other embodiments, the first power supply connecting line PL12 may be formed by a conductor located on the same layer, or by connecting multiple conductive parts located on three or more conductive pattern layers.

[0222] For example, referring to FIGS. 5 and 25, the area of ​​the third electrode Cc is Sc1, the overlap area between the orthogonal projection of the third electrode Cc on the base substrate BS and the orthogonal projection of the pixel opening P0 on the base substrate BS is Sc2, and Sc2 / Sc1≧0.9. The third electrode Cc can perform a planarizing function, flattening the bottom surface of the pixel opening P0 of the subpixel 100 and improving the flatness of the light-emitting layer, thereby improving display quality. For example, a subpixel satisfying Sc2 / Sc1≧0.9 may be a blue subpixel, thereby flattening the blue subpixel and improving the flatness of the light-emitting layer of the blue subpixel, thereby improving display quality. Furthermore, to better fulfill the planarizing function, for example, Sc2 / Sc1≧0.95.

[0223] 5 and 25, the width of the first power connecting line PL12 is W1, the overlap width between the first power connecting line PL12 and the pixel opening P0 is W2, and W2 / W1≧0.9, so that the first power connecting line PL12 can better planarize the pixel opening P0 of the subpixel 100, thereby improving the flatness of the light-emitting layer. Furthermore, for example, to better fulfill the planarization role, W2 / W1≧0.95.

[0224] In the embodiments of the present disclosure, the line width refers to the dimension in a direction perpendicular to the extension direction of the line.

[0225] For example, as shown in FIG. 25, the maximum dimension of the pixel aperture P0 along the second direction X is W0, and the value range of 2×W2 / W0 is [0.71, 0.99]. This enhances the planarizing role of the first power supply connecting line PL12 and improves the flatness of the light-emitting layer. Furthermore, the value range of the step voltage Uc (V) / dimension Lg (inches) is [0.32, 0.74], which is advantageous for improving current uniformity, where dimension Lg is the diagonal length of the display substrate. For example, the step voltage Uc is the pressure difference between the first electrode and the second electrode of the light-emitting element. For example, the step voltage Uc is the difference between the first voltage signal VDD and the second voltage signal VSS. Referring to FIG. 1, the largest rectangle represents the display substrate, and the diagonal of the rectangle is the diagonal of the display substrate, with the diagonal length measured in inches.

[0226] For example, in some embodiments, the first voltage signal VDD is 17V, the second voltage signal VSS is 2V, Uc=15V, Lg=27 inches, and the value of step voltage Uc (V) / dimension Lg (inches) is 0.55.

[0227] Furthermore, for example, the value range of 2×W2 / W0 is [0.80, 0.99], and the value range of step voltage Uc (V) / dimension Lg (inches) is [0.52, 0.74].

[0228] For example, as shown in FIG. 25, the pixel opening P0 has a central axis C0 extending along the first direction Y, the minimum distance from the first power supply connecting line PL12 to the central axis C0 is Xd1, the minimum distance from the third electrode plate Cc to the central axis C0 is Xd2, and the value range of Xd1 / Xd2 is [0.9, 1.1], thereby allowing the first power supply connecting line PL12 and the third electrode plate Cc to flatten the bottom surface of the pixel opening of the subpixel, which is advantageous in increasing the flatness of the light-emitting layer and improving display quality.

[0229] For example, in some embodiments, Xd1 = 1.57 micrometers, Xd2 = 1.73 micrometers, and Xd1 / Xd2 = 0.9. For example, in another embodiment, Xd1 = 1.73 micrometers, Xd2 = 1.57 micrometers, and Xd1 / Xd2 = 1.1. Xd1 and Xd2 are not limited to the above numerical values ​​and may be set as needed.

[0230] For example, as shown in FIG. 25, the display substrate further includes a plurality of signal lines 80 located on one side of the storage capacitor Cst (in FIG. 25, the storage capacitor Cst is represented by the third electrode plate Cc), the orthogonal projections of the plurality of signal lines 80 on the base substrate BS overlap with the orthogonal projections of the pixel opening P0 on the base substrate BS, the signal lines 80 extend along the second direction X, the distance between the third electrode plate Cc and the signal line closest to it is Xd3, the line width of the signal line is Xd4, and the value range of Xd3 / Xd4 is [0.9, 1.1], thereby enhancing the role of the signal lines 80 and the third electrode plate Cc in flattening the bottom surface of the pixel opening of the subpixel, thereby reducing color cast in the vertical direction and advantageously improving color cast consistency in the vertical direction.

[0231] For example, in some embodiments, Xd3 = 3 micrometers, Xd4 = 3 micrometers, and Xd3 / Xd4 = 1. Xd3 and Xd4 are not limited to the above values ​​and may be set as needed.

[0232] 26 is a plan view of a display substrate according to an embodiment of the present disclosure, showing two subpixels 100. The first subpixel 101 is a red subpixel, and the second subpixel 102 is a green subpixel.

[0233] For example, as shown in FIG. 26, the display substrate further includes a first power line PL1 configured to supply a first voltage signal to the pixel circuit 100a, and the first power line PL1 includes a first power connecting line PL12 extending along the first direction Y and a first power signal line PL11 extending along the second direction X, wherein the minimum distance from the first power connecting line PL12 to the central axis C0 is Xd1, the minimum distance from the first power connecting line PL12 to the third electrode plate Cc is Xd0, DP=|Xd1-Xd0| / 2, the maximum dimension of the pixel opening P0 along the second direction X (the width of the pixel opening P0) is W0, and the value range of DP / W0 is [0.01, 0.19], whereby the first power connecting line PL12 and the third electrode plate Cc play a role in planarizing the bottom surface of the pixel opening of the subpixel, which is advantageous for improving the planarity of the light-emitting layer. For example, the value range of DP / W0 for the red or green subpixels on the display substrate is [0.01, 0.19].

[0234] For example, in some embodiments, Xd1=22 micrometers, Xd0=8 micrometers, DP=7 micrometers, W0=52 micrometers, and DP / W0=0.13.

[0235] For example, in some embodiments, the display substrate further satisfies at least one of W2 / W1≧0.9, 2×W2 / W0 being in the range of [0.71, 0.99], step voltage Uc (V) / dimension Lg (inches) being in the range of [0.32, 0.74], Xd1 / Xd2 being in the range of [0.9, 1.1], Xd3 / Xd4 being in the range of [0.9, 1.1], and DP / W0 being in the range of [0.01, 0.19], thereby making the display substrate satisfy ΔU≦0.0020. In other words, the color cast of the display substrate is further reduced by designing at least one of the dimensions.

[0236] For example, as shown in FIG. 26 , the display substrate further includes a first signal line 801, the first signal line 801 extending along a first direction Y, the subpixel 100 including a first subpixel 101 and a second subpixel 102 adjacent to each other in a second direction X, the first signal line 801 configured to supply a data signal to the pixel circuit 100a of the first subpixel 101, the pixel aperture P0 of the first subpixel 101 and the pixel aperture P0 of the second subpixel 102 being spaced apart, and the first signal line 801 located between the pixel aperture P0 of the first subpixel 101 and the pixel aperture P0 of the second subpixel 102.

[0237] 26 , the minimum distances between the pixel opening P0 of the first subpixel 101 and the pixel opening P0 of the second subpixel 102 and the first signal line 801 are Xa1 and Xa2, respectively, and the value range of Xa1 / Xa2 is [0.8, 1.2]. The first signal line 801 extends along the first direction Y and is located between the pixel openings P0 of adjacent subpixels. A body material of the pixel confinement layer is provided directly above the first signal line 801. By limiting the ratio of the minimum distances between the first signal line 801 and adjacent pixel openings, the pressure drop is reduced, thereby reducing color cast.

[0238] For example, in some embodiments, Xa1 = 12 micrometers, Xa2 = 12 micrometers, and Xa1 / Xa2 = 1. Of course, Xa1 and Xa2 may vary up or down based on the above values, as long as the value range of Xa1 / Xa2 is [0.8, 1.2].

[0239] For example, as shown in FIG. 26 , the display substrate further includes a second signal line 802, which extends along the first direction Y, the first signal line 801 and the second signal line 802 are located on opposite sides of the same third electrode plate Cc, and the orthogonal projection of the second signal line 802 on the base substrate BS overlaps with the orthogonal projection of the pixel opening P0 of the second sub-pixel 102 on the base substrate BS.

[0240] For example, as shown in FIG. 26 , the distance between the third electrode plate Cc and the second signal line 802 is Xa3, the distance between the third electrode plate Cc and the first signal line 801 is Xa4, and the value range of Xa3 / Xa4 is [0.8, 1.2], thereby enhancing the role of the third electrode plate Cc and the second signal line 802 in flattening the bottom surface of the pixel opening of the second subpixel 102 and increasing the flatness of the light-emitting layer, thereby reducing color cast.

[0241] For example, in some embodiments, Xa3 = 8.6 micrometers, Xa4 = 10 micrometers, and Xa3 / Xa4 = 0.86. Of course, Xa3 and Xa4 may vary up or down based on the above values, as long as the value range of Xa3 / Xa4 is [0.8, 1.2].

[0242] For example, as shown in FIG. 26 , the display substrate further includes a third signal line 803, which extends along the first direction Y, and the orthogonal projection of the third signal line 803 on the base substrate BS overlaps with the orthogonal projection of the pixel opening P0 of the first subpixel 101 on the base substrate BS, the minimum distance between the third electrode plate Cc of the first subpixel 101 and the third signal line 803 is Xa5, the minimum distance between the third signal line 803 and the first signal line 801 is Xa6, and the value range of Xa5 / Xa6 is [0.8, 1.2], thereby enhancing the role of the third electrode plate Cc and the third signal line 803 in planarizing the bottom surface of the pixel opening of the first subpixel 101 and improving the planarity of the light-emitting layer, thereby reducing color cast.

[0243] For example, in some embodiments, Xa5 = 8.7 micrometers, Xa6 = 7.3 micrometers, and Xa5 / Xa6 = 1.2. Of course, Xa5 and Xa6 may vary up or down based on the above values, as long as the value range of Xa5 / Xa6 is [0.8, 1.2].

[0244] For example, as shown in Fig. 26, the first signal line 801 includes a data line DT, and at least one of the second signal line 802 and the third signal line 803 includes a first power supply connecting line PL12 or an initialization connecting line INT12. Fig. 26 illustrates an example in which the second signal line 802 and the third signal line 803 are both the first power supply connecting line PL12. In another embodiment, the second signal line 802 is the first power supply connecting line PL12, but the third signal line 803 is the initialization connecting line INT12. As shown in Fig. 26, the third signal line 803, the first signal line 801, and the second signal line 802 are sequentially arranged along the second direction X.

[0245] 27 and 28, the display substrate further includes a data line DT and a first power line PL1, where the data line DT is configured to supply a data voltage to the pixel circuit 100a, the data line DT extends along a first direction Y, the first power line PL1 is configured to supply a first voltage signal VDD to the pixel circuit 100a, the first power line PL1 includes a first power connecting line PL12 extending along the first direction Y and a first power signal line PL11 extending along the second direction X, the subpixel 100 includes a subpixel 121 and a subpixel 122 adjacent to each other in the second direction X, and the orthogonal projection of the first power connecting line PL12 on the base substrate overlaps with the orthogonal projection of the pixel opening P0 of the subpixel 121 on the base substrate and overlaps with the orthogonal projection of the pixel opening P0 of the subpixel 122 on the base substrate.

[0246] 27, two data lines DT are respectively installed on both sides of the first power connecting line PL12, and the orthogonal projections of the two data lines DT on the base substrate respectively overlap with the orthogonal projections on the base substrate of the pixel opening P0 of the subpixel 121 and the pixel opening P0 of the subpixel 122. Figure 27 shows data lines DT1 and DT2, which supply data voltages to the subpixels 121 and 122, respectively, and the orthogonal projections of the data lines DT1 and DT2 on the base substrate respectively overlap with the orthogonal projections on the base substrate of the pixel opening P01 of the subpixel 121 and the pixel opening P02 of the subpixel 122. As a result, by widening the first power supply connecting line PL12 and combining it with two data lines DT (data line DT1 and data line DT2), the sub-pixels 121 and 122 are flattened, the flatness of the light-emitting layer is improved, color cast is reduced, and the problem of pressure drop in medium and large-sized display substrates is solved, thereby improving brightness uniformity.

[0247] 27 illustrates an example in which the orthogonal projections of the two data lines DT on the base substrate overlap with the orthogonal projections of the pixel opening P0 of the subpixel 121 and the pixel opening P0 of the subpixel 122 on the base substrate, respectively, but the embodiments of the present disclosure are not limited to this. For example, by adjusting the circuit layout design, it is possible to prevent the orthogonal projections of the two data lines DT on the base substrate BS from overlapping with the orthogonal projections of the pixel opening P0 of the subpixel 121 on the base substrate BS and from overlapping with the orthogonal projections of the pixel opening P0 of the subpixel 122 on the base substrate BS. This allows the first power supply connecting line PL12 to be widened, and the combination of the first power supply connecting line PL12, the third electrode plate Cc of the subpixel 121, and the third electrode plate Cc of the subpixel 122 flattens the subpixels 121 and 122, thereby improving the flatness of the light-emitting layer and reducing color cast.

[0248] For example, as shown in FIG. 28, the display substrate further includes a first power supply line PL1 configured to supply a first voltage signal VDD to the pixel circuit 100a, the first power supply line PL1 including a first power supply connecting line PL12 extending along a first direction Y and a first power supply signal line PL11 extending along a second direction X, the orthogonal projection of the first power supply connecting line PL12 on the base substrate BS overlaps with the orthogonal projection of the pixel opening P0 on the base substrate BS, the maximum dimension of the pixel opening P0 of the sub-pixel 100 along the second direction X is W0, and the sub-pixel 100 has a width W1 in the second direction X. 28 shows a dimension W01 of the pixel opening P0 of the subpixel 131 along the second direction X and a dimension W02 of the pixel opening P0 of the subpixel 132 along the second direction X, and the dimension W0 of the subpixel 100 along the second direction X may be an average value of either or both of the dimensions W01 and W02. For example, one of the subpixels 131 and 132 may be a red subpixel, and the other of the subpixels 131 and 132 may be a green subpixel. In the embodiments of the present disclosure, a case where the subpixel 131 is a green subpixel and the subpixel 132 is a red subpixel will be described as an example.

[0249] For example, in some embodiments, Xb1 = 6 micrometers, Xb2 = 54 micrometers, W0 = 163 micrometers, and the value of (Xb1 + Xb2) / W0 is 0.37. The values ​​of Xb1, Xb2, and W0 are not limited to the above example, as long as the value range of (Xb1 + Xb2) / W0 is [0.08, 0.48].

[0250] For example, in some embodiments, the subpixels may include red, green, and blue subpixels, and the blue subpixels may be as shown in FIG. 25, while the red and green subpixels may be as shown in FIG. 26.

[0251] 29 is a layout diagram of a display substrate according to an embodiment of the present disclosure. Compared to the display substrate shown in FIG. 24, the initialization connecting line INT12 in the display substrate shown in FIG. 29 is located in the second sub-pixel 102, and two first power supply connecting lines PL1 are located in the first sub-pixel 101 and the third sub-pixel 103, respectively. That is, one first power supply connecting line PL12, the initialization connecting line INT12, and the other first power supply connecting line PL12 are sequentially arranged along the second direction X. Note that the arrangement of the initialization connecting line INT12 is not limited to that shown in the figure, as long as it can connect multiple initialization signal lines INT11 arranged in the first direction Y. Also, the arrangement of the first power supply connecting line PL12 is not limited to that shown in the figure, as long as it can connect multiple first power supply signal lines PL11 arranged in the first direction Y. The arrangement of the initialization connecting line INT12 and the first power supply connecting line PL12 may be set as needed.

[0252] 24 and 29, the first power supply connecting line PL12 and the initialization connecting line INT12 serve to planarize the subpixel, and the dimension of the first power supply connecting line PL12 in the second direction X is approximately half the dimension of the pixel opening P0 that overlaps it in the second direction X. To achieve a compatible design for the storage capacitor in the second subpixel 102 and provide installation space for the storage capacitor, the dimension of the initialization connecting line INT12 in the second direction X is made smaller than half the dimension of the pixel opening P0 that overlaps it in the second direction X.

[0253] FIG. 30 is a schematic diagram of a display substrate according to one embodiment of the present disclosure. For example, as shown in FIG. 30, the display substrate further includes a driving circuit CCT, where the driving circuit CCT is located on one side of the display substrate. The subpixel 100 (subpixel 151) farther from the driving circuit CCT has a first luminance L1, and the subpixel 100 (subpixel 152) closer to the driving circuit CCT has a second luminance L2. The value of |L1-L2| is in the range of [1, 9], where the unit of luminance is nits. The luminance difference between subpixels at different distances from the driving circuit CCT is reduced, e.g., to 9 nits or less, improving the current uniformity of the display substrate and thereby ensuring that the voltage drop meets design requirements. FIG. 30 shows two driving circuits CCT located on the same side of the display substrate. The distances between the subpixels 151 and 152 and the driving circuit CCT in the first direction Y are different, and the distance between the subpixels 151 and 152 in the second direction X is not limited. The driving circuit CCT may be a driving integrated circuit (IC).

[0254] 28 and 30, the display substrate satisfies the value range of (Xb1+Xb2) / W0 of [0.08, 0.48], thereby solving the problems of pressure drop and color cast, and also ensuring that the brightness difference is reduced, for example, by setting the value range of |L1-L2| to [1, 9]. That is, some display substrates satisfy the value range of (Xb1+Xb2) / W0 of [0.08, 0.48] and the value range of |L1-L2| of [1, 9].

[0255] FIG. 31 is a schematic diagram of a display substrate according to one embodiment of the present disclosure. For example, as shown in FIG. 31, the display substrate further includes two drive circuits CCT, where the two drive circuits CCT (drive circuit CCT1 and drive circuit CCT2) are located on opposite sides of the display region R01 of the display substrate. The subpixel 100 at the central axis of the display substrate has a third luminance L3, and the subpixel 100 adjacent to one of the two drive circuits CCT has a fourth luminance L4, where |L3-L4| is in the range of [1, 9], where the unit of luminance is nits. This reduces the luminance difference between subpixels at different distances from the drive circuit CCT, improves current uniformity of the display substrate, and ensures that the voltage drop meets design requirements. FIG. 31 also shows a central axis CR extending along the second direction X. As shown in FIG. 31, the extension direction of the central axis CR is the same as the extension direction of the drive circuits CCT. As shown in FIG. 31, the central axis CR is located between the two drive circuits CCT. The distances in the first direction Y between the sub-pixels 161 and 162 and one of the two driving circuits CCT are different, and the distances in the second direction X between the sub-pixels 161 and 162 and the driving circuit CCT are not limited.

[0256] 28 and 31, the display substrate satisfies the value range of (Xb1+Xb2) / W0 of [0.08, 0.48], thereby solving the problems of pressure drop and color cast, and also ensuring that the brightness difference is reduced, for example, by setting the value range of |L1-L2| to [1, 9]. That is, some display substrates satisfy the value range of (Xb1+Xb2) / W0 of [0.08, 0.48] and the value range of |L1-L2| of [1, 9].

[0257] In some embodiments, the display substrate satisfies the value range of |L1-L2| in [1, 9] and the value range of |L3-L4| in [1, 9].

[0258] FIG. 32 is a schematic diagram of a display substrate according to an embodiment of the present disclosure. For example, as shown in FIG. 32, the display substrate includes a power bus 501, a power bus 502, an initialization bus 503, and an initialization bus 504. For example, the power bus 501 is connected to a first power line PL1, the power bus 502 is connected to a second power line PL2, the initialization bus 503 is connected to an initialization line INT1, and the initialization bus 504 is connected to an initialization line INT2. A drive circuit is installed on the underside of the display substrate shown in FIG. 32. Note that the installation positions of the power bus 501, the power bus 502, the initialization bus 503, and the initialization bus 504 are not limited to those shown in the figure. FIGS. 30 to 32 show a display region R01.

[0259] 33A is a plan view of a pixel confining layer on a display substrate according to an embodiment of the present disclosure. Fig. 33B is a plan view of a pixel confining layer on a display substrate according to an embodiment of the present disclosure. For example, as shown in Figs. 33A and 33B , the pixel confining layer PDL includes a plurality of first confining portions 301 and a plurality of second confining portions 302, where the plurality of second confining portions 302 are arranged along the second direction X and extend along the first direction Y. The plurality of first confining portions 301 are arranged as a plurality of sets 0301, where the first confining portions 0301 of each set are located between two adjacent second confining portions 302, where the first confining portions 301 extend along the second direction X, and the first confining portions 301 of each set are arranged along the first direction Y.

[0260] 33A and 33B, a trench is formed between two adjacent second limiting portions 302, and each trench extends along a first direction Y. During inkjet printing, ink flows through the trench. For example, if the first direction Y is the column direction and the second direction X is the row direction, the display substrate has multiple columns of trenches. Each column of trenches defines multiple pixel openings P0.

[0261] 6, 33A, and 33B, the maximum height H1 from the first limiting portion 301 to the planarizing layer PLN is smaller than the maximum height H2 from the second limiting portion 302 to the planarizing layer PLN. That is, the thickness of the first limiting portion 301 is smaller than the thickness of the second limiting portion 302.

[0262] FIG. 34 is a schematic diagram of a display substrate according to one embodiment of the present disclosure. As shown in FIG. 34, the base substrate BS includes a display region R01 and a peripheral region R02 located on at least one side of the display region R01. As shown in FIG. 34, the orthogonal projection of the portion DT01 of the data line DT located in the display region R01 on the base substrate BS is located within the orthogonal projection of the second limiting portion 302 on the base substrate BS. The orthogonal projection of the data line DT on the base substrate BS overlaps with the orthogonal projection of the second limiting portion 302 of the pixel limiting layer PDL on the base substrate BS, thereby allowing the second limiting portion 302 to have a protrusion, which is advantageous for ink to flow to the pixel opening in the pixel limiting layer during inkjet printing. As shown in FIG. 34, the orthogonal projection of the display region R01 on the base substrate BS overlaps with the orthogonal projection of the pixel limiting layer PDL on the base substrate BS. The orthogonal projection of the pixel opening P0 of the pixel limiting layer PDL on the base substrate BS is located within the orthogonal projection of the display region R01 on the base substrate BS.

[0263] Only two data lines DT are shown in Fig. 34. For example, one second limiting portion 302 may correspond to one data line, but this is not limiting.

[0264] In the embodiments of the present disclosure, the pixel circuit is not limited to that shown in the given circuit diagram, and other appropriate pixel circuits may be used, and the layout diagram of the display substrate is also not limited to that shown in the given layout diagram, and may be adjusted based on the given layout diagram, or other layout methods may be used.

[0265] 34, a first limiting portion 301 is provided between two pixel openings P0 adjacent to each other in the first direction Y, and a second limiting portion 302 is provided between two pixel openings P0 adjacent to each other in the second direction X, so that the first direction Y and the second direction X intersect. As shown in Fig. 6, the thickness of the first limiting portion 301 is H1, and the thickness of the second limiting portion 302 is H2, where H1 ≠ H2. For example, H1 is smaller than H2.

[0266] Figure 35 is an electron microscope image of a display substrate according to one embodiment of the present disclosure. As shown in Figure 35, in the via VH, the gradient angle of the base angle θ1 is 65 to 75 degrees, and the gradient angle θ2 is between 45 to 55 degrees. The gradient angle θ2 is the gradient angle of the planarization layer PLN at the via VH when the reference plane (half the thickness of the planarization layer PLN) is the bottom surface. The base angle θ1 is the included angle between the planarization layer PLN at the bottom surface of the via VH and the structure below it.

[0267] For example, as shown in Figures 6 and 35, the display substrate further includes an insulating layer ISL, and the light-emitting element 100b includes a first electrode E1, a second electrode E2, and a light-emitting functional layer FL located between the first electrode E1 and the second electrode E2, and the first electrode E1 of the light-emitting element 100b is connected to the pixel circuit 100a by a via VH that penetrates the insulating layer ISL.

[0268] For example, as shown in Fig. 6, the display substrate further includes a package layer EPS configured to package the light emitting element 100b, and the package layer EPS includes a laminate of an inorganic package film and an organic package film. As shown in Fig. 6, the package layer EPS includes an inorganic package film EPS1, an organic package film EPS2, and an inorganic package film EPS3. Note that the stacking order of the organic package film and the inorganic package film is not limited to that shown in the figure, and the structure of the package layer EPS is not limited to that shown in the figure.

[0269] FIG. 36 is a schematic diagram of a display substrate according to an embodiment of the present disclosure. For example, as shown in FIG. 36, the display substrate further includes a barrier dam 701, and a package adhesive 702 for adhesive purposes is provided on the outer surface of the package layer EPS. FIG. 36 shows the package layer EPS at its boundary. As shown in FIGS. 6 and 36, the insulating layer ISL includes a planarization layer PLN, which includes a first planarization portion PLN1 and a second planarization portion PLN2. A groove GR is provided between the first planarization portion PLN1 and the second planarization portion PLN2. The barrier dam 701 is located on the outer periphery of the display region R01 of the display substrate, and the orthogonal projection of the barrier dam 701 on the base substrate BS covers the orthogonal projection of the groove GR on the base substrate BS, thereby reducing or preventing water vapor and oxygen from entering the display region R01 along the planarization layer PLN and affecting the light-emitting elements in the display region R01. Of course, in another embodiment, the orthogonal projection of the barrier dam 701 on the base substrate BS does not have to cover the orthogonal projection of the groove GR on the base substrate BS.

[0270] For example, the range of the minimum distance from the edge of the display region R01 to the edge of the peripheral region R02 is 1 to 5 mm, that is, the range of the frame dimensions is 1 to 5 mm.

[0271] For example, the grooves GR may be through-holes that penetrate the planarization layer PLN to better block water vapor and oxygen. As shown in FIG. 36, the portion of the planarization layer PLN located inside the grooves GR is the first flat portion PLN1, and the portion of the planarization layer PLN located outside the grooves GR is the second flat portion PLN2. FIG. 36 illustrates the first flat portion PLN1 at the boundary of the first flat portion PLN1, and the second flat portion PLN2 at the boundary of the second flat portion PLN2. While FIG. 36 illustrates an example in which one groove GR is provided, the number of grooves GR is not limited to one and may be set as needed. The number of grooves GR is determined by the narrowness of the frame. The narrower the frame, the fewer the number of grooves GR. Of course, in other embodiments, grooves GR may not be provided.

[0272] For example, as shown in FIGS. 3 to 5, the display substrate further includes a data line DT, a gate line G1, a gate line G2, and an initialization line INT1, and the pixel circuit 100a further includes a data write transistor T1 and a reset transistor T2, wherein a first pole of the data write transistor T1 is connected to the data line DT, a gate of the driving transistor T3 is connected to a second pole of the data write transistor T1, a gate of the data write transistor T1 is connected to the gate line G1, a first pole of the reset transistor T2 is connected to the initialization line INT1, a second pole of the reset transistor T2 is connected to the gate of the driving transistor T3, and a gate of the reset transistor T2 is connected to the gate line G2.

[0273] Fig. 37 is a schematic diagram of a display substrate according to an embodiment of the present disclosure, Fig. 38 is a schematic circuit diagram of a dummy sub-pixel on a display substrate according to an embodiment of the present disclosure, and Fig. 39 is a layout diagram of a dummy pixel circuit on a display substrate according to an embodiment of the present disclosure.

[0274] As shown in Figure 37, dummy sub-pixels 100d are provided near the edges of the display substrate. For clarity, not all dummy sub-pixels are shown in Figure 37, nor are all sub-pixels 100. As shown in Figure 37, the dummy sub-pixels 100d are located in the peripheral region R02, and the sub-pixels 100 are located in the display region R01. The dummy sub-pixels 100d do not emit light, and providing the dummy sub-pixels 100d can improve etching uniformity and display quality.

[0275] As shown in FIG. 38, the dummy sub-pixel 100d includes a dummy drive transistor dT3 and a dummy reset transistor dT2. The dummy reset transistor dT2 is connected to the gate of the dummy drive transistor dT3, and the dummy reset transistor dT2 is disconnected from the initialization line INT1, which is advantageous for reducing power consumption. The provision of the dummy sub-pixel 100d is advantageous for improving etching uniformity rather than for achieving a light-emitting function. As shown in FIG. 38, the dummy sub-pixel 100d includes a dummy pixel circuit 100da and a dummy light-emitting element 100db. As shown in FIG. 38, the configuration of the dummy pixel circuit 100da may refer to the configuration of the pixel circuit 100a, and the configuration of the dummy light-emitting element 100db may refer to the configuration of the light-emitting element 100b. However, there is a risk of an open circuit in the dummy pixel circuit 100da. The dummy pixel circuit 100da shown in FIG. 38 will be described as an example in which the first electrode E1 of the dummy light-emitting element 100db is not connected to node N2 (the first electrode T3a of the dummy drive transistor dT3), and the dummy reset transistor dT2 is not connected to the initialization line INT1. In other embodiments, other disconnection methods may be used to prevent the dummy sub-pixel 100d from emitting light. A thick cross in FIG. 38 indicates disconnection. For example, a via may not be installed to disconnect the dummy reset transistor dT2 of the dummy sub-pixel 100d from the initialization line INT1.

[0276] As shown in Figure 38, the dummy sub-pixel 100d further includes a dummy data write transistor dT1. Figures 38 and 39 also show a dummy data line dDT.

[0277] As shown in FIG. 38, the dummy sub-pixel 100d further includes a dummy storage capacitor dCst.

[0278] In the embodiment of the present disclosure, the components in the dummy sub-pixel 100d are assigned new reference numerals to the main components such as the transistor and the storage capacitor, and the reference numerals of the remaining components may refer to the reference numerals in the sub-pixel 100.

[0279] 40 is a schematic diagram of a display substrate according to an embodiment of the present disclosure. For example, as shown in FIG. 40, the display substrate further includes a dummy data line dDT, where the dummy data line dDT extends along the first direction Y, the dummy data line dDT and the data line DT are insulated from each other, and the dummy subpixel 100d includes at least two dummy subpixels 100d adjacent to each other in the second direction X, and the dummy data lines dDT of the at least two dummy subpixels 100d are connected to each other. As shown in FIG. 40, the dummy data line dDT is located in a peripheral region R02. As shown in FIG. 40, the peripheral region R02 surrounds the display region R01.

[0280] For example, the dummy data line dDT is configured to supply a constant voltage by being connected to a constant voltage terminal. For example, the constant voltage terminal includes a port for supplying a first voltage signal VDD, a port for supplying a second voltage signal VSS, or a port for supplying an initialization signal Vinit1. For example, the dummy data line dDT is connected to the first power line PL1, the second power line PL2, or the initialization line INT1. Connecting the dummy data line dDT to a constant voltage terminal reduces the resistance of the power line connected to the constant voltage terminal, which is advantageous for improving display quality.

[0281] For example, as shown in Fig. 40, the at least two dummy subpixels 100d include a first dummy subpixel 100d1, a second dummy subpixel 100d2, and a third dummy subpixel 100d3, and the three dummy data lines dDT of the first dummy subpixel 100d1, the second dummy subpixel 100d2, and the third dummy subpixel 100d3 are connected to each other. Fig. 40 shows the three dummy data lines dDT connected to each other.

[0282] For example, as shown in Figures 3 to 5, the display substrate further includes a first power line PL1, and the pixel circuit 100a further includes an emission control transistor T5, a first pole of the emission control transistor T5 is connected to the first power line PL1, and a second pole of the emission control transistor T5 is connected to the second pole of the driving transistor T3.

[0283] For example, as shown in Figures 38 and 39, the dummy sub-pixel 100d further includes a dummy light-emitting control transistor dT5, a first electrode of the dummy light-emitting control transistor dT5 is disconnected from the first power line PL1, and a second electrode of the dummy light-emitting control transistor dT5 is connected to or disconnected from the second electrode of the dummy driving transistor T3.

[0284] As shown in FIG. 39, a via is not provided within dotted box F1 (corresponding to via V7 in FIG. 5), thereby disconnecting the dummy reset transistor dT2 from the initialization line INT1. As shown in FIG. 39, a via is not provided within dotted box F2 (corresponding to via VH in FIG. 5), thereby disconnecting the dummy pixel circuit 100da from the dummy light-emitting element 100db. As shown in FIG. 39, a via is not provided within dotted box F3 (corresponding to via V11 in FIG. 5), thereby disconnecting the first pole of the dummy light-emitting control transistor dT5 from the first power line PL1. As shown in FIG. 39, a via is not provided within dotted box F4 (corresponding to via V13 in FIG. 5), thereby disconnecting the second pole of the dummy light-emitting control transistor dT5 from the second pole of the dummy drive transistor T3. Of course, vias must be provided at corresponding positions to connect the second pole of the dummy light-emitting control transistor dT5 to the second pole of the dummy drive transistor T3, and similarly for other positions.

[0285] 5, 6, 33A, and 33B, the display substrate further includes a pixel confining layer PDL, the pixel confining layer PDL including a confining portion 300, a pixel opening P0 being defined by the confining portion 300, the light-emitting element 100b including a first electrode E1 and a light-emitting functional layer FL, the pixel confining layer PDL being configured to expose at least a portion of the first electrode E1, and at least a portion of the film layer in the light-emitting functional layer FL covering the sidewall SW (shown in FIG. 6) of the confining portion 300. FIG. 6 illustrates an example in which all the light-emitting functional layers FL are located in the pixel opening P0. In another embodiment, the light-emitting functional layers FL may include a common layer, as shown in FIG.

[0286] For example, as shown in FIG. 6, the light-emitting element 100b further includes a second electrode E2, where the light-emitting functional layer FL is located between the first electrode E1 and the second electrode E2, and the second electrode E2 contacts the top wall of the limiting portion 300. Of course, as shown in FIG. 45, if the light-emitting functional layer FL includes a common layer, the second electrode E2 contacts the common layer in the light-emitting functional layer FL. For example, the second electrode E2 contacts the common layer in the light-emitting functional layer FL that is adjacent to the second electrode E2. The common layer in FIG. 45 is an electron injection layer EIL. As shown in FIGS. 6 and 45, the orthogonal projection of the second electrode E2 on the base substrate BS overlaps with the orthogonal projection of the top wall of the limiting portion 300 on the base substrate BS.

[0287] 6, the display substrate further includes an insulating layer ISL, the first electrode E1 of the light-emitting element 100b is connected to the pixel circuit 100a by a via VH penetrating the insulating layer ISL, and the orthogonal projection of the via VH on the base substrate BS overlaps with the orthogonal projection of the first limiting portion 301 on the base substrate BS. As shown in FIGS. 6, 33A, and 33B, the limiting portion 300 includes a first limiting portion 301 and a second limiting portion 302, and the thickness H1 of the first limiting portion 301 is smaller than the thickness H2 of the second limiting portion 302.

[0288] FIG. 41A is a schematic diagram of a display substrate according to one embodiment of the present disclosure. For example, as shown in FIG. 41A, the display substrate further includes a dummy pixel confining layer dPDL. The dummy pixel confining layer dPDL includes a plurality of dummy confining portions d300 (second dummy confining portions d302) arranged along the second direction X. The extension direction of the second dummy confining portions d302 is the same as the extension direction of the second confining portions 302. The distance W4 between two adjacent dummy confining portions d300 (second dummy confining portions d302) is greater than the distance W3 between two adjacent second confining portions 302. FIG. 41A also shows a plurality of first dummy confining portions d301 extending along the second direction X. As shown in FIG. 41, a plurality of first dummy confining portions d301 are provided between adjacent second dummy confining portions d302. FIG. 41A shows a display region R01 and a peripheral region R02. The spacing W4 is larger than the spacing W3, which is advantageous for wiring in the peripheral region R02. For example, the spacing W4 may be the maximum spacing, i.e., the maximum spacing W4 between two adjacent dummy limited portions d300 is larger than the maximum spacing W3 between two adjacent second limited portions 302. For example, the spacing W4 may be the minimum spacing, i.e., the minimum spacing W4 between two adjacent dummy limited portions d300 is larger than the minimum spacing W3 between two adjacent second limited portions 302. FIG. 41A illustrates an example in which three columns of dummy sub-pixels 100d are provided between two adjacent second dummy limited portions d302. However, this is not limiting, and one, two, or three or more columns of dummy sub-pixels 100d may be provided between two adjacent second dummy limited portions d302. That is, at least one column of dummy sub-pixels 100d is provided between two adjacent second dummy limited portions d302.

[0289] Note that Figure 41A shows an example in which a first dummy limiting portion d301 extending along the second direction X is provided in the peripheral region R02, but this is not limited to this, and in some embodiments, the first dummy limiting portion d301 may not be provided in the peripheral region R02, and in this case, the dummy pixel limiting layer dPDL includes only the second dummy limiting portion d302.

[0290] 41A, for example, the distance W4 between two adjacent dummy limited portions d300 is 2 to 20 times the distance W3 between two adjacent second limited portions 302. When multiple columns of dummy sub-pixels 100d are provided between the two adjacent second limited portions 302, the distance W4 may be a multiple of the distance W3.

[0291] 41A, the width W6 of the second dummy limited portion d302 in the second direction X is greater than the width W5 of the second limited portion 302 in the second direction X. For example, the widths W6 and W5 may refer to maximum widths. Of course, the widths W6 and W5 may also refer to minimum widths.

[0292] FIG. 41B is a schematic diagram of a display substrate according to another embodiment of the present disclosure. As shown in FIG. 41B, the width W6 is greater than the width W5, and the description of FIG. 41A may be referred to. FIG. 41B illustrates an example in which a column of dummy sub-pixels 100d is provided between two adjacent second dummy confining portions d302. The dummy pixel confining layer dPDL in FIG. 41B may include only the second dummy confining portion d302 without the first dummy confining portion d301.

[0293] Of course, in another embodiment, width W6 may be equal to width W5.

[0294] Fig. 42 is a schematic diagram of a display substrate according to an embodiment of the present disclosure. For example, as shown in Figs. 3 to 5 and 42, the display substrate further includes a reset transistor T4, an initialization line INT2, and an initialization bus 504. The initialization bus 504 is provided outside the display region R01 of the display substrate. A first electrode of the reset transistor T4 is connected to the initialization bus 504, a first electrode T4a of the reset transistor T4 is connected to the initialization bus 504 via the initialization line INT2, and a second electrode T4b of the reset transistor T4 is connected to the light-emitting element 100b via the drive transistor T3. The reset transistor T4 is connected to subpixels 100 in one row. For the subpixels 100 in the same row, the number of reset transistors T4 is set to be less than the number of subpixels 100 to reduce power consumption. Fig. 42 will be described using an example in which one subpixel in one row corresponds to one reset transistor T4.

[0295] As shown in Fig. 42, the second pole of the reset transistor T4 is connected to a reset signal transmission line INI. As shown in Fig. 42, the reset signal transmission line INI is connected to the subpixel 100. As shown in Fig. 5, the reset signal transmission line INI is connected to the first electrode E1 of the light-emitting element 100b by the drive transistor T3. With reference to Figs. 5 to 8E, the second pole T5b of the light-emitting control transistor T5 and the second pole T3b of the drive transistor T3 are connected by the reset signal transmission line INI.

[0296] As shown in Figure 42, the reset transistor T4 is located in the peripheral region R02. As shown in Figure 42, the initialization bus 504 is located in the peripheral region R02.

[0297] 43 is a schematic diagram of a display substrate according to an embodiment of the present disclosure. For example, as shown in FIGS. 5 and 43, the display substrate further includes an emission control transistor T5, a first power line PL1, and a first power bus 501, where the first power line PL1 is configured to supply a first voltage signal to the pixel circuit 100a, the first power line PL1 is connected to the first power bus 501, and the first power line PL1 includes a first power connection line PL12 extending along a first direction Y and a first power signal line PL11 extending along a second direction X, a first pole of the emission control transistor T5 is connected to the first power line PL1, and a second pole of the emission control transistor T5 is connected to the second pole of the driving transistor T3, and the number of the emission control transistors T5 of the sub-pixels 100 in one row may be equal to the number of the sub-pixels 100 in the row.

[0298] 44 is a circuit diagram of a display substrate according to one embodiment of the present disclosure. As shown in Fig. 44, the number of emission control transistors T5 in one row of sub-pixels 100 is less than the number of sub-pixels 100 in the row. For example, all three sub-pixels 100 in one pixel PX are connected to the same emission control transistor T5.

[0299] For example, all three sub-pixels 100 in each pixel PX are connected to the same emission control transistor T5, and different pixels PX are connected to different emission control transistors T5, in which case the number of emission control transistors T5 in one row of sub-pixels 100 is greater than the number of reset transistors T4.

[0300] 3 to 6 and 9 to 14, an embodiment of the present disclosure further provides a display substrate, comprising: a base substrate BS; and a plurality of sub-pixels 100 disposed on the base substrate BS, each sub-pixel 100 including a pixel circuit 100a and a light-emitting element 100b, the pixel circuit 100a including a driving transistor T3 and a storage capacitor Cst, the storage capacitor Cst including a first plate Ca and a second plate Cb, the first plate Ca of the storage capacitor Cst being connected to the gate of the driving transistor T3, and the second plate Cb of the storage capacitor Cst being connected to the first electrode of the driving transistor T3, the light-emitting element 100b being electrically connected to the pixel circuit 100a, the pixel circuit 100a being configured to drive the light-emitting element 100b, the sub-pixel 100 including a pixel aperture P0 configured to limit a light-emitting area of ​​the sub-pixel 100, and a normal projection of the storage capacitor Cst on the base substrate BS is formed on the pixel aperture P0. The orthogonal projection on the base substrate BS overlaps with the orthogonal projection on the base substrate BS of the channel of the driving transistor T3, and the orthogonal projection on the base substrate BS of the pixel opening P0 overlaps with the orthogonal projection on the base substrate BS. The second electrode plate Cb is disposed in the same layer as the channel of the driving transistor T3, and the second electrode plate Cb is closer to the base substrate BS than the first electrode plate Ca. The display substrate has a value range of (W*L+S2)*M1 / M2 in [0.014, 0.133], and P=k0*(W / L)*Uc. A certain relationship is satisfied, and the value range of k0 is [2.8*E-07, 5.8*E-06], W is the channel width of the driving transistor T3, L is the channel length of the driving transistor T3, S2 is the opposing area of ​​the second electrode plate Cb and the first electrode plate Ca, M1 is the number of pixel openings P0 on the display substrate, M2 is the area of ​​the display substrate, Uc is the step voltage of the light-emitting element 100b, and P is the power consumption of the sub-pixel 100.

[0301] The display substrate according to the embodiment of the present disclosure has a value range of (W*L+S2)*M1 / M2 in [0.014, 0.133] and satisfies the relationship P=k0*(W / L)*Uc, which is advantageous for obtaining a display substrate with lower power consumption.

[0302] 3 to 6, 9 to 14, 33A, 33B and 34, an embodiment of the present disclosure further provides a display substrate, comprising: a base substrate BS; and a plurality of sub-pixels 100 disposed on the base substrate BS, each sub-pixel 100 including a pixel circuit 100a and a light-emitting element 100b, the pixel circuit 100a including a driving transistor T3 and a storage capacitor Cst, the storage capacitor Cst including a first plate Ca and a second plate Cb, the first plate Ca of the storage capacitor Cst being connected to the gate of the driving transistor T3, and the second plate Cb of the storage capacitor Cst being connected to the first electrode of the driving transistor T3, the light-emitting element 100b being electrically connected to the pixel circuit 100a, and the pixel circuit 100a being configured to drive the light-emitting element 100b, the sub-pixel 100 including a pixel aperture P0 configured to limit a light-emitting area of ​​the sub-pixel 100, and a normal projection of the storage capacitor Cst on the base substrate BS on the base substrate BS of the pixel aperture P0 The orthogonal projection of the channel of the driving transistor T3 on the base substrate BS overlaps with the orthogonal projection of the pixel opening P0 on the base substrate BS, the second electrode plate Cb is disposed in the same layer as the channel of the driving transistor T3, the second electrode plate Cb is closer to the base substrate BS than the first electrode plate Ca, a first limiting portion 301 is disposed between two pixel openings P0 adjacent to each other in the first direction Y, and a second limiting portion 302 is disposed between two pixel openings P0 adjacent to each other in the second direction X, The display substrate intersects with the second direction X, the thickness of the first limiting portion 301 is H1, the thickness of the second limiting portion 302 is H2, and H1≠H2. The display substrate satisfies the relationship P=k0*(W / L)*Uc, where k0 has a value range of [2.8*E-07, 5.8*E-06], W is the channel width of the driving transistor T3, L is the channel length of the driving transistor T3, Uc is the step voltage of the light-emitting element 100b, and P is the power consumption of the sub-pixel 100.

[0303] 3 to 6, 9 to 14, 33A, 33B and 36, an embodiment of the present disclosure further provides a display substrate, including a base substrate BS and a plurality of sub-pixels 100 disposed on the base substrate BS, wherein the sub-pixels 100 include a pixel circuit 100a and a light-emitting element 100b, the pixel circuit 100a includes a driving transistor T3 and a storage capacitor Cst, the storage capacitor Cst includes a first plate Ca and a second plate Cb, the first plate Ca of the storage capacitor Cst is connected to the gate of the driving transistor T3, and the second plate Cb of the storage capacitor Cst is connected to the gate of the driving transistor T3. a first electrode of the drive transistor T3 connected to the first electrode of the drive transistor T4; a light-emitting element 100b electrically connected to the pixel circuit 100a; the pixel circuit 100a configured to drive the light-emitting element 100b; the sub-pixel 100 including a pixel aperture P0 configured to define a light-emitting area of ​​the sub-pixel 100; an orthogonal projection of the storage capacitor Cst on the base substrate BS overlaps with an orthogonal projection of the pixel aperture P0 on the base substrate BS; an orthogonal projection of the channel of the drive transistor T3 on the base substrate BS overlaps with an orthogonal projection of the pixel aperture P0 on the base substrate BS; the first electrode E1 of the light-emitting element 100b is connected to the pixel circuit 100a by a via VH penetrating the insulating layer ISL; the package layer EPS is configured to package the light-emitting element 100b; and the package layer EPS is configured to include an inorganic packaging film and an organic packaging film. The display substrate includes a laminate with a film, a package adhesive 702 is provided on the outside of the package layer EPS, the insulating layer ISL includes a planarization layer PLN, the planarization layer PLN includes a first planar portion PLN1 and a second planar portion PLN2, a groove GR is provided between the first planar portion PLN1 and the second planar portion PLN2, a barrier dam 701 is located on the outer periphery of the display region R01 of the display substrate, the orthogonal projection of the barrier dam 701 on the base substrate BS covers the orthogonal projection of the groove GR on the base substrate BS, and the display substrate satisfies the relationship P=k0*(W / L)*Uc, and the value range of k0 is [2.8*E-07,5.8*E-06], W is the channel width of the driving transistor T3, L is the channel length of the driving transistor T3, Uc is the step voltage of the light-emitting element 100b, and P is the power consumption of the subpixel 100.

[0304] The display substrate according to the embodiment of the present disclosure satisfies the relationship P=k0*(W / L)*Uc, which is advantageous for obtaining a display substrate with lower power consumption, and the orthogonal projection of the barrier dam 701 on the base substrate BS covers the orthogonal projection of the groove GR on the base substrate BS, thereby reducing or preventing water vapor and oxygen from entering the display area R01 along the planarization layer PLN and affecting the light-emitting elements in the display area R01.

[0305] 3 to 5 and 9 to 13, an embodiment of the present disclosure further provides a display substrate, comprising: a base substrate BS; and a plurality of sub-pixels 100 disposed on the base substrate BS, each sub-pixel 100 including a pixel circuit 100a and a light-emitting element 100b, the pixel circuit 100a including a driving transistor T3 and a storage capacitor Cst, the storage capacitor Cst including a first plate Ca and a second plate Cb, the first plate Ca of the storage capacitor Cst being connected to the gate of the driving transistor T3, and the second plate Cb of the storage capacitor Cst being connected to the first electrode of the driving transistor T3, the light-emitting element 100b being electrically connected to the pixel circuit 100a, and the pixel circuit 100a being configured to drive the light-emitting element 100b, and the sub-pixels 100 limit the light-emitting area of ​​the sub-pixels 100. the pixel aperture P0 is configured such that the orthogonal projection of the storage capacitor Cst on the base substrate BS overlaps with the orthogonal projection of the pixel aperture P0 on the base substrate BS, the orthogonal projection of the channel of the driving transistor T3 on the base substrate BS overlaps with the orthogonal projection of the pixel aperture P0 on the base substrate BS, the second electrode plate Cb is disposed on the same layer as the channel of the driving transistor T3, and the second electrode plate Cb is closer to the base substrate BS than the first electrode plate Ca, the display substrate satisfies the relationship P=k0*(W / L)*Uc, where k0 has a value range of [2.8*E-07, 5.8*E-06], W is the width of the channel of the driving transistor T3, L is the length of the channel of the driving transistor T3, Uc is the step voltage of the light-emitting element 100b, and P is the power consumption of the sub-pixel 100.

[0306] The display substrate according to the embodiment of the present disclosure satisfies the relationship P=k0*(W / L)*Uc, which is advantageous for obtaining a display substrate with lower power consumption; and the second electrode Cb is installed in the same layer as the channel of the driving transistor T3, which is advantageous for improving the capacitance retention ability, and for increasing the area ratio between the storage capacitor and the pixel opening, thereby improving the area occupancy rate of the storage capacitor and improving the display quality.

[0307] The embodiment of the present disclosure further provides a display substrate, which includes a base substrate BS and a plurality of sub-pixels 100 disposed on the base substrate BS. The sub-pixels 100 include a pixel circuit 100a and a light-emitting element 100b. The pixel circuit 100a includes a driving transistor T3 and a storage capacitor Cst. The storage capacitor Cst includes a first plate Ca and a second plate Cb. The first plate Ca of the storage capacitor Cst is connected to the gate of the driving transistor T3, and the second plate Cb of the storage capacitor Cst is connected to the first electrode of the driving transistor T3. The light-emitting element 100b includes a pixel circuit 100a. 00a, the pixel circuit 100a is configured to drive the light-emitting element 100b, the sub-pixel 100 includes a pixel aperture P0 configured to limit a light-emitting area of ​​the sub-pixel 100, an orthogonal projection of the storage capacitor Cst on the base substrate BS overlaps with an orthogonal projection of the pixel aperture P0 on the base substrate BS, an orthogonal projection of the channel of the driving transistor T3 on the base substrate BS overlaps with an orthogonal projection of the pixel aperture P0 on the base substrate BS, a second electrode plate Cb is disposed on the same layer as the channel of the driving transistor T3, and the second electrode plate Cb is disposed on a layer closer to the base substrate than the first electrode plate Ca. Adjacent to the BS, the display substrate further includes a data line DT, a gate line G1, a gate line G2 and an initialization line INT1, the pixel circuit 100a further includes a data write transistor T1 and a reset transistor T2, a first pole of the data write transistor T1 is connected to the data line DT, a gate of the driving transistor T3 is connected to a second pole of the data write transistor T1, a gate of the data write transistor T1 is connected to the gate line G1, a first pole of the reset transistor T2 is connected to the initialization line INT1, and a second pole of the reset transistor T2 is connected to the driving transistor T3. The gate of the reset transistor T2 is connected to the gate of the gate line G2, and a dummy sub-pixel 100d is provided near the edge of the display substrate, and the dummy sub-pixel 100d has a dummy drive transistor T3 and a dummy reset transistor dT2, and the dummy reset transistor dT2 is connected to the gate of the dummy drive transistor T3 and is disconnected from the initialization line INT1, and the display substrate satisfies the relationship P=k0*(W / L)*Uc, and the value range of k0 is [2.8*E-07,5.8*E-06], W is the channel width of the driving transistor T3, L is the channel length of the driving transistor T3, Uc is the step voltage of the light-emitting element 100b, and P is the power consumption of the subpixel 100.

[0308] The display substrate according to the embodiment of the present disclosure satisfies the relationship P=k0*(W / L)*Uc, which is advantageous for obtaining a display substrate with lower power consumption, and the dummy reset transistor dT2 is disconnected from the initialization line INT1, which is advantageous for reducing power consumption.

[0309] An embodiment of the present disclosure further provides a display substrate, comprising: a base substrate BS; and a plurality of sub-pixels 100 disposed on the base substrate BS, each sub-pixel 100 including a pixel circuit 100a and a light-emitting element 100b, the pixel circuit 100a including a driving transistor T3 and a storage capacitor Cst, the storage capacitor Cst including a first plate Ca and a second plate Cb, the first plate Ca of the storage capacitor Cst being connected to the gate of the driving transistor T3, and the second plate Cb of the storage capacitor Cst being connected to the first electrode of the driving transistor T3, the light-emitting element 100b being electrically connected to the pixel circuit 100a, and the pixel circuit 100a being configured to drive the light-emitting element 100b, the sub-pixel 100 including a pixel aperture P0 configured to define a light-emitting area of ​​the sub-pixel 100, an orthogonal projection of the storage capacitor Cst on the base substrate BS overlaps with an orthogonal projection of the pixel aperture P0 on the base substrate BS, and a base substrate of a channel of the driving transistor T3 The orthogonal projection on the plate BS overlaps with the orthogonal projection on the base substrate BS of the pixel opening P0, the second electrode plate Cb is disposed in the same layer as the channel of the driving transistor T3, and the second electrode plate Cb is closer to the base substrate BS than the first electrode plate Ca, the display substrate further includes a pixel confining layer PDL, the pixel confining layer PDL includes a confining portion 300, the pixel opening P0 is confined by the confining portion 300, the light-emitting element 100b includes a first electrode E1 and a light-emitting functional layer FL, and the pixel confining layer PDL is 1, the light-emitting functional layer FL covers the sidewall SW of the limiting portion 300 (shown in FIG. 6), and the display substrate satisfies the relationship P=k0*(W / L)*Uc, where k0 has a value range of [2.8*E-07, 5.8*E-06], W is the channel width of the driving transistor T3, L is the channel length of the driving transistor T3, Uc is the step voltage of the light-emitting element 100b, and P is the power consumption of the sub-pixel 100.

[0310] In the display substrate according to the embodiment of the present disclosure, the light-emitting functional layer FL covers the side wall SW of the limiting portion 300, and satisfies the relationship P=k0*(W / L)*Uc, which is advantageous in obtaining a display substrate with lower power consumption.

[0311] For example, in some embodiments, the first voltage signal VDD is 17V, the second voltage signal VSS is 2V, k=2.8*E-07, W=2 micrometers, L=30 micrometers, and U=15V, so that P=k*(W / L)*U=2.8*E-07 watts.

[0312] The power consumption P is the power consumption of a single subpixel. For subpixels emitting light of different colors, a differentiated design can be implemented to solve the power consumption matching problem of subpixels of different colors and reduce the power consumption of the entire panel. For example, for red, green, and blue subpixels, the power consumption of the red subpixel is smaller than that of the green subpixel, and the power consumption of the green subpixel is smaller than that of the blue subpixel, thereby solving the power consumption matching problem of the three colors and reducing the power consumption of the entire panel.

[0313] For example, in any one of the above display substrates satisfying P=k0*(W / L)*Uc, the display substrate may further satisfy the relationship that (W*L+S2)*M1 / M2 has a value range of [0.014, 0.133], where S2 is the opposing area of ​​the second electrode plate Cb and the first electrode plate Ca, M1 is the number of pixel openings P0 of the display substrate, and M2 is the area of ​​the display substrate, which is advantageous for forming a display substrate formed by an inkjet printing process with excellent performance.

[0314] For example, in an embodiment of the present disclosure, the display substrate may satisfy at least one of the following: (W*L+S2)*M1 / M2 has a value range of [0.014, 0.133]; S2 / (W*L) has a value range of [2.82, 28.85]; and P=k0*(W / L)*Uc. The meaning of each formula may refer to the above explanation, and detailed explanations will be omitted here.

[0315] In the embodiments of the present disclosure, in a mathematical formula, "*" indicates a multiplication symbol, " / " indicates a division symbol, the range [Mx, My] indicates a value greater than or equal to Mx and less than or equal to My, Mx and My are numbers, and numbers enclosed in [ ] with an E are numerical values ​​in scientific notation.

[0316] FIG. 45 is a schematic diagram of a display substrate according to an embodiment of the present disclosure. As shown in FIG. 45, the light-emitting functional layer FL includes a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, and an electron injection layer EIL. The materials of the hole injection layer HIL, the hole transport layer HTL, and the emission layer EML are located in the pixel opening defined by the pixel confinement layer PDL, and the electron injection layer EIL is a common layer. FIG. 45 also illustrates a display substrate having a light extraction layer CPL, which is advantageous for improving light extraction efficiency. For example, the hole injection layer HIL and the hole transport layer HTL may be gradient-doped or may be a single-layer stack. Of course, the structure of the display substrate according to the embodiment of the present disclosure is not limited to that shown in FIG. 45.

[0317] FIG. 46 is a schematic diagram of a luminance test of a display substrate according to one embodiment of the present disclosure. As shown in FIG. 46, the display substrate has a display area R01 and a peripheral area R02, and subpixels are located within the display area R01. Multiple test points are selected from the display area, and nine test points are selected in FIG. 46. The luminance of each test point is measured. FIG. 46 illustrates a case in which the subpixels can be divided into multiple subpixel groups PG, and FIG. 46 shows subpixel group PG1, subpixel group PG2, and subpixel group PG3. For example, in some embodiments, each subpixel group PG may correspond to one or more rows of subpixels. For example, in some embodiments, each subpixel group PG may correspond to one or more columns of subpixels.

[0318] As shown in Figure 46, the first to third test points are three test points at different positions in the sub-pixel group PG1, the fourth to sixth test points are three test points at different positions in the sub-pixel group PG2, and the seventh to ninth test points are three test points at different positions in the sub-pixel group PG3.

[0319] For example, the luminance of the subpixels in each subpixel group PG may be the average value of the luminance at the test point corresponding to that subpixel group PG. As shown in Fig. 46, the luminance of the subpixels in subpixel group PG1 is the average value of the luminance value at the first, second, and third test points, the luminance of the subpixels in subpixel group PG2 is the average value of the luminance value at the fourth, fifth, and sixth test points, and the luminance of the subpixels in subpixel group PG3 is the average value of the luminance value at the seventh, eighth, and ninth test points.

[0320] 46, for the same subpixel group, the test point located at the middle position may be located at the middle position of the test points close to the boundary of the display area. For example, the distance between the second test point and the first test point is equal to the distance between the second test point and the third test point. Correspondingly, the distance between the fifth test point and the fourth test point is equal to the distance between the fifth test point and the sixth test point, and the distance between the eighth test point and the seventh test point is equal to the distance between the eighth test point and the ninth test point.

[0321] For example, as shown in FIG. 46, when testing the brightness of the entire display substrate, the distance between the fourth test point and the first test point is equal to the distance between the fourth test point and the seventh test point, the distance between the fifth test point and the second test point is equal to the distance between the fifth test point and the eighth test point, and the distance between the sixth test point and the third test point is equal to the distance between the sixth test point and the ninth test point, but is not limited to these.

[0322] As shown in Figure 46, the following rule may be adopted when selecting a test point: Figure 46 shows the length Ly and width Lx of the display area R01. The distance Lx0 between the test point and the boundary of the display area R01 in the second direction X is equal to or greater than Lx / 10, and the distance Ly0 between the test point and the boundary of the display area R01 in the first direction Y is equal to or greater than Ly / 10.

[0323] 24 and 29, the data line DT includes a data line DT1, a data line DT2, and a data line DT3. The data line DT1 supplies a data signal to the first sub-pixel 101, the data line DT2 supplies a data signal to the second sub-pixel 102, and the data line DT3 supplies a data signal to the third sub-pixel 103.

[0324] 5, 24, and 29, the first power supply line PL1 and the initialization line INT1 of the pixel circuit 100a are formed by two conductive pattern layers. The first power supply line PL1 and the portion of the initialization line INT1 extending in the first direction Y are both formed in a stepwise manner. The first power supply line PL1 and the portion of the initialization line INT1 extending in the second direction X are both located on the second conductive pattern layer LY2.

[0325] As shown in FIGS. 5, 24 and 29, the signal connection lines 412 include at least one of a first power supply connection line PL12 and an initialization connection line INT12.

[0326] For example, as shown in Figures 24 and 29, the display substrate further includes a data line DT configured to supply a data voltage to the subpixel 100, and the orthogonal projection of at least one of the signal connection line 412 and the data line DT on the base substrate BS overlaps with the orthogonal projection of the pixel opening P0 of at least one of the plurality of subpixels 100 on the base substrate BS.

[0327] When inkjet printing is performed, the flatter the bottom surface of the pixel aperture P0 of the sub-pixel 100 (ie, the first electrode E1 of the light-emitting element) is, the more likely it is to reduce or avoid color cast, and the better the display effect of the display substrate will be.

[0328] The portion of the data line DT or the signal connection line 412 located on the second conductive pattern layer LY2 directly below the pixel opening P0 can play a role in planarization, thereby improving the display quality.

[0329] For example, the signal connection line 412 includes at least one of a portion of the first power supply line PL1 extending along the first direction Y and a portion of the initialization line extending along the first direction Y.

[0330] For example, as shown in FIGS. 5, 24, and 29, a signal connection line 412 and a signal transmission line 411 are connected by a via.

[0331] 5, 24, and 29, in order to flatten the bottom surface of the pixel aperture P0 of the subpixel 100, the display substrate further includes a signal transmission line 512 configured to supply a voltage signal to the subpixel 100, the signal transmission line 512 extending along the second direction X, and an orthogonal projection of the signal transmission line 512 on the base substrate BS overlaps with an orthogonal projection of the pixel aperture P0 of at least one subpixel of the plurality of subpixels 100 on the base substrate BS. This is advantageous for vertical leveling of ink during inkjet printing and reduces color cast in the vertical angle of view.

[0332] For example, referring to FIGS. 5, 24 and 29, the signal transmission line 512 includes at least one of the gate line G1, the gate line G2 and the portion of the initialization line INT11 extending along the second direction X.

[0333] In the embodiments of the present disclosure, at least one of the reset transistor T4 and the light-emitting control transistor T5 may not be installed in the pixel circuit 100a, and the structure of the pixel circuit 100a is not limited to that shown in the figure and may be installed as needed.

[0334] In the drawings of the embodiments of the present disclosure, an example is described in which the orthogonal projection of the pixel opening P0 of the subpixel on the base substrate does not overlap with the orthogonal projection of the via VH on the base substrate, but in other embodiments, the orthogonal projection of the pixel opening P0 of the subpixel on the base substrate and the orthogonal projection of the via VH on the base substrate may overlap.

[0335] For example, in the embodiments of the present disclosure, the design of the film layer of the rear panel, such as the design of the elements in the second conductive pattern layer, can accommodate pixel apertures of different sizes of sub-pixels, thereby improving the flatness of the light-emitting functional layer and further reducing color casts at the left and right viewing angles of the display substrate.

[0336] Since the luminous efficiency of sub-pixels emitting light of different colors is different, color cast can be reduced and display quality improved by adjusting the dimensions of the pixel aperture of the sub-pixel, adjusting the dimensions of the third electrode of the storage capacitor, and overlapping the aperture with the signal line.

[0337] For example, in the embodiments of the present disclosure, the thickness of an element refers to the dimension of the element in a direction perpendicular to the base substrate.

[0338] For example, in some embodiments, the dimension in the second direction X of the pixel aperture P0 of the first subpixel 101 is 28 to 36 micrometers, the dimension in the second direction X of the pixel aperture P0 of the second subpixel 102 is 30 to 38 micrometers, and the dimension in the second direction X of the pixel aperture P0 of the third subpixel 103 is 68 to 74 micrometers. Of course, the dimensions of the pixel aperture P0 of the subpixel 100 are not limited to these and may be set as needed.

[0339] 6, the insulating layer ISL includes a passivation layer PVX and a planarization layer PLN, the material of the passivation layer PVX includes an inorganic insulating material, and the material of the planarization layer PLN includes an organic insulating material. For example, the thickness of the planarization layer PLN is 3 to 7 micrometers.

[0340] The display substrate according to the embodiment of the present disclosure can reduce color cast at horizontal angles of view to less than 0.015. In addition, in the display substrate according to the embodiment of the present disclosure, by overlapping the pixel aperture of the subpixel with the signal connection line (by designing the position of the vertical wiring), the color cast problem of the second subpixel (green subpixel) is significantly improved, and the deviation at horizontal angles of view of 60 degrees is further reduced.

[0341] In typical inkjet-printed products, the thickness of the planarization layer PLN is thicker than that of vapor-deposited products. However, the display substrate according to the embodiment of the present disclosure can effectively reduce the thickness of the planarization layer by designing the rear panel. Furthermore, the width of the via VH can be reduced, thereby significantly improving color cast. For example, in the embodiment of the present disclosure, the thickness of the planarization layer is 3 to 7 micrometers.

[0342] For example, the insulating layer ISL shown in FIG. 6 may be composed of an inorganic material layer, an organic material layer, or both an organic material layer and an organic material layer. The vias in the insulating layer ISL may be formed not only once, but also multiple times and then trepanned to reduce the diameter of the vias, which is advantageous for planarizing the light-emitting functional layer and reducing color cast. For example, the ratio of the diameter of the via in the top layer to the width of the pixel opening of the subpixel is less than 0.3. The width of the pixel opening of the subpixel may refer to the maximum dimension of the pixel opening of the subpixel in the second direction X.

[0343] For example, gate line G1 may be referred to as the first gate line, gate line G2 may be referred to as the second gate line, gate line G4 may be referred to as the third gate line, reset transistor T2 may be referred to as the first reset transistor, and reset transistor T4 may be referred to as the second reset transistor.In this case, the display substrate further includes a data line, a first gate line, a second gate line, a third gate line, a first power supply line, a first initialization line, and a second initialization line, the data line is configured to supply a data voltage to the pixel circuit, the first gate line is configured to supply a scanning signal to the pixel circuit, the second gate line is configured to supply a first reset control signal to the pixel circuit, the third gate line is configured to supply a second reset control signal to the pixel circuit, the first power supply line is configured to supply a first voltage signal to the pixel circuit, the first initialization line is configured to supply the first initialization signal to the pixel circuit, and the second initialization line is configured to supply a second initialization signal to the pixel circuit, the pixel circuit further includes a data write transistor, a first reset transistor, and a second reset transistor, a first pole of the data write transistor is connected to the data line, a gate of the data write transistor is connected to the first gate line, a second pole of the data write transistor is connected to the gate of the driving transistor, a first pole of the first reset transistor is connected to the first initialization line, and a second electrode of the reset transistor connected to the gate of the drive transistor, a gate of the first reset transistor connected to the second gate line, a first electrode of the second reset transistor connected to the second initialization line, a second electrode of the second reset transistor connected to the first electrode of the light-emitting element, a gate of the second reset transistor connected to the third gate line, the first power supply line including a first power supply signal line extending along the second direction and a first power supply connecting line extending along the first direction, the first power supply signal line connected to the first power supply connecting line, The initialization line includes a first initialization signal line extending along the second direction and a first initialization connection line extending along the first direction, the first initialization signal line being connected to the first initialization connection line, the second initialization line includes a second initialization signal line extending along the second direction and a second initialization connection line extending along the first direction, the second initialization signal line being connected to the second initialization connection line, and an orthogonal projection on the base substrate of at least one of the first power supply connection line, the first initialization connection line and the second initialization connection line overlaps with an orthogonal projection on the base substrate of the pixel opening of the subpixel.

[0344] For example, the gate line G5 may be referred to as the fourth gate line, and the display substrate further includes a fourth gate line and a light-emitting control transistor, the fourth gate line is configured to supply a light-emitting control signal to the light-emitting control transistor, and the second electrode of the driving transistor is connected to the first power line by the light-emitting control transistor.

[0345] For example, the active layer of each transistor may include a source region, a drain region, and a channel located between the source region and the drain region, where the channel has semiconductor properties, the source region and the drain region are located on either side of the channel, and may be doped with impurities, so that they are conductive and can serve as a first pole and a second pole of the transistor, respectively, one of the first pole and the second pole of the transistor being a source electrode, and the other of the first pole and the second pole of the transistor being a drain electrode.

[0346] For example, the material of the semiconductor layer (semiconductor pattern) for manufacturing the active layer may include an oxide semiconductor, an organic semiconductor, amorphous silicon, polycrystalline silicon, etc. For example, the oxide semiconductor may include a metal oxide semiconductor (e.g., indium gallium zinc oxide (IGZO)), and the polycrystalline silicon may include low-temperature polycrystalline silicon or high-temperature polycrystalline silicon, etc., but the embodiments of the present disclosure are not limited thereto. In addition, the source region and drain region may be regions doped with n-type impurities or p-type impurities, but the embodiments of the present disclosure are not limited thereto.

[0347] For example, the base substrate BS, buffer layer BL, barrier layer BR, gate insulating layer GI, interlayer insulating layer ILD, planarization layer PLN, and pixel confining layer PDL are all made of insulating materials. For example, the base substrate BS may include, but is not limited to, a flexible material such as polyimide. At least one of the buffer layer BF, barrier layer BR, gate insulating layer GI, and interlayer insulating layer ILD is made of an inorganic insulating material or an organic insulating material. For example, inorganic insulating materials include, but are not limited to, silicon oxide, silicon nitride, and silicon oxynitride, while organic insulating materials include, but are not limited to, resin. For example, the pixel confining layer PDL and planarization layer PLN may be made of an organic material, for example, but is not limited to, resin.

[0348] For example, the first conductive pattern layer LY1 and the second conductive pattern layer LY2 are both made of metal materials, and the specific materials can be determined as needed. For example, the material of the first conductive pattern layer LY1 includes molybdenum (Mo). The material of the second conductive pattern layer LY2 includes titanium (Ti) and aluminum (Al), and may be, but is not limited to, a Ti / Al / Ti triple-layer structure.

[0349] For example, the material of the first electrode E1 of the light-emitting element includes a conductive material, such as, but not limited to, at least one of silver (Ag) or indium tin oxide (ITO). For example, the first electrode E1 of the light-emitting element has a three-layer stacked structure of ITO / Ag / ITO, but is not limited to this. In another embodiment, the material of the first electrode E1 of the light-emitting element includes aluminum (Al) and tungsten oxide (WOx), for example, the first electrode E1 includes a stacked layer of an aluminum layer and a tungsten oxide layer, and the aluminum layer is closer to the base substrate than the tungsten oxide layer.

[0350] For example, the material of the second electrode E2 of the light-emitting element includes a conductive material, such as, but not limited to, silver (Ag).

[0351] In the embodiments of the present disclosure, the patterns and vias of each single layer may be manufactured by a patterning process. For example, forming a specific pattern includes forming a film, forming a photoresist pattern on the film, and patterning the film using the photoresist pattern as a mask to form the specific pattern. The first conductive pattern layer LY1, the second conductive pattern layer LY2, the first electrode layer LY3, the third conductive pattern layer LY4, and vias in the insulating layer may all be formed by this method. For the active layer LY0, a semiconductor pattern may first be formed and doped by a doping process to form an active layer including a channel, a source region, and a drain region in the semiconductor pattern. An insulating layer may then be formed on the active layer, and a first conductive pattern layer LY1 may be formed on the insulating layer. Then, subsequent film layers may be sequentially formed.

[0352] Note that the layout of the subpixels of the display substrate according to the embodiments of the present disclosure is not limited to that shown in Figure 5, and other layout diagrams may be formed by converting based on Figure 5. Although the above description has been given of an example in which the subpixels have 4T1C pixel circuits, the embodiments of the present disclosure are not limited thereto. For example, each subpixel 101 may further include other numbers of transistors or other numbers of capacitors, and the pixel circuit operates under the control of data signals transmitted through data lines, gate scanning signals transmitted through gate lines, and emission control signals supplied by emission control signal lines, thereby driving the light-emitting elements to emit light and achieving operations such as display.

[0353] It should be noted that the embodiments of the present disclosure do not limit the number of thin film transistors and the number of capacitors included in a pixel circuit.

[0354] The display substrate according to the embodiments of the present disclosure may adopt other suitable layouts, and the wiring scheme is not limited to that shown in the drawings.

[0355] At least one embodiment of the present disclosure provides a display device including any one of the display substrates described above. The display device may be a large-scale display device, and at least one film layer in the light-emitting functional layer is manufactured by an inkjet printing process.

[0356] For example, the display device may be an organic light-emitting diode display device. The display device may be any product or component having a display function, such as a television, a digital camera, a mobile phone, a wristwatch, a tablet computer, a notebook computer, or a navigation device, which includes an organic light-emitting diode display device.

[0357] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto, and any modifications or replacements that can be easily thought of by those skilled in the art within the technical scope disclosed in the present disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims. [Explanation of symbols]

[0358] 100 subpixels 100a pixel circuit 100b Light-emitting element 101 First sub-pixel 102 second sub-pixel 103 3rd sub-pixel 300 limited edition 301 1st limited section 302 2nd limited edition 40, 400, 401 conductive structure 411 Signal Transmission Line 412 signal connection line 501, 502 Power Bus 503, 504 Initialization bus 512 Signal Transmission Line 701 Barrier Dam 702 Packaging adhesives 801 First signal line 802 Second signal line 803 Third signal line R01 Display area R02 Peripheral Area DT data line PL1 1st power line PL2 2nd power line E1 1st electrode E2 2nd electrode T1 Data write transistor T2, T4 Reset transistors T5 Light-emitting control transistor T3 drive transistor N1 node BS base board BR barrier layer BF buffer layer Ca 1st plate Cb 2nd plate Cba First plate Cbb Second plate-shaped part Cc 3rd plate CCT drive circuit CE connection electrode CL1 First edge CL2 2nd edge CL3 Third edge CL4 4th edge CPL light extraction layer Cst storage capacitor LY0 active layer LY1 First conductive pattern layer LY2 Second conductive pattern layer LY3 1st electrode layer G1, G2, G4, G5 gate lines GI gate insulating layer HIL hole injection layer HTL hole transport layer ILD Interlayer insulating layer INIT Initialization line ISL Insulation Layer PDL Pixel Limited Layer P0 pixel aperture FL Light-emitting functional layer

Claims

1. A display substrate, a base substrate; and a plurality of sub-pixels disposed on the base substrate; The sub-pixels are a pixel circuit including a drive transistor and a storage capacitor, the storage capacitor having a first plate and a second plate, the first plate of the storage capacitor connected to the gate of the drive transistor; a light-emitting element electrically connected to the pixel circuit, the pixel circuit configured to drive the light-emitting element; the sub-pixel includes a pixel aperture configured to define an emissive area of ​​the sub-pixel; an orthogonal projection of the storage capacitor on the base substrate overlaps with an orthogonal projection of the pixel opening on the base substrate, and an orthogonal projection of the channel of the drive transistor on the base substrate overlaps with an orthogonal projection of the pixel opening on the base substrate; The display substrate satisfies the relationship that the value range of (W*L+S2)*M1 / M2 is [0.014, 0.133] and the value range of S2 / (W*L) is [2.82, 28.85]; where W is the channel width of the driving transistor, L is the channel length of the driving transistor, S2 is the opposing area of ​​the second electrode plate and the first electrode plate, M1 is the number of pixel openings of the display substrate, and M2 is the area of ​​the display substrate.

2. 2. The display substrate of claim 1, wherein the second plate of the storage capacitor is connected to the first electrode of the driving transistor, the storage capacitor further includes a third plate, the third plate and the second plate are connected to each other, and the third plate and the second plate are respectively installed on both sides of the first plate.

3. 2. The display substrate of claim 1, wherein the channel of the driving transistor extends along a first direction, the pixel opening has a central axis extending along the first direction, the maximum dimension of the pixel opening along a second direction is W0, the first direction and the second direction intersect, a distance from the channel of the driving transistor to the central axis is D1, and a value range of 2*D1 / W0 is [0.2, 0.4] or [0.6, 0.8].

4. the pixel aperture has a dimension along the first direction of H0, a distance in the first direction between the furthest edges of the signal lines is Hs, and a value range of L / (H0-Hs) is [0.16, 0.61]; the display substrate further includes a data line, a first gate line, a second gate line, and a first initialization line, the pixel circuit further includes a data write transistor and a first reset transistor, a first pole of the data write transistor is connected to the data line, a gate of the driving transistor is connected to a second pole of the data write transistor, and a gate of the data write transistor is connected to the first gate line; a first pole of the first reset transistor is connected to the first initialization line, a second pole of the first reset transistor is connected to the gate of the drive transistor, and a gate of the first reset transistor is connected to the second gate line; The display substrate of claim 3 , wherein the plurality of signal lines include the first gate line, the second gate line, and the first initialization line.

5. 5. The display substrate according to claim 1, wherein the area of ​​the pixel opening is S0, the sum of the area of ​​the second electrode plate and the first electrode plate facing each other and the area of ​​the channel of the driving transistor is Ss, the relationship between Ss and S0 satisfies Ss = A * S0 + B, the value range of A is [0.42, 0.82], and the value range of B is [-2700, -3100].

6. an orthogonal projection of the pixel opening on the base substrate overlaps with an orthogonal projection of the third electrode plate on the base substrate; the third plate includes a first edge portion extending along a first direction and a second edge portion extending along the first direction, the pixel opening includes a first edge portion extending along the first direction and a second edge portion extending along the first direction, a first edge of the third plate being closer to a first edge of the pixel opening than a second edge of the third plate, and a second edge of the third plate being closer to a second edge of the pixel opening than the first edge of the third plate; The sub-pixels are the formula ΔU=|U02-U01| is satisfied, U01 is the coordinate distance between the chromaticity coordinate point at a first view angle and the chromaticity coordinate point at a view angle of 0 degrees, U02 is the coordinate distance between the chromaticity coordinate point at a second view angle and the chromaticity coordinate point at the view angle of 0 degrees, ΔU is the absolute value of the difference between U02 and U01, the chromaticity coordinate point at the view angle of 0 degrees is the chromaticity coordinate point on a normal line at which the center of the display substrate is located, the first view angle and the second view angle are located on opposite sides of the normal line, and the numerical values ​​of the included angles with the normal line are equal, 3. The display substrate according to claim 2, wherein ΔU≦0.0020.

7. a first power supply line configured to supply a first voltage signal to the pixel circuit, the first power supply line including a first power supply connecting line extending along a first direction and a first power supply signal line extending along a second direction, an orthogonal projection of the first power supply connecting line on the base substrate overlaps with an orthogonal projection of the pixel opening on the base substrate; a facing area between the third electrode plate and the first electrode plate is Sc1, an overlapping area between an orthogonal projection of the third electrode plate on the base substrate and an orthogonal projection of the pixel opening on the base substrate is Sc2, and Sc2 / Sc1≧0.9; 7. The display substrate according to claim 6, wherein the width of the first power supply connecting line is W1, the overlapping width between the first power supply connecting line and the pixel opening is W2, and W2 / W1≧0.

9.

8. a maximum dimension of the pixel aperture along the second direction is W0, and 2×W2 / W0 has a value range of [0.71, 0.99]; The display substrate of claim 6, wherein the value range of step voltage Uc / dimension Lg is [0.32, 0.74], the step voltage Uc is the step voltage of the light-emitting element, the unit of the step voltage Uc is volts, the dimension Lg is the diagonal length of the display substrate, and the unit of the dimension Lg is inches.

9. 7. The display substrate of claim 6, wherein the pixel opening has a central axis extending along the first direction, a minimum distance from the first power supply connection line to the central axis is Xd1, a minimum distance from the third electrode plate to the central axis is Xd2, and a value range of Xd1 / Xd2 is [0.9, 1.1].

10. 7. The display substrate of claim 6, further comprising a plurality of signal lines located on one side of the storage capacitor, wherein orthogonal projections of the plurality of signal lines on the base substrate overlap with orthogonal projections of the pixel openings on the base substrate, the plurality of signal lines are arranged along a first direction, the signal lines extend along a second direction, the first direction and the second direction intersect, a distance between the third plate and the signal line closest thereto is Xd3, a line width of the signal line is Xd4, and a value range of Xd3 / Xd4 is [0.9, 1.1].

11. 7. The display substrate of claim 6, further comprising a first power supply line, the first power supply line being configured to supply a first voltage signal to the pixel circuit, the first power supply line including a first power supply connecting line extending along a first direction and a first power supply signal line extending along a second direction, the pixel opening having a central axis extending along the first direction, a minimum distance from the first power supply connecting line to the central axis being Xd1, a minimum distance between the first power supply connecting line and the third electrode plate being Xd0, DP=|Xd1-Xd0| / 2, a maximum dimension of the pixel opening along the second direction being W0, and a value range of DP / W0 is [0.01, 0.19].

12. the pixel circuit of the first subpixel is configured to supply a data signal to the pixel circuit of the first subpixel; the pixel opening of the first subpixel and the pixel opening of the second subpixel are spaced apart from each other; and ... opening of the first subpixel and the pixel opening of the second subpixel are spaced apart from each other; and the pixel circuit of the first subpixel is configured to supply a data signal to the pixel circuit of the first subpixel and the pixel opening of the second subpixel.

7. The display substrate of claim 6, wherein the minimum distances between the pixel aperture of the first sub-pixel and the first signal line are Xa1 and Xa2, respectively, and Xa1 / Xa2 is in the range of [0.8, 1.2].

13. a second signal line extending along the first direction, the first signal line and the second signal line being located on opposite sides of the same third electrode plate, an orthogonal projection of the second signal line on the base substrate overlapping with an orthogonal projection of a pixel opening of the second sub-pixel on the base substrate; 13. The display substrate of claim 12, wherein the distance between the third electrode plate and the second signal line is Xa3, the distance between the third electrode plate and the first signal line is Xa4, and the value range of Xa3 / Xa4 is [0.8, 1.2].

14. a third signal line extending along the first direction; an orthogonal projection of the third signal line on the base substrate overlaps with an orthogonal projection of a pixel aperture of the first sub-pixel on the base substrate; 14. The display substrate of claim 13, wherein a minimum distance between the third electrode plate of the first subpixel and the third signal line is Xa5, a minimum distance from the third signal line to the first signal line is Xa6, and a value range of Xa5 / Xa6 is [0.8, 1.2].

15. The pixel circuit further includes a data line and a first power supply line, the data line being configured to supply a data voltage to the pixel circuit, the data line extending along a first direction; the first power supply line is configured to supply a first voltage signal to the pixel circuit, and the first power supply line includes a first power supply connection line extending along the first direction and a first power supply signal line extending along a second direction; The display substrate of any one of claims 1 to 4, wherein the subpixels include a first subpixel and a second subpixel adjacent to each other in the second direction, and the orthogonal projection of the first power supply connection line on the base substrate overlaps with the orthogonal projection of the pixel opening of the first subpixel on the base substrate and also overlaps with the orthogonal projection of the pixel opening of the second subpixel on the base substrate.

16. a first power supply line configured to supply a first voltage signal to the pixel circuit, the first power supply line including a first power supply connecting line extending along a first direction and a first power supply signal line extending along a second direction, an orthogonal projection of the first power supply connecting line on the base substrate overlaps with an orthogonal projection of the pixel opening on the base substrate; the maximum dimension of the pixel aperture along the second direction is W0; the sub-pixels include a first sub-pixel and a second sub-pixel adjacent to each other in the second direction, one of the two first power supply connection lines has a dimension Xb1 in the second direction, and the other of the two first power supply connection lines has a dimension Xb2 in the second direction; 5. The display substrate according to claim 1, wherein the value range of (Xb1+Xb2) / W0 is [0.08, 0.48].

17. 5. The display substrate according to claim 1, further comprising a drive circuit, the drive circuit being located on one side of the display substrate, a sub-pixel farther from the drive circuit having a first luminance L1, a sub-pixel closer to the drive circuit having a second luminance L2, and a value range of |L1-L2| being [1, 9].

18. 5. The display substrate according to claim 1, further comprising two drive circuits, the two drive circuits being located on opposite sides of a display area of ​​the display substrate, a subpixel at a central axis of the display substrate having a third luminance L3, a subpixel adjacent to one of the two drive circuits having a fourth luminance L4, the extension direction of the central axis of the display substrate being the same as the extension direction of the drive circuits, and a value range of |L3-L4| being [1, 9].

19. a first limiting portion is provided between two pixel openings adjacent to each other in a first direction, a second limiting portion is provided between two pixel openings adjacent to each other in a second direction, and the first direction and the second direction intersect with each other; 5. The display substrate of claim 1, wherein the thickness of the first limiting portion is H1, the thickness of the second limiting portion is H2, and H1≠H2.

20. the pixel circuit further includes a data line, a first gate line, a second gate line, and a first initialization line, the pixel circuit further includes a data write transistor and a first reset transistor, a first pole of the data write transistor is connected to the data line, a gate of the drive transistor is connected to a second pole of the data write transistor, and a gate of the data write transistor is connected to the first gate line; a first pole of the first reset transistor is connected to the first initialization line, a second pole of the first reset transistor is connected to the gate of the drive transistor, and a gate of the first reset transistor is connected to the second gate line; a dummy sub-pixel is provided near an edge of the display substrate, the dummy sub-pixel has a dummy drive transistor and a first dummy reset transistor, and the first dummy reset transistor is connected to a gate of the dummy drive transistor; 5. The display substrate according to claim 1, wherein the first dummy reset transistor is disconnected from the first initialization line.

21. The semiconductor memory device further includes a dummy data line, the dummy data line extends along a first direction, and the dummy data line and the data line are insulated from each other; the dummy sub-pixels include at least two dummy sub-pixels adjacent to each other in the second direction; the dummy data lines of the at least two dummy sub-pixels are connected to each other; the at least two dummy subpixels include a first dummy subpixel, a second dummy subpixel, and a third dummy subpixel; The display substrate of claim 20 , wherein three dummy data lines of the first dummy sub-pixel, the second dummy sub-pixel, and the third dummy sub-pixel are connected to each other.

22. a pixel limiting layer, the pixel limiting layer including a limiting portion, the pixel opening being limited by the limiting portion, the light-emitting element including a first electrode and a light-emitting functional layer, and the pixel limiting layer being configured to expose at least a portion of the first electrode; 5. The display substrate according to claim 1, wherein the light-emitting functional layer covers a side wall of the limiting portion.

23. 23. The display substrate of claim 22, wherein the light emitting element further comprises a second electrode, the light emitting functional layer being located between the first electrode and the second electrode, and the second electrode being in contact with a top wall of the limiting portion.

24. The light-emitting element further includes an insulating layer, wherein a first electrode of the light-emitting element is connected to the pixel circuit by a via penetrating the insulating layer, the limiting portion includes a first limiting portion and a second limiting portion, the thickness of the first limiting portion is smaller than the thickness of the second limiting portion, and an orthogonal projection of the via on the base substrate overlaps with an orthogonal projection of the first limiting portion on the base substrate; 23. The display substrate of claim 22, further comprising a dummy pixel limiting layer, the dummy pixel limiting layer including a plurality of dummy limiting portions, an extension direction of the dummy limiting portions being the same as an extension direction of the second limiting portions, and a distance between two adjacent dummy limiting portions being greater than a distance between two adjacent second limiting portions.

25. The display device further includes a second reset transistor, a second initialization line, and an initialization bus, the initialization bus being provided outside the display area of ​​the display substrate; a first electrode of the second reset transistor connected to the initialization bus by the second initialization line, and a second electrode of the second reset transistor connected to the light-emitting element by the drive transistor; 5. The display substrate according to claim 1, wherein the second reset transistors are connected to sub-pixels in one row, and the number of the second reset transistors for the sub-pixels in the same row is smaller than the number of the sub-pixels.

26. A display device comprising the display substrate according to any one of claims 1 to 4.

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