Metastability-free clockless single flux quantum logic circuits

Abstract

The device comprises a logic circuit having a clockless single flux quantum logic gate including a plurality of input ports, an output port, an output Josephson junction, and a plurality of dynamic storage loop circuits and an isolation buffer circuit. The output Josephson junction is coupled to the output of each dynamic storage loop circuit and configured to drive the output port. Each isolation buffer circuit is coupled to its respective input port and to its respective dynamic storage loop circuit and configured to absorb circulating current of injected antifluxons in its respective dynamic storage loop circuit to prevent antifluxons from being output from its respective input port, and to inject fluxons into its respective dynamic storage loop circuit to quench antifluxons present in its respective dynamic storage loop circuit in response to a single flux quantum pulse applied to its respective input port. (Figure 2)

Description

[Background technology]

[0001] STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT This invention was made with government support under the Intelligence Advanced Research Projects Activity (IARPA) under 2019-19051000001. The government has certain rights in this invention.

[0002] The present disclosure relates generally to superconducting logic circuits and systems, and more particularly to superconducting clockless single flux quantum (SFQ) logic circuits, such as superconducting clockless dynamic single flux quantum (DSFQ) logic circuits. Generally, superconducting logic circuits include, for example, superconducting passive elements (e.g., superconducting inductors, superconducting transmission lines, etc.), Josephson junctions (configured to operate as ultrafast Josephson junction switches), and logic gates designed based on magnetic flux quantization. For superconducting computing, superconducting electronic circuits are configured to operate at cryogenic temperatures (e.g., below 10 Kelvin).

[0003] Superconducting logic circuits can be implemented using different types of SFQ logic architectures that utilize SFQ pulses (also referred to as magnetic single flux quantum pulses) to encode, process, and transmit data. SFQ pulses are voltage pulses whose time integral equals a discrete amount of magnetic flux, i.e., a single magnetic flux quantum, referred to herein as a "fluxon." For superconducting applications, SFQ logic has been utilized as an alternative to conventional complementary metal-oxide-semiconductor (CMOS) circuits for high-performance computing (HPC) applications due to the higher operating speeds and lower power consumption achieved through the use of superconducting SFQ circuits compared to conventional room-temperature CMOS circuits. Furthermore, superconducting SFQ circuits can be readily fabricated using state-of-the-art thin-film very-large-scale integration ("VLSI") lithography fabrication techniques.

[0004] Current state-of-the-art SFQ logic architectures include direct current (DC)-driven SFQ logic families, such as rapid single flux quantum (RSFQ) logic and energy-efficient rapid single flux quantum (ERSFQ) logic, which essentially operate as state machines, where SFQ logic gates have internal logic states that require a clock signal to restore the internal logic state to a ground state after each clock cycle. The use of clock signals in SFQ logic networks, particularly the use of the register-transfer level (RTL) design paradigm, which is the foundation of VLSI digital design methodologies, creates significant challenges for VLSI SFQ digital design. The RTL VLSI design paradigm is based on partitioning large-scale digital circuits into clock-free, state-free logic networks of significant depth, called combinational logic clouds, where system clocking is achieved using clocked registers at the boundaries of the combinational logic clouds to hold all system states.

[0005] On the other hand, more recent state-of-the-art SFQ logic architectures include, for example, DC-driven clockless DSFQ logic circuits that include logic gates (without clocking) configured with self-resetting circuits that operate asynchronously and enable self-resetting of the logic gate's internal state to its ground state without the use of a clock signal. In this regard, DSFQ is highly compatible with RTL VLSI design methodologies that are based on the use of deep clouds of conventional combinational (clockless) logic separated by clocked register boundaries, as discussed above.

[0006] One problem associated with SFQ logic circuits, whether clocked or clockless, is that in some SFQ logic gates, there is a small but finite probability that a given logic gate may enter a metastable state due to, for example, two input SFQ pulses being applied to the input ports of the SFQ logic gate with a certain skew (e.g., a small skew of a few SFQ pulse widths or less). The metastable state of a given SFQ logic gate produced in a given clock cycle of a VLSI network of logic gates controlled with clocked register boundaries can result in the generation of erroneous data in the next clock cycle of the VLSI logic network, resulting in an error. Summary of the Invention

[0007] Exemplary embodiments of the present disclosure include superconducting clockless SFQ logic gates that are configured to prevent the possibility of entering a metastable state, for example, a metastable state caused by a relatively small skew between input SFQ pulses.

[0008] For example, an exemplary embodiment includes a device including a logic circuit having a clockless single flux quantum logic gate. The clockless single flux quantum logic gate has a plurality of input ports, an output port, a plurality of dynamic storage loop circuits, an output Josephson junction, and a plurality of isolation buffer circuits. The output Josephson junction is coupled to the output of each of the dynamic storage loop circuits and configured to drive the output port. Each isolation buffer circuit is coupled to a respective input port and a respective dynamic storage loop circuit. Each isolation buffer circuit is configured to absorb circulating current of antifluxons injected into a respective dynamic storage loop circuit as a result of the output Josephson junction switching to generate a single flux quantum output pulse on the output port, so as to prevent antifluxons from being output from a respective input port. Each isolation buffer circuit is configured to inject fluxons into a respective dynamic storage loop circuit and quench antifluxons present in a respective dynamic storage loop circuit in response to a single flux quantum pulse applied to a respective input port.

[0009] Advantageously, using antifluxons present in a given dynamic storage loop circuit to quench fluxons subsequently injected into the given dynamic storage loop circuit prevents the clockless SFQ logic gate from entering a metastable state as a result of a skewed pair of input SFQ pulses (e.g., a first (early) input SFQ pulse and a second (late) input SFQ pulse) being applied to different input ports of the clockless SFQ logic gate in the same clock cycle, where the skewed input SFQ pulses are separated by a delay of a few SFQ pulse widths or less. Furthermore, the isolation buffer circuit is configured to prevent counter-propagating antifluxons in the dynamic storage loop circuit from being output from the input port of the clockless SFQ logic gate, while allowing fluxons generated by late input SFQ pulses to be injected into the dynamic storage loop circuit and quenched by antifluxons that may be present in the dynamic storage loop circuit.

[0010] In an exemplary embodiment, the clockless single flux quantum logic gate comprises a clockless logic OR gate including at least two input ports. In another exemplary embodiment, the clockless single flux quantum logic gate comprises a clockless logic majority gate including at least three input ports.

[0011] In another exemplary embodiment, which may be combined with the preceding paragraph, the isolation buffer circuits have the same circuit architecture, and each of the isolation buffer circuits includes a multi-stage Josephson transmission line buffer circuit.

[0012] In another exemplary embodiment, as may be combined with the preceding paragraph, each multi-stage Josephson transmission line buffer circuit includes an output stage coupled to an input of a respective dynamic storage loop circuit, the output stage including a Josephson junction biased at a level that enables the Josephson junction of the output stage to absorb a counterpropagating antifluxon current flowing from the input of the respective dynamic storage loop circuit without switching as a result of a combination of the counterpropagating antifluxon current and a quiescent bias current biasing the Josephson junction of the output stage. In an exemplary embodiment, the Josephson junction of the output stage is biased at a level where the magnitude of the quiescent bias current is in a range from about 20 percent to about 40 percent of the critical current of the Josephson junction of the output stage.

[0013] Another exemplary embodiment includes a device comprising a logic circuit having a clockless single flux quantum logic gate comprising: a first input port, a second input port, an output port, a first dynamic storage loop circuit, a second dynamic storage loop circuit, an output Josephson junction coupled to an output of the first dynamic storage loop circuit and an output of the second dynamic storage loop circuit and configured to drive the output port, a first multi-stage Josephson transmission line buffer circuit coupled between the first input port and the first dynamic storage loop circuit, and a second multi-stage Josephson transmission line buffer circuit coupled between the second input port and the second dynamic storage loop circuit. The first multi-stage Josephson transmission line buffer circuit includes an output stage including a Josephson junction configured to absorb circulating current of antifluxons injected into the first dynamic storage loop circuit as a result of the output Josephson junction switching to generate a single flux quantum output pulse on the output port to prevent antifluxons from being output from the first input port, and configured to switch in response to a single flux quantum pulse applied to the first input port to inject fluxons into the first dynamic storage loop circuit and annihilate antifluxons present in the first dynamic storage loop circuit. The second multi-stage Josephson transmission line buffer circuit has an output stage including a Josephson junction configured to absorb circulating current of antifluxons injected into the second dynamic storage loop circuit as a result of the output Josephson junction switching to generate a single flux quantum output pulse on the output port to prevent antifluxons from being output from the second input port, and configured to switch in response to a single flux quantum pulse applied to the second input port to inject fluxons into the second dynamic storage loop circuit and annihilate antifluxons present in the second dynamic storage loop circuit.

[0014] In another exemplary embodiment, which may be combined with the preceding paragraph, a dynamic storage loop circuit has the same circuit architecture. The dynamic storage loop circuit includes a series combination of a superconducting inductor and a dynamic switch circuit coupled to an input port and an output port, respectively. The dynamic switch circuit includes a parallel combination of a first Josephson junction and a series combination of a second Josephson junction and a resistor. The dynamic switch circuit is configured to enable dynamic self-recovery of an internal state of the dynamic storage loop circuit based on a first time constant for temporarily storing fluxons or antifluxons and a second time constant for discharging the stored flux.

[0015] Another exemplary embodiment includes a method comprising: receiving a first single flux quantum pulse on a first input port of a clockless single flux quantum logic gate at a given clock cycle; injecting fluxons into a first dynamic storage loop circuit of the clockless single flux quantum logic gate in response to the first single flux quantum pulse; outputting a single flux quantum pulse on an output port of the clockless single flux quantum logic gate in response to the fluxons being injected into the first dynamic storage loop circuit; injecting antifluxons into a second dynamic storage loop circuit of the clockless single flux quantum logic gate in response to outputting the single flux quantum pulse on the output port; and utilizing an isolation buffer circuit coupled to an input of the second dynamic storage loop circuit to absorb circulating current of the antifluxons in the second dynamic storage loop circuit and prevent the antifluxons from being output from the second input port of the clockless single flux quantum logic gate.

[0016] In another exemplary embodiment, the method includes receiving a second single flux quantum pulse on the second input port of the clockless single flux quantum logic gate at the given clock cycle; and Utilizing the antifluxons in the second dynamic storage loop circuit to annihilate fluxons injected into the second dynamic storage loop circuit in response to the second single flux quantum pulse, so that the fluxons injected into the second dynamic storage loop circuit do not propagate to the output port.

[0017] Other embodiments are described in the following detailed description of illustrative embodiments, which is to be read in connection with the accompanying drawings. [Brief explanation of the drawings]

[0018] [Figure 1] 1 illustrates a schematic diagram of an exemplary embodiment of a confluence buffer circuit commonly utilized to implement SFQ logic gates, which may cause the SFQ logic gates to enter a metastable state.

[0019] [Figure 2] 1 illustrates a schematic diagram of a clockless SFQ logic OR gate according to an exemplary embodiment of the present disclosure.

[0020] [Figure 3A] 10 illustrates a schematic diagram of a clockless SFQ logic OR gate according to another exemplary embodiment of the present disclosure. [Figure 3B] 10 illustrates a schematic diagram of a clockless SFQ logic OR gate according to another exemplary embodiment of the present disclosure.

[0021] [Figure 4A] 10A and 10B illustrate schematically the modes of operation of a clockless SFQ logic OR gate according to an exemplary embodiment of the present disclosure. [Figure 4B] 10A and 10B illustrate schematically the modes of operation of a clockless SFQ logic OR gate according to an exemplary embodiment of the present disclosure. [Figure 4C] 10A and 10B illustrate schematically the modes of operation of a clockless SFQ logic OR gate according to an exemplary embodiment of the present disclosure.

[0022] [Figure 5] 1 illustrates a schematic diagram of a combinational logic circuit comprising clockless SFQ logic gates, according to an exemplary embodiment of the present disclosure.

[0023] [Figure 6] 10 illustrates a schematic diagram of a clockless SFQ logic gate according to another exemplary embodiment of the present disclosure.

[0024] [Figure 7] 1 illustrates a schematic diagram of a superconducting computing system implementing a combinational logic circuit having clockless SFQ logic gates, according to an exemplary embodiment of the present disclosure.

[0025] [Figure 8] 1 illustrates a schematic diagram of an exemplary architecture of a computing environment for hosting superconducting computing, according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0026] Exemplary embodiments of the present disclosure will now be described in further detail with respect to superconducting clockless (asynchronous) SFQ logic circuits comprising SFQ logic gates, such as SFQ logic OR gates, configured to prevent the possibility of entering a metastable state. It should be understood that the various features illustrated in the accompanying drawings are schematic diagrams and not drawn to scale. Also, the same or similar reference numerals are used throughout the drawings to indicate the same or similar features, elements, or structures, and thus, a detailed description of the same or similar features, elements, or structures will not be repeated in each of the drawings. Furthermore, as used herein, the term "exemplary" means "serving as an example, instance, or illustration." Any embodiment or design described herein as "exemplary" is not to be construed as preferred or advantageous over other embodiments or designs.

[0027] Furthermore, the phrase "configured to" when used in conjunction with a circuit, structure, element, component, etc. that performs or otherwise provides one or more functions is intended to encompass embodiments in which the circuit, structure, element, component, etc. is implemented in hardware, software, and / or combinations thereof, and in embodiments that include hardware, where it is understood that hardware may include superconducting circuit elements (e.g., Josephson junctions), discrete circuit elements (e.g., transistors, inverters, etc.), programmable elements (e.g., application specific integrated circuit (ASIC) chips, field programmable gate array (FPGA) chips, etc.), processing devices (e.g., central processing units (CPUs), graphics processing units (GPUs), etc.), one or more integrated circuits, and / or combinations thereof. Thus, by way of example only, when a circuit, structure, element, component, etc. is specified as being configured to provide a specific function, it is intended to encompass, without limitation, embodiments that enable the circuit, structure, element, component, etc., comprised of an element, processing device, and / or integrated circuit, to perform the specific function when in an operational state (e.g., connected or otherwise deployed in a system, powered on, receiving input, and / or generating output), as well as embodiments when the circuit, structure, element, component, etc., is in a non-operational state (e.g., not connected or otherwise deployed in a system, not powered on, not receiving input, and / or not generating output) or in a partially operational state.

[0028] As mentioned above, for superconducting computing applications (e.g., exascale computing or quantum computing), state-of-the-art superconducting integrated circuit (IC) fabrication techniques can be readily utilized to produce VLSI-level superconducting digital circuits, particularly SFQ logic circuits, that utilize SFQ pulses to encode, process, and transmit data. Superconducting SFQ logic circuits are particularly useful for HPC applications due to the high operating (GHz) speeds and low switching energy (less than femtojoules (fJ)) offered by SFQ logic circuits when operating at cryogenic temperatures (e.g., 4K). In particular, because clockless SFQ logic is based on the use of deep clouds of clockless combinational logic separated by clocked register boundaries, clockless SFQ logic circuits (e.g., DSFQ logic circuits) are highly desirable due to their compatibility with CMOS VLSI RTL design methodologies.

[0029] In VLSI logic circuits, a large number of clockless SFQ logic gates can be utilized to implement combinational logic clouds, where data is fed into a given combinational logic cloud (in a given clock cycle) using a set of clocked registers at the inputs of the given combinational logic cloud controlled by a system clock, and the output data produced by the given combinational logic cloud is captured by a set of clocked registers at the output of the given combinational logic cloud (in the next clock cycle). The captured data is then released to the next combinational logic cloud in the next clock cycle. In this configuration, the system clock controls the clock cycles for inputting data into a given combinational logic cloud and capturing the output data produced from a given combinational logic cloud.

[0030] With respect to timing closure, all operations occurring in a given combinational logic cloud in a given clock cycle must be completed and settled before the next clock cycle, when the output data of the given combinational logic cloud is captured by the clocked register at the output of the given combinational logic cloud. However, if a given logic gate in a given combinational logic cloud enters a metastable state in a given clock cycle, the given logic gate may not have settled to the desired stable state until the next clock cycle. In this regard, erroneous data generated in a given clock cycle as a result of the metastable state, or generated in the next clock cycle after the metastable state has settled to a stable state, can cause unspecified and inconsistent behavior of the logic circuit, which can result in errors.

[0031] As mentioned above, one problem associated with SFQ logic circuits, whether clocked or clockless, is that in some SFQ logic gates, there is a small but finite probability that a given logic gate may enter a metastable state. Generally, metastability occurs in any logic circuit that experiences different sequences of switching events for different input skews, and if the input skew of a logic gate is located exactly on the boundary between two modes of operation, it can cause an extremely long delay in the logic gate returning to its ground state. For example, some SFQ logic gate circuits, particularly those associated with logic functions, utilize a confluence buffer circuit that can cause the SFQ logic gate to enter a metastable state due to, for example, two input SFQ pulses being applied to the input ports of the SFQ logic gate with a certain skew (e.g., a small skew of about one SFQ pulse width, typically a few picoseconds).

[0032] 1 illustrates a schematic diagram of an exemplary embodiment of a confluence buffer circuit 100 commonly utilized to implement SFQ logic gates, which may cause the SFQ logic gates to enter a metastable state. The confluence buffer circuit 100 includes first and second input ports (designated Port A and Port B, respectively), an output port (designated Port Z), a first input node N1 coupled to Port A, a second input node N2 coupled to Port B, a node N3 coupled to Port Z, a bridge of four Josephson junctions 101, 102, 103, and 104, and a bias current I coupled to node N3. B The device includes a DC bias circuit 110 configured to apply a

[0033] Josephson junctions 101 and 103 are connected in series between output node N3 and a negative supply voltage node (designated VSS). Josephson junctions 102 and 104 are connected in series between output node N3 and a negative supply voltage node VSS. In some embodiments, to provide symmetrical input ports, Josephson junctions 101 and 102 are configured to have the same critical current, and Josephson junctions 103 and 104 are configured to have the same critical current, where the critical current of Josephson junctions 103 and 104 (e.g., 100 microamperes) is lower than the critical current of Josephson junctions 101 and 102 (e.g., 130 microamperes). DC bias circuit 110 provides a quiescent DC bias current I B to provide a quiescent bias current to bias Josephson junctions 101, 102, 103, and 104 of confluence buffer circuit 100. Josephson junctions 101, 102, 103, and 104 are biased with a quiescent DC current that is lower than the critical current of the Josephson junctions. While DC bias circuit 110 is shown generically in FIG. 1 , DC bias circuit 110 may be implemented using an RSFQ or ERSFQ bias circuit that includes a limiter Josephson junction connected in series with a large superconducting inductor, as known in the art.

[0034] The confluence buffer circuit 100 operates as follows: Assume that a first SFQ pulse is input to port A. The first input SFQ pulse is applied to node N1, which causes a current to flow through Josephson junction 101 and exceed its critical current, thus switching Josephson junction 101. In this case, Josephson junction 103 does not switch (remains in a superconducting state), and then, after a delay of about one pulse width, e.g., a few picoseconds, Josephson junction 104 switches, generating an output SFQ pulse at node N3 and outputting it from port Z. The switching of Josephson junction 104 prevents the output SFQ pulse from reaching input port B.

[0035] Assume further that a second SFQ pulse is input to port B with a time delay of several pulse widths (following the first input SFQ pulse applied to port A). The second input SFQ pulse is applied to node N2, causing a current to flow through Josephson junction 102 and exceed its critical current, thus switching Josephson junction 102. In this case, Josephson junction 104 does not switch (remains in a superconducting state), and then, after a delay of about one SFQ pulse width, e.g., a few picoseconds, Josephson junction 103 switches, generating an output SFQ pulse at node N3 and outputting it from port Z. The switching of Josephson junction 103 prevents the output SFQ pulse from reaching input port A. In this situation, a pair of sufficiently skewed (mutually delayed) input SFQ pulses for ports A and B generates two output SFQ pulses on output port Z.

[0036] On the other hand, if the skew (time delay) between the first and second input SFQ pulses applied to the respective ports A and B is small (e.g., less than one pulse width), the confluence buffer circuit 100 operates differently. In particular, when the first and second input SFQ pulses are applied to the respective input ports, i.e., ports A and B, with such a small time delay, Josephson junctions 101 and 102 and output port Z switch once, while Josephson junctions 103 and 104 do not switch. In this regard, the existence of these two distinct modes—(i) two output pulses resulting from two sufficiently skewed input pulses, and (ii) one output pulse resulting from two insufficiently skewed input pulses—leads to a metastable state on the boundary between these two distinct modes of operation that arises for very common input skews of a few picoseconds (approximately 1 SFQ pulse width) when a second pulse is emitted at port Z with a logarithmic divergence delay, and thus may be misplaced in the next system clock cycle, causing a digital error.

[0037] As mentioned above, while confluence buffer circuits such as those shown in FIG. 1 are commonly used to implement certain types of SFQ logic gates, such as two-input SFQ logic OR gates, confluence buffer circuit 100 is generally unsuitable for VLSI logic designs because first and second input SFQ pulses with a skew approaching one pulse width (a very common scenario) applied to the first and second input ports of the SFQ logic OR gate can cause the SFQ logic OR gate to enter a metastable state. A brute-force solution allows only ultra-low skew SFQ pulses to be applied to the input ports by utilizing clocked registers before the inputs to the SFQ logic OR gate. However, this solution cannot be applied to clockless SFQ logic. Exemplary embodiments of metastability-free, clockless SFQ logic gates are now discussed in more detail, e.g., in conjunction with FIGS. 2, 3A, 3B, 4A-4C, 5, and 6.

[0038] For example, Figure 2 schematically illustrates a clockless SFQ logic OR gate in accordance with an exemplary embodiment of the present disclosure. In particular, Figure 2 schematically illustrates a clockless DSFQ logic OR gate 200 comprising a first input port (Port A), a second input port (Port B), an output port (Port Z), a first dynamic storage loop circuit 210-1, a second dynamic storage loop circuit 210-2, an output Josephson junction 220, and a DC bias circuit 230. As will be explained in further detail below, Figure 2 schematically illustrates a two-input clockless DSFQ logic OR gate 200 configured to prevent the possibility of entering a metastable state when first and second input SFQ pulses with a skew approaching one pulse width are applied to the first and second input ports, i.e., Port A and Port B, of the clockless DSFQ logic OR gate 200.

[0039] The first dynamic storage loop circuit 210-1 has a superconducting storage inductor 211-1 (e.g., a quantized superconducting inductor) coupled in series with a first dynamic switch circuit, where the first dynamic switch circuit includes a first Josephson junction 212-1, a second Josephson junction 213-1, and a resistor 214-1. The first Josephson junction 212-1 is coupled in a first branch to a first node N1 and an output node N2. OUT A second Josephson junction 213-1 and a resistor 214-1 are connected in the second branch between the first node N1 and the output node N2. OUTIn this configuration, the first branch is connected in parallel with the second branch to provide a nonlinear flux leakage mechanism that allows the first dynamic storage loop circuit 210-1 to have two independent time constants, including (i) a first time constant corresponding to a dynamic holding time for temporarily storing fluxons (or temporarily storing antifluxons), and (ii) a second time constant corresponding to a self-recovery time for the stored fluxons (or stored antifluxons) to be removed (ejected) from the first dynamic storage loop circuit 210-1 and the first dynamic storage loop circuit 210-1 to return to its ground state.

[0040] Similarly, the second dynamic storage loop circuit 210-2 has a superconducting storage inductor 211-2 (e.g., a quantized superconducting inductor) coupled in series with a second dynamic switch circuit, where the second dynamic switch circuit includes a first Josephson junction 212-2, a second Josephson junction 213-2, and a resistor 214-2. The first Josephson junction 212-2 couples a second node N2 and an output node N3 in the first branch. OUT A second Josephson junction 213-2 and a resistor 214-2 are connected in the second branch between a second node N2 and an output node N OUT In this configuration, the first branch is connected in parallel with the second branch to provide a nonlinear flux leakage mechanism that allows the second dynamic storage loop circuit 210-2 to have two independent time constants, including (i) a first time constant corresponding to a dynamic holding time for temporarily storing fluxons (or temporarily storing antifluxons), and (ii) a second time constant corresponding to a self-recovery time for the stored fluxons (or stored antifluxons) to be removed (ejected) from the second dynamic storage loop circuit 210-2 and the second dynamic storage loop circuit 210-2 to return to its ground state.

[0041] In some embodiments, the SFQ logic OR gate 200 is implemented symmetrically, i.e., the first and second dynamic storage loop circuits 210-1 and 210-2 have the same or substantially the same circuit architecture. In particular, the superconducting storage inductor 211-1 has an inductance L A The superconducting storage inductor 211-2 has an inductance L B where L A and L B are substantially the same. In some embodiments, L A and L B is on the order of 10 picohenries (e.g., 13 pH). Furthermore, the first Josephson junctions 212-1 and 212-2 have a critical current I C1 and the second Josephson junctions 213-1 and 213-2 each have a critical current I C2 In some embodiments, I C1 and I C2 are substantially the same. In another embodiment, the critical current I C1 is the critical current I C2 For example, in some embodiments, I C1 is 70 microamperes (μA), and I C2 is 50 μA. Furthermore, resistor 214-1 has a resistance R A and resistor 214-2 has a resistance R B where R A and R B are substantially the same. For example, in some embodiments, R A and R B is 1 ohm or less.

[0042] As shown schematically in FIG. 2, first and second dynamic storage loop circuits 210-1 and 210-2 have an output node N OUT The output Josephson junction 220 has an output connected in common to the output node N OUT and a negative supply voltage node VSS. The output Josephson junction 220 has a critical current IC3 The output Josephson junction 220 is configured to have an output node N OUT , i.e., port Z. The DC bias circuit 230 is configured to drive the positive power supply node VDD and the output node N OUT The DC bias circuit 230 provides a quiescent bias current I B to bias the output Josephson junction 220. In some embodiments, the DC bias circuit 230 comprises an RSFQ or ERSFQ bias current source.

[0043] To implement a logical OR function in some embodiments, a bias current I B The magnitude of is selected to bias the output Josephson junction 220 higher than a typical value of about 70-75% of its critical current, enabling the output Josephson junction 220 to switch, i.e., generate an SFQ pulse, and thereby apply an output SFQ pulse to port Z, in response to a single-fluxon circulating current injected into either (i) the first dynamic storage loop circuit 210-1 in response to an input SFQ pulse applied to port A or (ii) the second dynamic storage loop circuit 210-2 in response to an input SFQ pulse applied to port B. In some embodiments, to achieve this higher bias level for the output Josephson junction 220, the DC bias circuit 230 adjusts the critical current I of the output Josephson junction 220 to a value higher than the critical current I of the output Josephson junction 220. C3 a quiescent bias current I having a magnitude of at least 75% (or greater) of B For example, in an exemplary non-limiting embodiment, the output Josephson junction 220 is configured to generate a critical current I C3 = 140 μA, the DC bias circuit 230 has a quiescent bias current I B =120 μA (e.g., providing a bias level of approximately 85%).

[0044] As is known in the art, the critical current (generally I c The πf (denoted by πf) indicates the maximum amount of current that can coherently flow through a Josephson junction without exhibiting resistive dissipation. In particular, a Josephson junction behaves as a nonlinear superconducting inductor when the amount of superconducting current flowing through the Josephson junction is lower than the critical current. However, when the current flow through the Josephson junction exceeds its critical current, the Josephson junction temporarily transitions to a resistive state, which generates a finite voltage across the Josephson junction. In the context of a dynamic storage loop as discussed, such temporary switching of a Josephson junction allows a discrete amount of magnetic flux (i.e., a single magnetic flux quantum, or "fluxon") to enter or exit the storage loop containing a given Josephson junction after the given Josephson junction becomes superconducting again.

[0045] It should be noted that each Josephson junction illustrated in the illustrative embodiment shown in the drawings comprises a Josephson tunnel junction device shunted with a resistor. In this regard, the term Josephson junction as used herein refers to a resistively shunted Josephson tunnel junction. The shunt resistor targets a specific value to achieve a condition referred to as critical damping (e.g., critical damping of the LC resonance of the Josephson tunnel junction between the capacitance C of the tunnel junction and the inductance L associated with the superconducting current of the tunnel junction), which directly affects the first-order time constant of the Josephson junction. For example, if the resistance of the shunt resistor is reduced by 50%, the time constant doubles.

[0046] More specifically, a Josephson junction has a critical current I C Josephson tunneling function and resistor R S where the product I for optimum circuit operation is C ×R S =V Cshould not exceed a specific value set by the fabrication process. For a typical process with a critical current density of 10 kA / cm2, the value V C is about 700uV, i.e., the critical current I C A Josephson junction having a current of V = 100 uA is implemented with a shunt resistor having a resistance of 7 ohms. For ease of explanation, the Josephson junction shunt resistor is not shown in the schematic circuit diagram of the drawings, but is assumed to be included with the Josephson junction symbol shown in the drawings (e.g., X symbol). The parameter V C sets the width of the SFQ pulse, e.g., V C Note that when V = 700 uV, the SFQ pulse width is about 2 ps, while its magnitude is about 1 mV. By using a smaller shunt resistor, V C It is also acceptable to decrease φ, which causes a proportional decrease in pulse height and an increase in pulse width since the pulse has a constant area of ​​one flux quantum.

[0047] In an exemplary embodiment, clockless DSFQ logic OR gate 200 operates as follows: Assume that a first (early) SFQ pulse (single fluxon) is applied to port A. As noted above, the SFQ pulse comprises a voltage pulse having a small magnitude (e.g., 1 millivolt (mV)) and short duration (e.g., 2 picoseconds), where the area of ​​the SFQ pulse (i.e., the integral of the voltage over time) is equal to one flux quantum Φ (or one fluxon), where Φ = h / (2e) ≈ 2.07 × 10 -15 Weber (volt-seconds), where h is Planck's constant and e denotes the magnitude of the electron charge. As is known in the art, a magnetic flux quantum Φ is the fundamental unit of magnetic flux that describes the quantization of magnetic flux through a superconducting loop. In this regard, an SFQ pulse has a magnitude (voltage) integral over the duration (time) of the SFQ pulse of approximately 2.07×10 -15A voltage pulse is any voltage pulse having a magnitude (in millivolts) and duration (in picoseconds) such that it is one Weber (volt-second), or one magnetic flux quantum (or one fluxon).

[0048] In response to a first (early) SFQ pulse applied to port A, fluxons are injected into the first dynamic storage loop circuit 210-1, which generates a circulating fluxon current that flows from port A through the first dynamic storage loop circuit 210-1 and through the output Josephson junction 220 into the negative supply voltage node VSS. Because the output Josephson junction 220 is relatively highly biased, a relatively high quiescent bias current I B When combined with the circulating fluxon current in the first dynamic storage loop circuit 210-1, the resulting critical current I of the output Josephson junction 220 C3 As a result, the output Josephson junction 220 transitions temporarily to a resistive state, which generates a voltage across the junction and thus an output SFQ pulse at the output node N OUT and output from port Z. In particular, the switching of the output Josephson junction 220 causes the stored fluxons in the first dynamic storage loop circuit 210-1 to be released from the first dynamic storage loop circuit 210-1 and output as an SFQ pulse on port Z (thereby decrementing the number of fluxons in the first dynamic storage loop circuit 210-1 from 1 to 0).

[0049] Also, when a stored fluxon in the first dynamic storage loop circuit 210-1 is released and output as an SFQ pulse on port Z (as a result of the output Josephson junction 220 switching to its resistive state), an “anti-fluxon” is generated at the output node N OUTand injects the antifluxons into the second dynamic storage loop circuit 210-2 (decrementing the number of fluxons in the (deactivated) second dynamic storage loop circuit 210-2 from 0 to −1). The antifluxons comprise substantially the same fluxons as those emitted from the first dynamic storage loop circuit 210-1 to generate the output SFQ pulse, but the antifluxons generate a circulating current in the second dynamic storage loop circuit 210-2 that flows in the opposite direction to the direction of the circulating current that would be generated if a second (late) input SFQ pulse were applied to port B in the same clock cycle as the first (early) input SFQ pulse applied to port A.

[0050] In this regard, the output node N OUT The antifluxons backpropagated from port A and injected into the second dynamic storage loop circuit 210-2 essentially serve to quench fluxons that would subsequently be injected into the second dynamic storage loop circuit 210-2 once a second (late) SFQ pulse is applied to port B in the same clock cycle as the first (early) input SFQ pulse applied to port A. This effectively prevents the clockless DSFQ logic OR gate 200 from entering a metastable state (as discussed above using the confluence buffer circuit in FIG. 1 ) when first and second input SFQ pulses with a skew close to one pulse width are applied to the first and second input ports, i.e., ports A and B, of the clockless DSFQ logic OR gate 200 in the same clock cycle. This occurs because the same sequence of events occurs regardless of whether the skew of the late pulse on port B versus the early pulse on port A is small (e.g., a fraction of the pulse width) or large (e.g., a multiple of the pulse width): antifluxons enter a given dynamic storage loop circuit from the output port, and then, as a result of SFQ pulses applied to the respective input ports, fluxons enter the given dynamic storage loop circuit, and the fluxons and antifluxons annihilate each other.

[0051] On the other hand, if a second (later) SFQ pulse is not applied to port B during the same clock cycle, the antifluxons in the second dynamic storage loop circuit 210-2 will eventually be removed by the self-resetting mechanism of the second dynamic storage loop circuit 210-2, where after a dynamic hold time has elapsed without generating an output pulse, the second dynamic storage loop circuit 210-2 will self-reset to its ground state (no circulating current). In particular, if a second (later) SFQ pulse is not applied to port B during the same clock cycle, the circulating current from the antifluxons applied over time to the dynamic switch circuit (comprised of Josephson junctions 212-2 and 213-2 and resistor 214-2) will cause the dynamic switch circuit to switch and remove (drain) the stored antifluxons, thereby stopping the flow of circulating current and thus restoring the clockless DSFQ logic OR gate 200 for the next clock cycle.

[0052] It should be understood that the first and second dynamic storage loop circuits 210-1 and 210-2 schematically illustrated in FIG. 2 are non-limiting exemplary embodiments of dynamic storage loop circuits configured to dynamically self-return to a ground state by draining flux of fluxons or antifluxons (temporarily stored in the dynamic storage loop circuit) after a period of time (e.g., a dynamic hold period). In this regard, the term “dynamic storage loop circuit,” as used herein, broadly refers to any type of dynamic storage loop circuit of a logic gate that includes a superconducting loop configured to temporarily store magnetic flux (e.g., fluxons or antifluxons) and includes a leakage mechanism that allows the stored magnetic flux to leak out over time such that the logic gate self-returns to the ground state. In general, dynamic (self-return) storage loop circuits typically utilize either a resistor or an overdamped Josephson junction inserted within the storage loop for magnetic flux leakage. Some dynamic storage loop circuits, particularly those that use plain resistors to implement leakage elements, cause each dynamic logic gate to exhibit a relatively narrow input skew tolerance due to a nearly constant rate of magnetic flux leakage based on a single time constant of the leakage element.

[0053] As noted above, however, the exemplary dynamic storage loop circuit shown in FIG. 2 includes a dynamic switch circuit topology that includes a first branch (including a first Josephson junction) connected in parallel with a second branch (including a second Josephson junction and a resistor connected in series) to provide a leakage mechanism that allows magnetic flux (e.g., fluxons or antifluxons) to escape (or otherwise be drained from) the superconducting storage loop after a dynamic hold period. In particular, the dynamic switch circuit enables the dynamic storage loop circuit to have two independent time constants: one time constant that defines a relatively long hold period (many SFQ pulse widths) and a second time constant that defines a relatively short return period (approximately one SFQ pulse width), where the leakage mechanism provides rapid relaxation to the ground state during the return period while providing slow leakage during the hold period.

[0054] For purposes of illustration, exemplary modes of operation of dynamic storage loop circuits having the same or similar circuit topology as the first and second dynamic storage loop circuits 210-1 and 210-2 (as shown in FIG. 2) will now be discussed in more detail with respect to the general operation of, for example, the first dynamic storage loop circuit 210-1, as implemented in any type of SFQ logic gate (not just the SFQ logic OR gate of FIG. 2). Assume that an input SFQ pulse is applied to port A, which injects fluxons into the first dynamic storage loop circuit 210-1, resulting in a circulating loop current (fluxon current). Further, for purposes of illustration, assume that the output Josephson junction 220 does not switch in response to the circulating fluxon current in the first dynamic storage loop circuit 210-1 alone. In this case, the circulating fluxon current transiently flows at a substantially constant level within the first dynamic storage loop circuit 210-1 for a given period (dynamic hold time) defined by the first time constant. (Note that this may be the case when the output Josephson junction 220 is biased to switch only in response to the combination of the circulating loop currents of the first and second fluxons stored in both the first and second dynamic storage loop circuits 210-1 and 210-2, respectively, thereby implementing an SFQ logic AND gate, as discussed in further detail below in conjunction with FIG. 5.)

[0055] First, on a short time scale, the resistance R of resistor 214-1 A Since I is very small (e.g., 1 ohm or less), the circulating fluxon current is initially distributed (e.g., evenly) between the first and second branches of the first dynamic switch circuit of the dynamic storage loop circuit 210-1. The amount of fluxon current injected into the first dynamic storage loop circuit 210-1 is proportional to the critical current I of the first and second Josephson junctions 212-1 and 213-1, respectively. C1 and I C2and the initial circulating fluxon current does not cause the first and second Josephson junctions 212-1 and 213-1 to switch. As discussed above, assuming for purposes of illustration that the output Josephson junction 220 does not switch in response to the circulating fluxon current in the first dynamic storage loop circuit 210-1 alone, the circulating fluxon current briefly flows at a substantially constant level in the first dynamic storage loop circuit 210-1 for a dynamic holding time defined by the first time constant.

[0056] During the dynamic hold time, the resistance R of resistor 214-1 A Due to this, the circulating fluxon current is redistributed between the first and second branches of the dynamic switch circuit such that more and more circulating fluxon current flows through the first Josephson junction 212-1 (in the first branch) and less and less circulating fluxon current flows through the second Josephson junction 213-1 (in the second branch). A / R A time constant), the total current flow through the first Josephson junction 212-1 reaches its critical current I C1 , which causes the first Josephson junction 212-1 to switch, and the switching of the first Josephson junction 212-1 causes the second Josephson junction 213-1 to switch. At this point, the nodes N1 and N2 as a result of the switching of the first and second Josephson junctions 212-1 and 213-1 OUT A finite voltage across causes removal of stored fluxons through Josephson junctions 212-1 and 213-1 and an associated rapid decrease in circulating fluxon current, thus dynamically self-returning the internal state of first dynamic storage loop circuit 210-1 to the ground state. This self-return process has a recovery time that is significantly faster than the previous retention time (e.g., the retention time could be 40-50 picoseconds (or longer)), as desired through tuning of circuit parameters, while the recovery time can be on the order of one SFQ pulse width, e.g., a few picoseconds).

[0057] 2, as described above, the output Josephson junction 220 switches in response to the circulating fluxon current in the first dynamic storage loop circuit 210-1 to generate an output SFQ pulse on port Z. In this case, the stored fluxons are released from the first dynamic storage loop circuit 210-1 at some point during the dynamic hold period, thereby placing the first dynamic storage loop circuit 210-1 in a ground state without the need for self-recovery.

[0058] The first dynamic storage loop circuit 210-1 may, for example, switch the output Josephson junction 220 and output node N in response to the injection of fluxons into the second dynamic storage loop circuit 210-2 in response to a first (early) pulse applied to port B. OUT Note that the first dynamic storage loop circuit 210-1 can operate in a similar manner to that discussed above when an antifluxon is injected into the first dynamic storage loop circuit 210-1 in response to the generation of the SFQ output pulse above. In this example, the antifluxon is either removed by the dynamic switch circuit of the first dynamic storage loop circuit 210-1, which performs the self-resetting operation as discussed above, or is extinguished by a later SFQ input pulse applied to port A, as described in further detail below in conjunction with FIGS.

[0059] In certain circumstances, depending on the configuration of the circuits driving the input ports, i.e., Port A and Port B, of the clockless DSFQ logic OR gate 200, stored antifluxons in the first dynamic storage loop circuit 210-1 may generate a circulating current that may cause the circuit driving Port A to erroneously switch, or stored antifluxons in the second dynamic storage loop circuit 210-2 may generate a circulating current that may cause the circuit driving Port B to erroneously switch. In this regard, in other embodiments, the clockless DSFQ logic OR gate 200 may be constructed with isolation buffer circuits coupled to the input ports, i.e., Port A and Port B, where the isolation buffer circuits are appropriately switchable to inject fluxons into the first and second dynamic storage loop circuits 210-1 and 210-2 in response to SFQ pulses applied to the input ports, i.e., Port A and Port B, while being configured to absorb (without switching) the circulating current of antifluxons that back-propagate to the input ports, i.e., Port A and Port B.

[0060] 3A and 3B, for example, schematically illustrate a clockless SFQ logic OR gate according to another exemplary embodiment of the present disclosure. In particular, FIG. 3A schematically illustrates a clockless DSFQ logic OR gate 300 comprising the same core DSFQ logic OR gate 200 of FIG. 2, but further comprising a first isolation buffer circuit 310-1 coupled between input port A and the first dynamic storage loop circuit 210-1, and a second isolation buffer circuit 310-2 coupled between port B and the second dynamic storage loop circuit 210-2. As described in further detail below, the first isolation buffer circuit 310-1 is configured to absorb (without switching) the circulating current of antifluxons injected and temporarily stored in the first dynamic storage loop circuit 210-1, preventing the antifluxon current from propagating back from port A to the upstream circuit driving port A. Similarly, the second isolation buffer circuit 310-2 is configured to absorb (without switching) the circulating current of antifluxons injected and temporarily stored in the second dynamic storage loop circuit 210-2, and to prevent the antifluxon current from propagating back from port B to the upstream circuit driving port B.

[0061] 3B schematically illustrates a buffer circuit that can be used to implement the first and second isolation buffer circuits 310-1 and 310-2 of FIG. 3A in accordance with an exemplary embodiment of the present disclosure. In some embodiments, the first and second isolation buffer circuits 310-1 and 310-2 are each implemented using Josephson transmission line (JTL) buffer circuits. Furthermore, in some embodiments, the first and second isolation buffer circuits 310-1 and 310-2 have the same circuit architecture so that the input ports of the clockless DSFQ logic OR gate 300, i.e., port A and port B, are driven symmetrically. In particular, the first isolation buffer circuit 310-1 and the second isolation buffer circuit 310-2 each include a two-stage JTL buffer circuit including a first stage 320 (or first JTL stage), a second stage 330 (or second JTL stage), and a DC bias circuit 340. The first stage 320 includes a first Josephson junction 322 and a first superconducting inductor 324 (e.g., a non-quantized inductor). The second stage 330 includes a second Josephson junction 332 and a second superconducting inductor 334 (e.g., a non-quantized inductor). A DC bias circuit 340 is connected between a positive supply voltage node VDD and an intermediate node N between the first and second superconducting inductors 324 and 334. B (bias current injection node) is connected between the intermediate node N B is the output node of the first stage 320 and the input node of the second stage 330.

[0062] As noted above, the first isolation buffer circuit 310-1 and the second isolation buffer circuit 310-2 have the same circuit architecture and operate in the same manner. However, in the first isolation buffer circuit 310-1, the first stage 320 includes an input node coupled to port A, and the second stage 330 includes an output node Z coupled to the input of the first dynamic storage loop circuit 210-1 (FIG. 3A). AAdditionally, in the second isolation buffer circuit 310-2, the first stage 320 includes an input node coupled to port B, and the second stage 330 includes an output node Z B Includes:

[0063] In the exemplary configuration, the first and second JTL stages 320 and 330 are both powered by the same DC bias circuit 340. In particular, the DC bias circuit 340 is connected to a node N B The bias current I BB where the bias current I BB is the first bias current I for biasing the first Josephson junction 322. B1 and a second bias current I for biasing the second Josephson junction 332. B2 In this configuration, the first and second superconducting inductors 324 and 334 divide to provide a bias current I according to the inductance ratio between the inductance L1 of the first superconducting inductor 324 in series with the Josephson junction 322 and the inductance L2 of the second superconducting inductor 334 in series with the Josephson junction 332. BB The first and second bias currents I B1 and I B2 forming an inductive current divider circuit configured to divide the inductive current into

[0064] In some embodiments, the inductance values ​​L1 and L2 are BB (Node N B ) to bias the first Josephson junction 322 and the second Josephson junction 332, respectively. B1 and I B2 In some embodiments, L1 and L2 have the same or substantially the same value, and the first and second bias currents I B1 and I B2are substantially the same. Furthermore, in some embodiments, the inductance values ​​L1 and L2 are selected to be small enough so that the first and second superconducting inductors 324 and 334 are configured as non-quantizing inductors to ensure that magnetic flux quanta cannot be trapped during the first and second JTL stages 320 and 330.

[0065] The first Josephson junction 322 has a critical current I C4 and the second Josephson junction 332 is designed to have a critical current I C5 where the critical current I C5 is the critical current I C4 In some embodiments, the first Josephson junction 322 has a voltage that drives the second Josephson junction 332, causing the second Josephson junction 332 to switch and provide a voltage to the output node (e.g., Z A or Z B ) is biased at a sufficiently high level to allow the generation of SFQ pulses on the second Josephson junction 332. On the other hand, the second Josephson junction 332 has a critical current I C5 , and counter-propagates to the output node (e.g., Z A or Z B ) is biased at a sufficiently low level to allow the second Josephson junction 332 to absorb the circulating current of antifluxons flowing into the second Josephson junction 332.

[0066] In some embodiments, the first Josephson junction 322 has an I ? of about 0.70 to about 0.75 (i.e., 0.70≦I B1 / I C4 ≦0.75) C4 Nominal bias current I B1 while the second Josephson junction 332 has a critical current I C5 bias current I B2The ratio of I to I is about 0.20 to about 0.40 (i.e., 0.20≦I B2 / I C5 ≦0.40). By way of example, a substantial difference in such bias conditions (only about 2-2.5 times between normal and low relative bias levels) can be seen in the critical current I of the second Josephson junction 332. C5 is the critical current I of the first Josephson junction 322. C4 is about 1.5 times larger than the bias current I B1 is the bias current I B2 In other embodiments, such bias conditions can be achieved by optimizing the size (critical current) of the first and second Josephson junctions 322 and 332 and / or the quiescent bias current I biasing the first and second Josephson junctions 322 and 332. B1 and I B2 This can be achieved by adjusting the level of

[0067] 4A, 4B, and 4C schematically illustrate modes of operation of the clockless DSFQ logic OR gate 300, according to exemplary embodiments of the present disclosure. In particular, FIG. 4A schematically illustrates an exemplary mode of operation 400-1 in which an SFQ pulse (e.g., a single fluxon) of the clockless DSFQ logic OR gate 300 is applied to a first port, i.e., port A, of the clockless DSFQ logic OR gate 300 in a given clock cycle. FIG. 4A also illustrates additional inductors 401 and 402, which represent input line inductances LL1 and LL2, respectively, of the interconnect lines connecting the input ports, i.e., port A and port B, to upstream circuitry. An SFQ pulse 410-1 is applied to the input of the first JTL stage 320 of the first isolation buffer circuit 310-1. Because the various inductors 401, 324, and 334 are non-quantized inductors, i.e., have relatively low inductance values ​​to prevent fluxon storage, an SFQ pulse 410-1 applied to the input of the first JTL stage 320 generates a relatively high magnitude circulating current in the first isolation buffer circuit 310-1. The SFQ pulse 410-1 applied to port A causes the first Josephson junction 322 to reach its critical current I C4 , which in turn switches the first Josephson junction 322 to generate an SFQ pulse 410-2 that is applied to the second JTL stage 330. The SFQ pulse 410-2 causes the second Josephson junction 332 to exceed its critical current I C5 , which in turn switches the second Josephson junction 332 to the output node Z A SFQ pulse 410-3 is generated above.

[0068] Next, an SFQ pulse 410-3 is applied to the input of the first dynamic storage loop circuit 210-1, which causes the core DSFQ logic OR gate 200 to output node N OUT4A , the SFQ pulse 410-3 is injected into the first dynamic storage loop circuit 210-1, generating an output pulse 410-4 output from port Z. In particular, the injection of the SFQ pulse 410-3 into the first dynamic storage loop circuit 210-1 causes a circulating fluxon current to flow in the first dynamic storage loop circuit 210-1. In FIG. 4A , the flow of circulating fluxon current in different branches of the storage loop is represented by unshaded arrows 420-1, 420-2, 420-3, and 420-4. The circulating fluxon current flows through the first dynamic storage loop circuit 210-1, through the output Josephson junction 220, into the negative supply voltage node VSS, through the second Josephson junction 332 of the first isolation buffer circuit 310-1, and back to the input of the first dynamic storage loop circuit 210-1. In this example, the bias current I B The circulating loop current 420-4 through the output Josephson junction 220, combined with C3 , which switches the output Josephson junction 220 to a resistive state, thereby OUT 4A shows the desired data flow (e.g., fluxon propagation) from the input port to the output port of the clockless SFQ logic OR gate.

[0069] As noted above, the first and second superconducting inductors L1 and L2 of the first and second isolation buffer circuits 310-1 and 310-2 are non-quantizing, such that no magnetic flux quanta can be stored between the first and second JTL stages 320 and 330. Thus, in the exemplary embodiment of FIG. 4A , the first isolation buffer circuit 310-1 essentially operates as an SFQ pulse repeater, where an input SFQ pulse 410-1 is actively reproduced by the first JTL stage 320 and the second JTL stage 330 in succession after a short propagation delay. In this regard, when the input SFQ pulse 410-1 is applied to port A, the input SFQ pulse 410-1 causes sequential switching of the first Josephson junction 322, the second Josephson junction 332, and the output Josephson junction 220, generating a current at the output node N. OUT This generates an output SFQ pulse 410-4 above, resulting in the upper branch circuit (including the first isolation buffer circuit 310-1 and the first dynamic storage loop circuit 210-1) returning to its ground state, i.e., a state in which no fluxons are stored in it.

[0070] Next, FIG. 4B shows the output node N OUT The output SFQ pulse 410-4 is generated on the output node N OUT 4B illustrates an exemplary mode of operation 400-2 of the clockless SFQ logic OR gate 300, in which the injection of antifluxons from the first dynamic storage loop circuit 210-1 into the second dynamic storage loop circuit 210-2 is caused. More specifically, as illustrated schematically in FIG. 4B, the circulating fluxon current in the first dynamic storage loop circuit 210-1 is terminated due to the stored fluxons exiting through the output port, and the first dynamic storage loop circuit 210-1 reaches its ground state. Furthermore, the output node N OUTThe generation of output pulse 410-4 above injects antifluxons into the second (non-activated) dynamic storage loop circuit 210-2. Figure 4B shows the reverse flow of antifluxons from the output port toward the input port of the clockless SFQ logic OR gate. In this regard, the term "antifluxon" refers to a counter-propagating fluxon from the output port toward the input port of the SFQ logic gate, which is opposite to the direction of a forward-propagating fluxon from the input port to the output port of the SFQ logic gate.

[0071] 4B, the injection of antifluxons into the second dynamic storage loop circuit 210-2 results in a flow of circulating antifluxon current toward port B, through Josephson junctions 212-2 and 213-2 and superconducting storage inductor 211-2, through the second Josephson junction 332 of the second JTL stage 330 of the second isolation buffer circuit 310-2, back to the negative supply voltage node VSS (e.g., ground), and from the VSS node back through the output Josephson junction 220. The counter-propagating circulating antifluxon current flows in the different branches of the storage loop are represented by shaded arrows 430-1, 430-2, 430-3, and 430-4.

[0072] As shown schematically in FIG. 4B, the total current flow through the second Josephson junction 332 of the second JTL stage 330 of the second isolation buffer circuit 310-2 is the quiescent bias current I B2 and the size of the output node Z B As noted above, the second Josephson junction 332 of the second JTL stage 330 is biased against the bias current I so that the second Josephson junction 332 of the second JTL stage 330 can absorb an additional amount of counterpropagating current 430-4 without causing the second Josephson junction 332 to switch. B2 and the critical current I, which is greater than the sum of the quantized counterpropagating current 430-4 (generated as a result of the antifluxon) C5In this situation, the second Josephson junction 332 remains in a superconducting state to divert the counter-propagating antifluxon current 430-4 to ground.

[0073] On the other hand, the counter-propagating antifluxon current 430-4 flows when the second Josephson junction 332 of the second JTL stage 330 reaches its critical current I C5 , the second Josephson junction 332 switches, generating a counter-propagating pulse that can be applied to the first JTL stage 320. The counter-propagating pulse also causes the first Josephson junction 322 of the first JTL stage 320 to switch, thereby generating a counter-propagating pulse to be output from port B to the upstream circuitry, which is undesirable. However, as discussed above, the second Josephson junction 332 of the second JTL stage 330 is appropriately sized and biased to enable the second Josephson junction 332 to absorb (without switching) the counter-flowing antifluxon current 430-4 and prevent the counter-propagating pulse from being generated and counter-propagating out port B.

[0074] In the exemplary state shown in FIG. 4B, assume that during a given clock cycle in which a first (early) input SFQ pulse is applied to port A (as shown in FIG. 4A), no second (late) input SFQ pulse is applied to port B of clockless DSFQ logic OR gate 300. In this situation, the stored antifluxons in second dynamic storage loop circuit 210-2 are eventually removed by the self-resetting mechanism of second dynamic storage loop circuit 210-2, which includes a dynamic switch circuit composed of Josephson junctions 212-2, 213-2 and resistor 214-2, where second dynamic storage loop circuit 210-2 self-resets to the ground state (no circulating current) for the next clock cycle after a dynamic hold time has elapsed.

[0075] In particular, when antifluxons are injected into the second dynamic storage loop circuit 210-2, resulting in an initial circulating antifluxon current on a short time scale, the resistance R of resistor 214-2 B is very small (e.g., 1 ohm or less), the circulating antifluxon current is initially distributed (e.g., evenly) between the first branch (including the first Josephson junction 212-2) and the second branch (including the second Josephson junction 213-2 and resistor 214-2 of the second dynamic storage loop circuit 210-2, which are connected in series). The amount of antifluxon current injected into the second dynamic storage loop circuit 210-2 is proportional to the critical current I of each of the first and second Josephson junctions 212-2 and 213-2. C1 and I C2 and the initial circulating antifluxon current does not cause the first and second Josephson junctions 212-2 and 213-2 to switch. The circulating antifluxon current temporarily flows at a substantially constant level in the second dynamic storage loop circuit 210-2 for a given period (dynamic holding time) defined by the first time constant.

[0076] During the hold time, the resistance R of resistor 214-2 B Due to this, the circulating antifluxon current is redistributed between the first and second branches of the dynamic switch circuit such that more and more of the circulating antifluxon current flows through the first Josephson junction 212-2 (in the first branch) and less and less of the circulating antifluxon current flows through the second Josephson junction 213-2 (in the second branch). B / R B time constant), the total current flow through the first Josephson junction 212-2 reaches its critical current I C1, which causes the first Josephson junction 212-2 to switch, and the switching of the first Josephson junction 212-2 causes the second Josephson junction 213-2 to switch. At this point, the nodes N2 and N3 as a result of the switching of the first and second Josephson junctions 212-2 and 213-2 OUT The voltage polarity across causes the removal of stored fluxons through Josephson junctions 212-2 and 213-2 and an associated fast decrease in the circulating antifluxon current, causing the internal state of second dynamic storage loop circuit 210-2 to dynamically self-return to the ground state.

[0077] 4C, on the other hand, schematically illustrates an exemplary mode of operation 400-3 in which a second (late) SFQ pulse 440-1 is applied to port B of clockless SFQ logic OR gate 300 during the same clock cycle in which a first (early) input SFQ pulse 410-1 is applied to port A (as shown in FIG. 4A). For example, for illustrative purposes, it is assumed that the second (late) SFQ pulse 440-1 is applied to port B with a short delay (e.g., a few picoseconds or less) from when the first (early) SFQ pulse 410-1 is applied to port A. In this situation, the second (late) SFQ pulse 440-1 injects fluxons into second dynamic storage loop circuit 210-2, where the fluxons cause the annihilation of antifluxons in second dynamic storage loop circuit 210-2. In this case, the fluxons and antifluxons cancel each other out, thereby placing the second dynamic storage loop circuit 210-2 in the ground state without having to self-restore.

[0078] In particular, as shown schematically in FIG. 4C, a second (late) input SFQ pulse 440-1 (input at port B) is applied to the input of the first JTL stage 320 of the second isolation buffer circuit 310-2, which causes the first Josephson junction 322 to reach its critical current I C4, which in turn switches the first Josephson junction 322 to generate an SFQ pulse 440-2 that is applied to the second JTL stage 330. The SFQ pulse 440-2 generates a relatively high circulating forward propagation current (represented by the unshaded arrow 450) that flows through the second Josephson junction 332. The bias current I B2 The combination of the counter-propagating antifluxon current 430-4 and the forward-propagating current 450 causes the second Josephson junction 332 to reach its critical current I C5 , which in turn switches the second Josephson junction 332, driving the output node Z B SFQ pulse 440-3 is generated above.

[0079] In this example, an SFQ pulse 440-3 is applied to the input of the second dynamic storage loop circuit 210-2, which results in the injection of fluxons into the second dynamic storage loop circuit 210-2, which annihilates the antifluxons stored in the second dynamic storage loop circuit 210-2. In this situation, the switching of the second Josephson junction 332 stops the flow of circulating current in the second dynamic storage loop circuit 210-2, thereby causing the output node N OUT 4A, 4B, and 4C occur with a first (early) input SFQ pulse applied to port B and a second (late) input SFQ pulse applied to port A in the same clock cycle.

[0080] In another embodiment, the first and second isolation buffer circuits 310-1 and 310-2 are configured to absorb (without switching) leakage currents flowing into the input ports, i.e., Port A and Port B, of the clockless DSFQ logic OR gate 300 from upstream logic circuits coupled to Port A and / or Port B. This feature is particularly important when the respective leakage currents are not constant but rather depend on the logic state of the upstream circuits, and cannot be eliminated by simply retuning the bias currents. In this regard, the use of first and second isolation buffer circuits 310-1 and 310-2 (e.g., two-stage JTL buffer circuits) enables the construction of tightly coupled composite dynamic SFQ logic gates with more than two inputs, an example embodiment of which is discussed in connection with FIG. 5. The two-stage JTL-based isolation buffer circuits 310-1 and 310-2 as discussed above can be optimized to absorb (without switching) counter-propagating antifluxon currents to prevent counter-propagating pulses from being output from Port A or Port B, protecting the upstream logic circuitry coupled to Port A and / or Port B (i.e., reverse isolation), and to absorb (without switching) any leakage current flowing from the upstream logic circuitry into Port A and / or Port B (i.e., forward isolation). The exemplary two-stage JTL-based isolation buffer circuit provides sufficient isolation in both the forward and reverse directions without loss of operating margin of the circuit and with a minimal physical space (footprint) required for the isolation buffer circuit.

[0081] For example, FIG. 5 schematically illustrates a combinational logic circuit including a clockless SFQ logic gate, according to an exemplary embodiment of the present disclosure. More specifically, FIG. 5 schematically illustrates a combinational logic circuit 500 including a two-input clockless DSFQ logic AND gate 505 coupled to a two-input clockless DSFQ logic OR gate 300. The combinational logic circuit 500 includes a first input port (Port A), a second input port (Port B), a third input port (Port C), and an output port (Port Z). In this regard, the combinational logic circuit 500 includes a three-input clockless DSFQ logic AND-OR gate configured to perform the logical operation Z=AB+C. In the exemplary embodiment of FIG. 5, the two-input clockless DSFQ logic OR gate 300 is similar in circuit architecture and operation to the two-input DSFQ logic OR gate 300 and the core OR gate circuit 200, as discussed above in connection with FIGS. 2, 3A, 3B, and 4A-4C, and the details thereof will not be repeated. However, as shown in FIG. 5, the first isolation buffer circuit 310-1 is coupled to the output of the clockless DSFQ logic AND gate 505, and the second isolation buffer circuit 310-2 has an input coupled to port C.

[0082] The two-input clockless DSFQ logic AND gate 505 has a circuit architecture similar to the two-input clockless DSFQ logic OR gate 200 of FIG. 2, but is configured to perform a logical AND function. In particular, the clockless DSFQ logic AND gate 505 includes a first dynamic storage loop circuit 510-1, a second dynamic storage loop circuit 510-2, an output Josephson junction 520, and a DC bias circuit 530. The first dynamic storage loop circuit 510-1 has a superconducting storage inductor 511-1 (e.g., a quantized superconducting inductor) coupled in series with a first dynamic switch circuit, where the first dynamic switch circuit includes a first Josephson junction 512-1, a second Josephson junction 513-1, and a resistor 514-1. The first Josephson junction 512-1 couples a first node N1 and an output node N2 in a first branch. OUTA second Josephson junction 513-1 and a resistor 514-1 are connected in the second branch between the first node N1 and the output node N2. OUT In this configuration, the first branch is connected in parallel with the second branch to provide a nonlinear flux leakage circuit that allows the first dynamic storage loop circuit 510-1 to have two independent time constants, including a first time constant corresponding to a dynamic hold time and a second time constant corresponding to a self-reset time.

[0083] Similarly, the second dynamic storage loop circuit 510-2 has a superconducting storage inductor 511-2 (e.g., a quantized superconducting inductor) coupled in series with a second dynamic switch circuit, where the second dynamic switch circuit includes a first Josephson junction 512-2, a second Josephson junction 513-2, and a resistor 514-2. The first Josephson junction 512-2 couples a second node N2 and an output node N3 in the first branch. OUT A second Josephson junction 513-2 and a resistor 514-2 are connected in the second branch between a second node N2 and an output node N OUT In this configuration, the first branch is connected in parallel with the second branch to provide a nonlinear flux leakage circuit that allows the second dynamic storage loop circuit 510-2 to have two independent time constants, including a first time constant corresponding to a dynamic hold time and a second time constant corresponding to a self-reset time.

[0084] In some embodiments, the first and second dynamic storage loop circuits 510-1 and 510-2 have the same (or substantially the same) circuit architecture. In particular, the superconducting storage inductor 511-1 and the superconducting storage inductor 511-2 have the same inductance (e.g., on the order of 10 picohenries (e.g., 13 pH)). Furthermore, the first Josephson junctions 512-1 and 512-2 have a critical current I C1 and the second Josephson junctions 513-1 and 513-2 each have a critical current IC2 In some embodiments, I C1 and I C2 are substantially the same. C1 I C2 For example, in some embodiments, I C1 is 70 microamperes (μA), and I C2 is 50 μA. Furthermore, resistor 514-1 has a resistance R SA and resistor 514-2 has a resistance R SB and R SA and R SB are substantially the same. For example, in some embodiments, R A and R B is 1 ohm or less.

[0085] The first and second dynamic storage loop circuits 510-1 and 510-2 are connected to an output node N OUT The output Josephson junction 520 has an output connected in common to the output node N OUT and a negative supply voltage node VSS. The output Josephson junction 520 has a critical current I C6 The output Josephson junction 520 is configured to drive the input of the first isolation buffer circuit 310-1 of the clockless DSFQ logic OR gate 300. The DC bias circuit 530 is connected to the positive power supply node VDD and the output node N OUT The DC bias circuit 530 provides a quiescent bias current I B3 to bias the output Josephson junction 520. In some embodiments, the DC bias circuit 530 comprises an RSFQ or ERSFQ bias current source.

[0086] In some embodiments, to implement a logical AND function, a bias current I B3The magnitude of is such that the output Josephson junction 520 switches only in response to a first input SFQ pulse applied to port A and a second input SFQ pulse applied to port B, thereby causing the output node N OUT The output Josephson junction 520 is selected to bias itself so as to generate an output SFQ pulse above a critical current I C6 bias current I B3 is in the range of about 0.30 to about 0.50 (i.e., 0.30≦I B3 / I C6 ≦0.50). For example, in an exemplary non-limiting embodiment, the output Josephson junction 520 is biased at a critical current I C6 = 140 μA, the DC bias circuit 530 has a quiescent bias current I B3 = 60 μA (providing a bias level of approximately 42%).

[0087] In operation, when a single SFQ pulse is applied to port A, a single fluxon is injected into the first dynamic storage loop circuit 510-1 and temporarily stored therein for a dynamic hold time set by targeting circuit parameters and a value of tens of picoseconds (i.e., greater than approximately 10 times the pulse width of the SFQ pulse), after which the fluxon is released via the dynamic loop self-resetting mechanism as discussed above. Similarly, when a single SFQ pulse is applied to port B, a single fluxon is injected into the second dynamic storage loop circuit 510-2 and temporarily stored therein for a dynamic hold time set by targeting circuit parameters and a value of tens of picoseconds (i.e., greater than approximately 10 times the pulse width of the SFQ pulse), after which the fluxon is released via the dynamic loop self-resetting mechanism as discussed above. In some embodiments, the first and second dynamic storage loop circuits 510-1 and 510-2 have the same circuit architecture, and both the dynamic storage loop circuits 510-1 and 510-2 have essentially the same dynamic hold time and self-recovery time.

[0088] As shown schematically in FIG. 5, the first and second dynamic storage loop circuits 510-1 and 510-2 are configured such that the circulating current of fluxons stored in only one of the first or second dynamic storage loop circuits 510-1 and 510-2 (bias current I B3 In combination with the output Josephson junction 520, its critical current I C6 a sufficiently small quiescent bias current I so that it is not sufficient to momentarily drive the output Josephson junction 520 beyond I B3 Therefore, when an input SFQ pulse is applied to only port A or only port B, the output node N of the clockless DSFQ logic AND gate 505 OUT If only one of the first or second dynamic storage loop circuits 510-1 and 510-2 receives a fluxon, the dynamic storage loop circuit generates an SFQ pulse at the output node NOUT The AND gate 300 then self-recovers after a dynamic hold time without generating an output SFQ pulse on the output Josephson junction 520 (in which case the internal state of the dynamic storage loop circuit returns to the ground state). However, while the fluxons dynamically stored in one of the two dynamic storage loops of the AND gate keep the output Josephson junction 520 from switching, they still change the bias point of the output Josephson junction 520 and therefore apply a state-dependent leakage current to the logic gate driven by the output Josephson junction 520, for example, to the input of the first isolation buffer circuit 310-1 of the clockless DSFQ logic OR gate 300.

[0089] On the other hand, if an input SFQ pulse is applied to both input ports, i.e., port A and port B, with a small to moderate skew (i.e., within the hold time of the clockless DSFQ logic AND gate 505), fluxons are injected and stored in each of the first and second dynamic storage loop circuits 510-1 and 510-2. In this situation, the resulting circulating current in the first and second dynamic storage loop circuits 510-1 and 510-2 is the bias current I B3 The output Josephson junction 520, together with its critical current I C6 , sufficient to temporarily drive the output Josephson junction 520 beyond the reference voltage V sigma to switch the output Josephson junction 520. The switching of the output Josephson junction 520 causes (i) the output node N OUT (ii) the stored fluxons exit the first and second dynamic storage loop circuits 510-1 and 510-2 through the output ports (in this case, the internal states of the first and second dynamic storage loop circuits 510-1 and 510-2 return to the ground state). The output SFQ pulse is then applied to the input of the first isolation buffer circuit 310-1 of the clockless DSFQ logic OR gate 300.

[0090] In the combinational logic circuit configuration of FIG. 5, the first isolation buffer circuit 310-1 is connected to the output node N of the clockless DSFQ logic AND gate 505.OUT For example, when fluxons are stored in at least one of the first and second dynamic storage loop circuits 510-1 and 510-2 of the clockless DSFQ logic AND gate 505, a portion of the circulating current from the stored fluxons flows through the output node N even when the output Josephson junction 520 does not switch. OUT The stored fluxons leak out of the first isolation buffer circuit 310-1 and flow into the first isolation buffer circuit 310-1 during the absence of stored fluxons, resulting in a smaller leakage current (referred to as state-dependent leakage current). However, as discussed above, the first isolation buffer circuit 310-1 is configured to absorb such leakage current without switching. In particular, the first and second Josephson junctions 322 and 332 of the first and second JTL stages 320 and 330 (FIG. 3) of the first isolation buffer circuit 310-1 can be sufficiently sized and / or biased to divert such input leakage current to ground without switching either of the first and second Josephson junctions 322 and 332 as a result of the additional portion of the input leakage current flowing through the first and second Josephson junctions 322 and 332 of the first and second JTL stages 320 and 330.

[0091] 6 is a schematic diagram of a clockless SFQ logic gate according to another exemplary embodiment of the present disclosure. In particular, FIG. 6 is a schematic diagram of a clockless SFQ logic gate 600 including a plurality of input ports, i.e., Port 1,...,Port N, a plurality of isolation buffer circuits 610-1,...,610-N, a plurality of dynamic storage loop circuits 620-1,...,620-N, an output Josephson junction 630, and a DC bias circuit 640. The input ports, i.e., Port 1,...,Port N, are coupled to inputs of the isolation buffer circuits 610-1,...,610-N, respectively. The isolation buffer circuits 610-1,...,610-N have outputs coupled to inputs of the dynamic storage loop circuits 620-1,...,620-N, respectively. The dynamic storage loop circuits 620-1,...,620-N provide output nodes N OUT The output Josephson junction 630 has an output commonly coupled to the output node N OUT and a negative supply voltage node VSS. The output Josephson junction 630 has a critical current I C7 The output Josephson junction 630 is configured to have an output node N OUT , i.e., port Z. The DC bias circuit 640 is configured to drive the positive power supply node VDD and the output node N OUT The DC bias circuit 640 provides a quiescent bias current I B4 to bias the output Josephson junction 630. Given a critical current I of the output Josephson junction 630, C7 With respect to the quiescent bias current I B4 can be set based on the number of active inputs of clockless SFQ logic gate 600 required for a given logic function performed by clockless SFQ logic gate 600 to switch output Josephson junction 630 to generate an SFQ output pulse on port Z.

[0092] In some embodiments, DC bias circuit 640 comprises an RSFQ or ERSFQ bias current source. In some embodiments, isolation buffer circuits 610-1,...,610-N have the same or substantially the same circuit architecture and are each implemented using a multi-stage JTL buffer circuit. For example, in some embodiments, isolation buffer circuits 610-1,...,610-N each implement a two-stage JTL buffer circuit as shown in FIG. 3B. In other embodiments, isolation buffer circuits 610-1,...,610-N can be implemented using three or more JTL stages to provide additional isolation, but with the last (output) JTL stage including a Josephson junction that is under-biased at a substantially lower percentage of its critical current, allowing the Josephson junction in the last (output) JTL stage to absorb antifluxon current without switching, as discussed above, and preventing antifluxons in a given dynamic storage loop circuit from being output from the input port.

[0093] In some embodiments, the dynamic storage loop circuits 620-1,...,620-N have the same or substantially the same circuit architecture, e.g., are each implemented using the same or similar dynamic storage loop circuit topology as the exemplary dynamic storage loop circuits 210-1 and 210-2 shown and discussed above in connection with FIG. 2. In some embodiments, the dynamic storage loop circuits 620-1,...,620-N can each be implemented using any suitable type of dynamic storage loop circuit for a logic gate, where the dynamic storage loop circuit includes a superconducting loop configured to temporarily store magnetic flux (e.g., fluxons or antifluxons) and including a leakage mechanism that allows the stored magnetic flux to leak out over time so that the logic gate returns to its ground state. For example, the flux leakage mechanism of the dynamic storage loop circuit can be implemented using a single Josephson junction connected in parallel with a resistor.

[0094] In some embodiments, the number (N) of input ports and corresponding isolation buffer circuits and dynamic storage loops can be, for example, N=2, 3, 5, etc., depending on the given type of logic gate. For example, in some embodiments, clockless SFQ logic gate 600 can be a three-input SFQ logic OR gate or a three-input SFQ majority voting (MAJ) logic gate. For a three-input SFQ logic OR gate (N=3) having input ports, i.e., port 1, port 2, and port 3, an input SFQ pulse applied to one of the three input ports injects fluxons into one “activating” dynamic storage loop circuit, and output Josephson junction 630 is biased to switch in response to the one activating input and generate an output SFQ pulse on port Z. Furthermore, antifluxons are injected into each of the two non-activated dynamic storage loop circuits (which were in their ground states before the switching of the output Josephson junction 630) to quench any fluxons that may later be injected into one of the other two non-activated dynamic storage loop circuits due to a late SFQ input pulse applied to another one of the input ports of the three-input SFQ logic OR gate in the same clock cycle, thereby achieving metastability-free logic gate functionality.

[0095] For a three-input SFQ logic MAJ gate (N=3) having input ports, i.e., port 1, port 2, and port 3, an input SFQ pulse applied to each of at least two input ports (out of the three input ports) injects fluxons into each of two “activated” dynamic storage loop circuits, and output Josephson junction 630 is biased to switch in response to the at least two activation inputs to generate an output SFQ pulse on port Z. Furthermore, an antifluxon is injected into one non-activated dynamic storage loop circuit (which was in its ground state before switching of output Josephson junction 630) to quench a fluxon that may later be injected into one non-activated dynamic storage loop circuit due to a later SFQ input pulse applied to the corresponding input port of the three-input SFQ logic MAJ gate in the same clock cycle, thereby achieving metastability-free logic gate functionality.

[0096] Similarly, for a 5-input SFQ logic MAJ gate (N=5) having input ports, i.e., port 1, port 2, port 3, port 4, and port 5, an input SFQ pulse applied to each of at least three input ports (out of the five input ports) injects fluxons into each of three “activated” dynamic storage loop circuits, and output Josephson junction 630 is biased to switch in response to the at least three activation inputs to generate an output SFQ pulse on port Z. Furthermore, antifluxons are injected into two non-activated dynamic storage loop circuits (which were in their ground states before the switching of output Josephson junction 630) to quench any fluxons that may later be injected into a given one of the non-activated dynamic storage loop circuits due to a later SFQ input pulse applied to the corresponding input port of the 5-input SFQ logic MAJ gate in the same clock cycle, thereby achieving metastability-free logic gate functionality.

[0097] 6, which includes dynamic storage loop circuits 620-1,...,620-N driving one output Josephson junction 630 biased with a quiescent DC current, can operate as a metastability-free clockless SFQ logic OR gate or logic MAJ gate. For example, with respect to a three-input port configuration of clockless SFQ logic gate 600, clockless SFQ logic gate 600 operates with a quiescent bias current I (generated by DC bias circuit 640). B4 It should be appreciated that output Josephson junction 630 can be dynamically configured to operate as a three-input logic AND gate, a three-input logic MAJ gate, or a three-input logic OR gate by adjusting the bias point of output Josephson junction 630 so that it switches and generates an output SFQ pulse on port Z in response to either 3, 2, or 1 active input, respectively, and does not switch and generates no output SFQ pulse when the number of active inputs is 2, 1, or 0, respectively. Input isolation buffer circuits 610-1,...,610-N are utilized to drive the inputs to each dynamic storage loop circuit 620-1,...,620-N to prevent backpropagation of antifluxons injected into deactivated dynamic storage loop circuits and to enable metastability-free clockless gating for the logic OR and MAJ gate functions using techniques as discussed above. Note that for a three-input SFQ logic AND gate, if the logic AND gate generates an output SFQ pulse on port Z in response to activation of all three input ports, no antifluxons are generated, which makes the use of an isolation buffer circuit optional for a clockless SFQ logic AND gate.

[0098] It should be noted that the exemplary DSFQ logic circuits discussed herein can be utilized to build various types of combinatorial logic circuits, which are fundamental components for various types of VLSI integrated circuits and devices, such as microprocessors for superconducting computing applications. For example, FIG. 7 schematically illustrates a superconducting computing system 700 comprising a control system 710. The control system 710 includes at least one processor 720, which includes a combinatorial DSFQ logic circuit 722, and a control circuit 730, which includes a combinatorial DSFQ logic circuit 732. In some embodiments, the control system 710 is disposed in a dilution refrigeration system 740 capable of generating cryogenic temperatures sufficient to operate the components of the control system 710 for superconducting computing applications, such as quantum computing applications. In some embodiments, the dilution refrigeration system 740 has five different temperature stages: 20 Kelvin (mK), 100 mK, 1 K, 3-4 K, and 40 K, where different components of the control system 710 can be cooled to desired target temperatures depending on the application.

[0099] In some embodiments, processor 720 is configured to execute program code to perform one or more HPC applications, where in some embodiments, superconducting combinatorial DSFQ logic circuitry 722 of processor 720 supports standard digital machine architectures and algorithms associated with standard room-temperature CMOS computing. In some embodiments, processor 720 is configured to execute computer-readable program instructions embodied on a computer program product including, for example, computer-readable storage medium(s) containing computer-readable program instructions for causing processor 720 to perform various control methods using superconducting control circuitry 730.

[0100] In some embodiments, control system 710 is implemented for quantum computing to control the operation of an array of superconducting quantum bits (qubits) of a quantum processor. Control system 710 can be configured to (i) control a multi-channel arbitrary waveform generator (AWG) system configured to generate control pulses applied to the superconducting qubits to perform single-qubit or multi-qubit (entangled) gating operations, (ii) control a qubit readout system to read out the quantum states of the superconducting qubits, (iii) perform quantum error correction operations, etc.

[0101] Various aspects of the present disclosure are described through narrative text, flowcharts, block diagrams of computer systems, and / or block diagrams of machine logic included in computer program product (CPP) embodiments. For any flowchart, depending on the technology involved, operations may be performed in an order different from that shown in a given flowchart. For example, again depending on the technology involved, two operations shown in successive flowchart blocks may be performed in reverse order, as a single integrated step, simultaneously, or in an at least partially overlapping manner.

[0102] A computer program product embodiment ("CPP embodiment" or "CPP") is a term used in this disclosure to describe any set of one or more storage media (also referred to as "media"), collectively contained in one or more storage devices, that collectively contain machine-readable code corresponding to instructions and / or data for performing the computer operations specified in a given CPP claim. A "storage device" is any tangible device that can hold and store instructions for use by a computer processor. The computer-readable storage medium may be, but is not limited to, an electronic storage medium, a magnetic storage medium, an optical storage medium, an electromagnetic storage medium, a semiconductor storage medium, a mechanical storage medium, or any suitable combination of the foregoing. Some known types of storage devices that include these media include diskettes, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), compact disk read-only memory (CD-ROM), digital versatile disk (DVD), memory stick, floppy disk, mechanically encoded device (such as a punch card or pits / lands formed on a major surface of a disk), or any suitable combination of the foregoing. Computer-readable storage media, as the term is used in this disclosure, is not to be construed as storage in the form of a transitory signal per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide, light pulses passing through fiber optic cables, electrical signals communicated through wires, and / or other transmission media. As will be appreciated by those skilled in the art, data is typically moved at some infrequent time during the normal operation of a storage device, such as during access, defragmentation, or garbage collection, but the foregoing does not qualify a storage device as transitory because the data is not transitory while it is stored.

[0103] 8 includes an example of an environment for execution of at least some of the computer code involved in performing the inventive method for high performance superconducting computing using superconducting DSFQ logic circuits, such as high performance computing application code in block 826 that is executable by a superconducting processor to perform high performance superconducting computing operations or superconducting quantum computing using superconducting DSFQ logic circuits, as discussed herein. In addition to block 826, computing environment 800 includes, for example, computer 801, wide area network (WAN) 802, end user device (EUD) 803, remote server 804, public cloud 805, and private cloud 806. In this embodiment, computer 801 includes a set of processors 810 (including processing circuitry 820 and cache 821), a communications fabric 811, volatile memory 812, persistent storage 813 (including operating system 822 and block 826, as identified above), a set of peripheral devices 814 (including a user interface (UI), a set of devices 823, storage 824, and a set of Internet of Things (IoT) sensors 825), and a network module 815. Remote server 804 includes a remote database 830. Public cloud 805 includes a gateway 840, a cloud orchestration module 841, a set of host physical machines 842, a set of virtual machines 843, and a set of containers 844.

[0104] Computer 801 may take the form of a desktop computer, a laptop computer, a tablet computer, a smartphone, a smartwatch or other wearable computer, a mainframe computer, a quantum computer, or any other form of computer or mobile device now known or later developed that is capable of executing programs, accessing a network, or querying a database, such as remote database 830. As is well understood in the field of computer technology, and depending on the technology, execution of a computer-implemented method may be distributed among multiple computers and / or among multiple locations. However, in this presentation of computing environment 800, to keep the presentation as concise as possible, the detailed discussion focuses on a single computer, specifically computer 801. Computer 801 may be located in a cloud, although it is not depicted within the cloud in FIG. 8 . However, computer 801 is not required to reside within a cloud except to any extent that may be expressly indicated.

[0105] Processor set 810 includes one or more computer processors of any type now known or later developed. Processing circuitry 820 may be distributed across multiple packages, e.g., multiple cooperating integrated circuit chips. Processing circuitry 820 may implement multiple processor threads and / or multiple processor cores. Cache 821 is memory located within the processor chip package and is typically used for data or code that should be available for fast access by threads or cores executing on processor set 810. Cache memory is typically organized into multiple levels depending on relative proximity to the processing circuitry. Alternatively, some or all of the cache for a processor set may be located “off-chip.” In some computing environments, processor set 810 may be designed to operate with qubits and perform quantum computing.

[0106] Computer-readable program instructions are typically loaded into computer 801 and a series of operational steps are executed by processor set 810 of computer 801, thereby performing a computer-implemented method, such that the instructions so executed instantiate the methods specified in the computer-implemented method flowcharts and / or narrative descriptions contained in this document (collectively, the "methods of the present invention"). These computer-readable program instructions are stored in various types of computer-readable storage media, such as cache 821 and other storage media discussed below. The program instructions and associated data are accessed by processor set 810 to control and direct the execution of the methods of the present invention. In computing environment 800, at least some of the instructions for performing the methods of the present invention may be stored in block 826 in persistent storage 813.

[0107] Communications fabric 811 is the signal-conducting pathway that allows various components of computer 801 to communicate with one another. Typically, this fabric is made up of switches and conductive pathways, such as switches and conductive pathways that make up buses, bridges, physical input / output ports, etc. Other types of signal communication pathways may be used, such as fiber optic and / or wireless communication pathways.

[0108] Volatile memory 812 may be any type of volatile memory now known or later developed. Examples include dynamic type random access memory (RAM) or static type RAM. Typically, volatile memory is characterized by random access, although this is not required unless expressly indicated. In computer 801, volatile memory 812 is located in a single package and is internal to computer 801; however, alternatively or additionally, volatile memory may be distributed across multiple packages and / or located external to computer 801.

[0109] Persistent storage 813 is any form of non-volatile computer storage, now known or later developed. The non-volatility of this storage means that stored data is maintained regardless of whether power is supplied to computer 801 and / or directly to persistent storage 813. Persistent storage 813 can be read-only memory (ROM), but typically at least a portion of persistent storage allows data to be written, data to be deleted, and data to be rewritten. Some well-known forms of persistent storage include magnetic disks and solid-state storage devices. Operating system 822 may take several forms, such as various known proprietary operating systems or open-source Portable Operating System Interface-type operating systems that utilize a kernel. The code contained in block 826 typically includes at least some of the computer code involved in performing the methods of the present invention.

[0110] Peripheral device set 814 includes a set of peripheral devices of computer 801. Data communication connections between peripheral devices and other components of computer 801 may be implemented in various ways, such as Bluetooth connections, near field communication (NFC) connections, connections formed by cables (such as universal serial bus (USB)-type cables), insertion-type connections (e.g., Secure Digital (SD) cards), connections formed through local area communication networks, and even connections formed through wide area networks such as the Internet. In various embodiments, UI device set 823 may include components such as display screens, speakers, microphones, wearable devices (such as goggles and smartwatches), keyboards, mice, printers, touchpads, game controllers, and haptic devices. Storage 824 may be external storage, such as an external hard drive, or insertable storage, such as an SD card. Storage 824 may be persistent and / or volatile. In some embodiments, storage 824 may take the form of a quantum computing storage device for storing data in the form of qubits. In embodiments where computer 801 is required to have a large amount of storage (e.g., where computer 801 stores and manages a large database locally), this storage may be provided by a peripheral storage device designed to store very large amounts of data, such as a storage area network (SAN) shared by multiple, geographically distributed computers. IoT sensor set 825 consists of sensors that can be used in Internet of Things applications. For example, one sensor may be a thermometer and another may be a motion detector.

[0111] The network module 815 is a collection of computer software, hardware, and firmware that enables the computer 801 to communicate with other computers over the WAN 802. The network module 815 may include hardware such as a modem or Wi-Fi signal transceiver, software for packetizing and / or depacketizing data for communication network transmission, and / or web browser software for communicating data over the Internet. In some embodiments, the network control and network forwarding functions of the network module 815 are performed on the same physical hardware device. In other embodiments (e.g., embodiments utilizing Software-Defined Networking (SDN)), the control and forwarding functions of the network module 815 are performed on physically separate devices, such that the control function manages several different network hardware devices. Computer-readable program instructions for carrying out the methods of the present invention may be downloaded to the computer 801 from an external computer or external storage device, typically through a network adapter card or network interface included in the network module 815.

[0112] WAN 802 is any wide area network (e.g., the Internet) capable of communicating computer data over non-local distances by any technology for communicating computer data now known or later developed. In some embodiments, a WAN may be replaced and / or supplemented by a local area network (LAN) designed to communicate data between devices located in a local area, such as a Wi-Fi network. WANs and / or LANs typically include copper transmission cables, optical fiber transmissions, wireless transmissions, and computer hardware such as routers, firewalls, switches, gateway computers, and edge servers.

[0113] End-user device (EUD) 803 is any computer system used and controlled by an end user (e.g., a customer of the enterprise operating computer 801) and may take any of the forms discussed above in connection with computer 801. EUD 803 typically receives useful and useful data from the operation of computer 801. For example, in the hypothetical case where computer 801 is designed to provide recommendations to the end user, the recommendations would typically be communicated from computer 801's network module 815 over WAN 802 to EUD 803. In this manner, EUD 803 can display or otherwise present the recommendations to the end user. In some embodiments, EUD 803 may be a client device such as a thin client, a heavy client, a mainframe computer, a desktop computer, and the like.

[0114] Remote server 804 is any computer system that provides at least some data and / or functionality to computer 801. Remote server 804 may be controlled and used by the same entity that operates computer 801. Remote server 804 represents a machine that collects and stores useful and useful data for use by other computers, such as computer 801. For example, in the hypothetical case where computer 801 is designed and programmed to provide recommendations based on historical data, then this historical data may be provided to computer 801 from remote database 830 of remote server 804.

[0115] A public cloud 805 is any computer system available for use by multiple entities that provides on-demand availability of computer system resources and / or other computer capabilities, particularly data storage (cloud storage) and computing power, without direct, active management by users. Cloud computing typically leverages resource sharing to achieve coherence and economies of scale. Direct, active management of the computing resources of the public cloud 805 is performed by the computer hardware and / or software of a cloud orchestration module 841. The computing resources provided by the public cloud 805 are typically implemented by virtual computing environments running on various computers comprising a host physical machine set 842, which is the universe of physical computers within and / or available in the public cloud 805. A virtual computing environment (VCE) typically takes the form of a virtual machine from a virtual machine set 843 and / or a container from a container set 844. It is understood that these VCEs may be stored as images and may be transferred among and between various physical machine hosts, either as images or after instantiation of the VCE. The cloud orchestration module 841 manages the transfer and storage of images, deploys new instantiations of the VCE, and manages active instantiations of VCE deployments. The gateway 840 is a collection of computer software, hardware, and firmware that enables the public cloud 805 to communicate over the WAN 802.

[0116] Some further description of virtualized computing environments (VCEs) is now provided. A VCE can be stored as an "image." A new, active instance of a VCE can be instantiated from the image. Two well-known types of VCEs are virtual machines and containers. A container is a VCE that uses operating system-level virtualization. This refers to a feature of an operating system in which the kernel allows the existence of multiple isolated user space instances, called containers. These isolated user space instances typically behave as real computers from the perspective of programs running within them. A computer program running on a typical operating system can utilize all of the computer's resources, such as connected devices, files and folders, network shares, CPU power, and quantifiable hardware capabilities. However, a program running inside a container can only use the contents of the container and of the devices assigned to the container; this feature is known as containerization.

[0117] Private cloud 806 is similar to public cloud 805, except that the computing resources are available only for use by a single enterprise. While private cloud 806 is shown as being in communication with WAN 802, in other embodiments, the private cloud may be completely disconnected from the Internet and accessible only through a local / private network. A hybrid cloud is a composite of multiple clouds of different types (e.g., private, community, or public cloud types), often each implemented by a different vendor. While each of the multiple clouds remains a separate, discrete entity, the larger hybrid cloud architecture is bound together by standardized or proprietary technologies that enable orchestration, management, and / or data / application portability between the constituent clouds. In this embodiment, both public cloud 805 and private cloud 806 are part of a larger hybrid cloud.

[0118] The description of various embodiments of the present disclosure has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein has been selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially available technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. a logic circuit having a clockless single flux quantum logic gate, the clockless single flux quantum logic gate comprising: a plurality of input ports and an output port; a plurality of dynamic storage loop circuits; an output Josephson junction coupled to an output of each of the dynamic storage loop circuits, the output Josephson junction configured to drive the output port; a plurality of isolation buffer circuits, wherein each isolation buffer circuit is coupled to a respective input port and a respective dynamic storage loop circuit; and each isolation buffer circuit configured to absorb circulating current of the antifluxons injected into the respective dynamic storage loop circuit as a result of the output Josephson junction switching to generate a single flux quantum output pulse at the output port, so as to prevent antifluxons from being output from the respective input port; Each isolation buffer circuit is configured to inject fluxons into the respective dynamic storage loop circuit and annihilate antifluxons present in the respective dynamic storage loop circuit in response to a single flux quantum pulse applied to the respective input port. device.

2. 2. The device of claim 1, wherein the output Josephson junction is biased at a level that enables the output Josephson junction to switch in response to a circulating current of fluxons injected into at least one of the dynamic storage loop circuits to generate the single flux quantum output pulse at the output port.

3. 10. A device according to any preceding claim, wherein the output Josephson junction is biased at a level that enables the output Josephson junction to switch in response to a circulating current of fluxons injected into each of at least two dynamic storage loop circuits to produce the single flux quantum output pulse on the output port.

4. 10. The device of claim 1, wherein the isolation buffer circuits have the same circuit architecture, and each of the isolation buffer circuits comprises a multi-stage Josephson transmission line buffer circuit.

5. 5. The device of claim 4, wherein each multi-stage Josephson transmission line buffer circuit comprises a two-stage Josephson transmission line buffer circuit.

6. 5. The device of claim 4, wherein each multi-stage Josephson transmission line buffer circuit includes an output stage that is a Josephson junction coupled to an input of the respective dynamic storage loop circuit, the output stage including the Josephson junction biased at a level that enables the Josephson junction of the output stage to absorb a counter-propagating antifluxon current flowing from the input of the respective dynamic storage loop circuit without causing the Josephson junction of the output stage to switch as a result of a combination of the counter-propagating antifluxon current and a quiescent bias current biasing the Josephson junction of the output stage.

7. 7. The device of claim 6, wherein the Josephson junctions of the output stage are biased at a level where the magnitude of the quiescent bias current is in the range of about 20 percent to about 40 percent of the critical current of the Josephson junctions of the output stage.

8. The dynamic storage loop circuits have the same circuit architecture, and the dynamic storage loop circuits include: a series combination of a superconducting inductor and a dynamic switch circuit coupled to an input port and to said output port; each including the dynamic switch circuit includes a parallel combination of a first Josephson junction and a series combination of a second Josephson junction and a resistor; 10. The device of any preceding claim, wherein the dynamic switch circuit is configured to enable dynamic self-restore of an internal state of the dynamic storage loop circuit based on a first time constant for temporarily storing fluxon or antifluxon magnetic flux and a second time constant for discharging the stored magnetic flux.

9. 10. A device according to any preceding claim, wherein the clockless single flux quantum logic gate comprises a clockless logic OR gate including at least two input ports.

10. 10. A device according to any preceding claim, wherein the clockless single flux quantum logic gate comprises a clockless logic majority gate including at least three input ports.

11. a logic circuit having a clockless single flux quantum logic gate, wherein the clockless single flux quantum logic gate comprises: a first input port, a second input port, and an output port; a first dynamic storage loop circuit; a second dynamic storage loop circuit; an output Josephson junction coupled to an output of the first dynamic storage loop circuit and an output of the second dynamic storage loop circuit, the output Josephson junction configured to drive the output port; a first multi-stage Josephson transmission line buffer circuit coupled between the first input port and the first dynamic storage loop circuit, the first multi-stage Josephson transmission line buffer circuit including an output stage including a Josephson junction configured to absorb a circulating current of antifluxons injected into the first dynamic storage loop circuit as a result of the output Josephson junction switching to generate a single flux quantum output pulse on the output port to prevent antifluxons from being output from the first input port, and configured to switch in response to a single flux quantum pulse applied to the first input port to inject fluxons into the first dynamic storage loop circuit and quench antifluxons present in the first dynamic storage loop circuit; and a second multi-stage Josephson transmission line buffer circuit coupled between the second input port and the second dynamic storage loop circuit, the second multi-stage Josephson transmission line buffer circuit having an output stage including a Josephson junction configured to absorb a circulating current of antifluxons injected into the second dynamic storage loop circuit as a result of the output Josephson junction switching to generate a single flux quantum output pulse on the output port to prevent antifluxons from being output from the second input port, and configured to switch in response to a single flux quantum pulse applied to the second input port to inject fluxons into the second dynamic storage loop circuit and quench antifluxons present in the second dynamic storage loop circuit; A device having:

12. 12. The device of claim 11, wherein the output Josephson junction is biased at a level where the magnitude of the quiescent bias current is at least 60 percent of the critical current of the output Josephson junction.

13. 13. The device of any preceding claim 11 or 12, wherein the first multi-stage Josephson transmission line buffer circuit and the second multi-stage Josephson transmission line buffer circuit each comprise a two-stage Josephson transmission line buffer circuit including a respective input stage and the output stage.

14. 14. The device of any of the preceding claims 11 to 13, wherein the Josephson junctions of the output stages of the first multi-stage Josephson transmission line buffer circuit and the second multi-stage Josephson transmission line buffer circuit are each biased with a respective quiescent bias current having a magnitude in a range from about 20 percent to about 40 percent of a critical current of the Josephson junctions of the output stages.

15. the first dynamic storage loop circuit and the second dynamic storage loop circuit have the same circuit architecture, and the first dynamic storage loop circuit and the second dynamic storage loop circuit are a first node and a second node coupled to the output port; a superconducting inductor coupled to the first node; and a dynamic switch circuit coupled to and between the first node and the second node; each having the dynamic switch circuit includes a first Josephson junction coupled between the first node and the second node, and a second Josephson junction and a resistor connected in series between the first node and the second node in parallel with the first Josephson junction; The dynamic switch circuit is configured to enable dynamic self-resetting of an internal state based on a first time constant for temporarily storing fluxon or antifluxon magnetic flux and a second time constant for discharging the stored magnetic flux. A device according to any of the preceding claims 11 to 14.

16. 16. The device of any preceding claim 11 to 15, wherein the logic circuit further includes a second clockless single flux quantum logic gate including an output port coupled to the first input port of the clockless single flux quantum logic gate, and wherein the first multi-stage Josephson transmission line buffer circuit is configured to absorb leakage current flowing from the output port of the second clockless single flux quantum logic gate without switching the Josephson junctions of the output stage of the first multi-stage Josephson transmission line buffer circuit.

17. 17. A device according to any preceding claim 11 to 16, wherein the clockless single flux quantum logic gate comprises a clockless single flux quantum logic OR gate.

18. receiving a first single flux quantum pulse on a first input port of a clockless single flux quantum logic gate at a given clock cycle; injecting fluxons into a first dynamic storage loop circuit of the clockless single flux quantum logic gate in response to the first single flux quantum pulse; outputting a single flux quantum pulse on an output port of the clockless single flux quantum logic gate in response to the fluxon being injected into the first dynamic storage loop circuit; injecting antifluxons into a second dynamic storage loop circuit of the clockless single flux quantum logic gate in response to outputting the single flux quantum pulse on the output port; and utilizing an isolation buffer circuit coupled to an input of the second dynamic storage loop circuit to absorb circulating current of the antifluxons in the second dynamic storage loop circuit and prevent the antifluxons from being output from a second input port of the clockless single flux quantum logic gate. A method for providing the above.

19. receiving a second single flux quantum pulse on the second input port of the clockless single flux quantum logic gate in the given clock cycle; and utilizing the antifluxons in the second dynamic storage loop circuit to quench the fluxons injected into the second dynamic storage loop circuit in response to the second single flux quantum pulse, such that the fluxons injected into the second dynamic storage loop circuit do not propagate to the output port.

20. The method of claim 18, further comprising:

20. 20. The method of any of claims 18 to 19, wherein injecting the antifluxons into the second dynamic storage loop circuit of the clockless single flux quantum logic gate in response to outputting the single flux quantum pulse on the output port comprises switching an output Josephson junction coupled to the output port in response to a circulating current of the fluxons injected into the first dynamic storage loop circuit to generate the single flux quantum pulse on the output port.

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