Cryogenically compatible hermetic packing for superconducting quantum chips

Abstract

A packaging structure (100) for a superconducting quantum processing unit (110) is disclosed. The packaging structure includes a ceramic support portion (101) for supporting the quantum processing unit (110), the support portion (101) including a plurality of electrical connections (104) for connecting the quantum processing unit to a plurality of electrical contacts on an outer surface of the ceramic packing structure (100). Additionally, a packaged quantum processing unit and a method for packaging a quantum processing unit using the above packaging structure are disclosed.

Description

[Technical Field]

[0001] The present invention relates generally to materials science, and more particularly to ceramic-based materials suitable for various solutions in cryogenic and superconducting applications such as quantum information processing and quantum hardware. [Background technology]

[0002] The heart of a superconducting QPU is a silicon or sapphire chip with a qubit structure made of superconducting metal on it. In large QPUs, the qubits are arranged in a two-dimensional lattice. To route control signals to the center of the lattice, wires must be drawn in perpendicular to the plane.

[0003] The wiring solution must simultaneously meet several criteria, including high bandwidth (for some signals), controlled impedance, low crosstalk, low dissipation, low microwave loss, shielding of the qubit circuitry from lossy materials, tight pitch to match the dimensions of the QPU unit cell and the number of signals per unit cell, high reliability, and the ability to replace the QPU.

[0004] Ceramic technology as a packaging solution for semiconductor dies is generally well known, for example in solutions using silicon substrates and multi-level interconnects using planarized dielectric materials. Summary of the Invention [Problem to be solved by the invention]

[0005] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. It is an object of the present invention to provide novel materials comprising a ceramic and a metallic component that imparts superconducting properties to a functionalized ceramic substrate. The materials can be fabricated using known manufacturing methods, for example, by utilizing a low-temperature co-fired ceramic (LTCC) base or green sheet or other substrate on which a mixture of a suitable metal and, for example, a polymeric carrier is deposited as a layer and then pre-fired or dried; functionalization layers are optionally developed on the pre-fired green sheet, including, for example, two- or three-dimensional physical structures such as trough vias, cavities, routes, etc., and finally pressed and fired to achieve a functionalized multilayer structure that can be utilized as a component for multiple different purposes, as disclosed below.

[0006] This type of material has many beneficial properties, including high stiffness, conductive properties, a thermal expansion coefficient suitable for various applications, impermeability to gases (due to its glass-like composition after firing), and machinability, to name a few, and can be easily used as a base layer or interposer layer for a variety of purposes.

[0007] This solution meets all of the design criteria disclosed in the background section while being relatively inexpensive and scalable to large substrate sizes (up to 6 inches or 15.24 cm) and many wiring layers (up to 38 layers), using readily available processes. Note that the compressible springs require a significant amount of force (typically 10 grams per contact), and the ceramic layers are required to avoid extensive warping of the chip stack, which would compromise the usefulness of the QPU and superconducting chip.

[0008] The problem(s) solved by the present invention include the following: - Vertical delivery and fan-out of signals from dense pitch silicon TSV pad arrays to conventional PCBs -Proposing a material with a CTE closer to silicon than conventional PCBs -Higher signal isolation than SiO2 / Si multi-layer wiring The rigidity of the hard ceramic stack allows for reusable packaging and the use of compressible spring contacts for easy sample exchange, which may enable good sample discovery at high throughput. [Means for solving the problem]

[0009] Proposed technical solutions and possible alternatives include ceramic-based multi-layer (possibly 30-50 layers) interposers with indium-based solder or spring contacts.

[0010] Accordingly, a first aspect of the present invention relates to a packaging structure for a superconducting quantum processing unit, the packaging structure comprising a ceramic support portion for supporting the quantum processing unit, the support portion including a plurality of electrical connections for connecting the quantum processing unit to a plurality of electrical contacts on an outer surface of the ceramic packing structure.

[0011] A second aspect of the invention relates to a packaged quantum processing unit comprising a packaging structure and a quantum processing unit.

[0012] The packaging structure may further include one or more sidewalls that surround the plurality of electrical connections in at least two dimensions, and a space enclosed by the one or more sidewalls may be configured to house the quantum processing unit. The one or more sidewalls may be formed from a ceramic material.

[0013] The packaging structure may further include a lid configured to enclose the plurality of electrical connections, such that the support portion, the one or more sidewalls, and the lid form a three-dimensional enclosed cavity configured to house the quantum processing unit. The lid may also be formed from a ceramic material. Alternatively, the lid may be formed from a metallic material.

[0014] One or more of the support portion, sidewall, and lid may be formed from a ceramic material that includes one or more layers or traces of superconducting material within or on a surface of the ceramic material. Thus, the ceramic material may include a layer of a superconducting metal. The ceramic material may be a low-temperature co-fired ceramic or a high-temperature co-fired ceramic.

[0015] The ceramic material, including one or more layers or traces of superconducting material, can shield the cavity from external electric and magnetic fields.

[0016] The packaging structure may further include one or more of activated carbon, a getter, and a molecular sieve.

[0017] The plurality of electrical connections on the support portion may extend over at least 50 mm in one direction.

[0018] The thermal expansion coefficient of the ceramic support portion may be within ±50% of the thermal expansion coefficient of silicon at 1K and 300K.

[0019] The cavity may be hermetically sealed, may be under vacuum, or may be filled with an inert gas.

[0020] The inert gas may be helium configured to form a superfluid when the packaged quantum processing unit is cryogenically cooled.

[0021] A third aspect of the present invention relates to a method of manufacturing a packaged quantum processing unit, the method comprising inserting the quantum processing unit into a packaging structure, the packaging structure comprising a ceramic support portion for supporting the quantum processing unit, and connecting the quantum processing unit to a plurality of electrical connections located on the support portion, the electrical connections configured to connect the quantum processing unit to a plurality of electrical contacts on an outer surface of the ceramic packing structure.

[0022] The packing structure may further comprise one or more sidewalls that surround the plurality of electrical connections in at least two dimensions, a space enclosed by the one or more sidewalls configured to house the quantum processing unit.

[0023] The method may further include enclosing the quantum processing unit in a packaging structure by sealing the enclosed space with a lid.

[0024] The lid and one or more sidewalls can form a hermetic seal around the quantum processing unit. Enclosing the quantum processing unit can be performed in a vacuum or inert gas environment, such as helium. [Brief explanation of the drawings]

[0025] [Figure 1] 1 shows a conventional method for manufacturing a ceramic functional layer. [Figure 2] 1 shows a schematic QPU or chip stack with an interposer layer made of superconducting material. [Figure 3] 1 shows a packaging structure for a superconducting quantum processing unit. [Figure 4] 4 shows a cross section of the packaging structure of FIG. 3. [Figure 5] 4 shows the underside of the packaging structure of FIG. 3. [Figure 6] A method for packaging a superconducting quantum processing unit is presented. DETAILED DESCRIPTION OF THE INVENTION

[0026] The present invention includes the general concept of utilizing ceramic materials as components within chips, such as superconducting chips containing at least one QPU, similar to conventional semiconductor chips on a printed circuit board. Because ceramic materials can be made superconducting as described above, they are particularly well suited as superconductors in quantum computers, for example, having quantum processing units (QPUs). In this context, "superconducting ceramic" means a ceramic material having one or more layers or traces of superconducting material within or on the surface of the ceramic material.

[0027] Essentially, ceramic materials can be made superconducting by including a suitable superconducting (metallic) material in their composition, for example, by incorporating the superconducting material into a slurry, coating an LTCC green base material or sheet, and fabricating a ceramic multilayer structure therefrom via conventional fabrication methods known in the art (see FIG. 1 ), for example, by incorporating a metallic material onto a green sheet in a slurry with a suitable binder, such as a polymer, and firing the resulting composition to provide a single body of superconducting ceramic material. This superconducting material may be, for example, aluminum-based or may contain niobium, molybdenum, or tungsten. The latter two may be particularly preferred due to their high melting points. Ceramic materials of such compositions, or even ceramic materials with a suitable metallic layer, provide low-loss routing structures within chip layers fabricated with this material, such as interposer layers within a chip stack. Superconducting ceramic materials are amorphous and substantially resonance-free. As an alternative to LTCC, high temperature co-fired ceramic (HTCC) can be used with metal pastes or slurries based on tungsten, molybdenum, niobium (eg, niobium nitride), and / or titanium (eg, titanium nitride).

[0028] The resulting superconducting ceramic material can be freely modified by machining it into a desired shape or structure, for example, with cavities, routing channels (either vertical or lateral), inlays, or any other suitable structure within, on, or through the material layer.

[0029] In one embodiment, niobium-based superconducting ceramic materials are used in a variety of superconducting applications. For example, they are fully compatible with any currently known flip-chip structure, and many more are envisioned. Aluminum nitrate is also a potential superconducting component that can be used. Printed circuit boards made from the superconducting ceramic material of the present invention can be used as a base layer for superconducting chip stacks containing a large number of qubits on the QPU layer, as the rigidity of the ceramic material allows for the fabrication of relatively large PCBs. In this way, it may be possible to fabricate QPU stacks containing more than 1,000 qubits.

[0030] Ceramic materials can be used as interposer layer(s) in a superconducting QPU stack (see Figure 2) to provide structural integrity to the stack, which includes the QPU and dielectric insulating layers on top of a printed circuit board (PCB). Signals and control lines carrying the necessary electrical components can be embedded or routed through ceramic interposer layer(s), which are bonded to the QPU chip layer, for example, by indium bumps, as known from state-of-the-art flip-chip QPUs. Similar to typical silicon chip layers, where through-silicon vias are utilized for this purpose, so-called through-vias can be used to route some electronic lines through the ceramic interposer layer according to the present invention without compromising the structural integrity of the ceramic interposer layer. The stack of different layers can then be pressed together to form a stacked superconductor element or chip by pressing the ceramic interposer layer instead of the fragile QPU or flip-chip layer. On PCTs, ardent connectors or equivalent can be used to direct the control lines to the outside of the chip stack. Thus, the stack can be aligned and pressed together to connect with the ardent connector pins without destroying structurally weaker portions or layers of the stack. The ceramic interposer layer can also be used to route signals via lines embedded laterally in the interposer layer. Thus, in essence, the ceramic interposer layer can be a functional structure rather than a mechanical structure.

[0031] Alternatively or additionally, the chip stack is a wiring stack with spring contact pins ("pogo pins" or "fuzz buttons") at one interface in the stack and indium or low-temperature solder contacts at another interface in the stack, and a ceramic layer is used to route electrical signals between the two interfaces.

[0032] The interposer stack is shown in Figure 2. From top to bottom, the components are: 1) the QPU chip ("QPU" in the sketch), 2) the first interposer ("IP"), which is a silicon chip with through-silicon vias and superconducting patterned metallization on both sides, 3) the ceramic wiring layer ("ceramic"), 4) the second interposer ("I.P2"), and 5) a conventional printed circuit board ("PCB"). Electrical contacts at the QPU-IP and ceramic-IP interfaces are realized as indium or low-temperature solder balls or bumps. Electrical contacts between the ceramic and PCB layers are realized as compressible springs embedded in IP2. The ceramic layer is pressed down (with a force F clamp) by a torus-shaped clamp (not shown).

[0033] Many variations are possible: the PCB layer can be replaced by a block where the coaxial wires terminate (similar to the Ardent TR interface); the compressible springs can be regular solder joints.

[0034] Superconducting ceramic materials may also be utilized in ceramic-based high-density microwave connector applications, for example, to direct signals from a room temperature environment to a cryostat or between different temperature zones of a cryostat.

[0035] Superconducting ceramic materials allow for a significant reduction in connector dimensions. For example, a connector dimensionally equivalent to an Ardent connector can implement hundreds of lines instead of the Ardent connector's 24. Figure 4 presents an exemplary structure of such a connector according to the present invention. This involves machining the above-described superconducting ceramic material into suitable shapes and sizes that allow for use in different multi-wire connector solutions. In one specific embodiment, commercially available nanoscale or picoscale coaxial cables are used to connect signal lines to the connector. Such cables can be arranged in a 50x50 or 100x100 lateral configuration, with the cables providing signal lines between different temperature zones of the cryostat to the QPU, and alternatively or additionally, providing signal lines between the cryostat and the room temperature environment. This significantly reduces the space occupied by wiring and cabling and also reduces the heat load from the signal lines.

[0036] The connector described above can be used as a cryogenic alternator between different temperature zones of a cryostat, allowing efficient delivery of signals through electrical lines realized through superconducting ceramic material based connectors.

[0037] Superconducting ceramic materials can also be used in feedthrough vacuum tight connectors or ultra-high vacuum coaxial high density microwave feedthroughs that provide control signals in and out of the cryostat.

[0038] Superconducting ceramic materials can also be utilized in the vacuum environmental control packaging of the QPU, as shown in Figures 5-7. For example, a suitable gas can be introduced into the cavity around the QPU to prevent oxidation and degradation of the QPU structure over time.

[0039] Such a package is exemplarily presented in Figure 3. Figure 4 is a cross-sectional view of the package shown in Figure 3. Figure 5 shows the underside of the package of Figures 5 and 6. Package 101 includes a support portion (base layer) 101 that is machined to create a suitable cavity for QPU 110 together with a lid (top layer) 103, and metal-coated or filled channels 104 for control lines to control the environment within the QPU cavity. Channels 104 are connected to electrical contacts 108 (shown in Figure 5) on the exterior surface of the package, forming an electrical (and optionally thermal) connection between the exterior and interior of package 100.

[0040] The QPU cavity is further defined by one or more sidewalls 102 that surround the electrical connections / channels 104 in at least two dimensions, i.e., if the surface of the support portion 101 on which the QPU 110 is supported defines an XY plane, then the sidewalls surround the cavity in at least the X and Y dimensions. The lid 103 surrounds the cavity in the Z direction. If the lid 103 and one or more sidewalls are integrally formed, then the cavity is also said to be surrounded in the Z dimension by the sidewall(s).

[0041] The space or cavity enclosed by the sidewall 102 and the lid 103 is configured to house the QPU 110. The sidewall 102, the lid 103, and the support portion 101 can form a hermetic seal around the cavity suitable for creating and supporting a vacuum. In this regard, the hermetic seal can be measured to measure a pressure of up to 1×10 psi in accordance with MIL-STD-750E Test Method 1071.9 or MIL-STD-883H Test Method 1014.13. -8 It can be defined as a seal that has a leak rate in cc / sec.

[0042] The sidewalls 102 and / or the lid 103 may also be formed of a superconducting ceramic material as described above with respect to FIG. 1. Thus, if the ceramic material is a superconducting ceramic material, the package 100 may provide a nearly completely isolated electromagnetic environment within the cavity. Alternatively, the sidewalls 102 and / or the lid 103 may be formed of a metallic material, which may form a Faraday shield around the cavity even if the metallic material is not superconducting to block high frequency electromagnetic fields.

[0043] The cavity may also be connectable to an ion pump, cryopump or other vacuum pump for creating and / or maintaining a vacuum within the cavity. Suitable channels 107 connecting the cavity to the vacuum pump are therefore provided in the support part 101 (as shown in FIG. 4 ) or in the side wall(s) 102 or the lid 103. Alternatively or additionally, a vacuum may be created within the cavity of the package 100 before sealing the cavity with the lid 103.

[0044] Alternatively, the cavity may be filled with an inert gas. The use of an inert gas in the cavity may allow for greater heat dissipation from the QPU and more uniform heat distribution within the cavity. In one example, the inert gas may be helium. The helium in the cavity forms a superfluid under the cryogenic conditions under which the QPU operates. As a superfluid, the helium in the cavity coats the interior walls of the QPU and cavity, allowing for excellent heat distribution and dissipation from the cavity.

[0045] The package 100 may include sorption elements 105, 106, such as one or more of an adsorption element (e.g., activated carbon, zeolite), an absorption element (e.g., palladium or palladium complex), and a molecular sieve for adsorbing harmful substances smaller than a certain molecular size. In this context, a "harmful" substance is one whose presence in the package results in a degradation of the performance of the QPU, for example, due to degraded qubit decoherence times. Additionally, control lines can be used to equalize the temperature within the package. The use of one or more sorption elements 105, 106 in the package also allows the vacuum within the cavity to be maintained for longer periods of time, despite the inevitable penetration of the cavity by small molecules.

[0046] Package 100 can also be used without sidewalls 102 or lid 103 as a tool for high-throughput testing of QPUs. In particular, the physical characteristics of ceramic support portion 101 allow clamps, such as the F-clamp shown in FIG. 2, to be used to apply significant force to the support portion (labeled "ceramic"), compressing temporary connectors, such as fuzz buttons, located in a land grid array on "IP2" against electrical connections on the underside of support portion 101. This is not possible with conventional silicon substrates because the force required to compress many, e.g., hundreds, of these temporary connections to form reliable electrical connections would cause the silicon to fracture. Therefore, using a ceramic material for support portion 101 allows a QPU located on support portion 101 to be quickly and easily inserted into and removed from a test environment.

[0047] The package 100 of the present invention is particularly effective in minimizing degradation of the QPU and its sensitive components, such as Josephson junctions. Exposure of the QPU to moisture and atmospheric gases, as well as repeated thermal cycling, degrades the QPU's performance, such as qubit coherence time. The package 100 protects the QPU from major contaminant sources, namely hydrogen, oxygen, and moisture. Furthermore, many ceramic materials have a thermal expansion coefficient (CTE) close to that of silicon, a common substrate used in superconducting quantum processing units, over the relevant temperature range, i.e., 0-300 K. This is important for large enclosures and large QPUs, e.g., those with connections between the QPU and the package support 101 that span at least 50 mm in at least one dimension, because the relative movement of contacts on the QPU and corresponding contacts on the support 101 under thermal cycling, i.e., temperature changes from room temperature to cryogenic temperatures, increases as the size of the QPU increases. Large relative movement between the QPU and the support leads to degradation and eventual failure of the electrical connections between the QPU and the support. In this context, a "closely matched" CTE means that the CTE of the ceramic material is ±50% of the CTE of silicon at 1K and 300K.

[0048] The present invention also includes a method for manufacturing a packaged quantum processing unit. Method 200 is shown in FIG.

[0049] In step 801, the quantum processing unit is inserted into a packaging structure that includes a ceramic support portion for supporting the quantum processing unit, for example as described above with respect to Figures 5-7.

[0050] In step 802, the quantum processing unit is connected to a plurality of electrical connections located on the support portion, such as electrical connection 104 shown in Figures 5-7. The electrical connections are configured to connect the quantum processing unit to a plurality of electrical contacts on the outer surface of the ceramic packing structure, such as electrical contact 107 shown in Figure 5.

[0051] 5-7, the packing structure can include one or more sidewalls that surround the electrical connections in at least two dimensions, and the space enclosed by the one or more sidewalls is configured to house the quantum processing unit.

[0052] In step 803, the quantum processing unit and open package structure are placed in a controlled environment, such as an inert gas environment or a vacuum.

[0053] In step 804, the quantum processing unit is enclosed within a packaging structure by sealing the enclosed space with a lid. The lid and one or more sidewalls may form an airtight seal around the quantum processing unit. Performing this step in a controlled environment ensures that the cavity enclosed by the sidewalls and lid is filled with an inert gas, such as helium, or is under vacuum.

Claims

1. A packaging structure (100) for a superconducting quantum processing unit (110), said packaging structure comprising: A packaging structure (100) comprising a ceramic support portion (101) for supporting a quantum processing unit, the support portion including a plurality of electrical connections (104) for connecting the quantum processing unit to a plurality of electrical contacts (108) on an outer surface of a ceramic packing structure.

2. A packaged quantum processing unit comprising the packaging structure (100) of claim 1 and a quantum processing unit (110).

3. The packaging structure (100) of claim 1 or the packaged quantum processing unit of claim 2 further comprises one or more side walls (102) surrounding the plurality of electrical connections in at least two dimensions, the space enclosed by the one or more side walls being configured to accommodate the quantum processing unit (110).

4. The packaging structure or packaged quantum processing unit of claim 3 , wherein the one or more sidewalls (102) are formed from a ceramic material.

5. 5. The packaging structure or packaged quantum processing unit of claim 3 or 4, further comprising a lid (103) configured to surround the plurality of electrical connections, whereby the support portion (101), one or more side walls (102), and the lid form a three-dimensionally enclosed cavity configured to accommodate the quantum processing unit.

6. 6. The packaging structure or packaged quantum processing unit of claim 5, wherein the lid (103) is made of a ceramic and / or metallic material.

7. 7. The packaging structure or packaged quantum processing unit of claims 4 and 6, wherein one or more of the support portion, sidewalls, and lid are formed from a ceramic material that includes one or more layers or traces of superconducting material within or on a surface of the ceramic material.

8. 8. The packaging structure or packaged quantum processing unit of claim 7, wherein the ceramic material comprises a layer of superconducting metal.

9. 9. The packaging structure or packaged quantum processing unit of claim 8, wherein the ceramic material is a low-temperature co-fired ceramic or a high-temperature co-fired ceramic.

10. 10. A packaging structure or packaged quantum processing unit according to any one of claims 7 to 9, wherein the ceramic material shields the cavity from external electric and magnetic fields.

11. 10. The packaging structure or packaged quantum processing unit of any one of the preceding claims, wherein the packaging structure (100) further comprises one or more of activated carbon, a getter, and a molecular sieve.

12. 10. A packaging structure or a packaged quantum processing unit according to any one of the preceding claims, wherein the plurality of electrical connections of the support portion extend over at least 50 mm in one direction.

13. 10. A packaging structure or a packaged quantum processing unit according to any one of the preceding claims, wherein the thermal expansion coefficient of the ceramic support part is within ±50% of the thermal expansion coefficient of silicon at 1K and 300K.

14. 10. A packaged quantum processing unit according to any one of the preceding claims, wherein the cavity is hermetically sealed.

15. 15. The packaged quantum processing unit of claim 14, wherein the cavity is under vacuum.

16. 16. The packaged quantum processing unit of claim 15, wherein the cavity is filled with an inert gas.

17. 17. The packaged quantum processing unit of claim 16, wherein the inert gas is helium, the helium configured to form a superfluid when the packaged quantum processing unit is cryogenically cooled.

18. 1. A method of manufacturing a packaged quantum processing unit, the method comprising: inserting a quantum processing unit into a packaging structure, the packaging structure comprising a ceramic support portion for supporting the quantum processing unit; connecting the quantum processing unit to a plurality of electrical connections located on the support portion, the electrical connections configured to connect the quantum processing unit to a plurality of electrical contacts on an outer surface of a ceramic packing structure.

19. 20. The method of claim 18, wherein the packing structure further comprises one or more sidewalls that surround the plurality of electrical connections in at least two dimensions, a space enclosed by the one or more sidewalls configured to accommodate the quantum processing unit.

20. 20. The method of claim 19, further comprising enclosing the quantum processing unit within the packaging structure by sealing the enclosed space with a lid.

21. 21. The method of claim 20, wherein the lid and one or more sidewalls form a hermetic seal around the quantum processing unit.

22. 22. The method of claim 21, wherein surrounding the quantum processing unit is performed in a vacuum or inert gas environment.

23. 23. The method of claim 22, wherein the inert gas is helium.

Images