Matching Table System
The matching table system optimizes cache management in network switches by prioritizing entry frequencies using a bidirectional linked list, enhancing cache hit rates and throughput efficiency.
Patent Information
- Application Number
- JP2025533598
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2022-12-13
- Filing Date
- 2022-12-19
- Publication Date
- 2025-11-28
AI Technical Summary
Existing cache replacement policies for FPGAs in network switches do not consider entry priority effectively, leading to reduced cache hit rates and increased hardware overhead, particularly due to the use of complex algorithms and limited memory resources.
A matching table system with a cache module and controller that maintains the matching table cache based on a bidirectional circular linked list, using a FIFO unit, multiplexer, and control unit to manage entry frequencies and prioritize cache updates, reducing hardware overhead and improving network throughput.
The system accelerates flow table matching and improves network throughput by efficiently managing cache entries, maintaining high cache hit rates with reduced complexity and hardware overhead, while being versatile and scalable.
Smart Images
Figure 2025538806000001_ABST
Abstract
Description
[Technical Field]
[0001] [Related Applications] This application claims priority from Chinese Patent Application No. 202211594603.X, entitled "Matching Table System," filed on December 13, 2022, the entire contents of which are incorporated herein by reference. The present invention relates to the field of network communication, and more particularly to a matching table system, which is applied to a network switch device in a software-defined network (SDN). [Background technology]
[0002] With the rapid development of Internet technology, CPU computing performance, communication bandwidth, and storage capacity are constantly being optimized and improved, and the shortcomings of the tight coupling of the control plane and data plane of traditional network architecture are becoming increasingly apparent, which to some extent affects the scalability and migration of networks. Therefore, software-defined network architecture is rapidly developing due to its characteristic of separating the control plane and data plane. In software-defined network architecture, the control plane grasps the global topology and realizes forwarding policy customization by issuing flow tables, and the data plane stores the flow tables and is responsible for high-speed matching and forwarding of network traffic, which is advantageous in solving the existing problems of traditional network architecture.
[0003] FPGAs (Field Programmable Gate Arrays) are often used to process network traffic with increasing data plane exponents. They have features such as high concurrency, high throughput, programmability, low development costs, and fast cycle times, making them suitable for data plane flow matching and offloading forwarding. They can use internal logic and memory resources to build a Match-Action model to achieve line speed matching and forwarding of network traffic.
[0004] Due to the limited memory resources of FPGAs, on-chip storage can only store a small number of frequently used flow tables by constructing a matching table cache, while other large number of infrequently used flow tables must be stored in off-chip storage. The relatively high memory access latency creates a bottleneck that limits network throughput. Therefore, interconnecting the on-chip matching table cache with the off-chip matching table and maintaining the on-chip matching table cache with an efficient cache replacement policy is key to accelerating matching and improving network throughput. Currently, cache replacement policies can be divided into four types: random replacement, first-in-first-out replacement, least recently used replacement, and least recently used replacement. The random replacement policy replaces entries in the cache based on the generated random number, while the first-in-first-out replacement policy always replaces the entry that entered the cache first. Both policies do not consider the priority of entries and will reduce the cache hit rate to some extent. The least frequently used replacement policy is to always replace the entry with the fewest hits, and the least recently used replacement policy is to always replace the entry that has not been hit for the longest time, both of which take into account the priority of the entries, but existing solutions require customized counters and sorting algorithms, and their time complexity scales with cache depth, resulting in increasing hardware overhead as the cache depth increases. Summary of the Invention [Problem to be solved by the invention]
[0005] The present invention aims to overcome the defects of the prior art in that entry priority is not taken into consideration when replacing a cache, or when entry priority is taken into consideration, the algorithm is complicated and hardware overhead is large. [Means for solving the problem]
[0006] In order to achieve the above object, the present invention provides a matching table system, the system including: a cache module and a matching table; The cache module is implemented based on an FPGA, and the cache module includes a matching table cache and a matching table cache controller; the matching table cache controller is connected to the matching table cache and the matching table, for maintaining the matching table cache and realizing transfer of the matching table entries to the matching table cache; The matching table transfers the matching key-value pair (KeyValuePair) and the matching result to the matching table cache controller; The match table cache transfers the index of the hit entry and the matching result to the match table cache controller; The match table cache controller transfers matching key-value pairs to the match table cache.
[0007] As an improvement to the above system, the matching table cache controller updates and maintains the frequency of use of the matching table cache based on a cache replacement algorithm, specifically: When the matching table cache controller receives the matching key-value pair and the matching result transferred by the matching table, it writes the matching key-value pair into the matching table cache, and if the matching table cache has a free space, it writes the matching key-value pair into the free space, and if the matching table cache is full, it replaces the least frequently used entry and updates the cache. When the matching table cache controller receives the index of the hit entry and the matching result transferred by the matching table cache, it changes the usage frequency of the hit entry to maintain the usage frequency.
[0008] As an improvement to the above system, the matching table cache controller comprises a FIFO (First In First Out) unit, a multiplexer, a control unit and a frequency of use memory; the FIFO unit includes a two-channel synchronous FIFO (First In First Out) buffer, for buffering valid data transferred by the matching table and the matching table cache, respectively, and adding sideband information to indicate a data source; The multiplexer is for merging data of two channels in the FIFO unit, and adopts a matching table priority policy; the control unit is for processing the data output from the multiplexer, and if the data is from the match table, writes a matching key-value pair to a match table cache, and if the data is from the match table cache, modifies the frequency of use of an entry in a frequency of use memory; The usage frequency memory is for storing the usage frequency of entries in the match table cache.
[0009] As an improvement to the above system, the usage frequency memory stores the usage frequency of the matching table cache entries based on the principle of a bidirectional circular linked list, is constructed using a block random memory with true dual port read-first mode reading, and includes two ports, port A and port B; The frequency of use memory sorts and manages all entries in the matching table cache based on a time axis, and its depth is the same as the depth of the matching table cache; Each storage unit in the frequency of use memory stores a predecessor entry address and a successor entry address of the same address entry in the matching table cache, the predecessor entry address is stored in the upper part of the storage unit and the successor entry address is stored in the lower part; The control unit maintains head / tail pointers of a bidirectional circular linked list, with the head pointer pointing to the least recently used entry, i.e., the entry that has not been hit in the longest time, and the tail pointer pointing to the most recently used entry, i.e., the entry that has just been hit.
[0010] As an improvement to the system described above, the control unit is responsible for receiving the requests output by the multiplexer and is connected to the frequency of use memory, When the matching table cache controller receives a request for the matching table or the matching table cache, it buffers both using the FIFO (First In First Out) unit, merges them using the multiplexer, and then transfers them to the control unit for processing. The control unit outputs matching key-value pairs to the matching table cache, moves the head / tail pointers, and reads and writes the usage frequency memory to change the structure of the bidirectional circular linked list, thereby updating the cache and maintaining the usage frequency, thereby accelerating matching.
[0011] As an improvement to the above system, the operation process of the control unit includes an initialization process, a cache update process, and a cache usage frequency maintenance process.
[0012] As an improvement to the above system, the control unit is constructed based on a finite state automaton and includes an initialization state, a request waiting state, a cache update state, and a cache frequency maintenance state; When the control unit is started, the control unit is in an initialization state, and triggers an initialization process by the control unit to complete the initialization of the frequency of use memory and head / tail pointers, and then transitions to a request waiting state to wait for a hit request; When the control unit receives a hit request from the matching table or the matching table cache, it processes it respectively according to the hit source; when the sideband information indicates that the hit request is from the matching table, it jumps to a cache update state to trigger a cache update process; when the sideband information indicates that the hit request is from the matching table cache, it jumps to a cache usage frequency maintenance state to trigger a cache usage frequency maintenance process; The control unit completes the cache update process or cache popularity maintenance process before returning to a request waiting state to wait for the next request.
[0013] As an improvement to the above system, the initialization process by the control unit includes initializing the frequency of use memory in address order, inputting the predecessor entry address and successor entry address of each entry in sequence, connecting the head and tail to form a bidirectional circular linked list, and the head / tail pointers point to the head and tail of the bidirectional circular linked list respectively, and at this point the matching table cache is empty.
[0014] As an improvement to the above system, the cache update process by the control unit comprises: When the match table is hit, initiating a hit request to the match table cache controller, transferring the matching key-value pair and the matching result, and triggering a cache update process by the control unit; When the matching table cache is not full, the matching key-value pair is written into an empty space in the matching table cache, and the added entry's frequency of use is changed to the most frequently used entry; when the matching table cache is full, the matching key-value pair replaces the least frequently used entry, and the added entry's frequency of use is changed to the most frequently used entry; and the specific operations are as follows: Step A1: writing a matching key-value pair into the matching table cache using a head pointer value as a write address; Step A2: updating a tail pointer value to a head pointer value, and initiating a read request to port A of the frequency-of-use memory, the read address of which is the head pointer value, and if the matching table cache is not full, the operation is for obtaining the next free or least frequently used entry address, and if the matching table cache is full, the operation is for obtaining the next least frequently used entry address; Step A3 includes reading the address of the successor entry of the entry pointed to by the head pointer and changing the value of the head pointer to that address, i.e., moving the head pointer until it points to the successor entry of the pointed entry.
[0015] As an improvement to the above system, the process of maintaining the cache frequency by the control unit comprises: a process for maintaining a frequency of use of said cache may be triggered when said match table cache is either full or not full; When the match table cache is hit, initiating a hit request to the match table cache controller, transferring the index of the hit entry and the matching result, and triggering a process of maintaining the cache frequency by the control unit; The cache usage frequency maintenance process performs the following in accordance with the relationship between the index value of the hit entry and the head pointer value and the tail pointer value: The index value of the hit entry is the same as the tail pointer value, i.e., the most frequently used entry in the matching table cache is hit. The second situation is that the index value of the hit entry is the same as the head pointer value, i.e., the least recently used entry in the matching table cache is hit; and The index value of the hit entry is divided into three situations: neither the head pointer value nor the tail pointer value is the same, i.e., an intermediate entry in the linked list is hit; and the third situation is when the hit entry is not the same as the head pointer value or the tail pointer value.
[0016] An improvement to the above system includes that in the process of processing the first situation, there is no need to change the frequency of use, and the control unit does not process and waits for the next match.
[0017] An improvement to the above system includes, in the process of handling the second situation, moving the tail pointer until the hit entry is marked as the most recently used entry, and moving the head pointer until it points to the next least recently used entry, without changing the structure of the linked list; The specific operations are: Step B1: change the value of the tail pointer to the value of the head pointer, and initiate a read request to port A of the frequency-of-use memory, and the read address is the value of the head pointer, i.e., obtain the next least frequently used entry address; Step B2 includes reading the successor entry address of the entry pointed to by the head pointer and changing the head pointer value to that address, i.e., moving the head pointer until it points to the next least frequently used entry.
[0018] As an improvement to the above system, the specific operations in the third situation processing process are as follows: Step C1: initiate a read request to port A of the frequency-of-use memory, and the read address is the index value of the hit entry, i.e., obtain the predecessor entry address and successor entry address of the hit entry; Step C2: if a response to the read request is received, a write request is initiated to port A and port B of the frequency of use memory, the write address of port A is the predecessor entry address of the hit entry, the write data is the successor entry address of the hit entry, with zeros at the upper end, and the byte enable signal indicates that the lower end of the write data is valid, the write address of port B is the successor entry address of the hit entry, the write data is the predecessor entry address of the hit entry, with zeros at the lower end, and the byte enable signal indicates that the upper end of the write data is valid, this operation is for the purpose of deleting the hit entry and establishing its predecessor and successor bidirectional logic; When the write request is completed, a write request is initiated again to ports A and B of the frequency of use memory, the write address of port A is the tail pointer value, the write data is the index value of the hit entry, with zeros padded at the upper part, and the byte enable signal indicates that the lower part of the write data is valid, the write address of port B is the head pointer value, the write data is the index value of the hit entry, with zeros padded at the lower part, and the byte enable signal indicates that the upper part of the write data is valid, with the purpose of this operation being to insert the hit entry between the entries pointed to by the head / tail pointers; step C3; When a write request is made, a write request is initiated to port A of the frequency-of-use memory, the write address is the index value of the hit entry, the write data is a combination of the tail pointer value and the head pointer value, the tail pointer is located at the upper position, the head pointer is located at the lower position, and the byte enable signal indicates that both the upper and lower positions of the write data are valid, and the operation is intended to establish a bidirectional logic between the hit entry and the entry pointed to by the head / tail pointer; step C4; and step C5 of changing the value of the tail pointer to the value of the index of the hit entry, thereby marking the hit entry as the most frequently used.
[0019] As an improvement to the above system, the matching table cache controller further comprises readable and writable control and status registers; the control register is for controlling the operation of the matching table cache controller; The status register is used to inquire about the matching table, the number of times valid data is transferred by the matching table cache, the number of times the matching table cache controller updates the cache or maintains its usage frequency, and its operating status. [Effects of the Invention]
[0020] Compared with the prior art, the advantages of the present invention are as follows:
[0021] (1) The present invention constructs a matching table cache controller and a matching table cache using hardware, and maintains the matching table cache based on, but not limited to, an LRU cache replacement algorithm, transferring matching table entries to the matching table cache, thereby achieving the purpose of accelerating flow table matching and improving network throughput.
[0022] (2) The present invention uses a common interface to accommodate multiple types of matching tables, has relatively high versatility and scalability, and allows users to meet their needs by changing the interface. It is also easy to extend to a matching acceleration scheme for transferring multiple levels of matching tables to a matching table cache.
[0023] (3) The present invention provides control and status registers that can be read and written by the host computer, allowing the host computer to control the functions and query the status of the matching table cache controller. [Brief explanation of the drawings]
[0024] [Figure 1] FIG. 1 is a structural diagram of a matching table system. [Figure 2] FIG. 2 is a block diagram showing the structure of the matching table cache controller. [Figure 3] FIG. 3 is a schematic diagram showing the data structure of the usage frequency of entries in the usage frequency memory. [Figure 4] FIG. 4 is a schematic diagram of the initial state of the usage frequency memory. [Figure 5] FIG. 5 is a schematic diagram illustrating changes to the frequency memory due to the cache update process. [Figure 6] FIG. 6 is a schematic diagram illustrating changes to the frequency memory caused by the cache frequency maintenance process. [Figure 7] FIG. 7 is a diagram showing state transitions of the control unit. DETAILED DESCRIPTION OF THE INVENTION
[0025] The present invention provides a matching table system, and relates to a matching table, a matching table cache, and a matching table cache controller. The matching table is a large-capacity and accurate matching flow table realized based on off-chip storage, and based on this, a matching table cache and a matching table cache controller are added. The matching table cache is an accurate matching flow table realized based on on-chip storage at line speed, and the matching table cache controller is connected to the matching table cache and the matching table, maintains the matching table cache, and realizes the transfer of matching table entries to the matching table cache, thereby accelerating flow table matching and improving network throughput.
[0026] The technical solution of the present invention will be described in detail below with reference to the drawings.
[0027] As shown in FIG. 1, the matching table is connected to the matching table cache controller and transfers the matching key-value pairs and the matching results, the matching table cache is connected to the matching table cache controller and transfers the index of the hit entry and the matching results, and the matching table cache controller is connected to the matching table cache and transfers the matching key-value pairs.
[0028] The matching table cache controller updates the matching table cache and maintains its usage frequency based on a least recently used (LRU) cache replacement algorithm, but is not limited to this, and further accelerates matching. When the matching table cache controller receives a matching key-value pair and a matching result transferred from the matching table, it writes the matching key-value pair to the matching table cache, and if the matching table cache has space, it writes it to the space, and if the matching table cache is full, it replaces the least frequently used entry and updates the cache. When the matching table cache controller receives the index of the hit entry and the matching result transferred from the matching table cache, it changes the usage frequency of the hit entry to maintain its usage frequency.
[0029] The matching table cache controller includes a FIFO (First In First Out) unit, a multiplexer, a control unit and a frequency of use memory.
[0030] The FIFO unit includes two channels of synchronous first-in-first-out buffers for buffering valid data transferred by the match table and match table cache, respectively, and adding sideband information to indicate the data source.
[0031] The multiplexer merges the data from the two channels and adopts a matching table priority policy.
[0032] The usage frequency memory stores the usage frequency of entries in the match table cache.
[0033] The control unit is the core module of the matching table cache controller, and processes the data output from the multiplexer, and if the data is from the matching table, writes a matching key-value pair to the matching table cache, and if the data is from the matching table cache, changes the frequency of use of the entry in the frequency of use memory.
[0034] The matching table cache controller also provides the host computer with readable and writable control and status registers, the control register for controlling the operation of the matching table cache controller, and the status register for querying the matching table, the number of valid data transfers by the matching table cache, the number of times the matching table cache controller updates the cache or maintains its usage frequency, and its operating status.
[0035] The matching table system according to the present invention is implemented based on FPGA in an embodiment, and the matching table cache controller and the matching table cache are constructed using on-chip resources and connected to an off-chip matching table.
[0036] This embodiment maintains the matching table cache based on, but not limited to, an LRU cache replacement algorithm, thereby realizing the transfer of matching table entries to the matching table cache, accelerating flow table matching and improving network throughput. The matching table cache controller includes a FIFO (First In First Out) unit, a multiplexer, a control unit and a usage frequency memory, and further includes control and status registers that can be read and written by the host computer.
[0037] The operating principle of the matching table system is as follows.
[0038] The matching table or matching table cache initiates a request after completing packet matching. If the matching table is hit, it transfers the matching key-value pair and the matching result. If the matching table cache is hit, it transfers the index of the hit entry and the matching result. The matching table cache controller receives and processes the two-channel requests. Inside the matching table cache controller, the two-channel requests first arrive at a FIFO unit, which includes a two-channel synchronous first-in-first-out buffer, buffers valid and hit requests in a cyclic buffer mode, and adds sideband information to indicate the request source, and then outputs them to a multiplexer. The multiplexer adopts a matching table priority policy, and when two-channel requests are valid at the same time, it prioritizes and outputs the matching table request; otherwise, it selectively outputs them according to whether they are valid. The control unit then receives the output of the multiplexer, distinguishes the request source based on the sideband information, and if it is from the matching table, writes the matching key-value pair to the matching table cache, updating the cache; and if it is from the matching table cache, changes the usage frequency of the entry in the usage frequency memory, maintaining the usage frequency.
[0039] The operation principle of the embodiment will be described in detail below with reference to the data structure of the frequency of use of entries in the frequency of use memory of the present invention and the operation process of the control unit.
[0040] The usage frequency memory stores the usage frequency of matching table cache entries based on the principle of a bidirectional circular linked list. It is constructed using block random memory with true dual-port read-first mode and two ports, Port A and Port B. It performs precise sorting and fine-grained management of all entries in the matching table cache based on the time axis. Its depth is the same as the depth of the matching table cache. Each storage unit stores the predecessor entry address and successor entry address of the same address entry in the matching table cache, with the predecessor stored at the top and the successor stored at the bottom. The control unit maintains head and tail pointers for the bidirectional circular linked list. The head pointer points to the least frequently used entry, i.e., the entry that has not been hit for the longest time, and the tail pointer points to the most frequently used entry, i.e., the entry immediately following a hit. Figure 3 is a schematic diagram showing the data structure of the usage frequency of entries in the usage frequency memory.
[0041] The control unit is the core module of the matching table cache controller, implemented using a finite-state automaton. It is responsible for receiving requests output from the multiplexer and is connected to the usage frequency memory. When the matching table cache controller receives a request for the matching table or matching table cache, it buffers both using a FIFO unit, merges them using a multiplexer, and then forwards them to the control unit for processing. The control unit outputs matching key-value pairs to the matching table cache, moves the head / tail pointer, and reads and writes the usage frequency memory to change the structure of the bidirectional circular linked list, thereby updating the cache and maintaining the usage frequency, thereby accelerating matching. The operation processes of the control unit include an initialization process, a cache update process, and a cache usage frequency maintenance process.
[0042] In the initialization process, the control unit initializes the frequency of use memory in address order during initialization, sequentially inputs the predecessor entry address and successor entry address of each entry, and interconnects the beginning and end to form a bidirectional circular linked list, with the head and tail pointers pointing to the head and tail of the bidirectional circular linked list, respectively, and the matching table cache is empty. This process involves one memory initialization operation.
[0043] FIG. 4 is a schematic diagram showing the initial state of an 8-deep usage frequency memory.
[0044] In the cache update process, when the matching table is hit, a hit request is initiated to the matching table cache controller, and the matching key-value pair and the matching result are transferred, and the control unit triggers the cache update process. If the matching table cache is not full, the matching key-value pair is written to an empty location in the matching table cache, and the frequency of use of the added entry is changed to the most frequently used entry. If the matching table cache is full, the matching key-value pair replaces the least frequently used entry, and the frequency of use of the added entry is changed to the most frequently used entry. The specific operation includes the following steps:
[0045] Step (1) Use the value of the head pointer as the write address and write the matching key-value pair to the matching table cache. Step (2) updates the tail pointer value to the head pointer value, and initiates a read request to the frequently used memory port A, where the read address is the value of the head pointer. If the matching table cache is not full, the operation aims to obtain the next empty or least frequently used entry address; if the matching table cache is full, the operation aims to obtain the next least frequently used entry address; Step (3) The address of the successor entry of the entry pointed to by the head pointer is read and the value of the head pointer is changed to that address, that is, the head pointer is moved until it points to the successor entry of the entry pointed to.
[0046] This process involves a total of one single-port memory read operation, which only moves the head / tail pointers and does not change the structure of the linked list, reducing unnecessary processing delays. Figure 5 is a schematic diagram of a cache update occurring in an 8-deep frequently used memory table.
[0047] Regarding the cache usage frequency maintenance process, the process can be triggered whether the matching table cache is full or not. When the matching table cache is hit, a hit request is initiated to the matching table cache controller, and the index of the hit entry and the matching result are transferred, and the cache usage frequency maintenance process by the control unit is triggered. According to the index of the hit entry, the following three situations can be distinguished:
[0048] In the first situation, the index value of the hit entry is the same as the tail pointer value, i.e., the most frequently used entry in the matching table cache is hit. The processing logic for this situation is the simplest, as there is no need to change the frequency of use, and the control unit does not process it and waits for the next match, reducing unnecessary processing delays.
[0049] In the second situation, the index value of the hit entry is the same as the value of the head pointer, that is, the least recently used entry in the matching table cache is hit. In this situation, the tail pointer is moved until it points to the hit entry marked as the most recently used entry, and then the head pointer is moved until it points to the next least recently used entry, without changing the structure of the linked list. The specific operation is as follows: Step (1) of changing the value of the tail pointer to the value of the head pointer, initiating a read request to port A of the frequency memory, and obtaining the read address that is the value of the head pointer, i.e., the next least frequently used entry address; and (2) reading the successor entry address of the entry pointed to by the head pointer and changing the value of the head pointer to that address, i.e., moving the head pointer until it points to the next least frequently used entry.
[0050] In this situation, the process involves a total of one single-port memory read operation.
[0051] The third situation is that the index values of the hit entries are not all the same as the head / tail pointer values, that is, the middle entry in the linked list is hit. In this situation, the control unit needs to perform two operations, namely, entry deletion and entry insertion, to maintain the usage frequency. The specific operations include the following steps:
[0052] Step (1) initiate a read request to port A of the frequency-of-use memory, and obtain the read address as the index value of the hit entry, i.e., the predecessor entry address and the successor entry address of the hit entry; Step (2) When a read request response is received, a write request is initiated to ports A and B of the frequency of use memory, the write address of port A is the predecessor entry address of the hit entry, the write data is the successor entry address of the hit entry, with zeros padded to the upper part, and the byte enable signal indicates that the lower part of the write data is valid; the write address of port B is the successor entry address of the hit entry, the write data is the predecessor entry address of the hit entry, with zeros padded to the lower part, and the byte enable signal indicates that the upper part of the write data is valid. The purpose of this operation is to delete the hit entry and establish its predecessor and successor bidirectional logic, Step (3) When the write request is completed, a write request is initiated again to ports A and B of the frequency of use memory, the write address of port A is the value of the tail pointer, the write data is the value of the index of the hit entry, with zeros padded to the upper part, and the byte enable signal indicates that the lower part of the write data is valid. The write address of port B is the value of the head pointer, the write data is the value of the index of the hit entry, with zeros padded to the lower part, and the byte enable signal indicates that the upper part of the write data is valid. The purpose of this operation is to insert the hit entry between the entries pointed to by the head / tail pointers, Step (4) After the write request is completed, a write request is initiated to port A of the frequency memory, the write address is the index value of the hit entry, the write data is a combination of the tail pointer value and the head pointer value, the tail pointer is located at the upper position, the head pointer is located at the lower position, and the byte enable signal indicates that both the upper and lower positions of the write data are valid. This operation is intended to establish a bidirectional logic between the hit entry and the entry pointed to by the head / tail pointer. Step (5) Change the value of the tail pointer to the index value of the hit entry, and mark the hit entry as the most frequently used.
[0053] In this situation, the process includes a total of one single-port memory read operation, two dual-port memory write operations, and one single-port memory write operation. Figure 6 is a schematic diagram showing how frequency maintenance occurs in the frequency memory after the third entry is hit in the eight-deep matching table cache.
[0054] The control unit is constructed based on a finite-state automaton and includes an initialization state, a request waiting state, a cache update state, and a cache usage frequency maintenance state. The initialization state triggers the control unit to initialize the usage frequency memory and head / tail pointers, and then enters the request waiting state to wait for a hit request. When the control unit receives a hit request from the matching table or matching table cache, it processes it based on the source of the hit. If the sideband information indicates that the hit request is from the matching table, it jumps to the cache update state to trigger the cache update process. If the sideband information indicates that the hit request is from the matching table cache, it jumps to the cache usage frequency maintenance state to trigger the cache usage frequency maintenance process. The control unit updates the matching table cache and maintains the usage frequency based on the above operating principles, realizes matching acceleration, and finally returns to the request waiting state to wait for the next request.
[0055] FIG. 7 is a diagram showing state transitions of the control unit.
[0056] In an embodiment of the present invention, an FPGA is used, and a matching table cache controller and a matching table cache are built based on on-chip resources and connected to the matching table. By performing the above steps, cache maintenance based on an LRU algorithm is realized, but is not limited to this, to achieve the purpose of accelerating matching. The LRU algorithm in the embodiment is implemented using a bidirectional circular linked list, and has a time complexity of O(1). Regardless of the depth and state of the matching table cache, it has less hardware overhead than counter and sorting algorithm solutions and lower matching delay than solutions using a unidirectional linked list and a bidirectional acyclic linked list. In addition, the present invention is relatively versatile and scalable, adaptable to multiple types of matching tables, and easily expandable to a matching acceleration scheme that transfers multiple levels of matching table entries to the matching table cache.
[0057] Finally, it should be noted that the above embodiments are only for illustrating the technical solution of the present invention, and are not intended to limit the same. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that any modifications or equivalent replacements made to the technical solution of the present invention do not deviate from the spirit and scope of the technical solution of the present invention, and should all be included in the scope of the claims of the present invention.
Claims
1. A matching table system including a cache module and a matching table, The cache module is implemented based on an FPGA, and the cache module includes a matching table cache and a matching table cache controller; the matching table cache controller is connected to the matching table cache and the matching table, and maintains the matching table cache to realize transfer of the matching table entries to the matching table cache; The match table transfers the matching key-value pairs and the matching results to the match table cache controller; The match table cache transfers the index of the hit entry and the matching result to the match table cache controller; The matching table system is characterized in that the matching table cache controller transfers matching key-value pairs to the matching table cache.
2. The matching table cache controller updates the matching table cache and maintains the frequency of use according to a cache replacement algorithm, and specifically: the matching table cache controller, when receiving the matching key-value pair and the matching result transferred by the matching table, writes the matching key-value pair into the matching table cache, and when there is space in the matching table cache, writes the matching key-value pair into the space, and when the matching table cache is full, replaces the least frequently used entry and updates the cache; The matching table system of claim 1, further comprising: when the matching table cache controller receives the index of the hit entry and the matching result transferred by the matching table cache, changing the usage frequency of the hit entry to maintain the usage frequency.
3. The matching table cache controller includes a FIFO (First In First Out) unit, a multiplexer, a control unit, and a usage frequency memory; the FIFO unit includes a two-channel synchronous first-in-first-out buffer, which buffers valid data transferred by the matching table and the matching table cache, respectively, and adds sideband information to indicate a data source; The multiplexer performs merging of data of two channels in the FIFO unit and adopts a matching table priority policy; the control unit processes the data output from the multiplexer, and if the data is from the match table, writes a matching key-value pair to a match table cache, and if the data is from the match table cache, modifies the frequency of use of the entry in the frequency of use memory; 3. The matching table system of claim 2, wherein the usage frequency memory stores the usage frequency of entries in the matching table cache.
4. The frequency of use memory stores the frequency of use of matching table cache entries based on the principle of a bidirectional circular linked list, is constructed using a block random memory with a read true dual port and read priority mode, and includes two ports, port A and port B; The frequency of use memory sorts and manages all entries in the matching table cache based on a time axis, and has a depth equal to the depth of the matching table cache; Each storage unit in the frequency of use memory stores a predecessor entry address and a successor entry address of the same address entry in the matching table cache, the predecessor entry address is stored in the upper part of the storage unit and the successor entry address is stored in the lower part; 4. The matching table system of claim 3, wherein the control unit maintains head / tail pointers of a bidirectional circular linked list, the head pointer pointing to the least frequently used entry, i.e., the entry that has not been hit for the longest time, and the tail pointer pointing to the most frequently used entry, i.e., the entry immediately after being hit.
5. the control unit is responsible for receiving the requests output from the multiplexer and is connected to the frequency-of-use memory; The matching table system of claim 4, characterized in that when the matching table cache controller receives a request for the matching table or the matching table cache, it buffers both using the FIFO unit, merges them using the multiplexer, and then transfers them to the control unit for processing, and the control unit outputs matching key-value pairs to the matching table cache, moves head / tail pointers, and reads and writes the usage frequency memory to change the structure of the bidirectional circular linked list, thereby updating the cache and maintaining usage frequency and accelerating matching.
6. 6. The matching table system according to claim 5, wherein the operation processes of the control unit include an initialization process, a cache update process, and a cache usage frequency maintenance process.
7. The control unit is constructed based on a finite state automaton and includes an initialization state, a request waiting state, a cache update state, and a cache frequency maintenance state; The control unit is in an initialization state when it is started up, and triggers an initialization process by the control unit to complete the initialization of the frequency of use memory and head / tail pointers, and then enters a request waiting state to wait for a hit request; When the control unit receives a hit request from the matching table or the matching table cache, it processes it based on the hit source, and when the sideband information indicates that the hit request is from the matching table, it jumps to a cache update state to trigger a cache update process, and when the sideband information indicates that the hit request is from the matching table cache, it jumps to a cache usage frequency maintenance state to trigger a cache usage frequency maintenance process; 7. The matching table system of claim 6, wherein the control unit returns to a request waiting state to wait for the next request after completing the cache update process or the cache frequency maintenance process.
8. 7. The matching table system of claim 6, wherein the initialization process by the control unit includes initializing the frequency of use memory in address order, sequentially inputting the predecessor entry address and successor entry address of each entry, linking the beginning and end to form a bidirectional circular linked list, with head / tail pointers pointing to the head and tail of the bidirectional circular linked list, respectively, and the matching table cache being empty at this time.
9. The cache update process by the control unit includes: When the match table is hit, initiating a hit request to the match table cache controller, transferring the matching key-value pair and the matching result, and triggering a cache update process by the control unit; When the matching table cache is not full, the matching key-value pair is written into an empty space in the matching table cache, and the added entry's frequency of use is changed to the most frequently used entry; when the matching table cache is full, the matching key-value pair replaces the least frequently used entry, and the added entry's frequency of use is changed to the most frequently used entry; and the specific operations are as follows: Step A1: writing a matching key-value pair into the matching table cache using a value of a head pointer as a write address; Step A2: changing the value of the tail pointer to the value of the head pointer, and initiating a read request to the frequently used memory port A, the read address being the value of the head pointer, and if the matching table cache is not full, the operation is for obtaining the next free or least frequently used entry address, and if the matching table cache is full, the operation is for obtaining the next least frequently used entry address; A matching table system as described in claim 6, characterized in that it includes step A3 of reading the successor entry address of the entry pointed to by the head pointer and changing the value of the head pointer to that address, i.e., moving the head pointer until it points to the successor entry of the entry pointed to.
10. The cache frequency maintenance process by the control unit includes: The cache frequency maintenance process may be triggered when the matching table cache is full or not full; When the match table cache is hit, initiating a hit request to the match table cache controller, transferring the index of the hit entry and the matching result, and triggering the cache usage frequency maintenance process by the control unit; The cache usage frequency maintenance process performs the following in response to the relationship between the index value of the hit entry and the values of the head pointer and the tail pointer: The first situation is that the index value of the hit entry is the same as the tail pointer value, i.e., the most frequently used entry in the matching table cache is hit. A second situation where the index value of the hit entry is the same as the head pointer value, i.e., the least recently used entry in the matching table cache is hit; and The matching table system of claim 6 is divided into three situations: a situation where the index value of the hit entry is not the same as either the head pointer / tail pointer value, i.e., a third situation where an intermediate entry in the linked list is hit.
11. The matching table system of claim 10, characterized in that in the process of processing the first situation, there is no need to change the frequency of use, and the control unit does not process it and waits for the next match.
12. In the process of handling the second situation, the method includes moving the tail pointer until the hit entry is marked as the most recently used entry, and moving the head pointer until the hit entry is marked as the next least recently used entry, without changing the structure of the linked list; The specific operations are: Step B1: change the value of the tail pointer to the value of the head pointer, initiate a read request to port A of the frequency-of-use memory, and obtain the read address that is the value of the head pointer, i.e., the next least frequently used entry address; The matching table system of claim 10, further comprising step B2 of reading the successor entry address of the entry pointed to by the head pointer and changing the value of the head pointer to that address, i.e., moving the head pointer until it points to the next least frequently used entry.
13. Regarding the third situation processing process, the specific operations are as follows: Step C1: initiate a read request to port A of the frequency-of-use memory, and the read address is the index value of the hit entry, i.e., obtain the predecessor entry address and successor entry address of the hit entry; Step C2, when a read request response is received, initiates a write request to ports A and B of the frequency of use memory, in which the write address of port A is the predecessor entry address of the hit entry, the write data is the successor entry address of the hit entry, with zeros padded to the upper part, and the byte enable signal indicates that the lower part of the write data is valid, and the write address of port B is the successor entry address of the hit entry, with zeros padded to the lower part, and the write data is the predecessor entry address of the hit entry, with zeros padded to the lower part, and the byte enable signal indicates that the upper part of the write data is valid, with the purpose of this operation being to delete the hit entry and establish its predecessor and successor bidirectional logic; When the write request is completed, a write request is initiated again to ports A and B of the frequency of use memory, the write address of port A is the value of the tail pointer, the write data is the value of the index of the hit entry, with zeros padded to the upper part, and the byte enable signal indicates that the lower part of the write data is valid, the write address of port B is the value of the head pointer, the write data is the value of the index of the hit entry, with zeros padded to the lower part, and the byte enable signal indicates that the upper part of the write data is valid, with the purpose of this operation being to insert the hit entry between the entries pointed to by the head / tail pointers; step C3; When the write request is completed, a write request is initiated to port A of the frequency of use memory, the write address is the index value of the hit entry, the write data is a combination of the tail pointer value and the head pointer value, the tail pointer is located at the upper position, the head pointer is located at the lower position, and the byte enable signal indicates that both the upper and lower positions of the write data are valid, and the operation is intended to establish a bidirectional logic between the hit entry and the entry pointed to by the head / tail pointer; step C4; and C5) changing the value of the tail pointer to the index value of the hit entry, thereby marking the hit entry as the most frequently used.
14. the matching table cache controller further includes readable and writable control and status registers; the control register is for controlling the operation of the matching table cache controller; The matching table system of claim 3, wherein the status register is for querying the matching table, the number of times valid data is transferred by the matching table cache, the number of times the matching table cache controller updates the cache or maintains its usage frequency, and its operating status.