Semiconductor device

Abstract

To reduce power consumption of a shift register or a display device having the shift register.SOLUTION: A clock signal is supplied to the shift register not through one wiring but through a plurality of wirings. Further, any one of the plurality of wirings does not supply a clock signal throughout an operation period of the shift register but supplies a clock signal only in part of the operation period. Therefore, it is possible to reduce the capacitive load driven in accordance with the supply of the clock signal. As a result, the power consumption of the shift register can be reduced.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a shift register and a display device having the shift register. do. [Background technology]

[0002] Thin-film transistors formed on flat plates such as glass substrates, as typified by liquid crystal display devices, Thin Film Transistors (hereinafter referred to as TFTs) are mainly used in It is made using semiconductor materials such as amorphous silicon or polycrystalline silicon. Silicon-based TFTs have low field-effect mobility but are compatible with larger glass substrates. On the other hand, TFTs using polycrystalline silicon have high field effect mobility but are not suitable for laser diodes. Crystallization processes such as annealing are required, and this is not necessarily suitable for large-area glass substrates. It has the following characteristics:

[0003] In response to this, TFTs that use oxide semiconductors as the semiconductor material are attracting attention. The TFT is fabricated using zinc oxide or In-Ga-Zn-O oxide semiconductor as the semiconductor material. The technology for fabricating such a semiconductor device and using it as a switching element in an image display device is described in Patent Documents 1 and 2. It is disclosed in.

[0004] The TFT with the channel region formed in the oxide semiconductor is similar to the TFT using amorphous silicon. The oxide semiconductor film has a higher field effect mobility than the FT. By using these methods, it is possible to form films at temperatures below 300°C, and TFTs using polycrystalline silicon It is easier to fabricate than

[0005] TFTs made using such oxide semiconductors are widely used in liquid crystal displays, electro- A device that configures the pixel section and driving circuit of a display device such as a luminescence display or electronic paper. For example, the above oxide semiconductors are expected to be used in switching devices. The technology for constructing the pixel section and driving circuit of a display device using TFTs manufactured using this method is a non-patent document. This is disclosed in reference 1.

[0006] However, all of the TFTs manufactured using the above oxide semiconductors are n-channel transistors. Therefore, a driver circuit is constructed using TFTs made of oxide semiconductors. In this case, the driving circuit is composed of only n-channel TFTs (hereinafter also referred to as unipolar). This will be accomplished. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2007-123861 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-96055 [Non-patent literature]

[0008] [Non-Patent Document 1] T.Osada, and 8 others, SID 09 DIGEST, pp.184-187(2009) Summary of the Invention [Problem to be solved by the invention]

[0009] The driving circuit is composed of a shift register, a buffer, etc. When the capacitor is composed of a unipolar TFT, the signal is reduced by the threshold voltage of the TFT. Therefore, in the places where such problems occur, Specifically, traps are often used to drive signal lines or scanning lines of a display device. It is often used to drive analog switches, etc.

[0010] Furthermore, if the load on the drive circuit using the bootstrap becomes large, It is necessary to increase the gate width of the TFT that constitutes the driving circuit. The parasitic capacitance generated in the FT also increases. A conductive layer functioning as an electrode or drain terminal must be overlapped with a gate insulating layer therebetween. In TFTs with a large capacitance (such as the so-called inverted staggered TFT), the parasitic capacitance becomes large. The power consumption of the clock signal input to the driver circuit increases due to the parasitic capacitance. There is a problem.

[0011] In view of the above-described problems, one embodiment of the present invention provides a shift register or a semiconductor memory device including the shift register. An object of the present invention is to reduce power consumption of a display device. [Means for solving the problem]

[0012] The above problem is solved by dividing the clock signal line of the shift register into a plurality of pulse signal lines. That is, the shift register has multiple flip-flops. Instead of the chip being electrically connected to a single clock signal line, multiple pulse signal lines are and some of the plurality of flip-flops are connected to any one of the plurality of pulse signal lines. Furthermore, the pulse signal line is electrically connected to the clock signal line throughout the operation period of the shift register. Instead of supplying a lock signal, the clock signal is supplied during a part of the operation period. This provides a clock signal to the shift register, which is driven in response to the clock signal. As a result, the power consumption of the shift register can be reduced. This can be done.

[0013] That is, in one aspect of the present invention, the operation period overlaps with the first period, the second period, and the first period. a third period including a period overlapping with the second period, and a fourth period including a period overlapping with the second period. A shift register that periodically cycles between a low power supply potential and a high power supply potential throughout a first period. a first pulse signal line that functions as a wiring for supplying a repeating clock signal; a second pulse signal line that functions as a wiring for supplying a clock signal through the third period It functions as a wiring that supplies an inverted clock signal, which is the inverted signal of the clock signal, through The third pulse signal line is used to supply the inverted clock signal during the fourth period. a fourth pulse signal line that functions; and a first period a first flip-flop that outputs a high power supply potential and a second pulse signal line that is electrically connected to the a second flip-flop connected to the first flip-flop and outputting a high power supply potential during a second period; a third period electrically connected to the first flip-flop and the third pulse signal line; a third flip-flop that outputs a high power supply potential; a fourth filter electrically connected to the pulse signal line and configured to output a high power supply potential during a fourth period; and a shift register having a flip-flop.

[0014] In addition, in one embodiment of the present invention, in the above-described structure, the first pulse signal line is The second pulse signal line functions as a wiring for supplying a low power supply potential throughout the period Throughout the period other than the period, it functions as a wiring that supplies a low power supply potential, and the third pulse signal The line functions as a wiring for supplying a low power supply potential throughout the period other than the third period, and the fourth The pulse signal line functions as a wiring that supplies a low power supply potential throughout periods other than the fourth period. It is a shift register.

[0015] In the above structure, the flip-flop has a channel formation region formed of an oxide semiconductor. A shift register including a transistor configured as above is also one embodiment of the present invention.

[0016] In the above configuration, the pulse signal line is configured to transmit a clock signal or an inverted clock signal. The reference clock signal line is connected to the transistor that is turned on during the period when the clock signal is supplied. Alternatively, a shift register electrically connected to the reference inverted clock signal line is also one aspect of the present invention. do.

[0017] In the above configuration, the pulse signal line is configured to transmit a clock signal or an inverted clock signal. A low power supply potential is supplied through a transistor that is turned on during a period when a lock signal is not supplied. A shift register electrically connected to a wiring is also one embodiment of the present invention.

[0018] Furthermore, a display device including the shift register having the above structure is also one embodiment of the present invention. [Effects of the Invention]

[0019] In the shift register of one embodiment of the present invention, a clock signal is supplied by a single wiring. Furthermore, one of the plurality of wirings is provided by a shift Instead of supplying a clock signal throughout the operation period of the register, Therefore, the capacitive load driven by the clock signal is As a result, the power consumption of the shift register can be reduced. [Brief explanation of the drawings]

[0020] [Figure 1] 1A shows a configuration example of a shift register described in Embodiment 1, and FIG. 1B is a timing chart. [Figure 2] 1A shows a configuration example of a flip-flop described in Embodiment 1, and FIG. 1B is a timing chart. [Figure 3] 1A is a diagram showing an example of the configuration of a pulse signal line described in the first embodiment, and FIG. 1B is a timing chart. [Figure 4] 1A is a diagram showing an example of the configuration of a pulse signal line described in the first embodiment, and FIG. 1B is a timing chart. [Figure 5] 4A to 4C are diagrams showing modified examples of the shift register described in the first embodiment. [Figure 6] 1A and 1B are diagrams showing modified examples of the shift register described in the first embodiment, and FIG. 1C is a timing chart showing the modified example. [Figure 7] 1A is a diagram showing a modified example of the flip-flop described in the first embodiment, and FIG. 1B is a timing chart showing the modified example. [Figure 8] 1A is a top view, and FIGS. 1B and 1C are cross-sectional views of a transistor described in Embodiment 2. [Figure 9] 1A and 1B are a top view and a cross-sectional view of a transistor described in Embodiment 2. [Figure 10] 1A and 1B are a top view and a cross-sectional view of a plurality of transistors described in Embodiment 2. [Figure 11] 4A to 4D are cross-sectional views illustrating a manufacturing process of a transistor described in Embodiment 2. [Figure 12]1A and 1B are a top view and a cross-sectional view of a plurality of transistors described in Embodiment 3. [Figure 13] 1A and 1B are a top view and a cross-sectional view of a plurality of transistors described in Embodiment 4. [Figure 14] 10A is a block diagram of a display device described in Embodiment 5, FIG. 10B is a block diagram of a scanning line driver circuit, and FIG. 10C is a block diagram of a signal line driver circuit. [Figure 15] 10A is a circuit diagram of a pixel of a liquid crystal display device described in Embodiment 6, FIG. 10B is a top view of the pixel, and FIG. 10C is a cross-sectional view of the pixel. [Figure 16] 13A is a circuit diagram of a pixel of a light-emitting display device described in Embodiment 7, and FIGS. 13B to 13D are cross-sectional views thereof. [Figure 17] 10A and 10B are a top view and a cross-sectional view of a light-emitting display device described in Embodiment 7. [Figure 18] 13A is a circuit diagram, FIG. 13B is a top view, and FIG. 13C is a cross-sectional view of a pixel of electronic paper described in Embodiment 7. [Figure 19] FIG. 20 is a diagram showing an example of an electronic book described in embodiment 8. [Figure 20] 10A and 10B illustrate examples of electronic devices described in Embodiment 9. [Figure 21] 10A and 10B illustrate examples of electronic devices described in Embodiment 9. [Figure 22] 10A and 10B illustrate examples of electronic devices described in Embodiment 9. DETAILED DESCRIPTION OF THE INVENTION

[0021] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications may be made without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the following embodiments.

[0022] The source and drain terminals of the transistor depend on the structure and operating conditions of the transistor. It is difficult to identify which is the source terminal and which is the drain terminal. Therefore, in this document, one of the source terminal and the drain terminal is referred to as the first terminal. The other of the source terminal and the drain terminal will be referred to as a second terminal to distinguish it from the other.

[0023] In addition, the size, layer thickness, or area of ​​each component shown in the drawings of each embodiment may be The figures may be exaggerated for clarity and are not necessarily limited to the scale. In addition, ordinal numbers such as "first," "second," and "third" used in this specification are not limited to the construction. It is added to avoid confusion of constituent elements and is not intended to limit the number. do.

[0024] (Embodiment 1) In this embodiment, an example of the configuration and operation of a shift register will be described with reference to FIGS. 1 to 7. Specifically, during a part of the operation period of the shift register, It functions as a wiring that supplies clock signals during this period and has low power consumption during other periods. a pulse signal line that functions as a wiring for supplying a voltage; and a A shift register having a flip-flop will be described.

[0025] <Example of shift register configuration> The shift register of this embodiment has first to sixth pulse signal lines and a third pulse signal line. The first flip-flop to the tenth flip-flop are included.

[0026] The first pulse signal line (PS1) is connected to the first flip-flop (FF1) and the third flip-flop (FF2). The second pulse signal line (PS2) is electrically connected to the flip-flop (FF3). Electrically connected to the fifth flip-flop (FF5) and the seventh flip-flop (FF7) The third pulse signal line (PS3) is electrically connected to the ninth flip-flop (FF9). The fourth pulse signal line (PS4) is connected to the second flip-flop (FF2) and A fifth pulse signal line (PS5) electrically connected to the fourth flip-flop (FF4) is electrically connected to the sixth flip-flop (FF6) and the eighth flip-flop (FF8). The sixth pulse signal line (PS6) is connected to the tenth flip-flop (FF10). (See FIG. 1(A)).

[0027] Furthermore, the output terminal of each flip-flop is electrically connected to the input terminal of the next flip-flop. The input terminal of the first flip-flop (FF1) is connected to the start It is electrically connected to the wiring that supplies the pulse (SP).

[0028] The first pulse signal line (PS1) is connected to a high power supply potential and a low power supply potential during the first period (t1). It functions as a wiring that supplies a clock signal that periodically repeats the power supply potential, and the second pulse signal The line (PS2) functions as a line that supplies a clock signal during the second period (t2). The third pulse signal line (PS3) supplies a clock signal during the third period (t3). The fourth pulse signal line (PS4) functions as a wiring for It functions as a wiring that supplies an inverted clock signal, which is the inverted signal of the clock signal, and is the fifth phase. The pulse signal line (PS5) is a line that supplies an inverted clock signal during the fifth period (t5). The sixth pulse signal line (PS6) functions as an inverted clock signal during the sixth period (t6). It functions as a wiring that supplies clock signals (see Figure 1(B)).

[0029] <Example of shift register operation> The operation of the shift register of this embodiment will be described below.

[0030] First, a start pulse (SP) is input to the input terminal of the first flip-flop (FF1). A signal with a high power supply potential is input. The first flip-flop (FF1) and after half a clock cycle, a high power supply potential signal is output from the output of the first flip-flop. Output as a signal (FF1out).

[0031] The output signal (FF1out) is input to the input terminal of the second flip-flop (FF2). The second flip-flop (FF2) is the same as the first flip-flop (FF1). Similarly, it operates using the input signal, and after half a clock period, it outputs a high power supply potential signal to the second flash. It is output as the output signal (FF2out) of the flip-flop.

[0032] Similarly, a signal at a high power supply potential is input to the input terminal of the next flip-flop, and After a lock period, the flip-flop outputs a signal at a high power supply potential.

[0033] <Example of a flip-flop> A specific example of a circuit configuration of the flip-flop of this embodiment mode is shown in FIG. In 2(A), for convenience, the first flip-flop (FF1) and the second flip-flop (FF2) are Only the configuration of the flip-flop (FF2) is shown.

[0034] The first flip-flop (FF1) includes transistors 101 to 106. Note that the transistors 101 to 106 are n-channel transistors. Let's say it's a transistor.

[0035] The gate terminal of the transistor 101 is connected to the output terminal of the second flip-flop (FF2). The first terminal is electrically connected to the wiring that supplies the high power supply potential (VDD) (hereinafter referred to as the high power supply potential It is electrically connected to a

[0036] The transistor 102 has a gate terminal connected to a line that supplies a start pulse (SP) (hereinafter, The first terminal of the transistor 101 is electrically connected to the second terminal of the transistor 101. The second terminal is electrically connected to the low power supply potential (VSS) The power supply line is electrically connected to the power supply.

[0037] The transistor 103 has a gate terminal electrically connected to the start pulse line and a first terminal is electrically connected to a high power supply potential line.

[0038] The transistor 104 has a gate terminal connected to the second terminal of the transistor 101 and the second terminal of the transistor 102. 102, the first terminal of which is electrically connected to the second terminal of the transistor 103. The first terminal is electrically connected to the low power supply potential line, and the second terminal is electrically connected to the low power supply potential line.

[0039] The transistor 105 has a gate terminal connected to the second terminal of the transistor 103 and the second terminal of the transistor 104. 104, and the first terminal is electrically connected to the first pulse signal line (PS1). are connected to the network.

[0040] The gate terminal of the transistor 106 is connected to the second terminal of the transistor 101. 102 and the gate terminal of the transistor 104, and the first terminal is electrically connected to the The second terminal is electrically connected to the low power supply potential line. To be continued.

[0041] In the following description, for convenience, the second terminal of the transistor 101 and the second terminal of the transistor 102 are referred to as a first terminal of the transistor 104, a gate terminal of the transistor 106, The point of electrical connection is node A, the second terminal of transistor 103, and the first terminal of transistor 104. The point where the first terminal and the gate terminal of the transistor 105 are electrically connected is called a node B. It shall be so decided.

[0042] In addition to the above configuration, a capacitance is provided between the gate terminal and the source terminal of the transistor 105. By providing the capacitance element, This ensures that the bootstrap operation can be performed correctly.

[0043] <Example of flip-flop operation> The following explains the behavior of the above-mentioned flip-flops, taking the first flip-flop (FF1) as an example. The operation will be described with reference to FIG. 2(B).

[0044] First, the voltage of the start pulse line electrically connected to the first flip-flop (FF1) is turned on. The signal level increases to a high level (hereinafter referred to as H level). The signal is input to the gate terminal of the transistor 102 and the gate terminal of the transistor 103. Therefore, the transistor 102 and the transistor 103 are turned on. The potential of node B drops to a low level (hereinafter referred to as an L level), and the potential of node B drops to an H level. As a result, the transistor 105 also turns on. The L level potential of the first pulse signal line (PS1) is the potential of the first flip-flop. It is output as an output signal (FF1out).

[0045] In the following period, the potential of the start pulse line drops to the L level. Transistor 102 and transistor 103 are turned off. As a result, nodes A and B At this time, the transistor 105 is in a floating state. There is a potential difference of H level from node B, and node B is in a floating state. The potential difference is maintained. In other words, the transistor 105 does not depend on the state of the potential of the source terminal. , and continues to be on. Also, the potential of the first pulse signal line (PS1) increases to the H level. This allows the floating state and the gate terminal of the transistor 105 to be electrically connected. The potential of node B is changed by the H level potential of the first pulse signal line (PS1) during this period. Thus, the transistor electrically connected to the floating node B The potential of node B increases due to the capacitive coupling between the gate terminal and the source terminal of the capacitor 105. This operation is called bootstrap. As a result, the potential of the first pulse signal line (PS1) A certain H level potential is output as the output signal (FF1out) of the first flip-flop. can be.

[0046] Note that the transistor 105 is an n-channel transistor. During the period when the potential of the pulse signal line (PS1) of transistor 1 becomes H level, In 05, the terminal electrically connected to the output terminal of the first flip-flop (FF1) is The terminal electrically connected to the first pulse signal line (PS1) is the drain terminal. The transistor is turned on and off by the potential difference between the source terminal and the gate terminal. Therefore, the voltage is determined by the voltage across an n-channel transistor that is not bootstrapped. The H level potential of the first pulse signal line (PS1) is the output signal of the first flip-flop. When the signal is output as a FF1out signal, the output potential is The threshold voltage (Vth) of the n-channel transistor is reduced. However, since the transistor 105 is performing bootstrap, the first pulse signal line (PS1) without lowering the potential of the output signal (FF1o ut).

[0047] Also, the H-level signal, which is the output signal of the first flip-flop (FF1), The second flip-flop (FF2) receives the ) is a first pulse signal line (PS) electrically connected to the first flip-flop (FF1). 1) is replaced with the fourth pulse signal line (PS4). Therefore, the detailed circuit operation is the same as that of FF1. During this period, the second flip-flop (FF2) The L-level potential, which is the potential of the fourth pulse signal line (PS4), is output.

[0048] In the following period, the potential of the first pulse signal line (PS1) drops to the L level. As a result, the potential of the fourth pulse signal line (PS4) increases to the H level. The output signal of the flip-flop (FF1out) drops to L level. The H level potential of the signal line (PS4) is the output signal (F F2out).

[0049] The output signal of the second flip-flop (FF2out) is The signal is input to a flip-flop (not shown) and is also output to the first flip-flop (FF1). The signal is also input to the gate terminal of the first flip-flop (FF1 ) is turned on. As a result, the potential of the node A becomes H level. Accordingly, the transistor 104 and the transistor 106 are also turned on. When 104 is turned on, the potential of node B drops to the L level. Therefore, the potential of the gate terminal of the transistor 105 drops to the L level. In addition, transistor 106 turns on, causing the first flip-flop The output signal (FF1out) of the flip-chip is the first The pulse signal (PS1) is set to the L level, and the low power supply potential (VS S) goes to the L level. t) does not change substantially, but its origin changes.

[0050] In the following period, the potential of the fourth pulse signal line (PS4) drops to the L level. As a result, the output signal (FF2out) of the second flip-flop drops to the L level. Therefore, the transistor 101 of the first flip-flop (FF1) is turned off. As a result, the node electrically connected to the gate terminal of the transistor 104 and the transistor The node electrically connected to the gate terminal of 106 is in a floating state while holding a high-level signal. That is, the transistor 104 and the transistor 106 remain on, and the first flip-flop The output signal (FF1out) of the flip-flop remains at L level. Until a high-level potential is again input to the input terminal of the first flip-flop (FF1) be maintained.

[0051] The first flip-flop (FF1) shown in FIG. 2(A) operates as described above. The input signal can be delayed by half a clock cycle before being output.

[0052] <Example of pulse signal line> The first pulse signal line (PS1) to the sixth pulse signal line (PS2) of the shift register of this embodiment The signal line (PS6) supplies the clock signal during a part of the operating period. It functions as a wiring and as a wiring that supplies a low power supply potential during periods other than the period. An example of wiring having this function will be described below with reference to FIGS.

[0053] The first pulse signal line (PS1) to the sixth pulse signal line (PS6) shown in FIG. The clock signal selection transistors 111, 112, and 113 and the inverted clock The source terminal and drain terminal of any one of the signal selection transistors 114, 115, and 116 The reference clock signal line (CK) or the inverted reference clock signal line (CKB) is connected via the pin. Here, the clock signal selection transistors 111, 112, 113 and the inverted clock signal selection transistors 114, 115, and 116 are n-channel It is assumed that the transistor is a type transistor.

[0054] Specifically, the clock signal selection transistor 111 has a gate terminal connected to a control terminal a. The first terminal is electrically connected to the first pulse signal line (PS1), and the second terminal is electrically connected to the The transistor for selecting the clock signal is electrically connected to the reference clock signal line (CK). The gate terminal of the inverter 112 is electrically connected to the control terminal b, and the first terminal is connected to the second pulse signal The first terminal is electrically connected to the reference clock signal line (CK). The clock signal selection transistor 113 has a gate terminal electrically connected to the control terminal c. , the first terminal is electrically connected to the third pulse signal line (PS3), and the second terminal is It is electrically connected to the reference clock signal line (CK).

[0055] The inverted clock signal selection transistor 114 has a gate terminal electrically connected to the control terminal d. The first terminal is electrically connected to the fourth pulse signal line (PS4), and the second terminal is connected to the reference Electrically connected to the inverted clock signal line (CKB). Transistor for selecting the inverted clock signal The gate terminal of the first terminal of the first gate electrode 115 is electrically connected to the control terminal e, and the first terminal of the first gate electrode 115 is electrically connected to the control terminal e. The first terminal is electrically connected to the reference inverted clock signal line (CKB). The inverted clock signal selection transistor 116 has a gate terminal electrically connected to the control terminal. The first terminal is electrically connected to the sixth pulse signal line (PS6). The second terminal is electrically connected to the reference inverted clock signal line (CKB).

[0056] As shown in FIG. 3B, the reference clock signal line is at a high power supply potential and a low power supply potential regardless of the period. This is the wiring that supplies a clock signal that periodically repeats the power supply potential, and the inverted clock signal line is , a wiring that supplies an inverted clock signal, which is an inverted signal of the clock signal, regardless of the period.

[0057] Furthermore, the potential of the control terminal a becomes H level during the first period (t1), and otherwise This causes the first pulse signal line (PS1) to go low during the first period. It can function as a wiring for supplying a clock signal during the time (t1). In other words, the first period is a period during which the potential of the control terminal a is at H level.

[0058] Similarly, the potentials of the control terminals b to f are set to the second period (t2) to the sixth period (t6), respectively. It becomes H level during either period, and becomes L level during other periods. The second pulse signal line is connected in the second period, and the third pulse signal line is connected in the third period. The fourth pulse signal line functions as a wiring for supplying a clock signal, and the fourth pulse signal line functions as a wiring for supplying a clock signal during the fourth period. The fifth pulse signal line is connected to the fifth period, and the sixth pulse signal line is connected to the sixth period. In other words, it can function as a wiring for supplying an inverted clock signal. During the second period (t2) to the sixth period (t6), the potentials of the control terminals b to f are at the H level, respectively. This is the period in which

[0059] In addition, the first pulse signal line (PS1) to the sixth pulse signal line (PS 6) is connected to the source of one of the low power supply potential selection transistors 121 to 126. The low power supply potential (VSS) is electrically connected to the wiring through the terminal and the drain terminal. Here, the low power supply potential selection transistors 121 to 126 are n-channel type. Let's say it's a transistor.

[0060] The low power supply potential selection transistor 121 has a gate terminal electrically connected to the control terminal g. , the first terminal is electrically connected to the first pulse signal line (PS1), and the second terminal is connected to a low power supply potential. The low power supply potential selection transistor 122 is electrically connected to a wiring that supplies a low power supply potential (VSS). The gate terminal is electrically connected to the control terminal h, and the first terminal is connected to the second pulse signal line (PS 2), and the second terminal is electrically connected to the wiring that supplies the low power supply potential (VSS). The low power supply potential selection transistor 123 has a gate terminal electrically connected to the control terminal i. The first terminal is electrically connected to the third pulse signal line (PS3), and the second terminal is Electrically connected to the wiring that supplies the power supply potential (VSS). The gate terminal of the inverter 124 is electrically connected to the control terminal j, and the first terminal of the inverter 124 is connected to the fourth pulse signal The second terminal is electrically connected to the wiring that supplies the low power supply potential (VSS). The low power supply potential selection transistor 125 has a gate terminal electrically connected to the control terminal k. The first terminal is electrically connected to the fifth pulse signal line (PS5), and the second terminal is electrically connected to the fifth pulse signal line (PS6). The terminal is electrically connected to the wiring that supplies the low power supply potential (VSS). The transistor 126 has a gate terminal electrically connected to the control terminal 1 and a first terminal electrically connected to the sixth pad. The second terminal is electrically connected to the power supply line (PS6), and the second terminal supplies the low power supply potential (VSS). It is electrically connected to the wiring.

[0061] Furthermore, the potential of the control terminal g becomes L level during the first period (t1), and otherwise This causes the first pulse signal line (PS1) to go high during the first period. This allows the line to function as a wiring that supplies low power supply potential (VSS) during periods other than the period (t1). This can be done.

[0062] Similarly, the potentials of the control terminals h to l are set to the second period (t2) to the sixth period (t6), respectively. It becomes L level during this period and becomes H level during other periods. The pulse signal line is connected to the third pulse signal line during a period other than the second period, and the third pulse signal line is connected to the third pulse signal line during a period other than the third period. During the fourth period, the fourth pulse signal line is connected to the fifth pulse signal line. during a period other than the fifth period, and the sixth pulse signal line during a period other than the sixth period. , and can function as wiring for supplying a low power supply potential (VSS).

[0063] In the shift register of this embodiment, the clock signal is supplied by one wiring. Furthermore, one of the plurality of wirings is provided by a shift The clock signal is supplied only for a part of the register's operation period, rather than throughout the register's operation period. This reduces the capacitive load that is driven when the clock signal is supplied. As a result, the power consumption of the shift register can be reduced.

[0064] <Modification> The above-described shift register is an example of an embodiment, and may differ in some respects from the above description. A soft register is also included in this embodiment.

[0065] For example, in the shift register mentioned above, two flip-flops are connected to each pulse signal line. The shift register is shown in Figure 1(A) where each pulse is electrically connected. A configuration in which more flip-flops are electrically connected to a signal line may also be used. Specifically, as shown in FIG. 5(A), for each pulse signal line, x (x is a natural number greater than or equal to 3) is For example, a configuration in which several flip-flops are electrically connected may be used.

[0066] In addition, in the above-mentioned shift register, the shift register has six pulse signal lines. However, a configuration having more pulse signal lines may be used. Specifically, as shown in FIG. 5(B), the clock is turned off during a part of the operation period. The first pulse signal line (PS1) to the yth pulse signal line (y is a natural number equal to or greater than 4) supply pulse signals. The pulse signal line (PSy) supplies an inverted clock signal during a part of the operating period. The y+1th pulse signal line (PSy+1) to the 2yth pulse signal line (PS2y) supply and two flip-flops are electrically connected to each pulse signal line. It is possible.

[0067] In addition, in the above-mentioned shift register, two flip-flops are connected to each pulse signal line. is electrically connected and has six pulse signal lines ( (See Figure 1(A)), but more flip-flops are electrically connected to each pulse signal line. Specifically, the configuration shown in FIG. 5( As shown in Fig. 1C, the first clock signal is supplied during a period included in the operating period. The pulse signal line (PS1) to the yth (y is a natural number equal to or greater than 4) pulse signal line (PSy) and the y+1th pulse that supplies an inverted clock signal during a part of the operating period. and a pulse signal line (PSy+1) to a pulse signal line (PS2y), For example, a configuration in which x number of flip-flops are electrically connected to a line may be used.

[0068] In the above-mentioned shift register, the flip-flops electrically connected to the respective pulse signal lines are The shift registers shown here have the same number of flips (Fig. 1(A), Fig. 5(A)). (See (C)) but the number of electrically connected flip-flops differs for each pulse signal line. Specifically, as shown in FIG. 6(A), a first pulse signal line (P x flip-flops are electrically connected to the fourth pulse signal line (PS1) and the fourth pulse signal line (PS4). The second pulse signal line (PS2) and the fifth pulse signal line (PS5) are connected to z (z is x A configuration in which two or more flip-flops (a natural number different from This can be done.

[0069] In the above-mentioned shift register, the first pulse signal line (PS1) and the fourth pulse signal line (PS2) are connected to each other. The number of flip-flops electrically connected to each line (PS4) is the same. The first pulse is shown in Fig. 1(A), Fig. 5(A) and Fig. 6(A). A flip-flop electrically connected to the signal line (PS1) and the fourth pulse signal line (PS4) The number of loops may be different. Specifically, as shown in FIG. 6(B), The signal line (PS1) is electrically connected to x flip-flops, and the fourth pulse signal The line (PS4) is configured so that x+z flip-flops are electrically connected. can be done.

[0070] In the above-described shift register, the first period (t1) and the second period (t2) are A non-overlapping shift register is shown (see FIG. 1(B)), but the first period (t1) and The first period (t1) may overlap with the second period (t2). As shown in (C), there is a period (T ) can be included. In short, the configuration shown in FIG. 1(B) and FIG. 6(C) can be included. As shown in FIG. 1, at least one of the plurality of pulse signal lines of the shift register outputs a clock signal. and at least one of the plurality of pulse signal lines functions as a wiring for supplying an inverted clock signal. Each period may be set so that the wiring functions as a supply line.

[0071] The circuit configuration of the flip-flop shown in FIG. 2(A) is an example, and the input signal Any circuit configuration may be used as long as it delays and outputs the signal. A circuit such as that shown in A) can be applied to the flip-flop of this embodiment. do.

[0072] The first flip-flop (FF1) shown in FIG. 7A includes transistors 131 to 134. Here, the transistors 131 to 134 are is an n-channel transistor.

[0073] The transistor 131 has a gate terminal and a first terminal electrically connected to the start pulse line. can be.

[0074] The gate terminal of the transistor 132 is connected to the output terminal of the second flip-flop (FF2). a first terminal electrically connected to the second terminal of the transistor 131; The two terminals are electrically connected to a low power supply potential line.

[0075] The transistor 133 has a gate terminal connected to the second terminal of the transistor 131 and the second terminal of the transistor 132. 132, and the first terminal is electrically connected to the first pulse signal line (PS1). are connected to the network.

[0076] The gate terminal of the transistor 134 is connected to the output terminal of the second flip-flop (FF2). a first terminal electrically connected to the second terminal of the transistor 133; The terminal is electrically connected to a low power supply potential line.

[0077] In the following description, for convenience, the second terminal of the transistor 131 and the second terminal of the transistor 132 are referred to as The point where the first terminal of the transistor 131 and the gate terminal of the transistor 133 are electrically connected is called node C. We will do so.

[0078] The operation of the first flip-flop (FF1) shown in FIG. 7(A) will be explained below with reference to FIG. This will be explained with reference to B).

[0079] First, the voltage of the start pulse line electrically connected to the first flip-flop (FF1) is turned on. This causes the H-level signal to be applied to the gate of transistor 131. The voltage is input to the terminal and the first terminal, and the diode-connected transistor 131 is turned on. As a result, the potential of the node C increases to the H level. As a result, the potential of the first pulse signal line (PS1) during this period is L level. The potential of the bell is output as the output signal (FF1out) of the first flip-flop.

[0080] In the following period, the potential of the start pulse line drops to the L level. The transistor 131 is turned off. This causes the node C to be in a floating state. There is a potential difference between the L level and the H level between the source terminal and the gate terminal of the capacitor 131. As a result, the node C is in a floating state, and the potential difference is maintained. The resistor 131 remains on regardless of the state of the potential of the source terminal. The potential of the signal line (PS1) increases to the H level. The potential of the node C electrically connected to the gate terminal of the transistor 133 is It is further increased by the H level potential of the pulse signal line (PS1). The H level potential of the pulse signal line (PS1) is the output signal of the first flip-flop. The signal is output as (FF1out).

[0081] Also, the H-level signal, which is the output signal of the first flip-flop (FF1), The second flip-flop (FF2) receives the ) is a first pulse signal line (P The first flip-flop is the same as the first flip-flop except that the first pulse signal line (PS1) is replaced by the fourth pulse signal line (PS4). (FF1) has the same configuration. Therefore, the detailed circuit operation is based on the above explanation. During this period, the second flip-flop (FF2) The L-level potential, which is the potential of the fourth pulse signal line (PS4) in the

[0082] In the following period, the potential of the first pulse signal line (PS1) drops to the L level. As a result, the potential of the fourth pulse signal line (PS4) increases to the H level. The output signal of the flip-flop (FF1out) drops to L level. The H level potential of the signal line (PS4) is the output signal (F F2out).

[0083] The output signal of the second flip-flop (FF2out) is The signal is input to a flip-flop (not shown) and is also output to the first flip-flop (FF1). The first filter 132 and the second filter 134 are also connected to the gate terminals of the first filter 132 and the second filter 134. The transistor 132 and the transistor 134 of the flip-flop (FF1) are turned on. As a result, the potential of the gate terminal (node ​​C) of the transistor 132 becomes L level. The output signal (FF1out) of the first flip-flop is a transition signal during the period. The first pulse signal (PS1) is at the L level via the transistor 133. 4 to the L level of the low power supply potential (VSS).

[0084] In the following period, the potential of the fourth pulse signal line (PS4) drops to the L level. As a result, the output signal (FF2out) of the second flip-flop drops to the L level. Therefore, the transistor 132 and the transistor In this state, the input terminal of the first flip-flop (FF1) is turned off. This is maintained until a high-level potential is input again.

[0085] The first flip-flop (FF1) shown in FIG. 7A operates as described above. Therefore, in this embodiment, the input signal can be delayed by half a clock period and output. The present invention can be applied to flip-flops in various states.

[0086] The contents of this embodiment or a part of the contents thereof may be the same as the contents of other embodiments or a part of the contents thereof. It can be freely combined with other parts.

[0087] (Embodiment 2) In this embodiment, a transistor that constitutes the shift register shown in Embodiment 1 is An example of a usable transistor will be described.

[0088] A structural example of a transistor in this embodiment will be described with reference to FIG. 8A and 8B are diagrams illustrating an example of a structure of a transistor according to this embodiment. 8(B) is a cross-sectional view taken along line Z1-Z2 in FIG. 8(A). do.

[0089] The transistor shown in FIGS. 8A and 8B includes a conductive layer 211 on a substrate 201 and a conductive The insulating layer 202 on the conductive layer 211, the oxide semiconductor layer 213 on the insulating layer 202, and the oxide semiconductor layer and conductive layer 215a and conductive layer 215b on body layer 213.

[0090] In the transistor, the conductive layer 211 functions as a gate terminal, and the insulating layer 2 The conductive layer 215a and the conductive layer 215b function as a source terminal. The oxide semiconductor layer 213 functions as a gate terminal and the other functions as a drain terminal. Note that the oxide semiconductor layer 213 is dehydrated or dehydrated during its formation. It has been subjected to a nitrification process.

[0091] Furthermore, in the transistors illustrated in FIGS. 8A and 8B, the oxide semiconductor layer 213 In addition to being subjected to hydration treatment or dehydrogenation treatment, a portion of the oxide semiconductor layer 213 is An oxide insulating layer 207 is provided. After dehydration or dehydrogenation treatment, the oxide insulating layer A transistor using the oxide semiconductor layer 213 on which the insulating layer 207 is formed as a channel formation region. The threshold voltage (Vth) of the transistor is less likely to shift due to long-term use or heavy loads. Therefore, it is highly reliable.

[0092] Note that a nitride insulating layer may be provided over the oxide insulating layer 207. The insulating layer 207 is configured to be in contact with the insulating layer 202 provided below the insulating layer 207 or the underlying insulating layer. It is preferable that moisture, hydrogen ions, and OH ions from the vicinity of the side surface of the substrate are removed. - Impurities such as In particular, the insulating layer 202 or the underlayer in contact with the oxide insulating layer 207 is blocked. It is effective to use a silicon nitride layer as the insulating layer. Providing a silicon nitride layer to surround the front and side surfaces of the transistor improves the reliability of the transistor.

[0093] In addition, on the oxide insulating layer 207 (on the nitride insulating layer if a nitride insulating layer is provided), A planarizing insulating layer may also be provided.

[0094] In addition, as shown in FIG. 8C, the transistor of this embodiment has an oxide semiconductor layer 21 An oxide conductive layer 214a and an oxide conductive layer 214b are provided on a part of the oxide conductive layer 3. A conductive layer 215a is provided in contact with the oxide conductive layer 214a, and a conductive layer 215b is provided in contact with the oxide conductive layer 214b. A structure in which a conductive layer 215b is provided as shown in FIG.

[0095] The oxide conductive layer 214a and the oxide conductive layer 214b have a higher conductivity than the oxide semiconductor layer 213. The source region (also called a low-resistance source region) of the transistor 251 and It functions as a drain region (also called a low-resistance drain region).

[0096] The oxide conductive layer 214a and the oxide conductive layer 214b are formed by using an oxide conductive material. The conductive film is made of a conductive material that is transparent to visible light, such as In-Sn-Zn. -O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, I Metal oxides of n-Sn-O, In-O, Sn-O, and Zn-O can be used. The film thickness is appropriately selected within the range of 1 nm to 300 nm. In this case, the film is formed using a target containing 2% to 10% by weight of SiO2. The conductive film with photoresistivity contains SiOx (X>0) which inhibits crystallization, and the desorption process is performed later. The oxide semiconductor layer 213 is crystallized during heat treatment for hydration or dehydrogenation. can be suppressed.

[0097] In addition, when an In-Ga-Zn-O based film is used as the oxide semiconductor layer, the channel formation The oxide semiconductor layer 213 functioning as a region, the oxide conductive layer 214a, and the oxide conductive layer 2 14b can be formed separately under different film forming conditions.

[0098] For example, when forming a film by sputtering, an oxide semiconductor film formed in argon gas is used. The oxide conductive layer 214a and the oxide conductive layer 214b have N-type conductivity, and the activated electrode The energy (ΔE) is between 0.01 eV and 0.1 eV.

[0099] In this embodiment, the oxide conductive layer 214a and the oxide conductive layer 214b are formed of I It is an n-Ga-Zn-O based film and contains at least an amorphous component. Furthermore, crystal grains (nanocrystals) are formed in the oxide conductive layer 214a and the oxide conductive layer 214b. The oxide conductive layer 214a and the oxide conductive layer 214b may contain crystal grains (nano). The diameter of the nanocrystals is 1 nm to 10 nm, typically about 2 nm to 4 nm.

[0100] The oxide conductive layer 214a and the oxide conductive layer 214b are not necessarily provided. The oxide semiconductor layer 213 serving as a channel formation region, the source terminal, and the drain terminal The oxide conductive layer 214a and the oxide conductive layer 214b are disposed between the conductive layer 215a and the conductive layer 215b, which function as a conductive layer. By providing the conductive layer 214b, a good electrical connection can be obtained, and the transistor 251 It is possible to perform stable operation and maintain good mobility even at high drain voltages. It can also be done as follows.

[0101] The transistors shown in FIGS. 8A and 8B may be formed by the same method as in FIGS. 9A and 9B. As shown, the oxide insulating layer 207 (or the oxide insulating layer 207 if a nitride insulating layer is provided) The conductive layer 217 is formed on the oxide semiconductor layer 213 with the nitride insulating layer (and nitride insulating layer) sandwiched therebetween. 9A and 9B show examples of the structure of the transistor of this embodiment. 9A is a top view of the transistor, and FIG. 9B is a top view of the transistor. The conductive layer 217 functions as a second gate terminal. By applying a second gate voltage to the conductive layer 217 via the second gate terminal, This allows the threshold voltage of the transistor 251 to be controlled. When a conductive layer 217 is provided, a conductive layer 217 may be provided on the planarization insulating layer.

[0102] For example, if the potential of the second gate terminal is made higher than the potential of the source terminal, The threshold voltage of the transistor shifts in the negative direction so that it is lower than the potential of the source terminal. This causes the threshold voltage of the transistor to shift in the positive direction.

[0103] As shown in FIGS. 8 and 9 as an example, the transistor of this embodiment has a channel forming The transistor has a channel formation region including an oxide semiconductor. It has higher mobility than conventional transistors that use amorphous silicon. Therefore, a shift register configured with the transistors can perform high-speed operation. .

[0104] In addition, regarding one mode in which a plurality of transistors shown in FIGS. 8A and 8C are used, This will be explained with reference to FIG. 10. FIG. 10 shows a shift register that is applicable to one embodiment of the present invention. 10(A) shows an example of a structure of a plurality of transistors. 10(B) is a cross-sectional view taken along line X1-X2 in FIG. 10(A). .

[0105] In FIG. 10A, a transistor 251 and a transistor 252 are shown. In this example, an oxide semiconductor layer and a conductive layer functioning as a source terminal or a drain terminal are used. 10 shows a structure in which an oxide conductive layer is provided between a metal layer and a conductive film.

[0106] The transistor 251 is the transistor shown in FIGS. Therefore, the above explanation will be used here.

[0107] The transistor 252 is formed by a conductive layer 211 on the substrate 201 and an insulating layer 202 on the conductive layer 211. 2, an oxide semiconductor layer 213 on the insulating layer 202, and an oxide conductive layer on the oxide semiconductor layer 213. The oxide conductive layer 214a and the oxide conductive layer 214b, and the conductive layer 215a and the conductive layer 215b are do.

[0108] In the transistor 252, the conductive layer 211 functions as a gate terminal, and the insulating layer The oxide semiconductor layer 202 functions as a gate insulating layer and has a higher conductivity than the oxide semiconductor layer 213. The conductive layer 214a and the oxide conductive layer 214b form a source region (also called a low-resistance source region) or The conductive layer 215a and the conductive layer 215b function as a drain region (also referred to as a low-resistance drain region). The oxide semiconductor layer 213 functions as a source terminal or a drain terminal. Note that the oxide semiconductor layer 213 is dehydrated or dehydrated during its formation. It has been subjected to a nitrification process.

[0109] Furthermore, the transistor 251 and the transistor 252 shown in FIGS. 10A and 10B 52 is a film in which the oxide semiconductor layer is subjected to dehydration or dehydrogenation treatment, and the oxide semiconductor An oxide insulating layer 207 is provided in contact with the conductor layer 213 and a part of the oxide semiconductor layer 2132. do.

[0110] Furthermore, the conductive layer 211 of the transistor 251 is formed through an opening in the insulating layer 202. This allows for good contact and reduces contact resistance. Therefore, the number of openings can be reduced, and the occupied area can be reduced by the reduction in the number of openings. Therefore, for example, a logic circuit can be constructed using two transistors with this structure. (For example, an inverter) can also be configured.

[0111] As shown in FIG. 10 as an example, in the shift register shown in the first embodiment, A conductive layer that functions as a gate terminal of a transistor is provided on an insulating layer that functions as a gate insulating layer. A conductor that functions as the source terminal or drain terminal of another transistor is connected through the opening. It is also possible to have a structure in which the insulating layer is electrically connected to the conductive layer.

[0112] Next, an example of a method for manufacturing the transistor shown in FIG. 8B will be described with reference to FIGS. 11A to 11D. 11A to 11D illustrate a method for manufacturing the transistor shown in FIG. FIG.

[0113] In the following, the term "film" refers to a film formed on the entire surface of a substrate, and is subsequently photolithographically The term refers to the state before processing, which is to be processed into a desired shape by a photolithography process or the like. And the "layer" is a material that is processed into a desired shape from a "film" by photolithography or other processes. , formed on the substrate, and those intended to be formed over the entire surface of the substrate.

[0114] First, a substrate 201 is prepared, a conductive film is formed on the substrate 201, and then a first photolithography is performed. A conductive layer 211 is formed by a lithography process (see FIG. 11(A)). The conductive layer 211 preferably has a tapered shape. This can improve the adhesion to the film in contact with the upper part.

[0115] The substrate 201 has an insulating surface and is at least resistant enough to withstand the subsequent heat treatment. The substrate 201 is, for example, a glass substrate. It is possible.

[0116] In addition, when the temperature of the subsequent heat treatment is high, the distortion point of the glass substrate is 730°C or higher. The above materials are recommended. For the glass substrate, for example, aluminosilicate glass, Glass materials such as aluminoborosilicate glass and barium borosilicate glass are used. Generally, it is recommended to include more barium oxide (BaO) than boric acid (B2O3). Therefore, glass containing more BaO than B2O3 is preferred. It is preferable to use a glass substrate.

[0117] Instead of the glass substrate, the substrate 201 may be a ceramic substrate, a quartz substrate, a surface treatment substrate, or the like. A substrate made of an insulating material such as a fiber substrate may also be used. Alternatively, a substrate made of a crystallized glass may be used. It is possible.

[0118] An insulating layer serving as a base layer may be provided between the substrate 201 and the conductive layer 211. The layer has a function of preventing the diffusion of impurity elements from the substrate 201, and is made of silicon nitride, silicon oxide, A layer made of silicon nitride oxide or silicon oxynitride or a stacked structure of these layers It can be formed more easily.

[0119] The conductive film material for forming the conductive layer 211 is, for example, molybdenum, titanium, quartz, or the like. Metallic materials such as chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium The conductive layer 211 can be formed using a material such as a fluorine-containing compound or an alloy material containing the material as a main component. The conductive film is formed by a single layer or a laminated film containing one or more of these materials. It can be achieved.

[0120] The conductive film for forming the conductive layer 211 is a film formed by depositing an aluminum layer on a titanium layer and then depositing the aluminum layer. Three-layer laminate structure with titanium layer laminated on aluminum layer, or aluminum layer laminated on molybdenum layer A three-layer laminate structure can be formed by laminating a molybdenum layer on an aluminum layer and a molybdenum layer on the aluminum layer. Of course, the conductive film may have a single layer, a two-layer structure, or a laminated structure of four or more layers. In addition, when a laminated conductive film of a titanium film, an aluminum film, and a titanium film is used as the conductive film, In this case, etching can be performed by dry etching using chlorine gas.

[0121] Next, the insulating layer 202 is formed on the conductive layer 211 .

[0122] The insulating layer 202 is formed by depositing a silicon oxide layer, a silicon nitride layer, or the like by using a plasma CVD method, a sputtering method, or the like. The silicon nitride layer, silicon oxynitride layer, or silicon nitride oxide layer can be formed as a single layer or a stacked layer. For example, oxynitride is produced by plasma CVD using SiH4, oxygen, and nitrogen as film-forming gases. The thickness of the insulating layer 202 is set to 100 nm or more and 500 nm or less. In the case of a laminated structure, for example, a first insulating layer having a film thickness of 50 nm or more and 200 nm or less and a second insulating layer having a film thickness of 100 nm or more ... film thickness of 100 nm or less are used. A second insulating layer having a thickness of 5 nm to 300 nm is laminated on the insulating layer. 2, an oxide film formed using a silicon target material doped with phosphorus or boron By using a silicon film, impurities (water, hydrogen ions, OH - Prevent the intrusion of It can be controlled.

[0123] In this embodiment, as an example, a silicon nitride film having a thickness of 200 nm is formed by plasma CVD. The insulating layer 202 is formed by depositing the insulating layer 202 on the silicon substrate.

[0124] Next, an oxide semiconductor film is formed on the insulating layer 202. The thickness of the oxide semiconductor film is 2n For example, the thickness can be as thin as 50 nm or less. Therefore, even if heat treatment for dehydration or dehydrogenation is performed after the formation of the oxide semiconductor film, the oxide semiconductor film is not easily oxidized. The oxide semiconductor film can be made amorphous. This prevents the oxide semiconductor film from being crystallized when heat treatment is performed after the film is formed. It is possible.

[0125] Before forming the oxide semiconductor film by sputtering, argon gas was introduced into the plasma. Reverse sputtering is performed to generate a smear, and dust adhering to the surface of the insulating layer 202 is removed. Reverse sputtering is a method in which a target is sputtered from the substrate side in an argon atmosphere without applying a voltage to the target side. This is a method of modifying the surface by applying voltage to the substrate using an RF power source to form plasma on the substrate. Instead of argon, nitrogen, helium, oxygen, etc. may be used.

[0126] As oxide semiconductor films, In-Ga-Zn-O based films, In-Sn-Zn-O based films, In -Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al- Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-Sn-O In this embodiment, an oxide semiconductor film based on a Zn-based oxide, an In—O based oxide, an Sn—O based oxide, or a Zn—O based oxide is used. The film is formed by sputtering using an In-Ga-Zn-O metal oxide target. The oxide semiconductor film is formed under a rare gas (typically, argon) atmosphere, an oxygen atmosphere, or a rare It can be formed by sputtering in an atmosphere of gas (typically argon) and oxygen. In addition, when using the sputtering method, the SiO2 content is 2% by weight or more and 10% by weight or less. The oxide semiconductor film is deposited using a target, and SiOx (x>0), which inhibits crystallization, is added to the oxide semiconductor film. This allows the subsequent heat treatment for dehydration or dehydrogenation to be carried out more efficiently. This can prevent crystallization during the process.

[0127] Here, a metal oxide target containing In, Ga, and Zn (composition ratio: In2 O3:Ga2O3:ZnO=1:1:1[mol], In:Ga:Zn=1:1:0.5 [at]), the distance between the substrate and the target was 100 mm, the pressure was 0.6 Pa, and the The film is formed in an oxygen atmosphere (oxygen flow rate 100%) with a DC power supply of 0.5 kW. By using a pulsed direct current (DC) power supply, powdery substances (particles, dust, etc.) generated during film formation can be removed. This is preferable because it can reduce the thickness of the oxide film and make the film thickness distribution uniform. The semiconductor film was deposited by sputtering using an In-Ga-Zn-O metal oxide target. An In-Ga-Zn-O based film is formed using this.

[0128] In addition to the target having the above composition, the metal oxide target may have a composition ratio of , In2O3:Ga2O3:ZnO=1:1:0.5[mol], In:Ga:Zn=1 :1:0.25 [at] or In2O3:Ga2O3:ZnO=1:1:2 [mol], It is also possible to use In:Ga:Zn=1:1:1 [at] or the like.

[0129] There are two types of sputtering methods: RF sputtering, which uses a high frequency power supply, and DC sputtering. There is also the pulsed DC sputtering method, which applies a pulsed bias. The DC sputtering method is mainly used to form insulating films, while the DC sputtering method is mainly used to form metal conductive films. It is used in such cases.

[0130] There are also multi-target sputtering devices that can accommodate multiple targets of different materials. The device can deposit layers of different materials in the same chamber, or multiple layers in the same chamber. It is also possible to form a film by discharging two different materials simultaneously.

[0131] In addition, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber ECR sputtering using plasma generated by microwaves without glow discharge. There are sputtering devices that use the TA method.

[0132] In addition, as a film formation method using the sputtering method, a target material and a sputtering gas compound are mixed during film formation. Reactive sputtering is used to form thin films of compounds by chemically reacting them with the metals. There is also a bias sputtering method in which a voltage is also applied to the substrate.

[0133] It is also preferable to use a cryopump as an exhaust means for the film-forming chamber where sputtering is performed. By using a cryopump to evacuate the chamber, impurities such as moisture can be removed. can be removed.

[0134] Next, the oxide semiconductor film is processed into an island shape by a second photolithography process. A conductor layer 213 is formed (see FIG. 11(B)). Thereafter, the oxide semiconductor layer 213 is etched in an inert gas atmosphere (nitrogen, helium, neon, argon, etc.). Heat treatment (400°C or higher but less than 750°C) is carried out under an atmosphere such as a Impurities such as hydrogen and water may be removed.

[0135] Next, the oxide semiconductor layer 213 is dehydrated or dehydrogenated. The temperature of the first heat treatment is 400°C or higher and lower than 750°C, preferably 425°C. If the temperature is 425°C or higher, the heat treatment time can be 1 hour or less. If the temperature is below 100°C, the heat treatment time should be longer than 1 hour. The substrate was placed in an electric furnace, which is one of the furnaces, and the oxide semiconductor layer 213 was heated in a nitrogen atmosphere. After the heat treatment, the oxide semiconductor layer 213 was cooled to room temperature and then exposed to air. In this embodiment, the oxide semiconductor layer 213 is dehydrated or dehydrogenated. The mixture is slowly cooled from the hot temperature to a temperature that is sufficient to prevent water from entering again using the same furnace. The sample is slowly cooled in a nitrogen atmosphere until the temperature drops by 100°C or more below the heating temperature. The atmosphere is not limited to a nitrogen atmosphere, but may be an inert gas atmosphere such as helium, neon, or argon. Any atmosphere is acceptable.

[0136] The heat treatment device is not limited to an electric furnace, but may be a device that uses heat conduction from a heating element such as a resistance heating element or the like. A device for heating the object to be treated by thermal radiation may be provided. For example, a GRTA (Ga s Rapid Thermal Anneal) equipment, LRTA (Lamp Rapi) d Thermal Anneal (RTA) equipment The LRTA device can be equipped with halogen lamps, metal halide lamps, etc. Iridium lamps, xenon arc lamps, carbon arc lamps, high pressure sodium lamps, A device that heats the object to be treated by radiating light (electromagnetic waves) emitted from a lamp such as a pressure mercury lamp. The GRTA device is a device that uses high-temperature gas to perform heat treatment. For example, rare gases such as argon or nitrogen react with the material to be treated by heat treatment. An inert gas that does not cause flammability is used.

[0137] The oxide semiconductor layer 213 is subjected to heat treatment at a temperature higher than or equal to 400° C. and lower than 750° C., whereby an oxide The semiconductor layer is dehydrated and dehydrogenated, preventing subsequent re-impregnation with water (H2O). do.

[0138] In the first heat treatment, nitrogen or a rare gas such as helium, neon, or argon is used. It is preferable that the gas does not contain water, hydrogen, etc. Or the purity of rare gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably, the impurity concentration is 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm or less, It is preferable to set the concentration to 0.1 ppm or less.

[0139] Note that depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer 213, The conductor layer 213 may be formed by including fine crystal grains and amorphous regions or by only crystal grains. For example, the crystallinity may be 90% or more, or 80% or more, ... In addition, depending on the conditions of the first heat treatment or the oxide semiconductor layer, Depending on the material of the oxide semiconductor layer 213, the oxide semiconductor layer 213 may be formed only by an amorphous region that does not contain crystal grains. It may also be configured as follows.

[0140] After the first heat treatment, the oxide semiconductor layer 213 becomes oxygen-deficient and has low resistance. The oxide semiconductor film after the heat treatment has a higher carrier concentration than the oxide semiconductor film immediately after deposition. Preferably 1×10 18 / cm 3 The oxide semiconductor layer has a carrier concentration of at least .

[0141] The conductive layer 211 may be a microcrystalline layer depending on the conditions of the first heat treatment or the material. For example, the conductive layer 211 may be made of indium oxide, silicon dioxide, or a polycrystalline layer. When a zinc alloy film is used, it is crystallized by heat treatment at 450° C. for 1 hour, and the oxide film is used as the conductive layer 211. When an indium oxide tin oxide alloy film containing silicon is used, crystallization does not occur.

[0142] The first heat treatment of the oxide semiconductor layer 213 is performed before processing into an island-shaped oxide semiconductor layer. In that case, the oxide semiconductor film can be heated by the heating device after the first heat treatment. The substrate is then removed and subjected to a photolithography process.

[0143] Next, a conductive film is formed over the insulating layer 202 and the oxide semiconductor layer 213.

[0144] The conductive film may be made of titanium (Ti), molybdenum (Mo), tungsten (W), or aluminum. an element selected from aluminum (Al), chromium (Cr), copper (Cu), and tantalum (Ta); The above elements are used as components, or alloys containing the above elements, or compounds combining the above elements. The conductive film is not limited to a single layer containing the above-mentioned element, and may be a stack of two or more layers. In this embodiment, a titanium film (thickness 100 nm) and an aluminum film (thickness 200 A conductive film with a three-layer structure consisting of a titanium film (thickness 100 nm) and a titanium film (thickness 100 nm) is formed. Alternatively, a titanium nitride film may be used.

[0145] If heat treatment at 200 to 600°C is to be carried out later, the heat resistance of the material must be sufficient to withstand this heat treatment. For example, an aluminum alloy containing an element for preventing hillocks is used. It is preferable to use a conductive film laminated with gold or a heat-resistant conductive film. The methods include sputtering, vacuum deposition (electron beam deposition, etc.), and arc discharge ion plating. The coating method and spraying method are used. Also, conductive nanopastes such as silver, gold, and copper are used for coating. It may also be formed by discharging using a screen printing method, an ink jet method, or the like, and then baking.

[0146] Next, a resist mask 233a and a resist mask The conductive film is selectively etched to form a conductive layer 215a and a conductive layer 233b. 15b is formed (see FIG. 11(C)).

[0147] In the third photolithography step, a conductive layer in contact with the oxide semiconductor layer 213 is formed. For example, the conductive film in contact with the In-Ga-Zn-O-based oxide semiconductor layer is selectively removed. In order to selectively remove only the metal conductive film, ammonia peroxide was used as an alkaline etchant. If you use water (weight ratio of hydrogen peroxide: ammonia: water = 5:2:2), The conductive film is selectively removed to leave an oxide semiconductor layer made of an oxide semiconductor. can.

[0148] In addition, depending on the etching conditions, the oxide semiconductor The exposed areas of layer 213 may be etched, in which case conductive layer 215a and conductive layer The oxide semiconductor layer in the region sandwiched between the conductive layer 215a and the conductive layer 215b is formed on the conductive layer 211. The thickness of the oxide semiconductor layer is thinner than that of the region where the layer 215b overlaps.

[0149] Next, the oxide insulating layer 207 is formed over the insulating layer 202 and the oxide semiconductor layer 213. At this stage, part of the oxide semiconductor layer 213 is in contact with the oxide insulating layer 207. A region of the oxide semiconductor layer overlapping with the conductive layer 211 with the layer 202 sandwiched therebetween becomes a channel formation region.

[0150] The oxide insulating layer 207 has a thickness of at least 1 nm and is formed by an oxide insulating method such as sputtering. The insulating layer can be formed by any suitable method that does not allow impurities such as water and hydrogen to be mixed into the insulating layer. In this embodiment, a silicon oxide film is formed as the oxide insulating layer by sputtering. The substrate temperature may be set to a temperature between room temperature and 300° C., and is set to 100° C. in this embodiment. The silicon oxide film is formed by sputtering under a rare gas (typically argon) atmosphere or an oxygen atmosphere. The process should be carried out under atmospheric pressure or under a mixture of rare gas (typically argon) and oxygen. In addition, a silicon oxide target or a silicon target can be used as the target. For example, a silicon target can be used in a sputtering method under an oxygen and rare gas atmosphere. Silicon oxide can be formed in contact with the oxide semiconductor layer having a low resistance. The oxide insulating layer is resistant to moisture, hydrogen ions, and OH - It does not contain impurities such as An inorganic insulating film is used to block the penetration of oxygen from the atmosphere. A film, an aluminum oxide film, an aluminum oxynitride film, or the like is used. The oxide insulating layer formed by this method is particularly dense, and it is possible to suppress the phenomenon of impurities diffusing into adjacent layers. It can be used as a single layer protective film. Doped targets can also be used to add phosphorus (P) or boron (B) to the oxide insulating layer. can.

[0151] In this embodiment, a columnar polycrystalline B-doped silicon target (resistivity value: 0.01Ωcm), the distance between the substrate and the target (TS distance) was 89mm, Pressure: 0.4 Pa, DC power: 6 kW, oxygen (oxygen flow rate: 100%) atmosphere The film is formed by DC sputtering to a thickness of 300 nm.

[0152] Note that the oxide insulating layer 207 is formed on a region to be a channel formation region of the oxide semiconductor layer 213. It is provided in contact with the substrate and also functions as a channel protection layer.

[0153] Next, a second heat treatment (preferably at 200°C or higher and 400°C or lower, for example, at 250°C or higher) is performed. 350°C or less) may be carried out in an inert gas atmosphere or a nitrogen gas atmosphere. Then, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere. A part of the oxide semiconductor layer 213 is heated while being in contact with the oxide insulating layer 207, and the oxide semiconductor layer 213 is oxidized. Another part of the compound semiconductor layer 213 is heated in a state where it is in contact with the conductive layer 215a and the conductive layer 215b. can be.

[0154] The oxide semiconductor layer 213 whose resistance is reduced by the first heat treatment is in contact with the oxide insulating layer 207. When the second heat treatment is performed in this state, the region in contact with the oxide insulating layer 207 becomes an oxygen-excess state. As a result, the oxide semiconductor layer 213 is divided into the following regions in contact with the oxide insulating layer 207: The oxide semiconductor layer 213 is made to have a high resistance (i-type) in the depth direction (see FIG. 11D). ).

[0155] The timing for performing the second heat treatment is immediately after the end of the third photolithography process. However, there is no particular limitation as long as it is a process subsequent to the third photolithography process. .

[0156] Through the above steps, the transistor illustrated in FIG. 8B can be manufactured.

[0157] Note that the contents of this embodiment or a part of the contents thereof may be the same as the contents of other embodiments or a part of the contents thereof. They can be freely combined.

[0158] (Embodiment 3) In this embodiment, a transistor that constitutes the shift register shown in Embodiment 1 is An example of a transistor that can be used in the present invention and is different from the transistor described in Embodiment 2 will be described. Reveal.

[0159] An example of the structure of a transistor in this embodiment will be described with reference to FIG. 12 is a diagram illustrating an example of a structure of a transistor according to this embodiment, and FIG. 12(A) 12(B) is a top view of the transistor, and FIG. 12(A) is a view of the line segment Z1-Z2 of FIG. FIG.

[0160] The transistor shown in FIGS. 12A and 12B includes a conductive layer 211 on a substrate 201 and a , the insulating layer 202 on the conductive layer 211, the conductive layer 215a and the conductive layer 215 on the insulating layer 202, b, and the oxide semiconductor layer 213 over the insulating layer 202 and the conductive layers 215a and 215b. and,

[0161] In the transistor, the conductive layer 211 functions as a gate terminal, and the insulating layer 2 The conductive layer 215a and the conductive layer 215b function as a source terminal. The oxide semiconductor layer 213 functions as a gate terminal and the other functions as a drain terminal. Note that the oxide semiconductor layer 213 is dehydrated or dehydrated during its formation. It has been subjected to a nitrification process.

[0162] Furthermore, the transistors illustrated in FIGS. 12A and 12B include an oxide semiconductor layer 213 In addition, the oxide semiconductor layer 213 is subjected to dehydration treatment or dehydrogenation treatment. After the dehydration or dehydrogenation treatment, an oxide insulating layer 207 is provided. The oxide semiconductor layer 213 on which the oxide insulating layer 207 is formed is used as a channel formation region. Transistors are less likely to experience a shift in threshold voltage (Vth) due to long-term use or heavy loads. Therefore, it is highly reliable.

[0163] Note that a nitride insulating layer may be provided over the oxide insulating layer 207. The insulating layer 207 is configured to be in contact with the insulating layer 202 provided below the insulating layer 207 or the underlying insulating layer. It is preferable that moisture, hydrogen ions, and OH ions from the vicinity of the side surface of the substrate are removed. - Impurities such as In particular, the insulating layer 202 or the underlayer in contact with the oxide insulating layer 207 is blocked. It is effective to use a silicon nitride layer as the insulating layer. Providing a silicon nitride layer to surround the front and side surfaces of the transistor improves the reliability of the transistor.

[0164] In addition, on the oxide insulating layer 207 (on the nitride insulating layer when the nitride insulating layer is provided), ) may also be provided with a planarizing insulating layer.

[0165] 9A and 9B, the transistor shown in FIG. 12 is made of an oxide semiconductor. On the oxide insulating layer 207 in the region overlapping with the layer 213 (if the planarizing insulating layer is provided), A structure having a conductive layer on the planar insulating layer may also be used. The conductive layer may be a second gate electrode. By applying a second gate voltage to the conductive layer, the transistor The threshold voltage of the transistor can be controlled.

[0166] Note that the planarization insulating layer is not necessarily provided. When the planarization insulating layer is not provided, A second gate electrode is formed on the oxide insulating layer 207 (on the nitride insulating layer if a nitride insulating layer is provided). It is also possible to have a structure having a conductive layer that functions as a port terminal.

[0167] For example, if the potential of the second gate terminal is made higher than the potential of the source terminal, The threshold voltage of the transistor shifts in the negative direction so that it is lower than the potential of the source terminal. This causes the threshold voltage of the transistor to shift in the positive direction.

[0168] As shown in FIG. 12, the transistor of this embodiment has a source terminal or a drain terminal. A so-called bottom-contact transistor having an oxide semiconductor layer on a conductive layer functioning as a The transistor is a conventional transistor using amorphous silicon for the channel formation region. It has a higher mobility than conventional transistors. The shift register can operate at high speed. By applying a transistor, the oxide semiconductor layer and the gate insulating film function as a source terminal or a drain terminal. This increases the contact area with the conductive layer, preventing peeling and other issues. .

[0169] Note that the contents of this embodiment or a part of the contents thereof may be the same as the contents of other embodiments or a part of the contents thereof. They can be freely combined.

[0170] (Fourth embodiment) In this embodiment, a transistor that constitutes the shift register shown in Embodiment 1 is usable transistors different from those shown in the second and third embodiments An example of this will be described.

[0171] An example of the structure of a transistor in this embodiment will be described with reference to FIG. 13 is a diagram illustrating an example of a structure of a transistor according to this embodiment, and FIG. 13(A) 13(B) is a top view of the transistor, and FIG. 13(A) is a view of the line segment Z1-Z2 of FIG. FIG.

[0172] The transistors shown in FIGS. 13A and 13B are similar to the transistors shown in FIG. A conductive layer 211 on the substrate 201, an insulating layer 202 on the conductive layer 211, and a the oxide semiconductor layer 213, the conductive layer 215a and the conductive layer 215b over the oxide semiconductor layer 213, b and

[0173] In the transistor, the conductive layer 211 functions as a gate terminal, and the insulating layer 2 The conductive layer 215a and the conductive layer 215b function as a source terminal. The oxide semiconductor layer 213 functions as a gate terminal and the other functions as a drain terminal. Note that the oxide semiconductor layer 213 is dehydrated or dehydrated during its formation. It has been subjected to a nitrification process.

[0174] Furthermore, the transistors illustrated in FIGS. 13A and 13B include an oxide semiconductor layer 213 In addition, the oxide semiconductor layer 213 is subjected to dehydration treatment or dehydrogenation treatment. An oxide insulating layer 207 is provided under the conductive layer 215a and the conductive layer 215b. The oxide insulating layer 207 shown in FIG. 3(A) and FIG. 13(B) functions as a channel protection layer. Has.

[0175] In addition, a nitride insulating layer is formed on the oxide insulating layer 207 and the conductive layer 215a and the conductive layer 215b. The nitride insulating layer may be formed between the insulating layer 202 and the oxide insulating layer 207. It is preferable that the insulating layer is in contact with the insulating layer serving as the base, and moisture and the like coming from the side of the substrate are prevented from entering. , hydrogen ions, OH - In particular, oxide insulation It is effective to use a silicon nitride layer for the insulating layer 202 in contact with the layer 207 or the underlying insulating layer. That is, a silicon nitride layer is provided so as to surround the bottom surface, top surface, and side surfaces of the oxide semiconductor layer 213. This improves the reliability of the transistor.

[0176] In addition, the oxide insulating layer 207 and the conductive layers 215a and 215b (the nitride When an insulating layer is provided, a planarizing insulating layer may be provided on the nitride insulating layer.

[0177] In addition, on the oxide insulating layer 207 (on the planarizing insulating layer when the planarizing insulating layer is provided), ) and a conductive layer is formed on the oxide semiconductor layer 213 with the oxide insulating layer 207 sandwiched therebetween. The conductive layer functions as a second gate terminal. By applying a voltage to the conductive layer, the threshold voltage of the transistor 251 can be controlled. Cut.

[0178] Note that the planarization insulating layer is not necessarily provided. When the planarization insulating layer is not provided, The conductive layer is formed on the oxide insulating layer 207 (on the nitride insulating layer if a nitride insulating layer is provided). It may also be a structure having layers.

[0179] For example, if the potential of the second gate terminal is made higher than the potential of the source terminal, The threshold voltage of the transistor shifts in the negative direction so that it is lower than the potential of the source terminal. This causes the threshold voltage of the transistor to shift in the positive direction.

[0180] In addition, the transistor of this embodiment is oxidized like the transistor shown in FIG. A pair of oxide conductive layers functioning as a pair of buffer layers are provided on a part of the compound semiconductor layer 213. The conductive layers 215a and 215b are electrodes that are in contact with the pair of oxide conductive layers, respectively. A structure in which a conductive layer 215b is provided may also be used.

[0181] As described above, in the transistor of this embodiment, a transistor having a junction region on a part of an oxide semiconductor layer is formed. This is a so-called channel protection type transistor, which has an insulating layer that serves as a channel protection layer. The transistor is a conventional transistor that uses amorphous silicon in the channel formation region. Therefore, the shift register composed of this transistor has a high mobility. The star is capable of high speed operation.

[0182] Note that the contents of this embodiment or a part of the contents thereof may be the same as the contents of other embodiments or a part of the contents thereof. They can be freely combined.

[0183] (Embodiment 5) In this embodiment, an example of a display device including the shift register described in Embodiment 1 will be described. This will be explained with reference to FIG.

[0184] The display device having the shift register shown in Embodiment 1 may be a liquid crystal display device or an electrophotographic display device. There are various display devices, such as electroluminescence (EL) display devices. The structure of the display device in this embodiment will be described with reference to FIG. 4(A) is a block diagram showing the configuration of the display device according to the present embodiment.

[0185] The display device shown in FIG. 14A includes a pixel portion 701, a scanning line driver circuit 702, and a signal line driver circuit. and an operating circuit 703.

[0186] Furthermore, the pixel section 701 has a dot matrix structure having a plurality of pixels 704. Specifically, the pixels 704 are arranged in rows and columns. 705 to the scanning line driving circuit 702, and the signal line 706 to the signal line It is electrically connected to the driving circuit 703 .

[0187] The scanning line driving circuit 702 is a circuit for selecting pixels 704 to which data signals are input. A selection signal is output to the pixel 704 via a scan line 705 .

[0188] The signal line driver circuit 703 is a circuit that outputs data to be written to the pixel 704 as a signal. Pixel data is transmitted to the pixel 704 selected by the scanning line driving circuit 702 via a signal line 706. The data is output as a signal.

[0189] The pixel 704 includes at least a display element and a switching element. For example, a light-emitting element such as a liquid crystal element or an EL element can be applied to the switching element. As the element, for example, a transistor or the like can be applied.

[0190] Next, a configuration example of the scanning line driver circuit 702 and the signal line driver circuit 703 will be described with reference to FIG. 14(B). 14(B) and (C) are block diagrams showing the configuration of the driving circuit. 14(B) is a block diagram showing the configuration of the scanning line driving circuit 702, and FIG. 14(C) is a block diagram showing the configuration of the scanning line driving circuit 702. 7) is a block diagram showing the configuration of the signal line driver circuit 703.

[0191] As shown in FIG. 14B, the scanning line driving circuit 702 includes a shift register 900 and a level The shifter 901 and the buffer 902 are included.

[0192] The shift register 900 receives a start pulse (GSP) for the scanning line driving circuit, A signal such as a reference clock signal (GCK) for the circuit is input, and each sequential logic circuit selects the The shift register 900 of this embodiment is similar to that shown in the first embodiment. As shown in the figure, the reference clock signal (GCK) for the scanning line driving circuit is The scanning line driving circuit includes a plurality of wirings for supplying a reference clock signal to the scanning line driving circuit.

[0193] As shown in FIG. 14C, the signal line driver circuit 703 includes a shift register 903, a first a latch circuit 904, a second latch circuit 905, a level shifter 906, and a buffer 907; It has.

[0194] The shift register 903 receives a start pulse (SSP) for the signal line driver circuit, A signal such as a reference clock signal (SCK) for the circuit is input, and each sequential logic circuit sequentially The shift register 903 of this embodiment is the same as that shown in the first embodiment. As shown in the figure, the reference clock signal (SCK) for the signal line driver circuit is The signal line driver circuit has a plurality of wirings for supplying a reference clock signal to the signal line driver circuit.

[0195] In this embodiment, only one of the shift registers 900 and 903 is used. The shift register shown in embodiment 1 may also be used.

[0196] A data signal (DATA) is input to the first latch circuit 904. 904 can be configured using a logic circuit.

[0197] The buffer 907 has a function of amplifying a signal and includes an operational amplifier. 907 can be configured using a logic circuit.

[0198] The second latch circuit 905 can temporarily hold a latch (LAT) signal. The latched signals are outputted all at once to the pixel section 701 in FIG. Therefore, if the pixel is driven by point sequential driving rather than line sequential driving, the second line The second latch circuit 905 can be omitted. It can be constructed using:

[0199] Next, the operation of the display device of this embodiment will be described.

[0200] First, the scanning line 705 is selected by the scanning line driving circuit 702. The electrically connected pixels 704 receive data from the signal line driver circuit 703 via a signal line 706. As a result, data is written to the pixel 704 and the display state is changed. The scanning line 705 is selected by the scanning line driving circuit 702, and all the pixels 704 are The data is written in the above manner. The operation of the display device according to this embodiment has been described above.

[0201] All of the circuits in the display device shown in FIG. 14 can be provided on the same substrate. By providing the transistors on the same substrate, It can be made smaller, and the process is simplified by using transistors of the same conductivity type. It is possible.

[0202] The contents of this embodiment or a part of the contents thereof may be the same as the contents of other embodiments or a part of the contents thereof. It can be freely combined with other parts.

[0203] (Sixth embodiment) In this embodiment, a liquid crystal display device will be described as an example of the display device described in Embodiment 5. This will be explained using FIG.

[0204] FIG. 15A shows a circuit diagram of a pixel included in the liquid crystal display device of this embodiment mode. The pixel shown in FIG. 1 includes a transistor 821, a liquid crystal element 822, and a capacitor 823. do.

[0205] The transistor 821 has a gate terminal electrically connected to the scanning line 804 and a first terminal The transistor 821 is electrically connected to the line 805. It functions as a selection transistor that controls the application of voltage to the element 822 .

[0206] One terminal of the liquid crystal element 822 is electrically connected to the second terminal of the transistor 821. The other terminal is electrically connected to the wiring that supplies the common potential (Vcom) (hereinafter referred to as the common potential line). The liquid crystal element 822 is connected to the first electrode, which is a part or the whole of one terminal. a first electrode and a second electrode that is part or all of the other terminal, and a second electrode between the first electrode and the second electrode The layer (called the liquid crystal layer) has liquid crystal molecules whose orientation changes when a voltage is applied. It is composed of:

[0207] One terminal of the capacitor 823 is electrically connected to the second terminal of the transistor 821. The other terminal is electrically connected to a common potential line. a first electrode that is a part or all of the other terminal, and a second electrode that is a part or all of the other terminal; The capacitor element is configured by a first electrode, a second electrode, and a dielectric layer provided between the first electrode and the second electrode. The capacitor 823 functions as a storage capacitor of the pixel. Although it is not necessary to provide the capacitor 823, the leakage current of the transistor 821 can be reduced by providing the capacitor 823. The effects of this can be suppressed.

[0208] The liquid crystal display device of this embodiment uses a TN (Twisted Nematic) method. ted Nematic mode, IPS (In-Plane-Switching) mode Mode, FFS (Fringe Field Switching) mode, MVA (Mu lti-domain Vertical Alignment) mode, PVA(Pa Interconnected Vertical Alignment mode, ASM (Axial ly Symmetric aligned Micro-cell) mode, OCB( Optically Compensated Birefringence mode, FLC (Ferroelectric Liquid Crystal) mode, AFL C (Antiferroelectric Liquid Crystal) can be done.

[0209] Alternatively, a liquid crystal that exhibits a blue phase without using an alignment film may be used. When the temperature of the cholesteric liquid crystal is increased, the cholesteric phase transitions to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to improve the liquid crystal layer, a liquid crystal composition containing 5% by weight or more of a chiral agent is used. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 10 μs to 100 μs. It is optically isotropic, so alignment treatment is not required, and viewing angle dependency is small.

[0210] When a signal is input to a pixel, the pixel to which the data is written is first selected. In the pixel, a transistor 821 is turned on by a signal input from a scanning line 804. do.

[0211] At this time, the data signal from the signal line 805 is input to the pixel via the transistor 821. The potential of one terminal of the liquid crystal element 822 becomes the potential of the data signal. 822 is set to an orientation state according to the voltage applied between one terminal and the other terminal. After the data is written, the transistor 821 is turned on by a signal input from the scanning line 804. The liquid crystal element 822 maintains the set orientation state during the display period, and is in the display state. The above operation is performed sequentially for each scanning line 804, and the liquid crystal display device has all the pixels. The above operation is performed.

[0212] When displaying moving images on a liquid crystal display device, the response of the liquid crystal molecules themselves is slow, which can cause afterimages. In order to improve the moving image characteristics of LCD devices, There is a driving technique called black insertion, which displays black every other frame.

[0213] In addition, the response speed can be improved by increasing the normal vertical synchronization frequency by 1.5 times, preferably by more than 2 times. There is also a driving technology called double speed driving that improves this.

[0214] In addition, in order to improve the video characteristics of LCD devices, multiple LEDs (light emitting diodes) are used as backlights. A surface light source is formed by using a light source such as a photodiode or multiple EL light sources. There is also a driving technology that drives each light source to light intermittently within one frame period. Three or more types of LEDs may be used, or white-emitting LEDs may be used. This allows multiple LEDs to be controlled, so the LEDs can be switched in accordance with the timing of the optical modulation of the liquid crystal layer. The timing of the ED light emission can also be synchronized. This driving technology allows the LEDs to be partially turned off. This is particularly useful when displaying images with a large proportion of black areas occupying the entire screen. This can reduce power consumption.

[0215] By combining these driving technologies, the display characteristics such as the video characteristics of the LCD display can be improved. The performance can be improved more than before.

[0216] Next, the structure of the liquid crystal display device according to this embodiment including the pixel will be described with reference to FIG. 15B and 15C show the display screen of the display device in this embodiment. 15(B) is a top view of the pixel, and FIG. 15(C) is a top view of the pixel shown in FIG. 5(B) are cross-sectional views taken along lines A1-A2 and B1-B2.

[0217] The liquid crystal display device shown in FIG. 15(B) and FIG. 15(C) has a substrate in the cross section taken along the line A1-A2. A conductive layer 2001 on the plate 2000, an insulating layer 2002 on the conductive layer 2001, and an insulating layer 200 2, and a conductive layer 2005a and a conductive layer 2005b on the oxide semiconductor layer 2003. the conductive layer 2005a, the conductive layer 2005b, and the oxide semiconductor layer 2003. The oxide insulating layer 2007 is connected to the conductive layer 2004 through an opening formed in the oxide insulating layer 2007. and a transparent conductive layer 2020 in contact with 2005b.

[0218] The conductive layer 2001 functions as a gate terminal, and the insulating layer 2002 functions as a gate insulating layer. One of the conductive layer 2005a and the conductive layer 2005b functions as a first terminal, and the other functions as the second terminal. The transistor (see FIG. 8B) is applied to the semiconductor device. The transistor shown in the fourth aspect can also be applied.

[0219] In addition, the liquid crystal display device shown in FIG. 15(B) and FIG. 15(C) has a cross section taken along the line B1-B2. 2000, a conductive layer 2008 on the substrate 2000, an insulating layer 2002 on the conductive layer 2008, and an insulating layer an oxide insulating layer 2007 on the insulating layer 2002; and a transparent conductive layer 2020 on the insulating layer 2007. , has.

[0220] Furthermore, the liquid crystal display device of this embodiment is a flexible printed circuit (FPC). Conductive layer 2022, which acts as an electrode or wiring for connecting to the and a transparent conductive layer 2029, a conductive layer 2023, a conductive layer 2024, and a transparent conductive layer 2028. It has the following.

[0221] The transparent conductive layer 2020, the transparent conductive layer 2029, and the transparent conductive layer 2028 are made of indium oxide. In2O3 and indium oxide tin oxide alloy (In2O3-SnO2, abbreviated as ITO) It is formed by sputtering or vacuum deposition using materials such as Etching is performed using a hydrochloric acid solution. However, etching ITO in particular leaves residue. Therefore, indium oxide zinc oxide alloy (In2 O3-ZnO) may also be used.

[0222] The contents of this embodiment or a part of the contents thereof may be the same as the contents of other embodiments or a part of the contents thereof. It can be freely combined with other parts.

[0223] (Embodiment 7) In this embodiment, an electroluminescent display device is used as an example of the display device shown in Embodiment 5. A light emitting display device having a light emitting element using sensing will be described with reference to FIGS. 16 and 17. do.

[0224] Light-emitting elements that utilize electroluminescence are either made of organic compounds or inorganic light-emitting materials. Generally, the former is an organic EL element, and the latter is an inorganic EL element. It's called a child.

[0225] In an organic EL element, when a voltage is applied to the light-emitting element, electrons and positive electrodes are released from a pair of electrodes. The holes are then injected into a layer containing a light-emitting organic compound, allowing a current to flow. Light is emitted by the recombination of carriers (electrons and holes). Such a light-emitting element is called a current-excited light-emitting element.

[0226] Inorganic EL elements are classified into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The emission mechanism is a donor- The thin-film inorganic EL element is an acceptor recombination type luminescence element. The luminescent layer is sandwiched between dielectric layers. The structure is sandwiched between electrodes, and the light emission mechanism is the inner shell electron transition of the metal ion. This is a localized light emission that utilizes organic EL elements. do.

[0227] FIG. 16A is a circuit diagram showing a circuit configuration of a pixel of a light-emitting display device according to this embodiment. be.

[0228] As shown in FIG. 16A, the pixel of the display device according to the embodiment includes a transistor 85 1, a capacitor 852 having a function as a storage capacitor of the pixel, and a transistor 853. and a light-emitting element 854.

[0229] The transistor 851 has a gate terminal electrically connected to a scanning line 855 and a first terminal electrically connected to a signal line. It is electrically connected to line 856.

[0230] One terminal of the capacitor 852 is electrically connected to the second terminal of the transistor 851. The other terminal is electrically connected to a low power supply potential line.

[0231] The gate terminal of the transistor 853 is connected to the second terminal of the transistor 851 and the capacitor 85 2, and the first terminal is electrically connected to the low power supply potential line.

[0232] The light-emitting element 854 has a first terminal electrically connected to the second terminal of the transistor 853 and a third terminal electrically connected to the second terminal of the transistor 853. Two terminals are electrically connected to a high power supply potential line.

[0233] When a signal is input to a pixel, the pixel to which data is written is first selected. In the pixel, the transistor 851 is turned on by a scanning signal input from a scanning line 855. A video signal (also called a data signal) having a predetermined voltage value is output from the signal line 856. This is input to the gate terminal of the transistor 853 .

[0234] The transistor 853 is turned on by a potential corresponding to a data signal input to the gate terminal. At this time, the light emitting element 854 is turned on or off. A current flows according to the applied voltage, and the light emitting element 854 emits light with a brightness according to the amount of current flowing. In addition, the gate voltage of the transistor 853 is held for a certain period of time by the capacitor 852. Therefore, the light emitting element 854 maintains the light emitting state for a certain period of time.

[0235] In addition, when the data signal input to the pixel from the signal line 856 is in digital format, the pixel The light emission state is controlled by switching the transistor on and off. The gradation can be displayed using the area gradation method or the time gradation method. The pixel is divided into multiple sub-pixels, and each sub-pixel is configured as shown in Figure 16(A) to independently store data. This is a driving method that displays gray scales by driving the liquid crystal based on a signal. This method is a driving method that performs gray scale display by controlling the period during which a pixel emits light.

[0236] Light-emitting elements have a higher response speed than liquid crystal elements, so they are more suitable for time gray scale methods than liquid crystal elements. When using the time gray scale method to display, one frame period is divided into multiple sub-frame periods. Then, in accordance with the video signal, the light emitting elements of the pixels are turned on in each sub-frame period. By dividing one frame period into multiple subframe periods, The total length of time that pixels actually emit light during a frame is controlled by the video signal. This allows for gradation to be displayed.

[0237] Next, the configuration of the light emitting element will be described with reference to FIGS. 16(B) to 16(D). Let us take the case where the transistor 853 is an n-channel type as an example and consider the cross-sectional structure of the pixel. The transistor 853 used in the light-emitting display device of FIGS. is a driving transistor.

[0238] The light emitting element 854 has at least one of the anode and cathode transparent to extract light. Then, the transistor and the light-emitting element are formed on the substrate, and the light-emitting element is formed on the opposite side of the substrate. Top emission, which extracts light from the surface on the substrate side, bottom emission, which extracts light from the surface on the substrate side, There is a light emitting element with a double-sided emission structure in which light is emitted from the opposite side of the pixel. It can be applied to any light emitting element with any emission structure.

[0239] A light emitting element with a top emission structure will be described with reference to FIG.

[0240] In FIG. 16B, a transistor 853 serving as a driving transistor is an n-channel transistor. This shows a cross-sectional view of a pixel when light emitted from a photoelement 854 exits to the anode 7005 side. In FIG. 16B, the cathode 7003 of the light emitting element 854 and the transistor serving as a driving transistor are The cathode 7003 is electrically connected to the light-emitting layer 7004, and the anode 7005 is electrically connected to the light-emitting layer 7004. The cathode 7003 is a conductive layer that has a small work function and reflects light. Various materials can be used, such as Ca, Al, CaF, MgAg, and A. The light-emitting layer 7004 may be composed of a single layer or a plurality of layers. It may be configured so that the layers are stacked. On the cathode 7003, an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer are formed in this order. It is not necessary to provide all of these layers. The anode 7005 is a transparent material that transmits light. The insulating film is formed using a conductive material having optical properties, for example, an indium oxide film containing tungsten oxide. oxide, indium zinc oxide with tungsten oxide, indium oxide with titanium oxide Indium tin oxide (ITO) ), indium zinc oxide, indium tin oxide with silicon oxide added, etc. Any conductive material may be used.

[0241] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 forms the light-emitting element 854. In the case of the pixel shown in FIG. 16(B), the light emitted from the light emitting element 854 is As shown, the light is emitted toward the anode 7005.

[0242] Next, a light-emitting element with a bottom emission structure will be described with reference to FIG. 853 is an n-channel type, and light emitted from the light-emitting element 854 is emitted to the cathode 7013 side. 16C shows a cross-sectional view of a pixel in the case where the transistor 853 is electrically connected to the A cathode 7013 of the light-emitting element 854 is formed on the light-transmitting conductive layer 7017. On the cathode 7013, a light-emitting layer 7014 and an anode 7015 are laminated in this order. When the 015 has a light-transmitting property, a shielding layer for reflecting or blocking light is applied to cover the anode. The cathode 7013 may be formed by a method similar to that shown in FIG. Various conductive materials with small electrical conductivity functions can be used. is set to a level that allows light to pass through (preferably, about 5 nm to 30 nm). For example, An aluminum layer having a thickness of 1000 nm can be used as the cathode 7013. The optical layer 7014 may be composed of a single layer, or may be composed of a plurality of layers stacked together, as in FIG. 16(B). The anode 7015 does not need to transmit light. However, similarly to FIG. 16B, the light-transmitting conductive material can be used. The shielding layer 7016 can be made of, for example, a metal that reflects light. There is no limitation, and for example, a resin to which a black pigment is added can also be used.

[0243] The region where the light-emitting layer 7014 is sandwiched between the cathode 7013 and the anode 7015 is the light-emitting element 854 In the case of the pixel shown in FIG. 16(C), the light emitted from the light emitting element 854 is As shown by the mark, the light is emitted toward the cathode 7013 side.

[0244] Next, a light emitting device with a dual emission structure will be described with reference to FIG. 16(D). ) is formed on a light-transmitting conductive layer 7027 electrically connected to the transistor 853. The cathode 7023 of the optical element 854 is formed as a film, and the light-emitting layer 7024 is formed on the cathode 7023. 7025 are stacked in order. The cathode 7023 is a work function, as in the case of FIG. 16(B). Various conductive materials can be used as long as the number of conductive materials is small. However, the film thickness is For example, an aluminum layer having a thickness of 20 nm is used as the cathode 702. 3. The light-emitting layer 7024 can be formed as a single It may be composed of one layer or a plurality of layers stacked together. The anode 7025 is made of a light-transmitting conductive material, similar to that shown in FIG. It can be formed by

[0245] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 is the light-emitting element 8. In the case of the pixel shown in FIG. 16(D), the light emitted from the light emitting element 854 is , and is emitted to both the anode 7025 side and the cathode 7023 side as shown by the arrows.

[0246] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements may also be used as the light-emitting element. An EL element may also be provided.

[0247] In this embodiment, a transistor (driving transistor) that controls driving of a light-emitting element is used. In the above example, a driving transistor (also called a driving transistor) and a light-emitting element are electrically connected. A current control transistor may be connected between the light emitting element and the light emitting element.

[0248] Next, the appearance and cross section of a light-emitting display device (also referred to as a light-emitting panel) in this embodiment will be described. This will be explained with reference to FIG. 17. FIG. 17(A) shows a transistor formed on a first substrate. FIG. 10 is a top view of a light-emitting display device in which a capacitor and a light-emitting element are sealed between a second substrate and the capacitor and a light-emitting element by a sealant. 17(B) corresponds to a cross-sectional view taken along line HI in FIG. 17(A).

[0249] A pixel portion 4502, a signal line driver circuit 4503a, and a signal line driver circuit 4504a are provided on a first substrate 4501. A sealant 450 is applied to surround the gate driver circuits 4503a and 4503b, and the scanning line driver circuits 4504a and 4504b. 5. In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. That is, the pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit The paths 4504a and 4504b are formed by a first substrate 4501, a sealant 4505, and a second substrate 4502. 4506 and the filler 4507 are sealed together. Highly airtight and low outgassing protective film (laminating film, UV curing It is preferable to package (enclose) the product in a resin film or a cover material.

[0250] In addition, a pixel portion 4502 and a signal line driver circuit 4503a are provided over the first substrate 4501. , 4503b, and the scanning line driver circuits 4504a, 4504b have a plurality of transistors. 17B, ​​a transistor 4510 included in a pixel portion 4502 and a signal line The transistors 4509 and 4555 included in the driver circuit 4503a are shown as examples. are.

[0251] The transistors 4509, 4510, and 4555 each include an oxide semiconductor layer as a semiconductor layer. Any of the transistors described in Embodiments 2 to 4 having high reliability is used. In this embodiment, the transistors 4509, 4510, and 4555 are n-channel transistors. The transistors 4509, 4510, and 4555 are of the same type. An insulating layer 4542 is formed on the insulating layer 4544, and the insulating layer 4542 and A conductive layer 4540 is provided over the transistor 4509 with an insulating layer 4544 interposed therebetween. 4540 functions as a second gate terminal.

[0252] In the pixel portion 4502, a planarizing insulating layer 4545 is provided over the insulating layer 4542. An insulating layer 4543 is provided over the planarization insulating layer 4545 .

[0253] Further, 4511 corresponds to a light-emitting element, and a first pixel electrode which is included in the light-emitting element 4511 is The electrode 4517 is electrically connected to the second terminal of the transistor 4510. The optical element 4511 is configured by a first electrode 4517, a light-emitting layer 4512, and a second electrode 4513. Although it has a stacked structure, it is not limited to the structure shown in this embodiment. The configuration of the light emitting element 4511 can be changed appropriately according to the direction of emitted light.

[0254] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode 4517, and the sidewall of the opening is It is preferable to form the inclined surface so that the inclined surface has a continuous curvature.

[0255] The light-emitting layer 4512 may be composed of a single layer or a plurality of layers stacked. It doesn't matter whether it's

[0256] The second electrode is provided to prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light emitting element 4511. A protective layer may be formed on the electrode 4513 and the partition wall 4520. The protective layer may be a silicon nitride layer. , silicon nitride oxide layer, DLC (Diamond-like Carbon) layer, etc. It is possible.

[0257] In addition, signal line driver circuits 4503a and 4503b, scanning line driver circuits 4504a and 4504 b, or various signals and voltages given to the pixel portion 4502 are applied to the FPC 4518a, 451 It is supplied by 8b.

[0258] In the light-emitting display device shown in FIG. 17, the connection terminal electrode 4515 is The terminal electrode 4516 is formed from the same conductive film as the first electrode 4517. The source and drain electrodes of the transistors 4509, 4510, and 4555 are The conductive layer is formed from the same conductive film as the conductive layer that functions as the conductive layer.

[0259] The connection terminal electrode 4515 is connected to a terminal of the FPC 4518a and an anisotropic conductive layer 4519. are electrically connected via

[0260] The substrate positioned in the direction in which light is extracted from the light emitting element 4511 must be transparent. In this case, the substrate may be glass, plastic, polyester film, or A light-transmitting material such as an acrylic film is used.

[0261] In addition to inert gases such as nitrogen and argon, filler 4507 can also be used with ultraviolet curing. Resin or thermosetting resin can be used, such as PVC (polyvinyl chloride), acrylic , polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or E VA (ethylene vinyl acetate) can be used. In this embodiment, the filler 450 Nitrogen is used as 7.

[0262] If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) may be attached to the light-emitting surface of the light-emitting element. ), retardation plates (λ / 4 plate, λ / 2 plate), color filters, and other optical films are provided as needed. Alternatively, an anti-reflection film may be provided on the polarizing plate or the circular polarizing plate. This allows for anti-glare treatment to be applied, which can diffuse reflected light and reduce glare.

[0263] Signal line driver circuits 4503a and 4503b, and scanning line driver circuits 4504a and 4504b The semiconductor layer is formed on a separately prepared substrate using a single crystal semiconductor layer or a polycrystalline semiconductor layer. Alternatively, only the signal line driver circuits 4503a and 4503b may be mounted. At least a part of the scanning line driver circuits 4504a and 4504b, or only a part of the scanning line driver circuits 4504a and 4504b, are separately formed. The present embodiment is not limited to the configuration of FIG.

[0264] Through the above steps, a light-emitting display device (display panel) can be manufactured.

[0265] The contents of this embodiment or a part of the contents thereof may be the same as the contents of other embodiments or a part of the contents thereof. It can be freely combined with other parts.

[0266] (Embodiment 8) In this embodiment, as an example of the display device shown in the fifth embodiment, Electronic paper that can be displayed without wiring will be explained with reference to FIGS. 18 and 19. do.

[0267] The electronic paper of this embodiment has a period during which an image is retained (image retention period) and a period during which the image is retained (image retention period). During this image retention period, Therefore, the electronic paper does not require power to maintain the image display. This is a display device with low power consumption.

[0268] The electronic paper is a display element that can control the display by applying a voltage. The display includes an element that maintains the display when no power is applied. Electrophoretic element, particle rotation element using twist ball, charged toner particle movement elements using electronic liquid powder (registered trademark), magnetic migration elements that express gradation through magnetism, Examples of the element include a moving element, a liquid moving element, a light scattering element, and a phase change element. As an example of electronic paper, electronic paper having an electrophoretic element will be described.

[0269] The electrophoretic element includes first particles that are positively charged and second particles that exhibit a color different from that of the first particles. and a microcapsule in which negatively charged second particles and a liquid solvent are enclosed. When a voltage is applied to the electrophoretic element, Display is achieved by assembling the first particles or the second particles on one side of the black capsule. When no voltage is applied to the electrophoretic display element, the first particles The first and second particles do not move. In other words, the display of the electrophoretic element is maintained. The electrophoretic element is composed of positively or negatively charged particles and a dissolving material that exhibits a different color from the particles. It is also possible to use an element having microcapsules in which a liquid medium is enclosed.

[0270] The positively or negatively charged particles enclosed in the microcapsules include conductive particles. Materials for semiconductors, insulators, semiconductors, magnetic materials, liquid crystal materials, ferroelectric materials, electroluminescent materials a material selected from the group consisting of a luminescent material, an electrochromic material, and a magnetophoretic material; A composite material of these may be used.

[0271] Next, an example of the structure of electronic paper in this embodiment will be described with reference to FIG. FIG. 18(A) is a circuit diagram of a pixel of the electronic paper, and FIG. 18(B) is a circuit diagram of the pixel. 18(C) is a cross-sectional view taken along line AB in FIG. 18(B).

[0272] In the pixel of the electronic paper of this embodiment, the gate terminal is electrically connected to the scanning line 630, A transistor 601 having a first terminal electrically connected to a signal line 631 and a transistor The other terminal is electrically connected to the common potential line. a capacitor 602 connected to the second terminal of the transistor 601 and a capacitor 60 2, and the other terminal is electrically connected to a common potential line. In this embodiment, the common electrode Place (V com ) can be ground potential or 0V.

[0273] The pixel has a structure including a substrate 600 and a transistor 6 601 and the capacitor 602, and an electric field provided on the transistor 601 and the capacitor 602. The electrophoretic device 603 has a substrate 604 provided on the electrophoretic device 603 (FIG. 18( 18(B) and (C). Note that the electrophoretic element 603 is omitted in FIG. 18(B).

[0274] The transistor 601 includes a conductive layer 610 electrically connected to a scan line 630 and a conductive layer 6 10, an insulating layer 611 on the insulating layer 611, a semiconductor layer 612 on the semiconductor layer 612, and a signal The conductive layer 613 and the conductive layer 614 are electrically connected to the line 631. The conductive layer 610 functions as a gate terminal, and the insulating layer 611 functions as a gate insulating layer. The conductive layer 613 functions as a first terminal, and the conductive layer 614 functions as a second terminal. The conductive layer 610 is a part of the scanning line 630, and the conductive layer 613 is a part of the signal line 631. It can also be expressed as being.

[0275] The capacitor 602 is electrically connected to the conductive layer 614, the insulating layer 611, and the common potential line 632. The conductive layer 614 functions as one terminal. The insulating layer 611 functions as a dielectric and the conductive layer 615 functions as the other terminal. The conductive layer 615 can also be expressed as a part of the common potential line 632 .

[0276] The electrophoretic element 603 is electrically connected to the conductive layer 614 through an opening provided in the insulating layer 620. A pixel electrode 616 electrically connected to the conductive layer 615 and a counter electrode 617 to which the same potential as that of the conductive layer 615 is applied are provided. and a layer 618 containing charged particles provided between the pixel electrode 616 and the counter electrode 617. The pixel electrode 616 functions as one terminal, and the counter electrode 617 It functions as the other terminal.

[0277] The electronic paper of this embodiment controls the voltage applied to the layer 618 containing charged particles. By doing so, the movement of the charged particles dispersed in the layer 618 containing the charged particles can be controlled. In addition, in the electronic paper of this embodiment, the counter electrode 617 and the substrate 604 are transparent. That is, the display device of this embodiment has a reflective display in which the substrate 604 side is the display surface. It is a display device.

[0278] Materials applicable to each component of the electronic paper of this embodiment are listed below.

[0279] The substrate 600 may be a semiconductor substrate (for example, a single crystal substrate or a silicon substrate), an SOI substrate, or the like. , a glass substrate, a quartz substrate, a conductive substrate with an insulating layer on its surface, or a plastic substrate , a laminated film, paper containing a fibrous material, or a flexible substrate such as a base film Examples of glass substrates include barium borosilicate glass and aluminoborosilicate glass. Acid glass or soda lime glass. An example of a flexible substrate is polyethylene. Polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone Plastics such as polystyrene (PES) or flexible synthetic resins such as acrylic etc.

[0280] The conductive layer 610, the conductive layer 615, the scanning line 630, and the common potential line 632 are made of aluminum. Al (Al), Copper (Cu), Titanium (Ti), Tantalum (Ta), Tungsten (W), Select from molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc). The elements mentioned above, alloys containing the elements mentioned above, or nitrides containing the elements mentioned above A laminated structure of these materials can also be applied.

[0281] The insulating layer 611 may be made of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, or silicon nitride. Insulators such as silicon, aluminum oxide, and tantalum oxide can be used. A laminated structure of these materials can also be applied. The composition of the gas is such that the oxygen content is higher than the nitrogen content, and the oxygen concentration ranges from 55 to 65%. atomic %, nitrogen 1-20 atomic %, silicon 25-35 atomic %, hydrogen 0.1-10 atomic % range, each element is contained at an arbitrary concentration so that the total is 100 atomic %. Silicon nitride oxide is a material that contains more nitrogen than oxygen. The concentration ranges are 15 to 30 atomic % for oxygen, 20 to 35 atomic % for nitrogen, and 25 to 35 atomic % for silicon. 35 atomic %, hydrogen in the range of 15 to 25 atomic %, each so that the total is 100 atomic % It refers to a substance that contains an element at any concentration.

[0282] The semiconductor layer 612 is made of a periodic material such as silicon (Si) or germanium (Ge). Table 14 Materials with Group 14 Elements as Main Components, Silicon Germanium (SiGe) or Ga Compounds such as GaAs, zinc oxide (ZnO) or indium (In) and oxides such as zinc oxide containing gallium (Ga), or organic compounds that exhibit semiconducting properties. Any semiconductor material can be used. The structure can also be applied.

[0283] The conductive layer 613, the conductive layer 614 and the signal line 631 are made of aluminum (Al), copper ( Cu), titanium (Ti), tantalum (Ta), tungsten (W), molybdenum (Mo) , chromium (Cr), neodymium (Nd), scandium (Sc), or Applying an alloy containing the above-mentioned elements or a nitride containing the above-mentioned elements It is also possible to apply a laminated structure of these materials.

[0284] The insulating layer 620 may be made of silicon oxide, silicon oxynitride, silicon nitride, or silicon nitride oxide. Insulators such as silicon oxide, aluminum oxide, and tantalum oxide can be used. Also, polyimide, polyamide, polyvinylphenol, benzocyclobutene, acrylic or or organic materials such as epoxy, siloxane materials such as siloxane resin, or oxazole resin. It is also possible to use a siloxane material containing a Si-O-Si bond. Siloxane has a skeletal structure made up of bonds between silicon (Si) and oxygen (O). The substituents include organic groups (e.g., alkyl groups, aromatic hydrocarbons) and fluoro groups. The organic group may have a fluoro group.

[0285] The pixel electrode 616 may be made of aluminum (Al), copper (Cu), titanium (Ti), or titanium. Ta (Ta), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium ( Elements selected from Nd, scandium (Sc), or alloys containing the above elements Alternatively, nitrides containing the above-mentioned elements can be used. Furthermore, a laminated structure of indium oxide containing tungsten oxide can be applied. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Indium tin oxide containing titanium dioxide, indium tin oxide, indium zinc oxide, acid By using a conductive material with light transmission such as indium tin oxide doped with silicon dioxide, It can also be done as follows.

[0286] The charged particles contained in the layer 618 containing charged particles include positively charged particles such as acid. Titanium dioxide and carbon black can be used as negatively charged particles. Electrical materials, insulating materials, semiconductor materials, magnetic materials, liquid crystal materials, ferroelectric materials, electro a material selected from the group consisting of luminescent materials, electrochromic materials, and magnetophoretic materials, Alternatively, a composite material of these may be used.

[0287] The counter electrode 617 is made of indium oxide containing tungsten oxide, tungsten oxide, Indium zinc oxide containing titanium oxide, Indium oxide containing titanium oxide Indium tin oxide, Indium tin oxide, Indium zinc oxide, Silicon oxide added A light-transmitting conductive material such as indium tin oxide can be used.

[0288] The substrate 604 may be made of barium borosilicate glass, aluminoborosilicate glass, or The substrate is made of glass such as soda lime glass, or polyethylene terephthalate (PET). Any light-transmitting substrate, typified by any flexible substrate, can be used.

[0289] The electronic paper of this embodiment can be used in any field of electronics as long as it displays information. For example, electronic paper can be used to create electronic books (e-books). , posters, in-car advertisements on trains and other vehicles, and on various cards such as credit cards. An example of an electronic device is shown in Figure 19. Figure 19 shows an electronic book. An example of 2700 is shown.

[0290] As shown in FIG. 19, the electronic book 2700 has two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are integrated by a shaft 2711. The shaft 2711 can be used as an axis for opening and closing operations. This allows the device to operate like a paper book.

[0291] The housing 2701 incorporates a display unit 2705, and the housing 2703 incorporates a display unit 2707. The display unit 2705 and the display unit 2707 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display (display 2705 in FIG. 19) and An image can be displayed on the display unit (display unit 2707 in FIG. 19).

[0292] 19 shows an example in which an operation unit is provided on the housing 2701. In 2701, a power switch 2721, operation keys 2723, a speaker 2725, etc. The operation keys 2723 can be used to turn pages. It may also be configured with a keyboard, pointing device, etc. on one side. Do not install external connection terminals (earphone terminal, USB terminal, AC adapter, etc.) on the back or side of the body. and a terminal that can be connected to various cables such as a USB cable), a recording medium insertion port, etc. Furthermore, the electronic book 2700 may have a function as an electronic dictionary. The configuration may be as follows.

[0293] The electronic book 2700 may also be configured to be capable of transmitting and receiving information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. It is also possible.

[0294] The contents of this embodiment or a part of the contents thereof may be the same as the contents of other embodiments or a part of the contents thereof. It is possible to combine it with the part.

[0295] (Embodiment 9) The display devices shown in the above-described Embodiments 5 to 8 can be used in various electronic devices (game machines, The electronic device can be applied to, for example, a television device (including a television TVs, computer monitors, digital cameras, etc. digital video cameras, digital photo frames, mobile phones (mobile phones, mobile phones devices), portable game machines, personal digital assistants, audio playback devices, pachinko machines, and other large Examples include game consoles.

[0296] FIG. 20A shows an example of a television device. The television device 9600 is A display portion 9603 is incorporated in the housing 9601. The display portion 9603 displays images. In addition, the housing 9601 is supported by a stand 9605. This shows the configuration.

[0297] The television device 9600 can be operated using an operation switch provided on the housing 9601 or a separate remote control. This can be done by using the remote control operation device 9610. The channel and volume can be controlled by the -9609, and the information displayed on the display 9603 In addition, the remote control operation device 9610 can operate the video. A display unit 9607 for displaying information output from the device 9610 may be provided.

[0298] The television device 9600 includes a receiver, a modem, and the like. It is possible to receive general television broadcasts, and also to receive wired or wireless signals via a modem. By connecting to a communication network, it can be one-way (sender to receiver) or two-way It is also possible to communicate information in both directions (between a sender and a receiver, or between receivers). .

[0299] FIG. 20(B) shows an example of a digital photo frame. The display frame 9700 has a display unit 9703 built into a housing 9701. 03 can display various images, such as images taken with a digital camera. By displaying image data, it can function like a regular photo frame.

[0300] The Digital Photo Frame 9700 has an operation panel, external connection terminals (USB terminal, It is equipped with a terminal that can be connected to various cables such as USB cable, a recording medium insertion section, etc. These components may be incorporated on the same surface as the display unit, but they may also be incorporated on the side or back It is preferable to prepare for this because it improves the design. For example, Insert the memory that stores the image data taken with the digital camera into the media insertion section to create the image data. The image data can be captured and the captured image data can be displayed on the display portion 9703 .

[0301] The digital photo frame 9700 may also be configured to be able to send and receive information wirelessly. It is also possible to configure the device to wirelessly retrieve and display desired image data.

[0302] FIG. 21(A) shows a portable gaming machine, which is composed of two cabinets, a cabinet 9881 and a cabinet 9891. The housing 9881 is connected by a connecting portion 9893 so as to be openable and closable. A display unit 9883 is incorporated in the housing 9891. The portable gaming machine shown in FIG. 21(A) also includes a speaker 9884, a recording medium insertion portion 988 6, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor 9 888 (force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, Chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration (including those with the ability to measure movement, smell, or infrared rays), microphones 9889) Of course, the configuration of the portable gaming machine is not limited to the above. It is sufficient that the device is provided, and other auxiliary equipment may be provided as appropriate. The portable gaming machine shown in FIG. 21(A) is a game machine that uses a program or data recorded on a recording medium. It has the function of reading data and displaying it on the display, and communicating information wirelessly with other portable gaming machines. The functions of the portable gaming machine shown in Figure 21(A) are not limited to these. The function is not limited and can have a variety of functions.

[0303] FIG. 21(B) shows an example of a slot machine, which is a large gaming machine. 9900 has a display unit 9903 built into a housing 9901. The 9900 also has other controls such as a start lever and stop switch, and a coin slot. , speakers, etc. Of course, the configuration of the slot machine 9900 is the same as that described above. There is no limitation, and it is sufficient if the display device has at least the display device shown in the above embodiment. Other auxiliary equipment may be provided as appropriate.

[0304] FIG. 22A shows an example of a mobile phone. The mobile phone 9000 has a housing 900 1, in addition to a display unit 9002, operation buttons 9003, an external connection port 9004, It is equipped with a speaker 9005, a microphone 9006, etc.

[0305] In the mobile phone 9000 shown in FIG. 22A, when a user touches a display portion 9002 with a finger or the like, You can input information. In addition, operations such as making a phone call or sending an email can be performed by using the This can be done by touching the part 9002 with a finger or the like.

[0306] The screen of the display unit 9002 has three main modes. The first mode is for displaying images. The first mode is a display mode, and the second mode is an input mode, which is mainly used for inputting information such as characters. The third mode is a display+input mode, which is a combination of the two modes. This is the power mode.

[0307] For example, when making a call or creating an email, the display unit 9002 is used mainly for inputting characters. In this case, you can enter the character input mode and input the characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 9002. It's nice.

[0308] In addition, the mobile phone 9000 is equipped with sensors for detecting tilt, such as a gyro and an acceleration sensor. By providing a detection device having a sensor, the orientation of the mobile phone 9000 (portrait or landscape) can be determined. The screen display on the display unit 9002 can be automatically switched.

[0309] The screen mode can be switched by touching the display unit 9002 or by operating the housing 9001. The type of image displayed on the display unit 9002 can be selected by operating the create button 9003. For example, the image signal to be displayed on the display unit 9002 can be switched by If the signal is video data, it switches to display mode, if it is text data, it switches to input mode. .

[0310] In the input mode, the optical sensor of the display unit 9002 detects a signal and displays the If there is no input by touch operation on the display unit 9002 for a certain period of time, the screen mode is changed to the input mode. Alternatively, the display mode may be switched from the normal mode to the display mode.

[0311] The display unit 9002 can also function as an image sensor. By touching the palm or fingers to 002 and capturing images of palm prints and fingerprints, identity authentication can be performed. In addition, the display unit has a backlight that emits near-infrared light or a sensing element that emits near-infrared light. If a conventional light source is used, it is also possible to capture images of finger veins, palm veins, etc.

[0312] FIG. 22B is also an example of a mobile phone. The mobile phone in FIG. 22B has a housing 9411 A display device 9410 including a display portion 9412 and an operation button 9413 is provided in the housing 9401. The operation button 9402, the external input terminal 9403, the microphone 9404, the speaker 94 9405, and a communication device 9400 including a light emitting unit 9406 that emits light when an incoming call is received. The display device 9410 having a display function is connected to the communication device 9400 having a telephone function in two directions of the arrow. Therefore, the display device 9410 and the communication device 9400 are attached to each other with their short axes facing each other. Alternatively, the display device 9410 and the communication device 9400 can be attached with their long axes facing each other. In addition, when only the display function is required, the display device 9410 can be removed from the communication device 9400. The display device 9410 may be used alone. can send and receive images or input information via wireless or wired communication, respectively. It has a rechargeable battery.

[0313] The contents of this embodiment or a part of the contents thereof may be the same as the contents of other embodiments or a part of the contents thereof. It is possible to combine it with the part. [Explanation of symbols]

[0314] 101 Transistor 102 transistor 103 Transistor 104 transistors 105 transistors 106 transistors 111 Clock signal selection transistor 112 Clock signal selection transistor 113 Clock signal selection transistor 114 Clock signal selection transistor 115 Clock signal selection transistor 116 Clock signal selection transistor 121 Low power supply potential selection transistor 122 Low power supply potential selection transistor 123 Low power supply potential selection transistor 124 Low power supply potential selection transistor 125 Low power supply potential selection transistor 126 Low power supply potential selection transistor 131 Transistor 132 transistors 133 Transistor 134 transistors 201 Substrate 202 Insulation layer 207 Oxide insulating layer 211 Conductive layer 213 Oxide semiconductor layer 214a Oxide conductive layer 214b Oxide conductive layer 215a conductive layer 215b Conductive layer 215c conductive layer 217 Conductive Layer 233a Resist mask 233b Resist mask 251 transistors 252 transistors 600 boards 601 Transistor 602 Capacitor element 603 Electrophoresis element 604 Substrate 610 Conductive layer 611 Insulating layer 612 Semiconductor layer 613 Conductive Layer 614 Conductive layer 615 Conductive Layer 616 Pixel electrode 617 Counter electrode 618 Layer containing charged particles 620 Insulation Layer 630 scan lines 631 Signal Line 632 Common potential line 701 Pixel section 702 Scanning line driving circuit 703 Signal Line Driver Circuit 704 pixels 705 scan lines 706 Signal Line 804 scan lines 805 signal line 821 Transistor 822 Liquid crystal element 823 Capacitor 851 Transistor 852 Capacitor 853 Transistor 854 Light-emitting element 855 scan lines 856 signal line 900 Shift Register 901 Level Shifter 902 buffer 903 Shift Register 904 Latch Circuit 905 Latch Circuit 906 Level Shifter 907 Buffer 2000 boards 2001 Conductive layer 2002 Insulation layer 2003 Oxide semiconductor layer 2005a conductive layer 2005b conductive layer 2007 Oxide insulating layer 2008 Conductive layer 2020 Transparent conductive layer 2022 Conductive layer 2023 Conductive layer 2024 conductive layer 2028 Transparent conductive layer 2029 Transparent conductive layer 2112 Conductive layer 2132 Oxide semiconductor layer 2142a Oxide conductive layer 2142b Oxide conductive layer 2700 e-books 2701 Case 2703 Housing 2705 ​​Display section 2707 Display section 2711 Shaft 2721 Power Switch 2723 Operation Key 2725 Speaker 4501 Circuit Board 4502 Pixel section 4503a Signal line driver circuit 4503b Signal line driver circuit 4504a Scanning line driver circuit 4504b Scanning line driver circuit 4505 Sealing material 4506 board 4507 Filling material 4509 Transistor 4510 transistor 4511 Light-emitting element 4512 Light-emitting layer 4513 Electrode 4515 Connection terminal electrode 4516 Terminal electrode 4517 Electrode 4518a FPC 4518b FPC 4519 Anisotropic conductive layer 4520 Bulkhead 4540 Conductive layer 4542 Insulation layer 4543 Insulation layer 4544 Insulation layer 4545 Planarizing insulating layer 4555 transistor 7003 Cathode 7004 Light-emitting layer 7005 Anode 7013 Cathode 7014 Light-emitting layer 7015 Anode 7016 Shielding layer 7017 Conductive layer 7023 Cathode 7024 Light-emitting layer 7025 Anode 7027 Conductive layer 9000 mobile phones 9001 Case 9002 Display section 9003 Operation button 9004 External connection port 9005 Speaker 9006 Microphone 9400 Communication Equipment 9401 Housing 9402 Operation button 9403 External input terminal 9404 Microphone 9405 Speaker 9406 Light-emitting part 9410 Display device 9411 Housing 9412 Display section 9413 Operation button 9600 Television Equipment 9601 Housing 9603 Display section 9605 Stand 9607 Display section 9609 Operation Key 9610 Remote Control Machine 9700 Digital Photo Frame 9701 Housing 9703 Display section 9881 Case 9882 Display section 9883 Display section 9884 Speaker 9885 Operation Key 9886 Recording medium insertion section 9887 Connection terminal 9888 Sensor 9889 Microphone 9890 LED Lamp 9891 Case 9893 Connection section 9900 slot machine 9901 Housing 9903 Display section

Claims

1. a first transistor and a second transistor; one of a source electrode or a drain electrode of the first transistor is electrically connected to one of a source electrode or a drain electrode of the second transistor; one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the first transistor; One of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring, a first conductive film having a region disposed on an insulating surface and functioning as a gate electrode of the first transistor; a second conductive film having a region disposed on the insulating surface and functioning as a gate electrode of the second transistor; a first silicon nitride film having a region disposed on the first conductive film and a region disposed above the second conductive film; a first oxide semiconductor film of the first transistor, the first oxide semiconductor film having a region disposed above the first conductive film with the first silicon nitride film interposed therebetween; a second oxide semiconductor film of the second transistor, the second oxide semiconductor film having a region disposed above the second conductive film with the first silicon nitride film interposed therebetween; a third conductive film having a region disposed above the first oxide semiconductor film and a region disposed above the second oxide semiconductor film; a fourth conductive film having a region disposed above the first oxide semiconductor film; an oxide insulating film having a region in contact with a top surface of the first oxide semiconductor film, a region in contact with a top surface of the second oxide semiconductor film, a region in contact with a top surface of the third conductive film, and a region in contact with a top surface of the fourth conductive film; a second silicon nitride film having a region disposed above the oxide insulating film, the third conductive film functions as one of a source electrode and a drain electrode of the first transistor and one of a source electrode and a drain electrode of the second transistor, the fourth conductive film functions as the other of the source electrode and the drain electrode of the first transistor, the oxide insulating film has a region in contact with a channel formation region of the first oxide semiconductor film, the first oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap each other in a plan view; the second oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap each other in a plan view; the first conductive film and the second conductive film are spaced apart from each other, the first oxide semiconductor film and the second oxide semiconductor film are spaced apart from each other; a period in which the potential of the fourth conductive film is at a high level and a period in which the potential of the fourth conductive film is at a low level; Semiconductor device.

2. a first transistor and a second transistor; one of a source electrode or a drain electrode of the first transistor is electrically connected to one of a source electrode or a drain electrode of the second transistor; one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the first transistor; One of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring, a first conductive film having a region disposed on an insulating surface and functioning as a gate electrode of the first transistor; a second conductive film having a region disposed on the insulating surface and functioning as a gate electrode of the second transistor; a first silicon nitride film having a region disposed on the first conductive film and a region disposed above the second conductive film; a first oxide semiconductor film of the first transistor, the first oxide semiconductor film having a region disposed above the first conductive film with the first silicon nitride film interposed therebetween; a second oxide semiconductor film of the second transistor, the second oxide semiconductor film having a region disposed above the second conductive film with the first silicon nitride film interposed therebetween; a third conductive film having a region disposed above the first oxide semiconductor film and a region disposed above the second oxide semiconductor film; a fourth conductive film having a region disposed above the first oxide semiconductor film; an oxide insulating film having a region in contact with a top surface of the first oxide semiconductor film, a region in contact with a top surface of the second oxide semiconductor film, a region in contact with a top surface of the third conductive film, and a region in contact with a top surface of the fourth conductive film; a second silicon nitride film having a region disposed above the oxide insulating film, the third conductive film functions as one of a source electrode and a drain electrode of the first transistor and one of a source electrode and a drain electrode of the second transistor, the fourth conductive film functions as the other of the source electrode and the drain electrode of the first transistor, the oxide insulating film has a region in contact with a channel formation region of the first oxide semiconductor film, the first oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap each other in a plan view; the second oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap each other in a plan view; the first conductive film and the second conductive film are spaced apart from each other, the first oxide semiconductor film and the second oxide semiconductor film are spaced apart from each other; In a plan view, the third conductive film has a region overlapping with the first conductive film with the first oxide semiconductor film interposed therebetween and a region overlapping with the second conductive film with the second oxide semiconductor film interposed therebetween; a period in which the potential of the fourth conductive film is at a high level and a period in which the potential of the fourth conductive film is at a low level; Semiconductor device.

3. a first transistor and a second transistor; one of a source electrode or a drain electrode of the first transistor is electrically connected to one of a source electrode or a drain electrode of the second transistor; one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the first transistor; One of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring, a first conductive film having a region disposed on an insulating surface and functioning as a gate electrode of the first transistor; a second conductive film having a region disposed on the insulating surface and functioning as a gate electrode of the second transistor; a first silicon nitride film having a region disposed on the first conductive film and a region disposed above the second conductive film; a first oxide semiconductor film of the first transistor, the first oxide semiconductor film having a region disposed above the first conductive film with the first silicon nitride film interposed therebetween; a second oxide semiconductor film of the second transistor, the second oxide semiconductor film having a region disposed above the second conductive film with the first silicon nitride film interposed therebetween; a third conductive film having a region disposed above the first oxide semiconductor film and a region disposed above the second oxide semiconductor film; a fourth conductive film having a region disposed above the first oxide semiconductor film; an oxide insulating film having a region in contact with a top surface of the first oxide semiconductor film, a region in contact with a top surface of the second oxide semiconductor film, a region in contact with a top surface of the third conductive film, and a region in contact with a top surface of the fourth conductive film; a second silicon nitride film having a region disposed above the oxide insulating film, the third conductive film functions as one of a source electrode and a drain electrode of the first transistor and one of a source electrode and a drain electrode of the second transistor, the fourth conductive film functions as the other of the source electrode and the drain electrode of the first transistor, the third conductive film has a region in contact with the first conductive film in the opening of the first silicon nitride film, the oxide insulating film has a region in contact with a channel formation region of the first oxide semiconductor film, the first oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap each other in a plan view; the second oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap each other in a plan view; the first conductive film and the second conductive film are spaced apart from each other, the first oxide semiconductor film and the second oxide semiconductor film are spaced apart from each other; a period in which the potential of the fourth conductive film is at a high level and a period in which the potential of the fourth conductive film is at a low level; Semiconductor device.

4. a first transistor and a second transistor; one of a source electrode or a drain electrode of the first transistor is electrically connected to one of a source electrode or a drain electrode of the second transistor; one of a source electrode and a drain electrode of the first transistor is electrically connected to a gate electrode of the first transistor; One of a source electrode and a drain electrode of the first transistor is electrically connected to a first wiring, a first conductive film having a region disposed on an insulating surface and functioning as a gate electrode of the first transistor; a second conductive film having a region disposed on the insulating surface and functioning as a gate electrode of the second transistor; a first silicon nitride film having a region disposed on the first conductive film and a region disposed above the second conductive film; a first oxide semiconductor film of the first transistor, the first oxide semiconductor film having a region disposed above the first conductive film with the first silicon nitride film interposed therebetween; a second oxide semiconductor film of the second transistor, the second oxide semiconductor film having a region disposed above the second conductive film with the first silicon nitride film interposed therebetween; a third conductive film having a region disposed above the first oxide semiconductor film and a region disposed above the second oxide semiconductor film; a fourth conductive film having a region disposed above the first oxide semiconductor film; an oxide insulating film having a region in contact with a top surface of the first oxide semiconductor film, a region in contact with a top surface of the second oxide semiconductor film, a region in contact with a top surface of the third conductive film, and a region in contact with a top surface of the fourth conductive film; a second silicon nitride film having a region disposed above the oxide insulating film, the third conductive film functions as one of a source electrode and a drain electrode of the first transistor and one of a source electrode and a drain electrode of the second transistor, the fourth conductive film functions as the other of the source electrode and the drain electrode of the first transistor, the third conductive film has a region in contact with the first conductive film in the opening of the first silicon nitride film, the oxide insulating film has a region in contact with a channel formation region of the first oxide semiconductor film, the first oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap each other in a plan view; the second oxide semiconductor film is surrounded by a region where the first silicon nitride film and the second silicon nitride film overlap each other in a plan view; the first conductive film and the second conductive film are spaced apart from each other, the first oxide semiconductor film and the second oxide semiconductor film are spaced apart from each other; In a plan view, the third conductive film has a region overlapping with the first conductive film with the first oxide semiconductor film interposed therebetween and a region overlapping with the second conductive film with the second oxide semiconductor film interposed therebetween; a period in which the potential of the fourth conductive film is at a high level and a period in which the potential of the fourth conductive film is at a low level; Semiconductor device.

5. In any one of claims 1 to 4, each of the third conductive film and the fourth conductive film includes a plurality of stacked conductive films; each of the plurality of conductive films contains at least one of titanium, molybdenum, tungsten, aluminum, chromium, copper, and tantalum; Semiconductor device.

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