Imaging device and method for manufacturing imaging device

Abstract

To provide a technique suitable for achieving a reliable imaging apparatus.SOLUTION: The substrate 60, the photoelectric conversion unit 13A, and the photoelectric conversion unit 12A are arranged in this order in the thickness direction Dt. The insulating layer 91 has a region located between the photoelectric conversion portion 13A and the photoelectric conversion portion 12A in the thickness direction Dt. A through hole 91h is provided in the insulating layer 91. The plug 70 is disposed in the 91h of the through hole, is used to electrically connect the substrate 60 and the photoelectric conversion unit 12A, and includes a first conductive layer 71, a second conductive layer 72, and a third conductive layer 73. The second conductive layer 72 surrounds the first conductive layer 71 so that the second conductive layer 72 is disposed between the first conductive layer 71 and the insulating layer 91. The third conductive layer 73 is disposed between the first conductive layer 71 and the photoelectric conversion unit 13A in the thickness direction Dt, and is in contact with the first conductive layer 71 in the through hole 91h.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present disclosure relates to an imaging device and a method for manufacturing an imaging device. [Background technology]

[0002] A stacked-type imaging device has been proposed as a MOS (Metal Oxide Semiconductor) type imaging device. In the stacked-type imaging device, a photoelectric conversion layer is stacked on a semiconductor substrate. The photoelectric conversion layer generates electric charges through photoelectric conversion. The electric charges are accumulated in a charge accumulation section. A CCD (Charge Coupled Device) circuit or a CMOS (Complementary MOS) circuit is provided on the semiconductor substrate. The imaging device reads out the accumulated electric charges using the CCD circuit or the CMOS circuit. For example, Patent Document 1 discloses such an imaging device. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2005-340571 Summary of the Invention [Problem to be solved by the invention]

[0004] The present disclosure provides techniques suitable for realizing a reliable imaging device. [Means for solving the problem]

[0005] An imaging device according to one aspect of the present disclosure includes: a semiconductor substrate; a first photoelectric conversion unit; an insulating layer; a second photoelectric conversion unit; a plug; the semiconductor substrate, the first photoelectric conversion unit, and the second photoelectric conversion unit are arranged in this order in a thickness direction of the semiconductor substrate; the insulating layer has a region located between the first photoelectric conversion unit and the second photoelectric conversion unit in the thickness direction, The insulating layer has a through hole, the plug is disposed in the through hole, electrically connects the semiconductor substrate and the second photoelectric conversion unit, and has a first conductive layer, a second conductive layer, and a third conductive layer; the second conductive layer surrounds the first conductive layer such that the second conductive layer is disposed between the first conductive layer and the insulating layer; The third conductive layer is disposed between the first conductive layer and the first photoelectric conversion portion in the thickness direction, and is in contact with the first conductive layer within the through hole. [Effects of the Invention]

[0006] The technology according to the present disclosure is suitable for realizing a reliable imaging device. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a block diagram of an imaging device according to an embodiment. [Figure 2] FIG. 2 is a circuit diagram of the imaging device according to the embodiment. [Figure 3] FIG. 3 is a cross-sectional view of a pixel of the imaging device according to the embodiment. [Figure 4] FIG. 4 is a plan view of a pixel of the imaging device according to the embodiment. [Figure 5] FIG. 5 is an enlarged view of a pixel electrode having a forward tapered sidewall portion. [Figure 6] FIG. 6 is an enlarged cross-sectional view of a pixel according to the embodiment. [Figure 7] FIG. 7 is an explanatory diagram of another example of the shape of the third conductive layer. [Figure 8] FIG. 8 is an explanatory diagram of another example of the shape of the third conductive layer. [Figure 9] FIG. 9 is an explanatory diagram of another example of the shape of the third conductive layer. [Figure 10] FIG. 10 is an explanatory diagram of another example of the shape of the third conductive layer. [Figure 11] FIG. 11 is an explanatory diagram of another example of the shape of the third conductive layer. [Figure 12] FIG. 12 is an explanatory diagram of another example of the shape of the third conductive layer. [Figure 13] FIG. 13 is an explanatory diagram of the flatness of the upper surface formed by the plug and the insulating layer. [Figure 14] FIG. 14 is an illustration of a plug, detailing the second conductive layer. [Figure 15] FIG. 15 is an explanatory diagram of a barrier layer having a multi-layer structure. [Figure 16] FIG. 16 is an explanatory diagram of a manufacturing process of the imaging device according to the embodiment. [Figure 17] FIG. 17 is an explanatory diagram of a manufacturing process of the imaging device according to the embodiment. [Figure 18] FIG. 18 is an explanatory diagram of a manufacturing process of the imaging device according to the embodiment. [Figure 19] FIG. 19 is an explanatory diagram of a manufacturing process of the imaging device according to the embodiment. [Figure 20] FIG. 20 is an explanatory diagram of a manufacturing process of the imaging device according to the embodiment. [Figure 21] FIG. 21 is an explanatory diagram of a manufacturing process of the imaging device according to the embodiment. [Figure 22] FIG. 22 is an explanatory diagram of a manufacturing process of the imaging device according to the embodiment. [Figure 23] FIG. 23 is an explanatory diagram of a manufacturing process of the imaging device according to the embodiment. [Figure 24] FIG. 24 is an explanatory diagram of a manufacturing process of the imaging device according to the embodiment. [Figure 25] FIG. 25 is an explanatory diagram of a manufacturing process of the imaging device according to the embodiment. [Figure 26] FIG. 26 is an explanatory diagram of a conductive film. [Figure 27] FIG. 27 is an explanatory diagram of a manufacturing process of the imaging device according to the embodiment. [Figure 28] FIG. 28 is an explanatory diagram of a manufacturing process of the imaging device according to the embodiment. [Figure 29]FIG. 29 is an explanatory diagram of a manufacturing process of the imaging device according to the embodiment. [Figure 30] FIG. 30 is an explanatory diagram of a manufacturing process of the imaging device according to the embodiment. [Figure 31] FIG. 31 is an explanatory diagram of a manufacturing process of the imaging device according to the embodiment. [Figure 32] FIG. 32 is an explanatory diagram of a scratch defect. [Figure 33] FIG. 33 is an explanatory diagram of a manufacturing process of the imaging device according to the embodiment. [Figure 34] FIG. 34 is an explanatory diagram of a manufacturing process of the imaging device according to the embodiment. [Figure 35] FIG. 35 is an explanatory diagram of a manufacturing process of the imaging device according to the embodiment. [Figure 36] FIG. 36 is a flowchart of a method for manufacturing an imaging device according to an embodiment. [Figure 37] FIG. 37 is an explanatory diagram of a manufacturing method including CMP. [Figure 38] FIG. 38 is an explanatory diagram of a manufacturing method including CMP. [Figure 39] FIG. 39 is an explanatory diagram of a manufacturing method including CMP. [Figure 40] FIG. 40 is an explanatory diagram of a manufacturing method including CMP. DETAILED DESCRIPTION OF THE INVENTION

[0008] (How one aspect of the present disclosure was achieved) In an imaging device according to an example studied by the present inventors, a semiconductor substrate, a first photoelectric conversion section, and a second photoelectric conversion section are arranged in this order in the thickness direction of the semiconductor substrate. The insulating layer has a region located between the first photoelectric conversion section and the second photoelectric conversion section in the thickness direction. A through hole is provided in the insulating layer. A plug is arranged in the through hole. The plug electrically connects the semiconductor substrate and the second photoelectric conversion section. The plug has a first conductive layer and a second conductive layer.

[0009] Ensuring flatness by keeping the size of the step between the insulating layer and the plug within an allowable range in the region on the second photoelectric conversion unit side can improve the reliability of the imaging device. To achieve this, for example, chemical mechanical polishing (CMP) can be considered. Figures 37 to 40 are explanatory diagrams of a manufacturing method for an imaging device according to a study example, which includes CMP.

[0010] In this example, a structure 719 shown in FIG. 37 is formed. In the structure 719, a first photoelectric conversion unit 513A, an insulating layer 591, and a connection electrode 515 are arranged above a semiconductor substrate (not shown). In FIG. 37, a thickness direction Dt is the thickness direction of the semiconductor substrate. An orthogonal direction Dv is a direction orthogonal to the thickness direction Dt. The thickness direction Dt corresponds to the up-down direction. The orthogonal direction Dv corresponds to the lateral direction.

[0011] In the structure 719, the first photoelectric conversion unit 513A includes a pixel electrode 513a and a photoelectric conversion layer 513b. The first photoelectric conversion unit 513A is covered from above and from the sides by an insulating layer 591. The insulating layer 591 has an upper surface 591t and a side surface 591s. A through-hole 591h is provided in the insulating layer 591. The through-hole 591h is defined by the side surface 591s. The through-hole 591h exposes the connection electrode 515.

[0012] 38, the second conductive film 672 is formed so as to extend along not only the side surface 591s and the connection electrode 515 but also the upper surface 591t. A bottomed hole 672h is formed in the second conductive film 672 at a position overlapping with the through hole 591h in plan view.

[0013] Next, as shown in FIG. 39, first conductive portion 671 is formed on second conductive film 672 so as to not only fill bottomed hole 672h but also cover upper surface 591t of insulating layer 591 from above.

[0014] 40, portions of the second conductive film 672 and the first conductive portion 671 located outside the through hole 591h are removed by CMP. This processes the second conductive film 672 and the first conductive portion 671 into the second conductive layer 572 and the first conductive layer 571, respectively. The combination of the second conductive layer 572 and the first conductive layer 571 forms the plug 570. As can be seen from FIGS. 37 to 40, this example employing CMP makes it possible to manufacture a manufacturing device in which the step between the insulating layer 591 and the plug 570 is within the tolerance range.

[0015] However, CMP can damage the photoelectric conversion layer 513b located below the upper surfaces of the insulating layer 591 and the plug 570. Specifically, the polishing pressure of CMP generates local stress that presses the photoelectric conversion layer 513b downward. Furthermore, friction caused by CMP generates shear stress in the lateral direction within the photoelectric conversion layer 513b. The photoelectric conversion layer 513b is damaged by the local stress and shear stress. This damage can impair the reliability of the imaging device. This problem is likely to become apparent when the photoelectric conversion layer 513b contains an organic substance. In fact, the present inventors have confirmed through experiments that CMP damages the photoelectric conversion layer 513b containing an organic substance.

[0016] In light of the above, the present inventors have investigated a design for an imaging device suitable for keeping the step between the insulating layer and the plug within an acceptable range without CMP, from the viewpoint of improving the reliability of the imaging device. Also, from the same viewpoint, the present inventors have investigated a manufacturing method for an imaging device suitable for keeping the step between the insulating layer and the plug within an acceptable range without CMP.

[0017] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.

[0018] The present disclosure is not limited to the following embodiments. Appropriate modifications are possible within the scope of the effects of the present disclosure. Furthermore, one embodiment can be combined with another embodiment. In the following description, the same or similar components are denoted by the same reference numerals. Furthermore, duplicated descriptions may be omitted. Furthermore, in the following embodiments, "plan view" refers to a view perpendicular to the semiconductor substrate.

[0019] In the following embodiments, terms such as "upper," "lower," "side," "upper surface," "lower surface," and "side surface" are used to specify the relative arrangement of components, and are not intended to limit the posture of the imaging device when in use. "Side surface" is an expression intended to include the inner surface that defines a hole in a structure and constitutes the inner contour of the structure in a planar view. Also, "side surface" is an expression intended to include the outer surface that constitutes the outer contour of the structure in a planar view.

[0020] In the following embodiments, a material contained in a certain element may be described. In the description, unless otherwise contradictory, the material may be the main component of the element. The main component means the component that is contained most abundantly by mass. In one example, the main component is a component that accounts for more than 50 mass%. In one specific example, the main component is a component that accounts for more than 80 mass%.

[0021] In the following embodiments, the expression "materials are different" may be used. This expression specifically refers to materials with different compositions.

[0022] In the following embodiments, ordinal numbers such as 1st, 2nd, 3rd, etc. may be used. When an element is assigned an ordinal number, it is not necessary that there is an element of the same type with a lower number. The ordinal number can be changed as needed.

[0023] (Embodiment) The structure and function of the imaging device according to the embodiment will be described with reference to FIGS.

[0024] Fig. 1 is a block diagram of an imaging device 100 according to an embodiment. The imaging device 100 shown in Fig. 1 has a plurality of pixels 10 and a peripheral circuit 40. The plurality of pixels 10 and the peripheral circuit 40 are provided on a semiconductor substrate 60. The pixel 10 has a photoelectric conversion unit 12 and a photoelectric conversion unit 13. The photoelectric conversion unit 12 and the photoelectric conversion unit 13 convert incident light into signal charges.

[0025] In the example of FIG. 1, the pixels 10 form m rows and n columns. m and n independently represent integers of 1 or greater. In this embodiment, m and n are integers of 2 or greater. The pixels 10 are arranged, for example, two-dimensionally on the semiconductor substrate 60 to form an imaging region R1.

[0026] In the example of FIG. 1, the center of each pixel 10 is located on a lattice point of a square lattice. However, the center of each pixel 10 may also be located on a lattice point of a triangular lattice or a hexagonal lattice. Alternatively, for example, a plurality of pixels 10 may be arranged one-dimensionally. In this case, the imaging device 100 can be used as a line sensor. The number of pixels 10 included in the imaging device 100 may be multiple or may be one.

[0027] 1, the peripheral circuit 40 includes a vertical scanning circuit 42, a horizontal signal readout circuit 44, and a control circuit 46. The peripheral circuit 40 may include a voltage supply circuit that supplies a predetermined voltage to the pixels 10, etc., a signal processing circuit, or an output circuit.

[0028] In the example of FIG. 1, the peripheral circuit 40 is provided in a peripheral region R2. The peripheral region R2 is located around the imaging region R1. In the example of FIG. 1, the peripheral region R2 is an L-shaped region along two sides of the imaging region R1. The peripheral region R2 may be an annular region surrounding the periphery of the imaging region R1, or may be an elongated region along one side of the imaging region R1.

[0029] An address signal line 34 is provided corresponding to each row of pixels 10. The plurality of address signal lines 34 is connected to a vertical scanning circuit 42. The vertical scanning circuit 42 is also called a row scanning circuit. A vertical signal line 35 is provided corresponding to each column of pixels 10. The plurality of vertical signal lines 35 is connected to a horizontal signal readout circuit 44. The horizontal signal readout circuit 44 is also called a column scanning circuit.

[0030] The control circuit 46 controls the entire imaging device 100. For example, the control circuit 46 performs this control based on command data and a clock of the imaging device 100. For example, the command data and the clock are provided to the imaging device 100 from outside the imaging device 100. Typically, the control circuit 46 has a timing generator and supplies drive signals to the vertical scanning circuit 42 and the horizontal signal readout circuit 44. In FIG. 1, arrows extending from the control circuit 46 schematically represent the flow of output signals from the control circuit 46. The control circuit 46 can be realized by, for example, a microcontroller including one or more processors. The functions of the control circuit 46 may be realized by a combination of a general-purpose processing circuit and software, or by hardware specialized for such processing.

[0031] Fig. 2 is a circuit diagram of the imaging device 100 according to the embodiment. Four pixels 10A arranged in two rows and two columns are shown as representative pixels. Each of these pixels 10A is an example of the pixel 10 shown in Fig. 1.

[0032] The pixel 10A has a photoelectric conversion unit 12A. The photoelectric conversion unit 12A is an example of the photoelectric conversion unit 12 shown in FIG. 1. The pixel 10A includes a signal detection circuit 14A. The signal detection circuit 14A is electrically connected to the photoelectric conversion unit 12A. The photoelectric conversion unit 12A includes a photoelectric conversion layer. The photoelectric conversion layer is disposed above the semiconductor substrate 60. In this example, the imaging device 100 is a stacked type.

[0033] The pixel 10A has a photoelectric conversion unit 13A. The photoelectric conversion unit 13A is an example of the photoelectric conversion unit 13 shown in Fig. 1. The photoelectric conversion unit 13A and elements related to the photoelectric conversion unit 13A are associated with the vertical scanning circuit 42 and the horizontal signal readout circuit 44, similar to the photoelectric conversion unit 12A and elements related to the photoelectric conversion unit 12A. The photoelectric conversion unit 13A and elements related to the photoelectric conversion unit 13A will not be illustrated in Fig. 2 and will not be described in detail.

[0034] In the example of FIG. 2, the photoelectric conversion unit 12A of each pixel 10A is connected to an accumulation control line 31. When the imaging device 100 is operating, a predetermined voltage is applied to the accumulation control line 31. For example, positive and negative charges are generated by photoelectric conversion. The positive charges are, for example, holes. The negative charges are, for example, electrons. When the positive charges are used as signal charges, a positive voltage can be applied to the accumulation control line 31 when the imaging device 100 is operating. The positive voltage is, for example, about 10 V. The following describes an example in which holes are used as signal charges.

[0035] 2, the signal detection circuit 14A includes a signal detection transistor 22, an address transistor 24, and a reset transistor 26. The signal detection transistor 22, the address transistor 24, and the reset transistor 26 are typically field effect transistors formed on a semiconductor substrate 60 that supports the photoelectric conversion unit 12A. Unless otherwise specified, the following describes an example in which an N-channel MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is used as the transistor.

[0036] As shown in FIG. 2, the charge accumulation unit FD and the gate of the signal detection transistor 22 are electrically connected to the photoelectric conversion unit 12A. By applying a predetermined voltage to the accumulation control line 31 during operation, signal charges can be accumulated in the charge accumulation unit FD. The charge accumulation unit FD is an impurity region provided in the semiconductor substrate 60. The charge accumulation unit FD temporarily holds the signal charges generated by the photoelectric conversion unit 12A. In addition to the charge accumulation unit FD, the imaging device 100 may have a portion that temporarily holds the charges generated by the photoelectric conversion unit 12A. Examples of such portions include the pixel electrode 12a, the first conductive structure 89x, and the gate electrode 22e of the signal detection transistor 22.

[0037] One of the drain and source of the signal detection transistor 22 is connected to a power supply wiring 32. The power supply wiring 32 supplies a power supply voltage VDD to each pixel 10A when the imaging device 100 is in operation. The power supply voltage VDD is, for example, 3.3 V. The other of the drain and source of the signal detection transistor 22 is connected to a vertical signal line 35 via an address transistor 24. The signal detection transistor 22 receives the power supply voltage VDD and outputs a signal voltage according to the amount of signal charge accumulated in the charge accumulation unit FD.

[0038] The address transistor 24 is connected between the signal detection transistor 22 and a vertical signal line 35. The address signal line 34 is connected to the gate of the address transistor 24. The vertical scanning circuit 42 applies a row selection signal that controls the on / off of the address transistor 24 to the address signal line 34, thereby selecting the pixel 10A. The output of the signal detection transistor 22 of the selected pixel 10A is read out to the corresponding vertical signal line 35. The address transistor 24 may be arranged between the drain of the signal detection transistor 22 and the power supply line 32.

[0039] A load circuit 45 and a column signal processing circuit 47 are connected to each vertical signal line 35. The load circuit 45 and the signal detection transistor 22 form a source follower circuit. The column signal processing circuit 47 performs, for example, noise suppression signal processing and analog-to-digital conversion. The horizontal signal readout circuit 44 sequentially reads out signals from the multiple column signal processing circuits 47 to a horizontal common signal line 49. The load circuit 45 and the column signal processing circuit 47 may be part of the peripheral circuit 40. The noise suppression signal processing is, for example, correlated double sampling. The column signal processing circuit 47 is also called a row signal accumulation circuit.

[0040] A reset signal line 36 is provided for each row of pixels 10A. The multiple reset signal lines 36 are connected to a vertical scanning circuit 42. The vertical scanning circuit 42 applies a row selection signal to the address signal line 34 to select the pixels 10A to be reset row by row. The vertical scanning circuit 42 also applies a reset signal to the gate of the reset transistor 26 via the reset signal line 36, thereby switching the reset transistor 26 of the selected row on and off. When the reset transistor 26 is turned on, the potential of the charge storage unit FD is reset.

[0041] In this example, a feedback line 53 is provided corresponding to each column of pixels 10. One of the drain and source of the reset transistor 26 is a charge storage unit FD. The other of the drain and source of the reset transistor 26 is connected to the feedback line 53 associated with the column to which the pixel 10A including the reset transistor 26 belongs. In this example, the voltage of the feedback line 53 is supplied to the charge storage unit FD as a reset voltage that initializes the charge of the photoelectric conversion unit 12A.

[0042] In the example of FIG. 2, the imaging device 100 includes a feedback circuit 16A. The feedback circuit 16A forms a feedback path. The feedback path includes an inverting amplifier 50. An inverting amplifier 50 is provided for each column of pixels 10. For each column, a feedback line 53 associated with that column is connected to the output terminal of the inverting amplifier 50 associated with that column. The multiple inverting amplifiers 50 may be part of the peripheral circuit 40.

[0043] In each column of pixels 10, the inverting input terminal of the inverting amplifier 50 associated with that column is connected to the vertical signal line 35 associated with that column, and a reference voltage Vref is supplied to the non-inverting input terminal of the inverting amplifier 50 associated with that column during operation of the imaging device 100. By turning on the address transistor 24 and the reset transistor 26, the output of the pixel 10 can be negatively fed back via a feedback path. The negative feedback causes the voltage of the vertical signal line 35 to converge to the reference voltage Vref. In other words, the negative feedback resets the voltage of the charge storage unit FD to a voltage that causes the voltage of the vertical signal line 35 to become the reference voltage Vref. The reference voltage Vref can be any voltage between the power supply voltage and the ground voltage. The reference voltage Vref is, for example, 1 V or a positive voltage close to 1 V. The negative feedback can reduce reset noise that occurs when the reset transistor 26 is turned off.

[0044] The device structure of the pixel 10A will be described in detail with reference to Fig. 3 and Fig. 4. Fig. 3 and Fig. 4 are a cross-sectional view and a plan view, respectively, of the pixel 10A of the imaging device 100 according to the embodiment. Fig. 4 schematically shows the arrangement of each element formed on the semiconductor substrate 60 when the pixel 10A shown in Fig. 3 is viewed along the normal direction of the semiconductor substrate 60. If the pixel 10A is cut along line III-III in Fig. 4 and unfolded, the cross section shown in Fig. 3 is obtained.

[0045] 4 shows the pixel electrode 12a of the photoelectric conversion unit 12A, the pixel electrode 13a of the photoelectric conversion unit 13A, the plug 70, and the plug 86y. The plug 70 is connected to the pixel electrode 12a. The plug 86y is connected to the pixel electrode 13a. In FIG. 4, the conductive structure 89, the interlayer insulating layer 90, the gate electrode 22e, the gate electrode 24e, the gate electrode 26e, the impurity region 69, etc. are not shown.

[0046] Referring to FIG. 3, the pixel 10A includes a semiconductor substrate 60, an interlayer insulating layer 90, a conductive structure 89, a photoelectric conversion unit 13A, a connection electrode 15, an insulating layer 91, a photoelectric conversion unit 12A, and a plug 70. In FIG. 3, a thickness direction Dt is the thickness direction of the semiconductor substrate 60. An orthogonal direction Dv is a direction orthogonal to the thickness direction Dt. The thickness direction Dt corresponds to the up-down direction. The orthogonal direction Dv corresponds to the lateral direction. The semiconductor substrate 60, the interlayer insulating layer 90, the photoelectric conversion unit 13A, and the photoelectric conversion unit 12A are arranged in this order, specifically from bottom to top, with respect to the thickness direction Dt of the semiconductor substrate 60.

[0047] The interlayer insulating layer 90 covers the semiconductor substrate 60. A conductive structure 89 is disposed inside the interlayer insulating layer 90. The insulating layer 91 has a region located between the photoelectric conversion unit 13A and the photoelectric conversion unit 12A in the thickness direction Dt. The interlayer insulating layer 90 and the insulating layer 91 support the photoelectric conversion unit 12A.

[0048] A through hole 91h is provided in the insulating layer 91. The through hole 91h is defined by a side surface 91s of the insulating layer 91. The plug 70 is disposed in the through hole 91h. The plug 70 electrically connects the semiconductor substrate 60 and the photoelectric conversion unit 12A. The plug 70 includes a portion located to the side of the photoelectric conversion unit 13A. In the illustrated example, the insulating layer 91 has a film shape.

[0049] The interlayer insulating layer 90 may include multiple insulating layers. The conductive structure 89 includes a portion of each of multiple wiring layers disposed inside the interlayer insulating layer 90. The multiple wiring layers may include, for example, a wiring layer having at least one of the address signal line 34, the reset signal line 36, the vertical signal line 35, the power supply line 32, and the feedback line 53 as a portion thereof. The number of insulating layers and the number of wiring layers in the interlayer insulating layer 90 are not limited to this example and can be set arbitrarily.

[0050] The photoelectric conversion unit 12A includes a pixel electrode 12a, a photoelectric conversion layer 12b, a counter electrode 12c, and an insulating layer 12d. The pixel electrode 12a is provided on the insulating layer 91. The counter electrode 12c is disposed on the light incident side as viewed from the pixel electrode 12a. The photoelectric conversion layer 12b is disposed between the pixel electrode 12a and the counter electrode 12c. The photoelectric conversion layer 12b receives light incident through the counter electrode 12c and generates positive and negative charges by photoelectric conversion. The insulating layer 12d is provided on the counter electrode 12c. The insulating layer 12d is a transparent layer. The insulating layer 12d is a protective layer. The insulating layer 12d has a film shape.

[0051] The photoelectric conversion layer 12b includes a photoelectric conversion material. The photoelectric conversion material may include at least one of an organic material and an inorganic material. The organic material may be an organic semiconductor material. The organic semiconductor material may include at least one of a p-type organic semiconductor and an n-type organic semiconductor. The inorganic material is, for example, amorphous silicon. The photoelectric conversion film 110 may be a mixed film of organic donor molecules and acceptor molecules, a mixed film of semiconducting carbon nanotubes and acceptor molecules, or a quantum dot-containing film. The photoelectric conversion layer 12b may be a metal oxide film. The metal oxide film is, for example, a copper oxide (CuO) film. In this embodiment, the photoelectric conversion layer 12b includes an organic material. The photoelectric conversion layer 12b may include a hole-blocking film. The photoelectric conversion layer 12b may include an electron-blocking film.

[0052] Typically, the photoelectric conversion layer 12b is provided continuously across the plurality of pixels 10A. That is, the photoelectric conversion layer 12b is shared by the plurality of pixels 10A. In other words, the photoelectric conversion unit 12A provided for each pixel 10A includes a different portion of the photoelectric conversion layer 12b for each pixel 10A. However, the photoelectric conversion layer 12b may be provided separately for each pixel 10A. In the illustrated example, the photoelectric conversion layer 12b has a film shape.

[0053] The counter electrode 12c is a light-transmitting electrode. Here, the counter electrode 12c being light-transmitting means that it transmits at least a portion of light having a wavelength that can be absorbed by the photoelectric conversion layer 12b. The counter electrode 12c includes a transparent conductive material. In this embodiment, the transparent conductive material includes ITO (Indium Tin Oxide). These descriptions regarding the material of the counter electrode 12c can also be applied to the counter electrode 13c.

[0054] Typically, the counter electrode 12c is provided continuously across the plurality of pixels 10A. That is, the counter electrode 12c is shared by the plurality of pixels 10A. In other words, the photoelectric conversion unit 12A provided for each pixel 10A includes a different portion of the counter electrode 12c for each pixel 10A. However, the counter electrode 12c may be provided separately for each pixel 10A.

[0055] The insulating layer 12d functions as a sealing film. The insulating layer 12d includes, for example, aluminum oxide (Al2O3). The insulating layer 12d is formed, for example, by performing atomic layer deposition on the counter electrode 12c. In the illustrated example, the insulating layer 12d has a film shape. The explanations regarding the material, manufacturing method, and shape of the insulating layer 12d can also be applied to the insulating layer 13d.

[0056] Although not shown in FIG. 3, the counter electrode 12c is connected to the aforementioned accumulation control line 31. In this embodiment, during operation of the imaging device 100, the potential of the accumulation control line 31 is controlled to make the potential of the counter electrode 12c, for example, higher than the potential of the pixel electrode 12a. This allows the pixel electrode 12a to selectively collect positive charges out of the positive and negative charges generated by photoelectric conversion. As described above, the counter electrode 12c may be formed as a single continuous layer across multiple pixels 10A. This makes it possible to collectively apply a predetermined potential to the counter electrodes 12c of multiple pixels 10A.

[0057] In this embodiment, the pixel electrode 12a is a transparent electrode. The pixel electrode 12a includes a transparent conductive material. The transparent conductive material includes at least one selected from the group consisting of transparent conductive oxide (TCO), ITO, indium zinc oxide (IZO), aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), SnO2, and TiO2. The pixel electrode 12a may include a metal. The metal can adjust the transmittance of the pixel electrode 12a. The metal includes at least one selected from the group consisting of TCO, aluminum (Al), and gold (Au). In this embodiment, the pixel electrode 12a includes ITO. The pixel electrode 12a is spatially separated from the pixel electrodes 12a of other adjacent pixels 10, and is thereby electrically isolated from the pixel electrodes 12a of other pixels 10.

[0058] The pixel electrode 12a may have a forward tapered sidewall portion. Fig. 5 is an enlarged view of the pixel electrode 12a having a forward tapered sidewall portion 12aw. The angle θ between the bottom surface 12ab and the side surface 12as of the sidewall portion 12aw is, for example, 10° or more and 80° or less. The angle θ may be 30° or more and 60° or less.

[0059] In a typical example, a color filter and a microlens (not shown) are arranged in this order above the photoelectric conversion unit 12A. The color filter contains, for example, a photosensitive resin in which at least one selected from the group consisting of a dye and a pigment is dispersed. The microlens contains, for example, an acrylic resin material.

[0060] The photoelectric conversion unit 13A includes a pixel electrode 13a, a photoelectric conversion layer 13b, a counter electrode 13c, and an insulating layer 13d. The pixel electrode 13a is provided on an interlayer insulating layer 90. The counter electrode 13c is disposed on the light incident side as viewed from the pixel electrode 13a. The photoelectric conversion layer 13b is disposed between the pixel electrode 13a and the counter electrode 13c. The photoelectric conversion layer 13b receives light incident through the counter electrode 13c and generates positive and negative charges by photoelectric conversion. The insulating layer 13d is provided on the counter electrode 13c. The insulating layer 13d is a transparent layer. The insulating layer 13d is a protective film. The insulating layer 13d has a film shape.

[0061] In this embodiment, the material contained in the photoelectric conversion layer 13b is different from the material contained in the photoelectric conversion layer 12b. Specifically, the photoelectric conversion layer 13b and the photoelectric conversion layer 12b contain an organic substance. However, the organic substance contained in the photoelectric conversion layer 13b is different from the organic substance contained in the photoelectric conversion layer 12b.

[0062] Specifically, in this embodiment, the photoelectric conversion layer 13b contains tin phthalocyanine represented by the following general formula (1). Hereinafter, the tin phthalocyanine represented by the following general formula (1) may be simply referred to as "tin phthalocyanine." The tin phthalocyanine represented by the following general formula (1) has absorption in a wavelength range of approximately 200 nm to 1100 nm. This wavelength range partially overlaps with the near-infrared wavelength range. [ka]

[0063] In general formula (1), R 1 ~R 24are independently a hydrogen atom or a substituent. The substituent is not limited to a specific substituent. Examples of the substituent include a deuterium atom, a halogen atom, an alkyl group (including a cycloalkyl group, a bicycloalkyl group, and a tricycloalkyl group), an alkenyl group (including a cycloalkenyl group and a bicycloalkenyl group), an alkynyl group, an aryl group, a heterocyclic group (which may also be called a heterocyclic group), a cyano group, a hydroxy group, a nitro group, a carboxy group, an alkoxy group, an aryloxy group, a silyloxy group, a heterocyclic oxy group, an acyloxy group, a carbamoyloxy group, an alkoxycarbonyloxy group, an aryloxycarbonyloxy group, an amino group (including an anilino group), an ammonio group, an acylamino group, an aminocarbonylamino group, an alkoxycarbonylamino group, an aryloxycarbonylamino group, a sulfamoyl The substituent may be an amino group, an alkylsulfonylamino group, an arylsulfonylamino group, a mercapto group, an alkylthio group, an arylthio group, a heterocyclic thio group, a sulfamoyl group, a sulfo group, an alkylsulfinyl group, an arylsulfinyl group, an alkylsulfonyl group, an arylsulfonyl group, an acyl group, an aryloxycarbonyl group, an alkoxycarbonyl group, a carbamoyl group, an arylazo group, a heterocyclic azo group, an imido group, a phosphino group, a phosphinyl group, a phosphinyloxy group, a phosphinylamino group, a phosphono group, a silyl group, a hydrazino group, a ureido group, a boronic acid group (-B(OH)), a phosphato group (-OPO(OH)), a sulfato group (-OSOH), or any other known substituent.

[0064] The photoelectric conversion layer 13b may include a hole-blocking film, an electron-blocking film, an organic p-type semiconductor film, or an organic n-type semiconductor film. The material contained in the photoelectric conversion layer 13b may be the same as the material contained in the photoelectric conversion layer 12b. The same description of the material of the photoelectric conversion layer 12b can be applied to the material of the photoelectric conversion layer 13b. The same description of the material of the photoelectric conversion layer 13b can be applied to the material of the photoelectric conversion layer 12b.

[0065] In this embodiment, the material of the counter electrode 13c is the same as the material of the counter electrode 12c. The material and manufacturing method of the insulating layer 13d are the same as the material and manufacturing method of the insulating layer 12d. However, the material of the counter electrode 13c may be different from the material of the counter electrode 12c. The material of the insulating layer 13d may be different from the material of the insulating layer 12d. The manufacturing method of the insulating layer 13d may be different from the manufacturing method of the insulating layer 12d.

[0066] The pixel electrode 13a includes, for example, at least one selected from the group consisting of a metal compound and a metal. The metal compound includes, for example, a metal nitride. The metal nitride includes, for example, at least one selected from the group consisting of titanium nitride (TiN) and tantalum nitride (TaN). The metal includes at least one selected from the group consisting of copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), and aluminum (Al). The pixel electrode 13a may include a compound and / or alloy using at least two of these materials. The pixel electrode 13a may include a layered structure using at least two of these materials. The layered structure is, for example, a TiN / Ti structure. The TiN / Ti structure is a layered structure in which a layer containing titanium nitride and a layer containing titanium are bonded together.

[0067] The explanation regarding the material of the pixel electrode 13a can also be applied to the connection electrode 15. The material of the connection electrode 15 may be the same as or different from the material of the pixel electrode 13a.

[0068] The conductive structure 89 includes, for example, at least one selected from the group consisting of a metal and a metal compound. The metal includes, for example, at least one selected from the group consisting of copper and tungsten. The metal compound includes, for example, at least one selected from the group consisting of a metal nitride and a metal oxide. The conductive structure 89 may include polysilicon that has been made conductive.

[0069] The conductive structure 89 includes a first conductive structure 89x and a second conductive structure 89y. The first conductive structure 89x and the second conductive structure 89y are electrically isolated from each other.

[0070] The second conductive structure 89y is electrically connected to the pixel electrode 13a. The pixel electrode 13a is electrically connected to transistors, circuits, etc. (not shown) provided on the semiconductor substrate 60 by the second conductive structure 89y.

[0071] The first conductive structure 89x is electrically connected to the pixel electrode 12a via the connection electrode 15 and the plug 70. The pixel electrode 12a is electrically connected to transistors, circuits, etc. provided on the semiconductor substrate 60 by the first conductive structure 89x, the connection electrode 15, and the plug 70.

[0072] The first conductive structure 89x is electrically connected to the charge accumulation portion FD. The charge accumulation portion FD is provided in the semiconductor substrate 60. In the illustrated example, the charge accumulation portion FD is an n-type impurity region 67.

[0073] The first conductive structure 89x includes a plug 86x. The second conductive structure 89y includes a plug 86y. In FIG. 3, the plug 86x and the plug 86y are depicted in a simplified manner. However, as will be understood from FIG. 6 and other figures described later, in this embodiment, the plug 86x and the plug 86y have a multi-layer structure. A multi-layer structure is a structure having multiple layers. However, the plug 86x and the plug 86y may have a single-layer structure. A single-layer structure is a structure having one layer.

[0074] FIG. 4 schematically illustrates the plug 70 and the plug 86y. The shapes of the plug 70 and the plug 86y in plan view are not particularly limited. This also applies to the plug 86x, the through hole 91h, the blind hole 172h, and the blind hole 72h. Specifically, the plug 70, the plug 86x, the plug 86y, the through hole 91h, the blind hole 172h, and the blind hole 72h may be circular, rectangular, or rounded-corner rectangular in plan view. The shapes of the plug 70, the plug 86x, and the plug 86y in plan view may be the same or different from each other. The shapes of the through hole 91h and the blind hole 172h in plan view may be the same or different from each other. The shapes of the through hole 91h and the blind hole 72h in plan view may be the same or different from each other.

[0075] 3, the semiconductor substrate 60 includes a p-type semiconductor layer 61. The p-type semiconductor layer 61 is formed by ion implantation of impurities into a semiconductor layer formed by epitaxial growth. The p-type semiconductor layer 61 includes an n-type impurity region 67, an n-type impurity region 68an, an n-type impurity region 68bn, an n-type impurity region 68cn, and an n-type impurity region 68dn.

[0076] An impurity region 69 is provided in the p-type semiconductor layer 61. In the example of Fig. 3, the impurity region 69 is an element isolation region. In this embodiment, the element isolation region is an implantation isolation region. However, the element isolation region may be an STI (Shallow Trench Isolation).

[0077] An insulating layer is partially disposed on the surface of the semiconductor substrate 60 on the side of the photoelectric conversion unit 12A. In this example, this insulating layer is a gate insulating layer 65. Typically, the gate insulating layer 65 is a gate oxide film.

[0078] Gate electrodes 22e, 24e, and 26e are provided on the gate insulating layer 65. In this embodiment, the gate electrodes 22e, 24e, and 26e contain a polysilicon material. The gate electrodes 22e, 24e, and 26e contain n-type impurities implanted by ion implantation, thereby lowering their resistance and providing conductivity.

[0079] 3, the n-type impurity region 67 is electrically connected to the pixel electrode 12a via the first conductive structure 89x and the plug 70. In this example, the n-type impurity region 67 is a charge accumulation section FD, in which signal charges generated in the photoelectric conversion section 12 are accumulated.

[0080] The signal detection circuit 14A is provided on the semiconductor substrate 60. As described above, the signal detection circuit 14A includes the signal detection transistor 22, the address transistor 24, and the reset transistor .

[0081] The signal detection transistor 22 includes an n-type impurity region 68bn as one of the source and drain. The signal detection transistor 22 includes an n-type impurity region 68cn as the other of the source and drain. The signal detection transistor 22 includes a gate electrode 22e. The gate electrode 22e is provided on the gate insulating layer 65. The gate electrode 22e is electrically connected to the pixel electrode 12a via a first conductive structure 89x and a plug 70. The gate electrode 22e is also electrically connected to the n-type impurity region 67 via the first conductive structure 89x. In the illustrated example, the first conductive structure 89x includes a portion 39. The portion 39 belongs to the layer in which the address signal line 34 and the reset signal line 36 are located.

[0082] The address transistor 24 includes an n-type impurity region 68cn as one of the source and drain. The address transistor 24 includes an n-type impurity region 68dn as the other of the source and drain. The address transistor 24 includes a gate electrode 24e. The gate electrode 24e is provided on the gate insulating layer 65. The address signal line 34 is electrically connected to the gate electrode 24e. In this example, the n-type impurity region 68cn is shared between the address transistor 24 and the signal detection transistor 22. This electrically connects the address transistor 24 and the signal detection transistor 22.

[0083] The reset transistor 26 includes an n-type impurity region 67 as one of the source and drain. The reset transistor 26 includes an n-type impurity region 68an as the other of the drain and source. That is, in the example shown, one of the source and drain of the reset transistor 26 is an n-type charge storage unit FD. The reset transistor 26 includes a gate electrode 26e. The gate electrode 26e is provided on the gate insulating layer 65. The reset signal line 36 is electrically connected to the gate electrode 26e.

[0084] The n-type impurity region 68bn is electrically connected to a power supply wiring 32 serving as a source follower power supply. The power supply wiring 32 is not shown in FIG. 3. The n-type impurity region 68dn is electrically connected to a vertical signal line 35. The n-type impurity region 68an is electrically connected to a feedback line 53.

[0085] FIG. 6 is an enlarged cross-sectional view of a pixel 10A according to the embodiment. The imaging device 100 will be further described below with reference to FIG. 6. In the following description, the terms first charge and second charge may be used. The first charge is a charge generated by the photoelectric conversion layer 13b through photoelectric conversion and collected by the pixel electrode 13a. The second charge is a charge generated by the photoelectric conversion layer 12b through photoelectric conversion and collected by the pixel electrode 12a.

[0086] The pixel electrode 13a and the plug 86y are electrically connected. Therefore, the first charge is collected by the pixel electrode 13a and flows through the plug 86y. The pixel electrode 12a, the plug 70, the connection electrode 15, and the plug 86x are electrically connected. Therefore, the second charge is collected by the pixel electrode 12a and flows through the plug 70, the connection electrode 15, and the plug 86x. The combination including the pixel electrode 13a and the plug 86y is electrically isolated from the combination including the pixel electrode 12a, the plug 70, the connection electrode 15, and the plug 86x. This electrical isolation prevents the first charge and the second charge from mixing. This configuration can contribute to obtaining high-quality images.

[0087] The photoelectric conversion layer 13b performs photoelectric conversion on light in the first wavelength region. The photoelectric conversion layer 12b performs photoelectric conversion on light in the second wavelength region. In this embodiment, the center wavelength of the first wavelength region and the center wavelength of the second wavelength region are different from each other. Specifically, the center wavelength of the first wavelength region is longer than the center wavelength of the second wavelength region.

[0088] In this embodiment, the first wavelength range includes at least a portion of the near-infrared wavelength range. The near-infrared wavelength range refers to a wavelength range of 680 nm or more and 3000 nm or less. The first wavelength range may include at least a portion of the wavelength range of 700 nm or more and 2000 nm or less, or may include at least a portion of the wavelength range of 700 nm or more and 1600 nm or less. The second wavelength range includes at least a portion of the visible light wavelength range. The visible light wavelength range refers to a wavelength range of 380 nm or more and less than 680 nm.

[0089] In this embodiment, the pixel electrodes 13a and 12a contain different materials. Specific examples of the pixel electrodes 13a and 12a and their associated elements will be described below.

[0090] The plug 86y is in contact with the pixel electrode 13a. The plug 86y contains copper. The pixel electrode 13a contains a metal nitride. The metal nitride has a barrier property that suppresses the diffusion of copper. Therefore, the diffusion of copper from the plug 86y to the pixel electrode 13a can be suppressed. Specifically, the metal nitride is titanium nitride (TiN).

[0091] The pixel electrode 12a transmits light of a specific wavelength. The photoelectric conversion unit 13A converts the light of the specific wavelength into an electric signal by photoelectric conversion. This configuration makes it less likely that the pixel electrode 12a will block the light of the specific wavelength from reaching the photoelectric conversion unit 13A, thereby hindering the photoelectric conversion of the photoelectric conversion unit 13A. This configuration can contribute to obtaining high-quality images.

[0092] When the pixel electrode 12a transmits light of a specific wavelength, the layout constraints of the pixel electrode 12a can be reduced in order to ensure that light of the specific wavelength reaches the photoelectric conversion unit 13A. Taking advantage of the flexibility of the layout of the pixel electrode 12a, a configuration in which the pixel electrode 12a overlaps the photoelectric conversion unit 13A in a plan view may be adopted. This layout can suppress the recombination of positive and negative charges generated by photoelectric conversion in the photoelectric conversion unit 13A. This makes it possible to efficiently collect either the positive or negative charges in the pixel electrode 12a. This configuration can contribute to obtaining high-quality images.

[0093] The plug 86x is in contact with the connection electrode 15. The plug 86x contains copper. The connection electrode 15 contains a metal nitride. Specifically, the metal nitride is titanium nitride (TiN).

[0094] In the example of FIG. 6 , the plug 70 includes a first conductive layer 71, a second conductive layer 72, and a third conductive layer 73. In a plan view, the second conductive layer 72 surrounds the first conductive layer 71 and is disposed between the first conductive layer 71 and the insulating layer 91. The insulating layer 91 and the third conductive layer 73 are in contact with the pixel electrode 12 a. The second conductive layer 72 is in contact with the insulating layer 91 and the connection electrode 15. Specifically, the second conductive layer 72 has a bottomed cylindrical shape, and its side is in contact with the side surface 91 s of the insulating layer 91 and its bottom is in contact with the connection electrode 15. Typically, the first conductive layer 71, the second conductive layer 72, and the third conductive layer 73 include different materials.

[0095] An upper end 71u of the first conductive layer 71 is located below an upper surface 91t of the insulating layer 91. The third conductive layer 73 is disposed between the first conductive layer 71 and the photoelectric conversion unit 12A in the thickness direction Dt. The third conductive layer 73 contacts the first conductive layer 71 inside a through-hole 91h provided in the insulating layer 91. This configuration is advantageous from the perspective of realizing a reliable imaging device 100. The reason for this will be explained below.

[0096] That is, without performing CMP to make the combination of the first conductive layer 71 and the second conductive layer 72 flush with the upper surface 91t of the insulating layer 91, it is not necessarily easy to reduce the step between the combination and the insulating layer 91. Specifically, the combination may be disposed below the upper surface 91t of the insulating layer 91, causing the combination to be recessed relative to the upper surface 91t of the insulating layer 91. However, in this embodiment, the third conductive layer 73 may enter the recess and reduce the step. Therefore, the third conductive layer 73 may contribute to reducing the step between the insulating layer 91 and the plug in the region on the photoelectric conversion unit 12A side without CMP. Furthermore, the third conductive layer 73 may realize a photoelectric conversion unit 13A that is not exposed to local stress and shear stress caused by CMP and therefore suffers less damage. Therefore, the design of the imaging device 100 according to this embodiment is suitable for ensuring flatness between the insulating layer 91 and the plug 70 without CMP.

[0097] In this embodiment, the photoelectric conversion layer 13b contains an organic material. In this case, the above-mentioned benefit of realizing a photoelectric conversion unit 13A that is less damaged is easily achieved. This is because the photoelectric conversion layer 13b containing an organic material can contribute to good imaging, but tends to be easily damaged by external forces. Also, in this embodiment, the photoelectric conversion layer 12b contains an organic material.

[0098] An upper end 72u of the second conductive layer 72 is located below an upper surface 91t of the insulating layer 91. The third conductive layer 73 is located between the second conductive layer 72 and the photoelectric conversion unit 12A in the thickness direction Dt. The third conductive layer 73 contacts the second conductive layer 72 inside the through hole 91h. This configuration is advantageous from the viewpoint of realizing a reliable imaging device 100.

[0099] Specifically, the third conductive layer 73 contacts the first conductive layer 71 below the upper end 91hu of the through hole 91h. The third conductive layer 73 contacts the second conductive layer 72 below the upper end 91hu.

[0100] 6, the dotted lines indicate the vertical positions of the upper end 71u of the first conductive layer 71 and the upper end 72u of the second conductive layer 72. In the example of Fig. 6, the vertical positions of the upper ends 71u and 72u are the same. However, these positions may be different.

[0101] In the example shown in FIG. 6 , the second conductive layer 72 has a cylindrical shape with a bottom and an upward opening. The opening of the second conductive layer 72 tends to be more susceptible to damage than the bottom. However, the upper end 72u of the second conductive layer 72 is located below the upper end 91hu of the through-hole 91h provided in the insulating layer 91. This configuration makes it easier to protect the opening of the second conductive layer 72 within the through-hole 91h. This can contribute to improving the reliability of the imaging device 100. For example, during the manufacturing of the imaging device 100, a fluid such as a cleaning solution may flow along the upper surface 91t of the insulating layer 91. In one specific example, after an ashing process for the mask 75 (described later), two-fluid cleaning is performed to remove foreign matter (e.g., particles) from the upper surface 91t of the insulating layer 91. In two-fluid cleaning, a jet of water flowing along the upper surface 91t of the insulating layer 91 can cause a strong physical impact. If the upper end 72u of the second conductive layer 72 were at the same height as the upper surface 91t of the insulating layer 91, the second conductive layer 72 would be easily damaged. However, this configuration makes it easier to protect the opening of the second conductive layer 72 from such fluids. Furthermore, even if stress is applied to layers above the insulating layer 91 when the imaging device 100 is incorporated into a product such as a camera, this configuration makes it easier to protect the opening of the second conductive layer 72 from that stress.

[0102] Typically, the third conductive layer 73 is a coating that covers the first conductive layer 71. The third conductive layer 73 may be a coating that covers the first conductive layer 71 and the second conductive layer 72.

[0103] The shape of the third conductive layer 73 is not limited to the shape shown in FIG. 6. FIGS. 7 to 12 are explanatory diagrams of other examples of the shape of the third conductive layer 73. In the examples shown in FIGS. 6, 9, and 12, the upper surface of the first conductive layer 71 is planar, and the third conductive layer 73 is flat. In the examples shown in FIGS. 7 and 10, the upper surface of the first conductive layer 71 is convexly curved upward, and the third conductive layer 73 is also convexly curved upward. In the examples shown in FIGS. 8 and 11, the upper surface of the first conductive layer 71 is convexly curved downward, and the third conductive layer 73 is also convexly curved downward. In the examples shown in FIGS. 6 to 11, the first conductive layer 71 and the third conductive layer 73 are in contact with each other, and the second conductive layer 72 and the third conductive layer 73 are in contact with each other. Specifically, in the examples shown in FIGS. 6 to 8, the upper surface of the second conductive layer 72 is in contact with the third conductive layer 73. 9 to 11, the side surface of the second conductive layer 72 is in contact with the third conductive layer 73. The top surface of the second conductive layer 72 and the top surface of the third conductive layer 73 may be flush. The third conductive layer 73 may be in contact with both the top surface and the side surface of the second conductive layer 72. In the example of FIG. 12, the first conductive layer 71 and the third conductive layer 73 are in contact, while the second conductive layer 72 and the third conductive layer 73 are not in contact. In the examples of FIGS. 6 to 12, the first conductive layer 71 and the second conductive layer 72 are in contact.

[0104] In a cross section parallel to the thickness direction Dt, the dimension Lt3 of the third conductive layer 73 in the thickness direction Dt is smaller than the dimension Lv3 of the third conductive layer in the orthogonal direction Dv. The dimension Lt3 is, for example, 5 nm or more and 60 nm or less. The dimension Lt3 may be 10 nm or more and 40 nm or less. The dimension Lv3 may be, for example, 80 nm or more and 200 nm or less. The dimension Lv3 may be 90 nm or more and 120 nm or less. The ratio Lt3 / Lv3 of the dimension Lt3 to the dimension Lv3 is, for example, 1 / 40 or more and 3 / 4 or less. The ratio Lt3 / Lv3 may be 1 / 12 or more and 4 / 9 or less.

[0105] Here, the dimensions Lt3 and Lv3 will be explained with reference to FIG. 7. In a cross section parallel to the thickness direction Dt, the smallest rectangle that can accommodate the third conductive layer 73 and has a side extending in the thickness direction Dt and a side extending in the orthogonal direction Dv is defined as the evaluation rectangle Q. Here, the concept of rectangle includes a square. The dimension Lt3 is the length of the side of the evaluation rectangle Q that extends in the thickness direction Dt. The dimension Lv3 is the length of the side of the evaluation rectangle Q that extends in the orthogonal direction Dv.

[0106] In this embodiment, the plug 70 and the insulating layer 91 cooperate to form an upper surface that is highly flat. This makes it easy to ensure the flatness of elements located above the plug 70 and the insulating layer 91. This is advantageous from the perspective of realizing a reliable imaging device 100. In this embodiment, the photoelectric conversion layer 12b corresponds to the element located above. High flatness of the photoelectric conversion layer 12b is advantageous from the perspective of suppressing dark current in the photoelectric conversion layer 12b.

[0107] 13 is an explanatory diagram of the top surface formed by the plug 70 and the insulating layer 91. In the following, the terms first surface S1, second surface S2, evaluation surface Se, proximal point Ep, distal point Ed, and evaluation distance Le are used. These terms are defined as follows: The first surface S1 is a surface of the insulating layer 91 that faces away from the semiconductor substrate 60. The second surface S2 is a surface of the plug 70 that faces the opposite side to the semiconductor substrate 60. The evaluation surface Se is a portion of the combination of the first surface S1 and the second surface S2 that overlaps with the pixel electrode 12a in plan view. The proximal point Ep is the point on the evaluation surface Se that is closest to the semiconductor substrate 60. The farthest point Ed is the point on the evaluation surface Se that is farthest from the semiconductor substrate 60. The evaluation distance Le is the distance between the proximal point Ep and the distal point Ed in the thickness direction Dt.

[0108] The evaluation distance Le is reduced by the third conductive layer 73. That is, when the plug 70 includes the third conductive layer 73, the evaluation distance Le is smaller than when the third conductive layer 73 is omitted from the plug 70. In this embodiment, the evaluation distance Le is 0 nm or more and 40 nm or less. The evaluation distance Le may also be 0 nm or more and 30 nm or less.

[0109] 13, the first surface S1 of the insulating layer 91 is the top surface 91t of the insulating layer 91. The second surface S2 of the plug 70 is the top surface of the third conductive layer 73. The evaluation surface Se is the top surface.

[0110] In this embodiment, one of the proximal point Ep and the distal point Ed belongs to the third conductive layer 73, and the other of the proximal point Ep and the distal point Ed belongs to the insulating layer 91. In the example of FIG. 13 , the proximal point Ep belongs to the third conductive layer 73, and the distal point Ed belongs to the insulating layer 91.

[0111] 13, point Ex indicates the proximal point Ep when the third conductive layer 73 is omitted from the plug 70. In the example of FIG. 13, point Ex belongs to the second conductive layer 72. However, point Ex may also belong to the first conductive layer 71.

[0112] The upper end 73u of the third conductive layer 73 may be located below or above the upper surface 91t of the insulating layer 91. In terms of the thickness direction Dt, the upper end 73u may be located at the same position as the upper surface 91t of the insulating layer 91.

[0113] The characteristics, materials, dimensions, etc. of the first conductive layer 71, the second conductive layer 72, the third conductive layer 73, and the insulating layer 91 according to this embodiment will be further described below.

[0114] The first conductive layer 71 has conductivity. Therefore, the first conductive layer 71 can pass a first charge. The first conductive layer 71 includes, for example, a metal. The metal includes, for example, at least one selected from the group consisting of copper (Cu) and tungsten (W). In this embodiment, the first conductive layer 71 includes copper.

[0115] 7, the dimension Lt1 of the first conductive layer 71 in the thickness direction Dt will be described. In a cross section parallel to the thickness direction Dt of the semiconductor substrate 60, the dimension Lt1 is, for example, 300 nm or more and 2000 nm or less. The dimension Lt1 may be 600 nm or more and 1200 nm or less. The ratio Lt3 / Lt1 of the dimension Lt3 to the dimension Lt1 is, for example, 1 / 400 or more and 1 / 50 or less. The ratio Lt3 / Lt1 may be 1 / 120 or more and 1 / 15 or less. The dimension Lt1 is the length of a side extending in the thickness direction Dt of the smallest rectangle that can accommodate the first conductive layer 71 in a cross section parallel to the thickness direction Dt, the rectangle having a side extending in the thickness direction Dt and a side extending in the perpendicular direction Dv.

[0116] The second conductive layer 72 is a seed barrier film. A seed barrier film is a film including a barrier layer and a seed layer. In this embodiment, the seed layer of the second conductive layer 72 promotes the formation of the first conductive layer 71 during its formation. The barrier layer of the second conductive layer 72 prevents the material contained in the first conductive layer 71 from diffusing into the insulating layer 91 and the connection electrode 15. This diffusion prevention effect can contribute to improving the reliability of the imaging device 100. For example, if the material contained in the first conductive layer 71 diffuses into the insulating layer 91, the interlayer insulating layer 90, or the like, leakage may occur between electrical paths, such as between wirings. The diffusion may be, for example, thermal diffusion or electrodiffusion. Specifically, if there is a potential difference between the plug 70 and the pixel electrode 13a, an electric field may be applied to the region between them. If the above material is present in the portion of the region belonging to the insulating layer 91 and / or the portion belonging to the interlayer insulating layer 90, the plug 70 and the pixel electrode 13a may become conductive, resulting in a so-called leakage current. However, the above-described diffusion prevention effect makes such problems less likely to occur. Copper, in particular, easily diffuses through an insulator due to thermal diffusion, electrodiffusion, and the like. Therefore, the diffusion prevention effect is particularly effective when the first conductive layer 71 contains copper. The diffusion prevention effect is more likely to be exhibited when the barrier layer contains a metal nitride.

[0117] 14 is an explanatory diagram of the plug 70, depicting the second conductive layer 72 in detail. The second conductive layer 72 includes a seed layer 72s and a barrier layer 72b. The seed layer 72s and the barrier layer 72b have a bottomed cylindrical shape. The seed layer 72s is located within the barrier layer 72b.

[0118] The seed layer 72s includes, for example, a metal. The metal includes, for example, at least one selected from the group consisting of an elemental metal and an alloy. The elemental metal includes, for example, copper (Cu). The alloy includes, for example, a copper alloy. For example, a copper alloy includes copper and silver (Ag). Also, for example, a copper alloy includes copper and aluminum (Al). The copper alloy may include copper, aluminum, and silicon (Si). Note that a copper alloy refers to an alloy that includes copper in its composition. A cobalt alloy refers to an alloy that includes cobalt in its composition. A nickel alloy refers to an alloy that includes nickel in its composition. The same applies to other types of alloys.

[0119] The barrier layer 72b includes, for example, at least one selected from the group consisting of a metal, a metal compound, and a metal silicide. The metal may include a refractory metal. The metal compound may include a refractory metal compound. The metal silicide may include a refractory metal silicide. The melting points of the "refractory metal," "refractory metal compound," and "refractory metal silicide" are, for example, 1300°C or higher. The metal may include, for example, tantalum (Ta). The metal compound may include, for example, a metal nitride. The metal nitride may include, for example, at least one selected from the group consisting of tantalum nitride (TaN), tungsten nitride (WN), and titanium nitride (TiN). The metal silicide may include, for example, at least one selected from the group consisting of tantalum silicon nitride (TaSiN) and titanium silicon nitride (TiSiN).

[0120] The barrier layer 72b may have a single-layer structure or a multi-layer structure. The layer constituting the single-layer structure includes, for example, at least one selected from the group consisting of tantalum and tantalum nitride. FIG. 15 is an explanatory diagram of a barrier layer 72b having a multi-layer structure. In the example of FIG. 15, the barrier layer 72b includes a first layer 72b1 and a second layer 72b2. The first layer 72b1 includes, for example, tantalum. The second layer 72b2 includes, for example, tantalum nitride. In the example of FIG. 15, the first layer 72b1 is located within the second layer 72b2. Specifically, the first layer 72b1 and the second layer 72b2 are cylindrical with a bottom.

[0121] The thickness of the second conductive layer 72 is, for example, not less than 15 nm and not more than 200 nm. The thickness of the second conductive layer 72 may be, for example, not less than 30 nm and not more than 70 nm. The thickness of the seed layer 72s is, for example, not less than 5 nm and not more than 150 nm. The thickness of the seed layer 72s may be, for example, not less than 10 nm and not more than 30 nm. The thickness of the barrier layer 72b is, for example, not less than 10 nm and not more than 50 nm. The thickness of the barrier layer 72b may be, for example, not less than 20 nm and not more than 40 nm.

[0122] In this embodiment, at 25° C., the conductivity of the first conductive layer 71 is higher than the conductivity of the second conductive layer 72. The second conductive layer 72 prevents the material contained in the first conductive layer 71 from diffusing from the first conductive layer 71 to the insulating layer 91 and the connection electrode 15. This configuration makes it possible to realize a plug 70 that combines high conductivity derived from the first conductive layer 71 with barrier properties that prevent the diffusion of the material contained in the first conductive layer 71.

[0123] The third conductive layer 73 at least partially blocks the through hole 91h provided in the insulating layer 91. In a cross section perpendicular to the thickness direction Dt, the third conductive layer 73 may completely block the through hole 91h. In this embodiment, the third conductive layer 73 forms a metal cap.

[0124] The third conductive layer 73 may be a layer that suppresses electromigration of the first conductive layer 71. Suppression of electromigration is particularly effective when the first conductive layer 71 contains copper.

[0125] The third conductive layer 73 includes at least one selected from the group consisting of, for example, nickel (Ni), cobalt (Co), palladium (Pd), platinum (Pt), gold (Au), silver (Ag), ruthenium (Ru), and alloys thereof. In one specific example, the alloy includes at least one selected from the group consisting of cobalt and nickel.

[0126] In this embodiment, the third conductive layer 73 includes at least one selected from the group consisting of a cobalt alloy and a nickel alloy. The cobalt alloy includes at least one selected from the group consisting of cobalt tungsten phosphorus (CoWP), cobalt molybdenum phosphorus (CoMoP), cobalt tungsten boron (CoWB), cobalt molybdenum boron (CoMoB), cobalt phosphorus boron (CoPB), and cobalt tungsten phosphorus boron (CoWPB). The nickel alloy includes at least one selected from the group consisting of nickel tungsten phosphorus (NiWP), nickel molybdenum phosphorus (NiMoP), nickel tungsten boron (NiWB), nickel molybdenum boron (NiMoB), nickel phosphorus boron (NiPB), nickel tungsten phosphorus boron (NiWPB), and nickel phosphorus (NiP).

[0127] In this embodiment, the first conductive layer 71 and the third conductive layer 73 are plated layers. Specifically, the first conductive layer 71 is an electrolytic plated layer. The third conductive layer 73 is an electroless plated layer.

[0128] The insulating layer 91 ensures insulation between the element through which the first charge flows and the element through which the second charge flows. The insulating layer 91 includes, for example, at least one selected from the group consisting of silicon nitride and silicon oxynitride.

[0129] In this embodiment, the interlayer insulating layer 90 includes silicon oxide (SiO2).

[0130] The plug 86y includes a fourth conductive layer 86y1 and a fifth conductive layer 86y2. In a plan view, the fifth conductive layer 86y2 surrounds the fourth conductive layer 86y1 and is disposed between the fourth conductive layer 86y1 and the interlayer insulating layer 90. The fourth conductive layer 86y1 and the fifth conductive layer 86y2 are in contact with the pixel electrode 13a. The plug 86y does not necessarily include the fifth conductive layer 86y2.

[0131] The description regarding the material of the first conductive layer 71 may also apply to the fourth conductive layer 86y1. The material of the fourth conductive layer 86y1 may be the same as or different from the material of the first conductive layer 71. The description regarding the material of the second conductive layer 72 may also apply to the fifth conductive layer 86y2. The material of the fifth conductive layer 86y2 may be the same as or different from the material of the second conductive layer 72.

[0132] The plug 86x includes a sixth conductive layer 86x1 and a seventh conductive layer 86x2. In a plan view, the seventh conductive layer 86x2 surrounds the sixth conductive layer 86x1 and is disposed between the sixth conductive layer 86x1 and the interlayer insulating layer 90. The sixth conductive layer 86x1 and the seventh conductive layer 86x2 are in contact with the connection electrode 15. The plug 86x does not necessarily include the seventh conductive layer 86x2.

[0133] The description regarding the material of the first conductive layer 71 may also apply to the sixth conductive layer 86x1. The material of the sixth conductive layer 86x1 may be the same as or different from the material of the first conductive layer 71. The description regarding the material of the second conductive layer 72 may also apply to the seventh conductive layer 86x2. The material of the seventh conductive layer 86x2 may be the same as or different from the material of the second conductive layer 72.

[0134] 16 to 35 are explanatory diagrams of the manufacturing process of the imaging device 100 according to the embodiment. Fig. 36 is a flowchart of the manufacturing method of the imaging device 100 according to the embodiment. The manufacturing method of the imaging device 100 according to the present embodiment will be described below with reference to Figs. 16 to 36.

[0135] In step S11, a structure 211 shown in FIG. 16 is formed. The structure 211 includes a semiconductor substrate 60, an insulating portion 190a, and plugs 86x and 86y. The semiconductor substrate 60 is not shown, and the insulating portion 190a, plugs 86x, and plugs 86y are provided above the semiconductor substrate 60. The plugs 86x and 86y are disposed within the insulating portion 190a. The upper surfaces of the plugs 86x and 86y are exposed. The upper surfaces of the plugs 86x, 86y, and insulating portion 190a form the upper surface of the structure 211. The upper surface of the structure 211 may be planarized by CMP. The insulating portion 190a includes silicon oxide (SiO2).

[0136] 17, an electrode film 114 is formed on the upper surfaces of the plugs 86x, 86y, and the insulating portion 190a. The explanations regarding the materials of the pixel electrodes 13a and the connection electrodes 15 can also be applied to the electrode film 114.

[0137] 18, the electrode film 114 is processed into a plurality of island-shaped portions by photolithography and dry etching. In this way, the electrode film 114 is processed into the pixel electrodes 13a and the connection electrodes 15.

[0138] 19, an insulating portion 190b is formed by chemical vapor deposition (CVD) and physical vapor deposition (PVD) so as to cover the pixel electrode 13a and the connection electrode 15. The insulating portion 190b includes silicon oxide (SiO2).

[0139] Next, in step S15, as shown in FIG. 20, the insulating portion 190b is ground down to the insulating portion 190c by CMP and etch-back. The combination of the insulating portion 190a and the insulating portion 190c constitutes the interlayer insulating layer 90. In this embodiment, the grinding process continues even after the upper surfaces of the pixel electrode 13a and the connecting electrode 15 are exposed, so that a certain amount of the pixel electrode 13a and the connecting electrode 15 are ground down. This makes it possible to suppress residues of the insulating portion 190b. Furthermore, the step between the pixel electrode 13a and the connecting electrode 15 is suppressed, and the film thickness of the pixel electrode 13a and the connecting electrode 15 is made uniform.

[0140] Next, in step S16, as shown in FIG. 21, a photoelectric conversion film 113b, a counter electrode film 113c, and an insulating film 113d are formed in this order from bottom to top so as to cover the interlayer insulating layer 90, the pixel electrode 13a, and the connection electrode 15 from above.

[0141] The photoelectric conversion film 113b is formed by, for example, a wet method or a dry method. An example of the wet method is a coating method. An example of the coating method is spin coating. An example of the dry method is a vacuum deposition method. The vacuum deposition method is a method in which a layer material is vaporized by heating under vacuum and deposited on a predetermined object.

[0142] The counter electrode film 113c is formed on the photoelectric conversion film 113b. In this embodiment, the counter electrode film 113c is formed by a PVD method. The counter electrode film 113c includes ITO.

[0143] The insulating film 113d is formed on the counter electrode film 113c. In this embodiment, the insulating film 113d is formed by atomic layer deposition. The insulating film 113d contains aluminum oxide (Al2O3).

[0144] Next, in step S17, as shown in FIG. 22, the photoelectric conversion film 113b, the counter electrode film 113c, and the insulating film 113d are processed into the photoelectric conversion layer 13b, the counter electrode 13c, and the insulating layer 13d, respectively, by photolithography and dry etching. This forms the photoelectric conversion section 13A. Furthermore, the connection electrode 15 is exposed by photolithography and dry etching. In this way, the structure 217 is formed. In this embodiment, the dry etching is anisotropic dry etching.

[0145] Specifically, in step S17, a resist pattern (not shown) is formed above the insulating film 113d by photolithography. This resist pattern is formed so as not to cover the region that overlaps with the connection electrode 15 in a plan view. Next, using the resist pattern as a mask, a first-stage dry etching and a second-stage dry etching are performed in this order.

[0146] The first-stage dry etching processes the counter electrode film 113c and the insulating film 113d into the counter electrode 13c and the insulating layer 13d, respectively. The first-stage dry etching is performed using, for example, a gas containing halogen. The halogen includes, for example, at least one selected from the group consisting of fluorine, chlorine, bromine, and iodine. In one specific example, the first-stage dry etching is performed using a gas containing at least one selected from the group consisting of fluorine and chlorine.

[0147] The photoelectric conversion film 113b is processed into the photoelectric conversion layer 13b by the second-stage dry etching. The second-stage dry etching is performed using a gas containing oxygen.

[0148] Next, in step S18, as shown in FIG. 23, an insulating film 191 is formed to cover the photoelectric conversion unit 13A and the connection electrode 15. In this embodiment, the insulating film 191 is formed by plasma vapor deposition. The insulating film 191 includes at least one selected from the group consisting of silicon nitride and silicon oxynitride. In the plasma vapor deposition, at least one selected from the group consisting of a mixed gas and an oxygen compound is used as a raw material. The mixed gas includes, for example, silane (SiH4) and ammonia (NH3). The oxygen compound includes, for example, nitrous oxide (NO gas). Specifically, the insulating film 191 including silicon nitride can be formed from a mixed gas. The insulating film 191 including silicon oxynitride can be formed from a mixed gas and an oxygen compound. In this embodiment, before step S18 is performed, the structure 217 shown in FIG. 22 has a step 217s between the photoelectric conversion unit 13A and the connection electrode 15. Due to the step 217s, a recess 191c recessed downward is formed in the upper part of the insulating film 191 that overlaps with the connection electrode 15 in plan view in step S18.

[0149] Next, in step S19, as shown in FIG. 24, the insulating film 191 is processed into the insulating layer 91 by photolithography and dry etching. In this embodiment, this dry etching is anisotropic dry etching. As described above, the insulating layer 91 has through holes 91h. In step S19, the connection electrodes 15 are exposed through the through holes 91h. In step S19, the structure 219 is formed.

[0150] Specifically, in step S19, a resist pattern (not shown) is formed above the insulating film 191 by photolithography. This resist pattern is formed so as not to cover part of the region that overlaps with the connection electrode 15 in plan view. More specifically, a multi-layer resist method is used to form a resist pattern with a multi-layer structure. This reduces the effect of the recesses 191c, and a highly flat resist pattern is formed. This makes it possible to form the insulating layer 91 with high processing precision.

[0151] The resist pattern is used as a mask for dry etching. In this embodiment, the dry etching is reactive dry etching. The conditions for the dry etching, including the dry etching gas, are not particularly limited. The dry etching gas includes at least one selected from the group consisting of, for example, CF4 / CHF3 / Ar, CF4 / CHF3 / O2, and CF4 / CHF3 / Ar / O2.

[0152] 25, a conductive film 172 is formed to cover the upper surface 91t and side surface 91s of the insulating layer 91 and the upper surface 15t of the connection electrode 15. The conductive film 172 formed in step S20 has a bottomed hole 172h. Specifically, the bottomed hole 172h is defined by a portion of the conductive film 172 that covers the side surface 91s and a portion that covers the upper surface 15t. The conductive film 172 is a seed barrier film.

[0153] 26 is an explanatory diagram of the conductive film 172 formed in step S20. As shown in FIG. 26, the conductive film 172 includes a barrier film 171b and a seed film 172s. The seed film 172s is formed to cover the barrier film 172b from above and sides. In other words, the barrier film 172b is formed between the structure 219 shown in FIG. 24 and the seed film 172s.

[0154] For example, a barrier film 172b containing tantalum nitride (TaN) is formed by reactive ionization sputtering. A tantalum (Ta) target is used in this reactive ionization sputtering. The conditions for this reactive ionization sputtering are an Ar gas flow rate of 56 sccm, an N2 gas flow rate of 36 sccm, a pressure of 4 mTorr, a high-frequency power for plasma generation of 2500 W, and a substrate temperature of 100°C. The thickness of the barrier film 172b formed in step S20 is, for example, 15 nm to 35 nm.

[0155] Next, a seed film 172s is formed on the barrier film 172b by a PVD method. The thickness of the seed film 172s thus formed is, for example, 30 nm or less. The thickness of the seed film 172s may be 10 nm or less. The explanation regarding the material of the seed layer 72s can also be applied to the seed film 172s.

[0156] Next, in step S21, as shown in FIG. 27, a mask 75 is formed in the bottomed hole 172h. In this embodiment, the mask 75 is a photoresist mask. Specifically, a photoresist (not shown) is formed to cover the conductive film 172 from above and from the sides. The photoresist can be formed by coating. Then, the entire surface is exposed using a reduction projection exposure apparatus and developed. This forms the mask 75. The exposure amount of the reduction projection exposure apparatus is set so that exposure is performed under conditions near the limit at which the photoresist is exposed to light. Specifically, the exposure amount is set to a threshold value Eth. The threshold value Eth is the exposure amount at which the thickness of the photoresist rapidly decreases when the exposure amount is changed. By setting the exposure amount in this manner, the photoresist in the bottomed hole 172h remains unexposed. The remaining photoresist constitutes the mask 75. Note that the method for forming the mask 75 is not limited to a method based on a reduction projection exposure apparatus, exposure, and development. The mask 75 can also be formed in the bottomed hole 172h by applying photoresist and etching back the resist using a dry etching apparatus.

[0157] Next, in step S22, as shown in FIG. 28, a portion of the conductive film 172 is removed to process it into the second conductive layer 72. The portions of the conductive film 172 that are removed are an outside-hole portion 172o located outside the through hole 91h and an inside-hole portion 172i located inside the through hole 91h (see FIGS. 25 and 27). The outside-hole portion 172o and the inside-hole portion 172i are continuous with each other. Specifically, the outside-hole portion 172o is the entire portion of the conductive film 172 located outside the through hole 91h. The inside-hole portion 172i is a portion of the conductive film 172 located inside the through hole 91h. The above removal forms the second conductive layer 72. The second conductive layer 72 is located inside the through hole 91h. An upper end 72u of the second conductive layer 72 is located below an upper surface 91t of the insulating layer 91. The bottomed holes 72h provided in the second conductive layer 72 are part of the bottomed holes 172h provided in the conductive film 172.

[0158] In this embodiment, the outside-hole portion 172o and the inside-hole portion 172i are removed by etch-back. Specifically, the etch-back is a full-surface etch-back performed on the entire region that overlaps with the semiconductor substrate 60 in a plan view. The etch-back includes a first stage and a second stage. The first stage etch-back and the second stage etch-back are performed in this order.

[0159] The first-stage etch-back removes the portions of the seed film 172s outside the hole 172o and inside the hole 172i. This forms the seed layer 72s. The first-stage etch-back is performed, for example, by sputter etching. In sputter etching, a wafer is held between two electrically biased electrodes in a vacuum chamber. Gas is supplied into the vacuum chamber to generate plasma that bombards the wafer surface. The wafer surface is etched by ionized gas particles. The sputter etching gas includes at least one selected from the group consisting of argon (Ar), helium (He), neon (Ne), xenon (Xe), nitrogen (N), hydrogen (H), ammonia (NH), and diazene (N). The gas may include only one of these or a mixture thereof. The gas may be a pure gas. In this embodiment, the gas includes argon. That is, the sputter etching is argon sputter etching. Example conditions for argon sputter etching are: argon gas flow rate 20 sccm, temperature 20 °C, upper electrode bias power 400 kHz and 750 W, table bias power 13.56 MHz and 400 W, and process pressure approximately 0.6 mTorr.

[0160] The second-stage etch-back removes the portions of the barrier film 171b outside the hole 172o and inside the hole 172i. This forms a barrier layer 72b. In this embodiment, the second-stage etch-back is performed by ICP (Inductively Coupled Plasma) etching. The ICP etching conditions are as follows: The etching gas is a mixed gas containing CF4 and Cl2. The gas flow rates of CF4 and Cl2 are each 30 sccm. A 13.56 MHz RF (Radio Frequency) power of 500 W is applied to a coil-shaped electrode at a pressure of 1 Pa to generate plasma, and etching is performed for approximately 30 seconds. A 13.56 MHz RF power of 20 W is also applied to the substrate side, applying a substantially negative self-bias voltage.

[0161] The manufacturing method according to the study example described with reference to FIGS. 37 to 40 employs CMP. In this case, the insulating layer 591 and the second conductive layer 572 are substantially flush with each other. In contrast, in this embodiment, the conductive film 172 is processed into the second conductive layer 72 by etch-back. In this case, if processing conditions were employed such that the portions 172o of the conductive film 172 outside the holes were exactly removed, a portion of the conductive film 172 may remain on the upper surface 91t of the insulating layer 91 due to processing errors. The conductive film 172 remaining on the upper surface 91t may prevent the insulating layer 91 from achieving its intended insulating performance. Therefore, in this embodiment, processing conditions are employed such that the etch-back removes not only the portions 172o of the conductive film 172 outside the holes but also the portions 172i inside the holes—in other words, over-etching. This prevents a portion of the conductive film 172 from remaining on the upper surface 91t of the insulating layer 91. The fact that the upper end 72u of the second conductive layer 72 is located below the upper surface 91t of the insulating layer 91 may be due to a trace left when the conductive film 172 is processed into the second conductive layer 72 by etch-back instead of CMP.

[0162] Next, in step S23, as shown in FIG. 29, the mask 75 is removed from the bottomed hole 72h. In step S23, a structure 223 is formed. In this embodiment, the removal is performed by ashing. Specifically, the ashing is plasma ashing. Examples of ashing conditions are as follows: the substrate temperature is 100°C; the chamber pressure is about 200 Pa; the flow rate of oxygen gas is about 1000 sccm; and the discharge time is 10 minutes. The plasma generation source is a microwave power source. The microwave power is about 1000 W.

[0163] Next, in step S24, as shown in FIG. 30, a first conductive layer 71 is formed. In step S24, a structure 224 is formed. In this embodiment, the first conductive layer 71 contains copper. The first conductive layer 71 is formed by electrolytic plating. Specifically, a solution containing copper sulfate (CuSO4) as a main component is used as a plating solution. The structure 223 obtained in step S23 is immersed in the plating solution. As a result, copper is deposited on the seed layer 72s. The deposited copper forms the first conductive layer 71. Examples of electrolytic plating conditions are as follows: The plating solution has a composition of 250 g / liter of copper sulfate pentahydrate (CuSO4 5H2O), 180 g / liter of sulfuric acid (H2SO4), and 60 mg / liter of hydrochloric acid (HCl). The temperature of the plating solution is 25°C. The current density applied to the seed layer 72s is 5 mA / cm 2 The plating solution may contain an additive.

[0164] Due to the above-described over-etching, the upper end of the seed layer 72s is located below the upper surface 91t of the insulating layer 91. The region in which the first conductive layer 71 is formed depends on the seed layer 72s. In this embodiment, the first conductive layer 71 is formed so that its upper end is located below the upper surface 91t of the insulating layer 91. The region in which the first conductive layer 71 is formed can be adjusted by adjusting the electrolytic plating time, etc.

[0165] Next, in step S25, as shown in FIG. 31, a third conductive layer 73 is formed. This forms the plug 70. In this embodiment, the third conductive layer 73 contains a cobalt alloy. The third conductive layer 73 is formed by electroless plating. The reducing agent in the plating solution is, for example, dimethylamine borane (DMAB).

[0166] For example, the plating solution is prepared as follows: 0.01 M cobalt sulfate heptahydrate, 0.04 M citric acid, 0.5 g / L ammonium tungstate, 0.06 M DMAB, and 0.03 M ammonium dihydrogen phosphate are mixed, and the pH is adjusted to 9 using TMAH (tetramethyl ammonium hydroxide). 0.01 g / L of SPS (4,5-dithiaoctane-1,8-disulfonic acid) is added to the resulting solution as a stabilizer to improve stability. This completes the plating solution.

[0167] Meanwhile, the structure 224 obtained in step S24 is immersed in a 1:200 ammonia solution for 30 seconds. This removes copper oxide on the surface of the structure 224. The surface of the structure 224 is then rinsed with ultrapure water. This removes any residues present on the surface. The pretreated structure 224 is then immersed in the above plating solution maintained at a temperature of 90°C for 1 minute. This forms the third conductive layer 73.

[0168] Due to the above-described over-etching, the upper end 71u of the first conductive layer 71 and the upper end 72u of the second conductive layer 72 are located below the upper surface 91t of the insulating layer 91. In this embodiment, taking this into consideration, the third conductive layer 73 is formed so that the upper surface 91t of the insulating layer 91 and the upper surface of the third conductive layer 73 are substantially flush with each other. The thickness of the formed third conductive layer 73 is, for example, 40 nm. The thickness can be adjusted by the immersion time of the structure 224.

[0169] The above description of the formation of the second conductive layer 72, the first conductive layer 71, and the third conductive layer 73 should help us understand the following. That is, due to the overetching, the upper end 71u of the first conductive layer 71 and the upper end 72u of the second conductive layer 72 are located below the upper surface 91t of the insulating layer 91. This means that the combination of the first conductive layer 71 and the second conductive layer 72 is recessed downward relative to the upper surface 91t of the insulating layer 91, creating a step. However, the third conductive layer 73 can enter the recess and reduce the step. Therefore, the third conductive layer 73 can contribute to reducing the step between the insulating layer 91 and the plug in the region on the photoelectric conversion unit 12A side without CMP.

[0170] First, by avoiding the above-described CMP, the photoelectric conversion unit 13A is not exposed to local stress and shear stress resulting from CMP, and therefore, less damaged, which is advantageous from the viewpoint of improving the reliability of the imaging device 100.

[0171] Second, avoiding the CMP prevents scratch defects from being formed on the upper surface 91t of the insulating layer 91. A scratch defect is a concave defect formed by CMP. FIG. 32 is an explanatory diagram of a scratch defect 91d that may occur if the insulating layer 91 is subjected to CMP. Depending on its depth, the step formed by the scratch defect 91d may cause a crack in the photoelectric conversion layer 12b during deposition of the photoelectric conversion layer 12b. The crack may increase the dark current in the photoelectric conversion layer 12b. Therefore, avoiding the CMP is advantageous from the viewpoint of preventing a decrease in yield due to defects in the photoelectric conversion layer 12b. Furthermore, avoiding the CMP is advantageous from the viewpoint of improving the reliability of the imaging device 100.

[0172] According to the inventors' investigations, the demand for high resolution is relatively high for image components in the visible light wavelength region, but relatively low for image components in the near-infrared wavelength region. Suppressing dark current can contribute to improving resolution. In this regard, in this embodiment, the photoelectric conversion layer 12b is sensitive to light in at least a portion of the visible light wavelength region, and the photoelectric conversion layer 12b is located above the insulating layer 91. Therefore, the photoelectric conversion layer 12b is susceptible to an increase in dark current due to scratch defects on the upper surface 91t of the insulating layer 91. Therefore, in a configuration in which the photoelectric conversion layer 12b is located above the insulating layer 91, it can be particularly beneficial to prevent scratch defects from forming on the upper surface 91t of the insulating layer 91.

[0173] Next, in step S26, as shown in FIG. 33, the pixel electrode film 112a is formed so as to cover the insulating layer 91 and the third conductive layer 73 from above. In this embodiment, the pixel electrode film 112a is formed by a PVD method. The pixel electrode film 112a includes ITO. In one specific example, the pixel electrode film 112a is formed by sputtering using a mixed sintered target of indium oxide and tin oxide at an oxygen introduction rate of 3 sccm, an argon introduction rate of 600 sccm, a pressure of 0.3 Pa, and a power density of 1.5 W / cm.

[0174] The method for forming the pixel electrode film 112a containing ITO is not limited to sputtering. Examples of the PVD method for this purpose include, in addition to sputtering, an electron beam method, and a resistance heating evaporation method. Examples of the method for this purpose include, in addition to the PVD method, a chemical reaction method and a coating method. An example of the chemical reaction method is the sol-gel method. In the coating method, for example, a dispersion of indium tin oxide is applied. After forming the pixel electrode film 112a containing ITO, the pixel electrode film 112a may be subjected to UV-ozone treatment, plasma treatment, or the like.

[0175] Next, in step S27, as shown in Fig. 34, the pixel electrode film 112a is patterned by photolithography and dry etching. As a result, the pixel electrode film 112a is processed into the pixel electrode 12a. Exemplary conditions for the dry etching are a methane flow rate of 20 SCCM, an argon (Ar) flow rate of 20 SCCM, a pressure of 1.5 Pa, and a bias power of 1000 W.

[0176] The thickness of the pixel electrode 12a formed in steps S26 and S27 is, for example, 10 nm or more and 20 nm or less. By adjusting the methane flow rate and bias power in the dry etching of step S27, it is possible to form the pixel electrode 12a having a forward tapered sidewall portion 12aw as shown in FIG. 5. The forward tapered sidewall portion 12aw makes it difficult for cracks to occur in the photoelectric conversion layer 12b when the photoelectric conversion layer 12b is formed in the next step S28. This can improve the reliability of the photoelectric conversion layer 12b.

[0177] Next, in step S28, the photoelectric conversion layer 12b, the counter electrode 12c, and the insulating layer 12d are formed from bottom to top in this order so as to cover the insulating layer 91 and the pixel electrode 12a, as shown in Fig. 35. In this way, the photoelectric conversion unit 12A is formed.

[0178] In this embodiment, a photoelectric conversion layer 12b containing an organic material is formed. The photoelectric conversion layer 12b is formed by a wet method or a dry method. The wet method is, for example, a coating method. The coating method is, for example, spin coating. The dry method is, for example, a vacuum deposition method.

[0179] The description of the method for forming the counter electrode film 113c can be applied to the method for forming the counter electrode 12c, and the description of the method for forming the insulating film 113d can be applied to the method for forming the insulating layer 12d.

[0180] Although not shown, a color filter and a microlens may be formed in this order from bottom to top on the photoelectric conversion unit 12A. The color filter may be formed as an on-chip color filter by patterning, for example. The microlens may be formed as an on-chip microlens, for example.

[0181] As can be understood from the above description, the manufacturing method of this embodiment includes a step of forming a structure 219. The structure 219 includes a semiconductor substrate 60, a photoelectric conversion unit 13A, and an insulating layer 91. The photoelectric conversion unit 13A is located above the semiconductor substrate 60. The insulating layer 91 includes a region located above the photoelectric conversion unit 13A. A through-hole 91h is provided in the insulating layer 91. Specifically, the structure 219 includes a connection electrode 15. The photoelectric conversion unit 13A includes a pixel electrode 13a and a photoelectric conversion layer 13b. The step of forming the structure 219 includes a film formation step and a film etching step. The film formation step is a step of forming a photoelectric conversion film 113b so as to cover the connection electrode 15 and the pixel electrode 13a from above. The film etching step is a step of etching the photoelectric conversion film 113b to process the photoelectric conversion film 113b into the photoelectric conversion layer 13b and exposing the connection electrode 15 through the through-hole 91h. Specifically, this etching is anisotropic dry etching. An example of the structure 219 is shown in Figure 24. An example of the film formation process is shown in Figure 21. An example of the film etching process is shown in Figure 22.

[0182] The manufacturing method of this embodiment includes a step of forming a conductive film 172. The conductive film 172 extends along an upper surface 91t of the insulating layer 91 and a side surface 91s of the insulating layer 91 that defines a through hole 91h. The conductive film 172 defines a bottomed hole 172h at a position that overlaps with the through hole 91h in a plan view. Specifically, the conductive film 172 extends along the upper surface of the connection electrode 15. An example of the conductive film 172 is shown in FIG. 25 .

[0183] The manufacturing method of this embodiment includes a step of forming a mask 75 in the bottomed hole 172h. Specifically, this step includes a resist forming step and an exposure step. The resist forming step is a step of forming a photoresist so as to cover the conductive film 172 from above. The photoresist can be applied to the entire area that overlaps with the semiconductor substrate 60 in a planar view. The exposure step is a step of performing exposure so that the portion of the photoresist that constitutes the mask 75 remains. The exposure can be a full-surface exposure, that is, exposure of the entire area that overlaps with the semiconductor substrate 60 in a planar view. An example of the mask 75 is as shown in FIG. 27.

[0184] The manufacturing method of this embodiment includes a step of etching the conductive film 172 using a mask 75 to process the conductive film 172 into the second conductive layer 72. The second conductive layer 72 has a bottomed hole 72h. The second conductive layer 72 is located within the through-hole 91h. The upper end 72u of the second conductive layer 72 is located below the upper end 91hu of the through-hole 91h. Specifically, the conductive film 172 is etched back by etching using the mask 75. The etch-back can be performed on the entire region that overlaps with the semiconductor substrate 60 in a planar view. The second conductive layer 72 includes a seed layer 72s and a barrier layer 72b. The barrier layer 72b is located between the seed layer 72s and the insulating layer 91. The barrier layer 72b prevents material contained in the first conductive layer 71 from diffusing into the insulating layer 91. During the etching, portions of the conductive film 172 not covered by the mask 75 are removed, leaving portions corresponding to the second conductive layer 72. The etching is dry etching. More specifically, the etching is anisotropic dry etching. An example of the second conductive layer 72 is as shown in FIG.

[0185] The manufacturing method of this embodiment includes a step of removing the mask 75 from the bottomed hole 72h. An example of this step is shown in FIG. 29. Specifically, the mask 75 is removed by ashing. The ashing can be performed on the entire region that overlaps with the semiconductor substrate 60 in a plan view.

[0186] The manufacturing method of this embodiment includes a step of forming a first conductive layer 71 in the bottomed hole 72h. An upper end 71u of the first conductive layer 71 is located below an upper end 91hu of the through hole 91h. Specifically, in this step, the material of the first conductive layer 71 is deposited on the seed layer 72s by an electrolytic plating reaction, thereby forming the first conductive layer 71. An example of the first conductive layer 71 is shown in FIG. 30 .

[0187] The manufacturing method of this embodiment includes a step of forming a third conductive layer 73 in the through hole 91h. Specifically, in this step, the material of the third conductive layer 73 is deposited on the first conductive layer 71 by an electroless plating reaction, thereby forming the third conductive layer 73. The third conductive layer 73 contacts the first conductive layer 71 from above within the through hole 91h. An example of the third conductive layer 73 is as shown in FIG.

[0188] The manufacturing method of this embodiment includes a step of forming a photoelectric conversion unit 12A above a third conductive layer 73. The semiconductor substrate 60 and the photoelectric conversion unit 12A are electrically connected via a plug 70 including a first conductive layer 71, a second conductive layer 72, and a third conductive layer 73. An example of the photoelectric conversion unit 12A is as shown in FIG.

[0189] The manufacturing method of this embodiment does not require CMP to make the combination of the first conductive layer 71 and the second conductive layer 72 flush with the upper surface 91t of the insulating layer 91. Specifically, the manufacturing method of this embodiment does not require CMP for this purpose. During the manufacturing method, the upper end 71u of the first conductive layer 71 and the upper end 72u of the second conductive layer 72 are located below the upper surface 91t of the insulating layer 91, resulting in a depression. However, according to the manufacturing method of this embodiment, the third conductive layer 73 can enter the depression and reduce the step. Therefore, the third conductive layer 73 can contribute to reducing the step between the insulating layer 91 and the plug 70 in the region on the photoelectric conversion unit 13A side without CMP. Furthermore, the third conductive layer 73 can prevent the photoelectric conversion unit 13A from being exposed to local stress and shear stress caused by CMP, thereby reducing damage. Therefore, the manufacturing method of this embodiment can prevent the photoelectric conversion unit 13A from being exposed to local stress and shear stress caused by CMP, thereby reducing damage. Therefore, the manufacturing method of this embodiment can realize a reliable imaging device.

[0190] In the manufacturing method of this embodiment, the third conductive layer 73 is formed by electroless plating. The deposition rate of electroless plating tends to be slow. Therefore, according to the manufacturing method of this embodiment, it is easy to fine-tune the size of the third conductive layer 73 in the thickness direction Dt, and therefore the third conductive layer 73 can easily contribute to reducing the step between the insulating layer 91 and the plug 70. For example, in the manufacturing method of this embodiment, the first conductive layer 71 is formed by electrolytic plating. The deposition rate of electroless plating tends to be slower than the deposition rate of electrolytic plating. In fact, the deposition rate of the third conductive layer 73 can be made slower than the deposition rate of the first conductive layer 71.

[0191] In the manufacturing method of this embodiment, the photoelectric conversion layer 13b photoelectrically converts light in a first wavelength region. The first wavelength region includes at least a portion of the near-infrared wavelength region. The film-forming temperature of the electroless plating for forming the third conductive layer 73 is 200°C or lower. The types of photoelectric conversion layers that photoelectrically convert light in the near-infrared wavelength region are limited. For this reason, the manufacturing method for an imaging device may be restricted to sufficiently reducing the heat applied to the photoelectric conversion layer. In this regard, the above-mentioned film-forming temperature is sufficiently low. Therefore, the heat generated when forming the third conductive layer 73 is unlikely to damage the photoelectric conversion layer 13b. The film-forming temperature may be 150°C or lower, or may be 100°C or lower. As a specific example, the third conductive layer 73 containing cobalt tungsten phosphorus (CoWP) can be formed by electroless plating at a film-forming temperature of 70°C to 90°C. The third conductive layer 73 containing nickel phosphorus (NiP) can be formed by electroless plating at a film formation temperature of 70° C. to 80° C. The film formation time of the electroless plating to form the third conductive layer 73 is, for example, 60 minutes or less. The film formation time may be 45 minutes or less, or may be 30 minutes or less.

[0192] Although the imaging device and the manufacturing method of the imaging device according to the present disclosure have been described based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the gist of the present disclosure, various modifications that a person skilled in the art can make to the embodiments and other forms constructed by combining some of the components in the embodiments are also included within the scope of the present disclosure.

[0193] For example, in the imaging device 100, the upper surface formed by the insulating layer 91 and the plug 70 in cooperation with each other may be planarized by CMP. Even in such a case, the imaging device 100 may enjoy one or more of the benefits included in the above description. For example, as described above, the upper end 72u of the second conductive layer 72 may be located below the upper end 91hu of the through hole 91h provided in the insulating layer 91. With this configuration, the opening of the second conductive layer 72 may be protected within the through hole 91h.

[0194] (Addendum) The present disclosure provides the following techniques.

[0195] (Technology 1) a semiconductor substrate; a first photoelectric conversion unit; an insulating layer; a second photoelectric conversion unit; a plug; the semiconductor substrate, the first photoelectric conversion unit, and the second photoelectric conversion unit are arranged in this order in a thickness direction of the semiconductor substrate; the insulating layer has a region located between the first photoelectric conversion unit and the second photoelectric conversion unit in the thickness direction, The insulating layer has a through hole, the plug is disposed in the through hole, electrically connects the semiconductor substrate and the second photoelectric conversion unit, and has a first conductive layer, a second conductive layer, and a third conductive layer; the second conductive layer surrounds the first conductive layer such that the second conductive layer is disposed between the first conductive layer and the insulating layer; the third conductive layer is disposed between the first conductive layer and the first photoelectric conversion unit in the thickness direction and is in contact with the first conductive layer within the through hole. Imaging device.

[0196] Technique 1 can realize a reliable imaging device.

[0197] (Technology 2) the third conductive layer is disposed between the second conductive layer and the first photoelectric conversion unit in the thickness direction and is in contact with the second conductive layer within the through hole. The imaging device according to technology 1.

[0198] The configuration of the imaging device of Technique 2 is an example.

[0199] (Technology 3) the first photoelectric conversion unit has a first photoelectric conversion layer that performs photoelectric conversion, the first photoelectric conversion layer contains an organic material; The imaging device according to Technology 1 or 2.

[0200] In Technique 3, the first photoelectric conversion layer contains an organic material. In this case, it is easy to enjoy the benefit of Technique 1, that is, a reliable imaging device can be realized.

[0201] (Technology 4) The first photoelectric conversion unit is a first photoelectric conversion layer that generates a first charge by photoelectric conversion; a first pixel electrode that collects the first charges; a second charge generated by photoelectric conversion in the second photoelectric conversion unit flows through the plug; the first pixel electrode and the plug are electrically isolated from each other; The imaging device according to any one of the first to third aspects.

[0202] Technique 4 can contribute to obtaining high-quality images.

[0203] (Technology 5) The second photoelectric conversion unit is a second photoelectric conversion layer that generates second charges by photoelectric conversion; a second pixel electrode that collects the second charges; the second pixel electrode is electrically connected to the plug; The imaging device according to any one of the first to fourth aspects.

[0204] The second pixel electrode of technique 5 can collect the second charges generated in the second photoelectric conversion layer and provide them to the plug. This configuration can contribute to obtaining high-quality images.

[0205] (Technology 6) the second pixel electrode transmits light of a specific wavelength; the first photoelectric conversion unit photoelectrically converts the light of the specific wavelength by photoelectric conversion; The imaging device according to technology 5.

[0206] Technique 6 can contribute to obtaining high-quality images.

[0207] (Technology 7) In a plan view, the second pixel electrode overlaps with the first photoelectric conversion unit. The imaging device according to technology 6.

[0208] Technique 7 can contribute to obtaining high-quality images.

[0209] (Technology 8) the insulating layer has a first surface facing away from the semiconductor substrate; the plug has a second surface facing away from the semiconductor substrate; a portion of the combination of the first surface and the second surface that overlaps with the second pixel electrode in a plan view is defined as an evaluation surface; A point on the evaluation surface that is closest to the semiconductor substrate is defined as a proximal point; A point on the evaluation surface that is farthest from the semiconductor substrate is defined as a distal point; When the distance between the proximal point and the distal point in the thickness direction is defined as an evaluation distance, The evaluation distance is reduced by the third conductive layer. The imaging device according to any one of techniques 5 to 7.

[0210] Technique 8 can realize a reliable imaging device.

[0211] (Technology 9) The evaluation distance is 0 nm or more and 40 nm or less. The imaging device according to Art. 8.

[0212] Technique 9 can realize a reliable imaging device.

[0213] (Technology 10) the second conductive layer has a cylindrical shape with a bottom that opens upward, an upper end of the second conductive layer is located below an upper end of the through hole; The imaging device according to any one of the first to ninth aspects.

[0214] The technique 10 can realize a reliable imaging device.

[0215] (Technology 11) In a cross section parallel to the thickness direction, a dimension of the third conductive layer in the thickness direction is smaller than a dimension of the third conductive layer in a direction perpendicular to the thickness direction. The imaging device according to any one of the first to tenth aspects.

[0216] The configuration of the imaging device of Technique 11 is an example.

[0217] (Technology 12) the insulating layer includes at least one selected from the group consisting of silicon nitride and silicon oxynitride; The imaging device according to any one of the first to eleventh aspects.

[0218] The configuration of the imaging device of Technique 12 is an example.

[0219] (Technology 13) the first conductive layer comprises copper; 13. The imaging device according to any one of claims 1 to 12.

[0220] The configuration of the imaging device of Technique 13 is an example.

[0221] (Technology 14) the third conductive layer includes at least one selected from the group consisting of a cobalt alloy and a nickel alloy; The imaging device according to any one of the first to thirteenth aspects.

[0222] The configuration of the imaging device of Technique 14 is an example.

[0223] (Technology 15) forming a structure including a semiconductor substrate, a first photoelectric conversion unit located above the semiconductor substrate, and an insulating layer including a region located above the first photoelectric conversion unit and having a through hole; forming a conductive film extending along an upper surface of the insulating layer and a side surface of the insulating layer that defines the through hole, the conductive film defining a first bottomed hole at a position that overlaps with the through hole in a plan view; forming a mask in the first blind hole; processing the conductive film into a second conductive layer having a second bottomed hole formed therein by a first etching using the mask, the second conductive layer being located within the through hole and having an upper end lower than an upper end of the through hole; removing the mask from the second blind hole; forming a first conductive layer in the second blind hole, the first conductive layer having an upper end lower than an upper end of the through hole; forming a third conductive layer in the through hole such that the third conductive layer contacts the first conductive layer from above within the through hole; forming a second photoelectric conversion unit above the third conductive layer so that the semiconductor substrate and the second photoelectric conversion unit are electrically connected via a plug including the first conductive layer, the second conductive layer, and the third conductive layer; A method for manufacturing an imaging device.

[0224] The manufacturing method of technique 15 can realize a reliable imaging device.

[0225] (Technology 16) forming a photoresist to cover the conductive film from above; and exposing the photoresist to light so that a portion of the photoresist constituting the mask remains. The manufacturing method described in Technology 15.

[0226] According to technique 16, a mask can be formed.

[0227] (Technology 17) the structure comprises a connection electrode; the first photoelectric conversion unit includes a first pixel electrode and a first photoelectric conversion layer, forming a photoelectric conversion film so as to cover the connection electrode and the first pixel electrode from above; and processing the photoelectric conversion film into the first photoelectric conversion layer by second etching and exposing the connection electrode through the through hole, The conductive film is formed so as to extend along the top surface of the insulating layer, the side surface of the insulating layer, and the top surface of the connection electrode. The manufacturing method according to technique 15 or 16.

[0228] According to Technique 17, the second photoelectric conversion unit can be electrically connected to the connection electrode.

[0229] (Technology 18) The second conductive layer is a seed layer; and a barrier layer located between the seed layer and the insulating layer, the barrier layer suppressing diffusion of a material contained in the first conductive layer into the insulating layer; forming the first conductive layer by depositing the material on the seed layer by an electrolytic plating reaction; The manufacturing method according to any one of techniques 15 to 17.

[0230] According to Technique 18, a barrier layer that suppresses the diffusion of a specific material into an insulating layer can be formed. Furthermore, the seed layer can promote the formation of the first conductive layer.

[0231] (Technology 19) The third conductive layer is formed by electroless plating. The manufacturing method according to any one of the techniques 15 to 18.

[0232] According to technique 19, it is easy to finely adjust the size of the third conductive layer in the thickness direction of the semiconductor substrate, and therefore it is easy to make the third conductive layer contribute to reducing the step between the insulating layer and the plug.

[0233] (Technology 20) the first photoelectric conversion unit includes a first photoelectric conversion layer that photoelectrically converts light in a first wavelength region; the first wavelength range includes at least a portion of a near-infrared wavelength range; The film formation temperature of the electroless plating is 200°C or less. The manufacturing method described in Technology 19.

[0234] According to Technique 20, heat generated when forming the third conductive layer is unlikely to damage the first photoelectric conversion layer. [Industrial Applicability]

[0235] According to the technology disclosed herein, the flatness of the insulating layer and the plug provided in the insulating layer can be ensured without damaging the photoelectric conversion unit located below the upper surface of the insulating layer and the plug. The imaging device disclosed herein is useful for, for example, digital cameras. More specifically, the imaging device disclosed herein can be used for, for example, medical cameras, robot cameras, security cameras, cameras mounted on vehicles, and the like. [Explanation of symbols]

[0236] 10,10A pixels 12, 12A, 13, 13A, 513A Photoelectric conversion unit 12a,12c,13a,13c,15,513a,515 electrode 12ab bottom 12as,91s,591s side 12aw side wall 12b, 13b, 513b Photoelectric conversion layer 12d, 13d, 90, 91, 591 Insulating layer 14A signal detection circuit 16A feedback circuit 22, 24, 26 transistors 22e, 24e, 26e Gate electrodes 31 Storage control line 32 Power wiring 34 Address signal line 35 Vertical signal line 36 Reset signal line 39 parts 40 Peripheral Circuits 42 Vertical scanning circuit 44 Horizontal signal readout circuit 45 Load circuit 46 Control circuit 47 Signal Processing Circuit 49 Horizontal common signal line 50 Inverting amplifier 53 Feedback Line 60 Semiconductor substrate 61 p-type semiconductor layer 65 Gate insulating layer 67,68an,68bn,68cn,68dn,69 impurity region 70,86x,86y,570 plug 71,72,73,86x1,86x2,86y1,86y2,571,572 conductive layer 71u,72u,73u,91hu upper end 72h,172h,672h Bottom hole 72s seed layer 72b Barrier layer 72b1,72b2 layer 75 Mask 89,89x,89y conductive structure 91d Scratch defect 91h,591h Through hole 15t,91t,591t top surface 100 Imaging device 112a,113c,114 Electrode film 113b Photoelectric conversion film 113d Insulating film 172,672 Conductive film 172s seed film 172b Barrier film 172i Inside the hole 172o Outside the hole 190a, 190b, 190c Insulation part 191 insulating film 191c recess 211,217,219,223,224,719 Structure 217s Step 671 Conductive part Dt,Dv direction Ed, Ep, Ex points FD charge storage section Q evaluation rectangle R1 imaging area R2 surrounding area S1,S2,Se surface

Claims

1. a semiconductor substrate; a first photoelectric conversion unit; an insulating layer; a second photoelectric conversion unit; a plug; the semiconductor substrate, the first photoelectric conversion unit, and the second photoelectric conversion unit are arranged in this order in a thickness direction of the semiconductor substrate; the insulating layer has a region located between the first photoelectric conversion unit and the second photoelectric conversion unit in the thickness direction, The insulating layer has a through hole, the plug is disposed in the through hole, electrically connects the semiconductor substrate and the second photoelectric conversion unit, and has a first conductive layer, a second conductive layer, and a third conductive layer; the second conductive layer surrounds the first conductive layer such that the second conductive layer is disposed between the first conductive layer and the insulating layer; the third conductive layer is disposed between the first conductive layer and the first photoelectric conversion unit in the thickness direction and is in contact with the first conductive layer within the through hole. Imaging device.

2. the third conductive layer is disposed between the second conductive layer and the first photoelectric conversion unit in the thickness direction and is in contact with the second conductive layer within the through hole. The imaging device according to claim 1 .

3. the first photoelectric conversion unit has a first photoelectric conversion layer that performs photoelectric conversion, The first photoelectric conversion layer contains an organic material. The imaging device according to claim 1 .

4. The first photoelectric conversion unit is a first photoelectric conversion layer that generates first charges by photoelectric conversion; a first pixel electrode that collects the first charges; a second charge generated by photoelectric conversion in the second photoelectric conversion unit flows through the plug; the first pixel electrode and the plug are electrically isolated from each other; The imaging device according to claim 1 .

5. The second photoelectric conversion unit is a second photoelectric conversion layer that generates second charges by photoelectric conversion; a second pixel electrode that collects the second charges; the second pixel electrode is electrically connected to the plug; The imaging device according to claim 1 .

6. the second pixel electrode transmits light of a specific wavelength; the first photoelectric conversion unit photoelectrically converts the light of the specific wavelength by photoelectric conversion; The imaging device according to claim 5 .

7. the second pixel electrode overlaps with the first photoelectric conversion unit in a plan view; The imaging device according to claim 6 .

8. the insulating layer has a first surface facing away from the semiconductor substrate; the plug has a second surface facing away from the semiconductor substrate; a portion of the combination of the first surface and the second surface that overlaps with the second pixel electrode in a plan view is defined as an evaluation surface; A point on the evaluation surface that is closest to the semiconductor substrate is defined as a proximal point; A point on the evaluation surface that is farthest from the semiconductor substrate is defined as a distal point; When the distance between the proximal point and the distal point in the thickness direction is defined as an evaluation distance, the evaluation distance is reduced by the third conductive layer; The imaging device according to claim 5 .

9. The evaluation distance is 0 nm or more and 40 nm or less. The imaging device according to claim 8 .

10. the second conductive layer has a cylindrical shape with an upward opening and a bottom, an upper end of the second conductive layer is located below an upper end of the through hole; The imaging device according to claim 1 .

11. In a cross section parallel to the thickness direction, a dimension of the third conductive layer in the thickness direction is smaller than a dimension of the third conductive layer in a direction perpendicular to the thickness direction. The imaging device according to claim 1 .

12. the insulating layer includes at least one selected from the group consisting of silicon nitride and silicon oxynitride; The imaging device according to claim 1 .

13. the first conductive layer comprises copper; The imaging device according to claim 1 .

14. the third conductive layer includes at least one selected from the group consisting of a cobalt alloy and a nickel alloy; The imaging device according to claim 1 .

15. forming a structure including a semiconductor substrate, a first photoelectric conversion unit located above the semiconductor substrate, and an insulating layer including a region located above the first photoelectric conversion unit and having a through hole; forming a conductive film extending along an upper surface of the insulating layer and a side surface of the insulating layer that defines the through hole, the conductive film defining a first bottomed hole at a position that overlaps with the through hole in a plan view; forming a mask in the first blind hole; processing the conductive film into a second conductive layer having a second bottomed hole formed therein by a first etching using the mask, the second conductive layer being located within the through hole and having an upper end lower than an upper end of the through hole; removing the mask from the second blind hole; forming a first conductive layer in the second blind hole, the first conductive layer having an upper end lower than an upper end of the through hole; forming a third conductive layer in the through hole such that the third conductive layer contacts the first conductive layer from above within the through hole; forming a second photoelectric conversion unit above the third conductive layer such that the semiconductor substrate and the second photoelectric conversion unit are electrically connected via a plug including the first conductive layer, the second conductive layer, and the third conductive layer; A method for manufacturing an imaging device.

16. forming a photoresist to cover the conductive film from above; and exposing the photoresist to light so that a portion of the photoresist constituting the mask remains. The method of claim 15.

17. the structure comprises a connection electrode; the first photoelectric conversion unit includes a first pixel electrode and a first photoelectric conversion layer, forming a photoelectric conversion film so as to cover the connection electrode and the first pixel electrode from above; and processing the photoelectric conversion film into the first photoelectric conversion layer by second etching and exposing the connection electrode through the through hole, The conductive film is formed so as to extend along the top surface of the insulating layer, the side surface of the insulating layer, and the top surface of the connection electrode. The method of claim 15.

18. The second conductive layer is a seed layer; and a barrier layer positioned between the seed layer and the insulating layer, the barrier layer inhibiting diffusion of a material contained in the first conductive layer into the insulating layer; forming the first conductive layer by depositing the material on the seed layer by an electrolytic plating reaction; The method of claim 15.

19. The third conductive layer is formed by electroless plating. The method of claim 15.

20. the first photoelectric conversion unit includes a first photoelectric conversion layer that photoelectrically converts light in a first wavelength region; the first wavelength range includes at least a portion of a near-infrared wavelength range, The film formation temperature of the electroless plating is 200°C or less. The method of claim 19.

Images