Power conversion device

Abstract

To provide a power conversion device capable of suppressing generation of a surge voltage without causing an increase in cost and size of the device.SOLUTION: When a switching off timing overlap determination means (103) determines that switching off timings overlap among a plurality of phases, a next output PWM duty correction means (104) outputs a corrected next output PWM duty value obtained by adding a correction PWM duty value to a next output PWM duty value to a switching element of a phase arm whose switching off timing is determined to overlap.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a power conversion device. [Background technology]

[0002] Power conversion devices that perform power conversion between DC power and AC loads by controlling multiple switching elements using PWM (Pulse Width Modulation) are well known. However, with such power conversion devices, if the switching timings of multiple switching elements overlap, surge voltages may be generated due to inductance components in the connected AC load or in the circuit of the power conversion device.

[0003] For this reason, power conversion devices have been proposed that adjust the switching timing of multiple switching elements so that the switching timings of the switching elements do not overlap. However, with such conventional power conversion devices, torque ripple may occur in the motor as a load due to the high frequency of switching prohibited periods.

[0004] Therefore, a power conversion device has been disclosed that uses multiple independent PWM carrier waves, sets a phase difference between these PWM carrier waves at 180 degrees, and adjusts the relationship between the frequencies of the two based on the calculated worst value of the surge voltage, thereby shifting the switching timing between multiple switching elements (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent No. 6364199 Summary of the Invention [Problem to be solved by the invention]

[0006] The conventional power conversion device disclosed in Patent Document 1 requires multiple independent PWM carriers to shift the switching timing of the switching elements, and in the case of a microcontroller that does not have multiple PWM carriers, it is necessary to implement multiple microcontrollers, which poses the problem of increasing costs and the size of the device.

[0007] The present disclosure discloses technology for solving the above-mentioned problems, and aims to provide a power conversion device that can suppress the occurrence of surge voltages without increasing costs or the size of the device. [Means for solving the problem]

[0008] The power conversion device of the present disclosure includes: a bridge circuit in which a plurality of phase arms, each having a switching element in an upper arm and a lower arm connected in series, are connected in parallel, AC terminals are led out from series-connected portions of the upper arms and lower arms of the plurality of phase arms, and DC terminals are led out from both ends of the plurality of parallel-connected phase arms; a computing device that controls the switching of the switching elements of the plurality of phase arms by PWM control; Equipped with A power conversion device configured to perform power conversion between an AC load connected to AC terminals of the bridge circuit and a DC power supply connected to DC terminals of the bridge circuit by PWM control of the switching elements, The computing device an output PWM duty calculation unit that calculates output PWM duty values ​​of the switching elements of the plurality of phase arms and provides PWM signals to the switching elements of the plurality of phase arms based on the calculated output PWM duty values, The output PWM duty calculation unit a current output duty acquisition means for acquiring a current output PWM duty value currently being output in the switching elements of the plurality of phase arms; a next output PWM duty calculation means for calculating a next output PWM duty value to be output next to the switching elements of the plurality of phase arms; a switching-off timing overlap determination means for determining whether or not the switching-off timings of the switching elements of any of the plurality of phase arms overlap; next output PWM duty correction means for outputting a corrected next output PWM duty value obtained by adding a correction PWM duty value to the next output PWM duty value when the switching-off timing overlap determination means determines that the switching-off timings overlap, to the switching elements of the phase arms for which it has been determined that the switching-off timings overlap; Equipped with The switching-off timing overlap determination means the determination is made based on a comparison between the current output PWM duty value and the next output PWM duty value of the plurality of phase arms. It is characterized by: [Effects of the Invention]

[0009] According to the power conversion device of the present disclosure, it is possible to obtain a power conversion device that can suppress the occurrence of surge voltage without increasing the size and complicating the control. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a block diagram showing an internal configuration of a power conversion device according to a first embodiment. [Figure 2] 2 is a block diagram showing an internal configuration of an output PWM duty calculation unit in the power conversion device according to the first embodiment. FIG. [Figure 3] FIG. 10 is a time chart showing the switching timing of switching elements of a plurality of phase arms when the next output PWM duty value correction is not performed. [Figure 4]4 is a timing chart showing the switching timing of switching elements of a plurality of phase arms when correcting a next output PWM duty value in the power conversion device according to the first embodiment. FIG. [Figure 5] FIG. 10 is a timing chart showing output duty values ​​when an equal output PWM duty correction amount is added to the next output PWM duty values ​​of all phase arms in the power conversion device according to the second embodiment. [Figure 6] FIG. 10 is a timing chart showing the difference in output PWM duty value between the phase arms in the power conversion device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Embodiment 1 Hereinafter, a power conversion device according to the present disclosure will be described with reference to the drawings. Fig. 1 is a block diagram showing the internal configuration of a power conversion device according to embodiment 1. In Fig. 1, the power conversion device 1 includes a three-phase bridge circuit 11 and a computing device 10.

[0012] The three-phase bridge circuit 11 includes a U-phase arm UA configured with a U-phase upper arm Up and a U-phase lower arm Un connected in series, a V-phase arm VA configured with a V-phase upper arm Vp and a V-phase lower arm Vn connected in series, and a W-phase arm WA configured with a W-phase upper arm Wp and a W-phase lower arm Wn connected in series.

[0013] The U-phase upper arm Up has a switching element Q1, and the U-phase lower arm Un has a switching element Q2. The V-phase upper arm Vp has a switching element Q3, and the V-phase lower arm Vn has a switching element Q4. The W-phase upper arm Wp has a switching element Q5, and the W-phase lower arm Wn has a switching element Q6. Each of the switching elements Q1, Q2, Q3, Q4, Q5, and Q6 is formed, for example, by an IGBT (Insulated Gate Bipolar Transistor) equipped with a freewheeling diode.

[0014] U-phase AC terminal Ut is derived from the series connection between U-phase upper arm Up and U-phase lower arm Un, V-phase AC terminal Vt is derived from the series connection between V-phase upper arm Vp and V-phase lower arm Vn, and W-phase AC terminal Wt is derived from the series connection between W-phase upper arm Wp and W-phase lower arm Wn. Positive-side DC terminal Dp is derived from one interconnection between U-phase arm UA, V-phase arm VA, and W-phase arm WA, and negative-side DC terminal Dn is derived from the other interconnection between U-phase arm UA, V-phase arm VA, and W-phase arm WA.

[0015] The load 2 is, for example, a three-phase synchronous motor having a U-phase winding, a V-phase winding, and a W-phase winding on the stator and permanent magnet field poles on the rotor. The U-phase winding, the V-phase winding, and the W-phase winding of the three-phase synchronous motor serving as the load 2 are connected to a U-phase AC terminal Ut, a V-phase AC terminal Vt, and a W-phase AC terminal Wt, respectively, of a three-phase bridge circuit 11. The positive terminal of the battery 3 is connected to a positive-side DC terminal Dp of the three-phase bridge circuit 11, and the negative terminal of the battery 3 is connected to a negative-side DC terminal Dn of the three-phase bridge circuit 11.

[0016] The arithmetic device 10 is configured, for example, by an ECU (Electronic Control Unit). The ECU is configured with a processor and a storage device, and the storage device includes a volatile storage device such as a random access memory and a non-volatile auxiliary storage device such as a flash memory. Alternatively, a hard disk auxiliary storage device may be provided instead of the flash memory. The processor executes a program input from the storage device. In this case, the program is input to the processor from the auxiliary storage device via the volatile storage device. The processor may also output data such as calculation results to a volatile storage device of the storage device, or may store the data in the auxiliary storage device via the volatile storage device.

[0017] The arithmetic device 10, which is constituted by an ECU, includes an output PWM duty calculation unit 100. The output PWM duty calculation unit 100 generates PWM signals P1, P2, P3, P4, P5, and P6 for PWM control of the switching elements Q1, Q2, Q3, Q4, Q5, and Q6 of the three-phase bridge circuit 11, based on a command from a command unit (not shown), and supplies these PWM signals P1, P2, P3, P4, P5, and P6 to the gate terminals of the switching elements Q1, Q2, Q3, Q4, Q5, and Q6 of the three-phase bridge circuit 11, respectively.

[0018] The PWM signals P1, P2, P3, P4, P5, and P6 for PWM control of the three-phase bridge circuit 11 are generated by comparing, for example, three modulation waves having a phase difference of 120 degrees with a PWM carrier wave, which is a triangular wave having a predetermined frequency.

[0019] The three modulated waves correspond to the U-phase arm UA, the V-phase arm VA, and the W-phase arm WA of the three-phase bridge circuit 11, respectively, and when the level of these modulated waves is equal to or lower than the level of the triangular wave serving as the PWM carrier wave, a PWM signal is generated that turns on the switching element of the corresponding phase arm. Therefore, by adjusting the level of each modulated wave, it is possible to adjust the on-duty of the switching element in the corresponding phase arm.

[0020] In the PWM control of the three-phase bridge circuit 11, the upper arm may be fully ON during one carrier wave period, i.e., 100 μs if the carrier wave period is 10 kHz. For example, if the PWM duty of the U phase is calculated to be 100%, the PWM duty of the V phase is 25%, and the PWM duty of the W phase is 25%, the U phase upper arm will be fully ON. On the other hand, if the PWM duty of the U phase is calculated to be 0%, the PWM duty of the V phase is 75%, and the PWM duty of the W phase is 75%, the U phase lower arm will be fully ON.

[0021] In addition to the above, if the PWM duty of the U phase is calculated to be 75%, the PWM duty of the V phase to be 37.5%, and the PWM duty of the W phase to be 37.5%, 25% is added to the PWM duties of all phases to maintain the relationship between the phases, and PWM control can be performed to make the PWM duty of the U phase 100%, the PWM duty of the V phase 62.5%, and the PWM duty of the W phase 62.5%. In this case, the upper arm of the U phase will be fully ON.

[0022] Also, for example, if you try to output a sine wave as AC to the fullest extent possible without any special corrections from the DC power supply voltage supplied to the power conversion device, there will be one time in 360 degrees for each phase where the PWM duty will be 100%.

[0023] When the PWM control described above is applied, generally at least one of the six arms consisting of the upper and lower arms of each phase of the three-phase bridge circuit will be turned on.

[0024] The PWM control described above has the effect of reducing losses by reducing the number of times the switching elements are switched, and making it possible to output an AC voltage higher than the DC voltage.

[0025] Output PWM duty calculation unit 100 further includes the configuration shown in Fig. 2. That is, Fig. 2 is a block diagram showing the internal configuration of the output PWM duty calculation unit in the power conversion device according to embodiment 1. In Fig. 2, output PWM duty calculation unit 100 includes next output PWM duty calculation means 101, current output PWM duty acquisition means 102, switching-off timing overlap determination means 103, and next output PWM duty correction means 104.

[0026] Based on a command from a command unit (not shown), the next output PWM duty calculation means 101 calculates the next output PWM duty value to be applied to the switching elements Q1 and Q2 of the U-phase arm UA, the next output PWM duty value to be applied to the switching elements Q2 and Q4 of the V-phase arm VA, and the next output PWM duty value to be applied to the switching elements Q5 and Q6 of the W-phase arm WA.

[0027] The current output PWM duty acquisition means 102 acquires the current output PWM duty values ​​of the switching elements Q1 and Q2 of the U-phase arm UA, the current output PWM duty values ​​of the switching elements Q3 and Q4 of the V-phase arm VA, and the current output PWM duty values ​​of the switching elements Q5 and Q6 of the W-phase arm WA.

[0028] The switching-off timing overlap determining means 103 determines whether or not the switching-off timings of the switching elements of any of the plurality of phase arms overlap.

[0029] More specifically, the switching-off timing overlap determination means 103 is configured to determine that the switching-off timings of the switching elements overlap between the one phase arm and another phase arm when the current output PWM duty value acquired for one phase arm is a value at which the upper arm switching element in that phase is fully on, and the next output PWM duty value calculated for the one phase arm is a value at which the upper arm switching element in that phase arm is not fully on, and further, the current output PWM duty value acquired for another phase arm is a value at which the lower arm switching element in that other phase arm is not fully off, and the next output PWM duty value calculated for the other phase arm is a value at which the lower arm switching element in that other phase arm is fully off.

[0030] When the switching-off timing overlap determination means 103 determines that the switching-off timings of the switching elements of a plurality of phase arms overlap, the next output PWM duty correction means 104 generates a corrected next output PWM duty value by adding a correction PWM duty value to the next output PWM duty value calculated by the next output PWM duty calculation means 101, and outputs the corrected next output PWM duty value to the switching elements of the phase arms determined to have overlapping switching-off timings.

[0031] When the switching-off timing overlap determination means 103 does not determine that the switching-off timings of the switching elements overlap, the next output PWM duty correction means 104 outputs the next output PWM duty values ​​calculated by the next output PWM duty calculation means 101 as they are to each of the switching elements Q1, Q2, Q3, Q4, Q5, and Q6.

[0032] 1 operates as an inverter that converts DC power from a battery 3 into three-phase AC power having U, V, and W phases. A switching element Q1 in a U-phase upper arm Up and a switching element Q2 in a U-phase lower arm Un of a three-phase bridge circuit 11 are PWM-controlled by PWM signals P1 and P2 generated using a triangular wave as a PWM carrier wave and a rectangular wave as a U-phase modulating wave.

[0033] Similarly, switching element Q3 in V-phase upper arm Vp and switching element Q4 in V-phase lower arm Vn of three-phase bridge circuit 11 are PWM controlled by PWM signals P3 and PWM signals P4 generated using a triangular wave as a PWM carrier wave and a rectangular wave as a V-phase modulating wave.

[0034] In addition, switching element Q5 in W-phase upper arm Wp and switching element Q6 in W-phase lower arm Wn of three-phase bridge circuit 11 are PWM controlled by PWM signals P5 and PWM signals P6 generated using a triangular wave as a PWM carrier wave and a rectangular wave as a W-phase modulating wave.

[0035] The U-phase modulated wave, V-phase modulated wave, and W-phase modulated wave have a phase difference of 120 degrees from each other. The PWM duty value of each switching element is controlled by changing the level of the modulated wave of each phase relative to the PWM carrier wave.

[0036] FIG. 3 is a time chart showing the switching timing of the switching elements of multiple phase arms when the next output PWM duty value is not corrected, and shows an example of a case where the switching-off timings overlap at the time of switching between the current output PWM duty value and the next output PWM duty value.

[0037] On the vertical axis of Figure 3, A represents the PWM carrier wave Carr, B represents the PWM signal P1 applied to the switching element Q1 of the U-phase upper arm Up, C represents the PWM signal P2 applied to the switching element Q2 of the U-phase lower arm Un, D represents the PWM signal P3 applied to the switching element Q3 of the V-phase upper arm Vp, and E represents the PWM signal P4 applied to the switching element Q4 of the V-phase lower arm Vn.

[0038] In Fig. 3, the section from time T0 to switching time T3 corresponds to an electrical angle of 120 degrees and is the current section Tc in which the PWM signal is being sent, and the section from switching time T3 to time T7 corresponds to an electrical angle of 120 degrees and is the next section Tn in which the next PWM signal will be sent. The PWM carrier wave Carr shown in Fig. 3A is sent as the same triangular wave in both the current section Tc and the next section Tn.

[0039] During the current section Tc from time T0 to switching time T3, the voltage level of the U-phase modulated wave Umod1, indicated by the dashed-dotted line, is equal to or lower than the voltage level of the PWM carrier wave Carr throughout the entire 120-degree section. Therefore, the PWM signal P1 sent to the switching element Q1 of the U-phase upper arm Up, indicated by B, becomes one full-duty pulse during the current section Tc, and the switching element Q1 is on throughout the 120-degree current section Tc (hereinafter referred to as "always on"). Thus, during the current section Tc, the PWM signal P1 has the current output PWM duty value of "always on."

[0040] On the other hand, the PWM signal P2 of the U-phase lower arm Un shown at C is at low level throughout the current section Tc, and the switching element Q2 of the U-phase lower arm Un is off throughout the current section Tc (hereinafter referred to as "all off").

[0041] Furthermore, in the current section Tc, from time T0 to time T1, the voltage level of the V-phase modulated wave Vmod1 shown by the dashed line is higher than the voltage level of the PWM carrier wave Carr, and the PWM signal P3 of the V-phase upper arm Vp shown in D is at a low level in the section from time T0 to time T1.

[0042] Next, in the section from time T1 to time T2, the voltage level of V-phase modulating wave Vmod1 is equal to or lower than the voltage level of PWM carrier wave Carr, and in the section from time T1 to time T2, PWM signal P3 shown in D is at high level. Furthermore, from time T2 onwards, the voltage level of V-phase modulating wave Vmod1 becomes higher than the voltage level of PWM carrier wave Carr, and from time T2 onwards, PWM signal P3 is at low level.

[0043] On the other hand, PWM signal P4 of V-phase lower arm Vn shown in E is at low level from just before time T1 to just after time T2, during which time switching element Q4 of V-phase lower arm Vn is off.

[0044] At the switching time T3, the current section Tc switches to the next section Tn, and the current output PWM duty is switched to the next output PWM duty. That is, as shown in A of Fig. 3, at the switching time T3, the current U-phase modulated wave Umod1 is switched to the next U-phase modulated wave Umod2, and the current V-phase modulated wave Vmod1 is switched to the next V-phase modulated wave Vmod2.

[0045] As a result, the PWM signal P1 of the U-phase upper arm shown in B switches from high to low at switching time T3, changes from low to high at time T5, and then changes from high to low at time T6. Thus, in the next interval Tn, the PWM signal P1 has a next output PWM duty value other than "solid on." Meanwhile, the PWM signal P2 of the U-phase lower arm Un shown in C remains solid off in the next interval Tn, continuing from the current interval Tc.

[0046] Furthermore, since the V-phase modulated wave Vmod1 in the current section Tc switches to the V-phase modulated wave Vmod2 in the next section Tn at the switching time T3, the PWM signal P3 of the V-phase upper arm Vp shown in D changes from low level to high level at time T4 and becomes low level at time T7.

[0047] The PWM signal P4 of the V-phase lower arm Vn shown in E switches from high level to low level at the time T3 when the current section Tc switches to the next section Tn, and remains low throughout the entire next section Tn, and the switching element Q4 of the V-phase lower arm Vn remains solid off throughout the next section Tn.

[0048] As described above, when the current output PWM duty value of the U-phase upper arm Up in the current section Tc is a value at which switching element Q1 of the U-phase upper arm Up is always on, and the next output PWM duty value of the U-phase upper arm in the next section Tn is a value at which switching element Q1 of the U-phase upper arm Up is not always on, switching element Q1 of the U-phase upper arm Up is switched off at switching time point T3, which is the PWM duty switching timing.

[0049] On the other hand, when the current output PWM duty value of the V-phase lower arm Vn in the current section Tc is a value that puts the switching element Q4 of the V-phase lower arm Vn in a state other than solid off, and the next output PWM duty value of the V-phase lower arm Vn in the next section Tn is a value that puts the switching element Q4 of the V-phase lower arm Vn in solid off, the switching element Q4 of the V-phase lower arm Vn is switched off at the switching time T3, which is the PWM duty switching timing.

[0050] According to the power conversion device 1 of embodiment 1, the switching-off timing overlap determination means 103 determines whether the switching-off timings overlap based on a comparison between the current output PWM duty value acquired for the U-phase upper arm and the next output PWM duty value calculated for the U-phase upper arm, and a comparison between the current output PWM duty value acquired for the V-phase lower arm and the next output PWM duty value calculated for the V-phase lower arm.

[0051] The switching-off timing overlap determination means 103 determines that the switching-off timing of the switching elements overlaps between the U-phase arm and the V-phase arm when the current output PWM duty value acquired for the U-phase upper arm is a value at which the switching element of the U-phase upper arm is fully on, and the next output PWM duty value calculated for the U-phase upper arm is a value at which the switching element of the U-phase upper arm is not fully on, and further, the current output PWM duty value acquired for the V-phase lower arm is a value at which the switching element of the V-phase lower arm is not fully off, and the next output PWM duty value calculated for the V-phase lower arm is a value at which the switching element of the V-phase lower arm is not fully off.

[0052] Furthermore, the switching-off timing overlap determination means 103 determines whether or not there is an overlap in the switching-off timing between the U phase and the V phase of the three phases as described above, and also determines whether or not there is an overlap in the switching-off timing between the V phase and the W phase, and between the W phase and the U phase, in the same manner as described above and between the U phase and the V phase.

[0053] If the determination result from the switching-off timing overlap determination means 103 is that there is no overlap in the switching-off timing, the next output PWM duty correction means 104 outputs the PWM signals calculated by the next output PWM duty calculation means 101 as they are to the respective switching elements Q1, Q2, Q3, Q4, Q5, and Q6 of the three-phase bridge circuit 11.

[0054] However, if the switching-off timing overlap determination means 103 determines that the switching-off timings overlap, then next output PWM duty correction means 104 adds correction duty values ​​to the next U-phase output PWM duty value and the next V-phase output PWM duty value, respectively. As a result, as will be described later, the switching-off timing of switching element Q4 of V-phase lower arm Vn is delayed, and overlap with the switching-off timing of switching element Q1 of U-phase upper arm Up at switching time point T3, which is the PWM duty switching timing, is avoided.

[0055] FIG. 4 is a timing chart showing the switching timing of the switching elements of multiple phase arms when correcting the next output PWM duty value in the power conversion device according to embodiment 1, and parts that are the same as or correspond to those in FIG. 3 are given the same reference numerals.

[0056] That is, as shown in Fig. 4, if the switching-off timing overlap determination means 103 determines that the switching-off timings overlap, the next output PWM duty correction means 104 corrects the U-phase modulated wave Umod2 in the next interval Tn to the U-phase modulated wave Umod21, thereby correcting the PWM signal P1 of the U-phase upper arm Up to the PWM signal P12 as shown in B of Fig. 4. As a result of this correction, the PWM signal P12 in the next interval Tn has a high level that is reduced, as shown by the solid line, compared to the high level in the case where no correction is made, as shown by the dashed line.

[0057] Furthermore, the next output PWM duty correcting means 104 corrects the V-phase modulated wave Vmod2 in the next section Tn to the V-phase modulated wave Vmod21, thereby correcting the PWM signal P3 of the V-phase upper arm Vp to the PWM signal P32, as shown in D of Fig. 4. As a result of this correction, the PWM signal P3 in the next section Tn becomes a high level that is reduced, as shown by the solid line, compared to the high level in the case where no correction is made, as shown by the dashed line.

[0058] Furthermore, as shown in E, next output PWM duty correcting means 104 corrects PWM signal P4 of V-phase lower arm Vn to PWM signal P42. As a result of this correction, PWM signal P4 in the next interval Tn becomes a low level that is reduced, as shown by the solid line, from the low level without correction, as shown by the dashed line. As a result, switching element Q4 of V-phase lower arm Vn changes from a solid off state before correction to a non-solid off state in the next interval Tn.

[0059] By correcting the PWM signal in this manner, the switching-off timing of the switching element Q4 of the V-phase lower arm Vn is delayed from the switching time point T3, which is the switching timing, and overlap with the switching-off timing of the switching element Q1 of the U-phase upper arm Up at the switching time point T3 is avoided.

[0060] The above is an explanation of the correction of the next output PWM duty value between the U phase and the V phase, but the same applies to the correction between the V phase and the W phase, and between the W phase and the U phase.

[0061] As described above, according to the power conversion device of embodiment 1, even in a configuration in which PWM signals for multiple phases are generated by a single PWM carrier wave, when the switching-off timings of switching elements of multiple phases overlap, the overlap of the switching-off timings can be avoided by correcting the output PWM duty value, and it is possible to suppress the occurrence of surges due to the simultaneous switching-off of multiple switching elements.

[0062] Furthermore, in recent years, in order to save space and improve efficiency, modules that combine switching elements of multiple phases into a single package are sometimes adopted. However, such switching elements tend to have larger stray inductances and are more likely to cause surge voltages due to the simultaneous switching-off described above. However, according to the power conversion device of embodiment 1, even when such modularized switching elements are adopted, it is possible to suppress the occurrence of surge voltages due to the characteristics of the module, as described above.

[0063] Embodiment 2, Next, a description will be given of a power conversion device according to embodiment 2. According to the power conversion device according to embodiment 1, when it is determined that the switching-off timings of switching elements of a plurality of phases overlap, the overlap of the switching-off timings is avoided by correcting the next output PWM duty value of the phases whose switching-off timings overlap. However, this correction of the output PWM duty changes the voltage of the output terminal of the power conversion device 1 connected to the load 2, which may affect the dynamic characteristics of the load 2.

[0064] Therefore, the power conversion device according to the second embodiment is configured so that an output PWM duty correction amount is added equally to the next output PWM duty value to be output to the switching elements of all phases. The block diagram of Fig. 1 showing the internal configuration of the power conversion device according to the first embodiment and the block diagram of Fig. 2 showing the internal configuration of the output PWM duty calculation unit in the power conversion device according to the first embodiment are common to the power conversion device according to the second embodiment.

[0065] FIG. 5 is a timing chart showing the output PWM duty values ​​when the same output PWM duty correction value is added to the next output PWM duty values ​​of all phase arms in the power conversion device according to embodiment 2. The timing chart shows the PWM duty values ​​output to multiple phases, with the vertical axis representing the output PWM duty value [%] and the horizontal axis representing time.

[0066] In Fig. 5, when it is determined that the switching-off timings overlap at switching time point T3, the power conversion device according to the second embodiment adds an equal output PWM duty correction amount to the next output PWM duty values ​​of all phases, U, V, and W. In the example shown in Fig. 5, the duty values ​​are corrected by "-10" [%].

[0067] 5, the timing of switching from the current section Tc to the next section Tn is switching time T3, and by correcting the output PWM duty values ​​Udu, Vdu, and Wdu of all phases by -10% at this switching time T3, the PWM duty values ​​of all these phases decrease discontinuously from the current section Tc to the next section Tn. However, the difference in PWM duty values ​​between two phases does not become discontinuous even when the output PWM duty value of each phase is corrected at switching time T3.

[0068] 6 is a timing chart showing the difference in output PWM duty value between the arms of each phase in the power conversion device according to the second embodiment, where the vertical axis represents the difference in output PWM duty value between the U phase as viewed from the W phase, the V phase as viewed from the U phase, and the W phase as viewed from the V phase, and the horizontal axis represents time.

[0069] As shown in FIG. 6, the difference WUdu between the output PWM duty value of the W phase and the U phase, the difference UVdu between the output PWM duty value of the U phase and the V phase, and the difference VWdu between the output PWM duty value of the V phase and the W phase do not become discontinuous even when the output PWM duty value of each phase is corrected at the timing of switching time T3.

[0070] In this way, the power conversion device according to the second embodiment can correct the next output PWM duty value while maintaining the relationship between the multiple phases of the load 2 connected to the output terminal of the power conversion device 1. Therefore, the dynamic characteristics of the load 2 are not affected.

[0071] In the second embodiment, the number of phases is set to three for ease of explanation, but other numbers of phases can be used in the same manner.

[0072] Embodiment 3, Next, a power conversion device according to embodiment 3 will be described. As described above with reference to Fig. 3, when the current output PWM duty value of the U-phase is a value that causes switching element Q1 of the U-phase upper arm Up to be always on, the switching-off timing of switching element Q4 of the V-phase lower arm Vn and the switching-off timing of switching element Q1 of the U-phase upper arm Up may overlap at time T3 when the PWM duty value is switched.

[0073] In this way, if the current output duty value of the upper arm of any of the multiple phases is a value that causes the switching element of that upper arm to be completely on, there is a possibility that the off timings of the switching elements of the multiple phases will overlap.

[0074] Therefore, in the power conversion device according to the third embodiment, the switching-off timing overlap determination means 103 determines whether the switching-off timing overlaps by comparing the current output PWM duty value of the upper arm of any one of the multiple phases with the next output PWM duty value of the other phases only when the current output duty value of the upper arm of that phase is a value that turns the switching element of that upper arm completely on.

[0075] The block diagram of FIG. 1 showing the internal configuration of the power conversion device according to embodiment 1 and the block diagram of FIG. 2 showing the internal configuration of the output PWM duty calculation unit in the power conversion device according to embodiment 1 are common to the power conversion device according to embodiment 3.

[0076] According to the power conversion device of embodiment 3, only when the current output duty value of the upper arm of any of the multiple phases is a value that causes the switching element of that upper arm to be always on, the current output duty value is compared with the next output PWM duty value to determine whether there is an overlap in switching-off timing. This limits the circumstances in which overlap in switching-off timing is determined, making it possible to simplify the processing.

[0077] As described above, the power conversion device according to each embodiment can suppress surge voltages by preventing the overlap of the switching-off timings of the switching elements using a single PWM carrier wave. Furthermore, it can eliminate the influence on the dynamic characteristics of power exchanged with the load caused by the correction of the PWM duty value to prevent the overlap of the switching-off timings.

[0078] Although various exemplary embodiments and examples are described in this disclosure, the various features, aspects, and functions described in one or more embodiments are not limited to the application of a particular embodiment, but may be applied to the embodiments alone or in various combinations. Therefore, countless modifications not illustrated are anticipated within the scope of the technology disclosed in this application. For example, this includes cases where at least one component is modified, added, or omitted, and even cases where at least one component is extracted and combined with components of another embodiment.

[0079] Next, aspects of the power conversion device disclosed in the present application will be described below as supplementary notes. (Appendix 1) a bridge circuit in which a plurality of phase arms, each having a switching element in an upper arm and a lower arm connected in series, are connected in parallel, AC terminals are led out from series-connected portions of the upper arms and lower arms of the plurality of phase arms, and DC terminals are led out from both ends of the plurality of parallel-connected phase arms; a computing device that controls the switching of the switching elements of the plurality of phase arms by PWM control; Equipped with A power conversion device configured to perform power conversion between an AC load connected to AC terminals of the bridge circuit and a DC power supply connected to DC terminals of the bridge circuit by PWM control of the switching elements, The computing device an output PWM duty calculation unit that calculates output PWM duty values ​​of the switching elements of the plurality of phase arms and provides PWM signals to the switching elements of the plurality of phase arms based on the calculated output PWM duty values, The output PWM duty calculation unit a current output duty acquisition means for acquiring a current output PWM duty value currently being output in the switching elements of the plurality of phase arms; a next output PWM duty calculation means for calculating a next output PWM duty value to be output next to the switching elements of the plurality of phase arms; a switching-off timing overlap determination means for determining whether or not the switching-off timings of the switching elements of any of the plurality of phase arms overlap; next output PWM duty correction means for outputting a corrected next output PWM duty value obtained by adding a correction PWM duty value to the next output PWM duty value when the switching-off timing overlap determination means determines that the switching-off timings overlap, to the switching elements of the phase arms for which it has been determined that the switching-off timings overlap; Equipped with The switching-off timing overlap determination means the determination is made based on a comparison between the current output PWM duty value and the next output PWM duty value of the plurality of phase arms. A power conversion device characterized by: (Appendix 2) The switching-off timing overlap determination means The current output PWM duty value acquired for one phase arm is a value at which the upper arm switching element in the one phase is always on, and the next output PWM duty value calculated for the one phase arm is a value at which the upper arm switching element in the one phase arm is not always on, and further, When the current output PWM duty value acquired for another phase arm is a value that causes the switching element of the lower arm of the other phase arm to be other than solid off, and the next output PWM duty value calculated for the other phase arm is a value that causes the switching element of the lower arm of the other phase arm to be solid off, a determination unit configured to determine whether the switching-off timings of the switching elements of the one phase arm and the other phase arm overlap; 2. The power conversion device according to claim 1, (Appendix 3) The next output PWM duty correction means the switching-off timing overlap determination means is configured to output the corrected next output PWM duty value to all switching elements of the plurality of phase arms when it determines that the switching-off timings overlap. 3. The power conversion device according to claim 1 or 2. (Appendix 4) The switching-off timing overlap determination means The determination is made only when the acquired current output PWM duty value is a value that causes a switching element of an upper arm in at least one of the plurality of phase arms to be fully on. 4. The power conversion device according to claim 1, wherein: (Appendix 5) The switching elements of the plurality of phase arms are integrated into a single module. 5. The power conversion device according to claim 1, wherein: [Explanation of symbols]

[0080] 1 power conversion device, 2 load, 3 battery, 10 computing device, 11 Three-phase bridge circuit, 100 Output PWM duty calculation unit, 101 next output PWM duty calculation means, 102 current output PWM duty acquisition means; 103 switching-off timing overlap determination means, 104 next output PWM duty correction means, UA U-phase arm, VA V-phase arm, WA W-phase arm, Up U-phase upper arm, Un U-phase lower arm, Vp V-phase upper arm, Vn V-phase lower arm, Wp W-phase upper arm, Wn W-phase lower arm, Q1, Q2, Q3, Q4, Q5, Q6 switching elements, P1, P2, P3. P4, P5, P6 PWM signal, Tc current section, Tn next section, Umod1 current U phase modulated wave, T3 Switching time, Umod2 Next U phase modulation wave, Vmod1: Current V-phase modulation wave, Vmod2: Next V-phase modulation wave

Claims

1. a bridge circuit in which a plurality of phase arms, each having a switching element in an upper arm and a lower arm connected in series, are connected in parallel, AC terminals are led out from series-connected portions of the upper arms and lower arms of the plurality of phase arms, and DC terminals are led out from both ends of the plurality of parallel-connected phase arms; a computing device that controls the switching of the switching elements of the plurality of phase arms by PWM control; Equipped with a power conversion device configured to perform power conversion between an AC load connected to AC terminals of the bridge circuit and a DC power supply connected to DC terminals of the bridge circuit by PWM control of the switching elements, The computing device an output PWM duty calculation unit that calculates output PWM duty values ​​of the switching elements of the plurality of phase arms and provides PWM signals to the switching elements of the plurality of phase arms based on the calculated output PWM duty values; The output PWM duty calculation unit a current output duty acquisition means for acquiring a current output PWM duty value currently being output in the switching elements of the plurality of phase arms; a next output PWM duty calculation means for calculating a next output PWM duty value to be output next time to the switching elements of the plurality of phase arms; a switching-off timing overlap determination means for determining whether or not the switching-off timings of the switching elements of the phase arms overlap among any of the plurality of phase arms; next output PWM duty correction means for outputting a corrected next output PWM duty value obtained by adding a correction PWM duty value to the next output PWM duty value when the switching-off timing overlap determination means determines that the switching-off timings overlap, to the switching elements of the phase arms determined to have the switching-off timings overlap; Equipped with The switching-off timing overlap determination means the determination is made based on a comparison between the current output PWM duty value and the next output PWM duty value of the plurality of phase arms. A power conversion device characterized by:

2. The switching-off timing overlap determination means The current output PWM duty value acquired for one phase arm is a value at which the upper arm switching element in the one phase is always on, and the next output PWM duty value calculated for the one phase arm is a value at which the upper arm switching element in the one phase arm is not always on, and further, When the current output PWM duty value acquired for another one of the phase arms is a value that causes the switching element of the lower arm of the other one of the phase arms to be other than solid off, and the next output PWM duty value calculated for the other one of the phase arms is a value that causes the switching element of the lower arm of the other one of the phase arms to be solid off, a determination unit configured to determine whether the switching-off timings of the switching elements of the one phase arm and the other phase arm overlap; 2. The power conversion device according to claim 1.

3. The next output PWM duty correction means the switching-off timing overlap determination means is configured to output the corrected next output PWM duty value to all switching elements of the plurality of phase arms when it determines that the switching-off timings overlap.

3. The power conversion device according to claim 1 or 2.

4. The switching-off timing overlap determination means the determination is made only when the acquired current output PWM duty value is a value that causes a switching element of an upper arm in at least any one of the plurality of phase arms to be fully on.

3. The power conversion device according to claim 1 or 2.

5. The switching-off timing overlap determination means the determination is made only when the acquired current output PWM duty value is a value that causes a switching element of an upper arm in at least any one of the plurality of phase arms to be fully on.

4. The power conversion device according to claim 3.

6. the switching elements of the plurality of phase arms are integrated into a single module; 3. The power conversion device according to claim 1 or 2.

7. the switching elements of the plurality of phase arms are integrated into a single module; 4. The power conversion device according to claim 3.

8. the switching elements of the plurality of phase arms are integrated into a single module; 5. The power conversion device according to claim 4.

9. the switching elements of the plurality of phase arms are integrated into a single module; 6. The power conversion device according to claim 5.

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