PWM signal generation circuit, image forming apparatus, multifunction peripheral, PWM signal generation method, and program

Abstract

To control the temporal context of a plurality of PWM signals.SOLUTION: A PWM signal generation circuit for generating a plurality of PWM signals for PWM-driving a plurality of motors, the PWM signal generation circuit comprising a plurality of individual circuits corresponding to the plurality of motors, each of the individual circuits receives one reference signal common to the plurality of individual circuits and first data designating a delay time corresponding to each of the motors from the outside, and generates, for each of the motors, a PWM signal having a start time as a start time of a first PWM cycle from a start time delayed by the delay time designated by the first data from a change time when the reference signal changes from a first level to a second level.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present disclosure relates to a PWM signal generation circuit, an image forming apparatus and a multifunction peripheral including the same, a PWM signal generation method, and a program. [Background technology]

[0002] At least some multifunction peripherals having at least an image forming unit and an image reading unit include multiple motors, such as a motor for driving a printer head, a motor for transporting recording paper, a motor that serves both a cleaning mechanism and an automatic feed mechanism, and a motor for transporting an image reading sensor. At least some image forming devices having at least an image forming unit include multiple motors, such as a motor for driving a printer head, a motor for transporting recording paper, and a motor that serves both a cleaning mechanism and an automatic feed mechanism. Each of these multiple motors is PWM-driven by a PWM signal generated based on a command from a control unit (e.g., a processor) that controls each motor. Multiple PWM signals are used to control the multiple motors. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-14357 Summary of the Invention [Problem to be solved by the invention]

[0004] Here, the rising and falling timings of multiple PWM signals may coincide by chance. In particular, if multiple PWM signals share a common cycle, the start timings of the multiple PWM signal cycles may coincide for a continuous period, resulting in a continuous period in which the rising timings of multiple PWM signals coincide. When the rising timings of multiple PWM signals coincide, a problem may arise in that the timings of the switching currents generated in the multiple motors driven by these signals overlap. Patent Document 1 discloses a configuration in which a processor transmits data specifying the cycle and pulse width of each PWM signal to a motor drive circuit via serial communication, and the motor drive circuit generates PWM signals based on the received data. However, even the configuration of Patent Document 1 can still encounter the above-mentioned problems.

[0005] The present disclosure has been made in view of the above-mentioned problems, and aims to make it possible to control the temporal relationship between multiple PWM signals. [Means for solving the problem]

[0006] One embodiment of the present disclosure is a PWM signal generation circuit for generating a plurality of PWM signals for PWM driving a plurality of motors, the PWM signal generation circuit including a plurality of individual circuits corresponding to the plurality of motors, each of which receives a single reference signal common to the plurality of individual circuits and first data specifying a delay time corresponding to each motor from the outside, and generates a PWM signal for each motor, with the start time of a first PWM period being delayed from a change time at which the reference signal changes from a first level to a second level by the delay time specified by the first data. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to control the temporal relationship between multiple PWM signals. [Brief explanation of the drawings]

[0008] [Figure 1] 1A and 1B are perspective views showing the overall configuration of a multifunction peripheral equipped with a plurality of motors. [Figure 2] FIG. 2 is a circuit diagram showing a hardware configuration of a motor control circuit. [Figure 3] FIG. 2 is a timing diagram illustrating a serial interface protocol. [Figure 4] FIG. 10 is a format diagram showing details of a register group of the control signal generating unit. [Figure 5] 1A is a conceptual diagram for explaining a method for generating data for parity check, and FIG. 1B is a conceptual diagram for explaining a parity check method. [Figure 6] FIG. 10 is a timing diagram showing how the processor changes the pulse width of the PWM signal of the motor control signal using the serial interface. [Figure 7] 3 is a circuit diagram showing a configuration of the PWM signal generating circuit shown in FIG. 2 according to a first embodiment. FIG. [Figure 8] 3 is a timing chart showing the operation of the PWM signal generating circuit shown in FIG. 2 according to the first embodiment. FIG. [Figure 9] 4 is another timing diagram showing the operation of the PWM signal generating circuit shown in FIG. 2 according to the first embodiment. FIG. [Figure 10] FIG. 10 is a timing chart for explaining the second embodiment. [Figure 11] 10 is a flowchart illustrating a method for adjusting the pulse width of a PWM signal in the second embodiment. [Figure 12] 3 is a circuit diagram showing a configuration of a PWM signal generating circuit shown in FIG. 2 according to a second embodiment. FIG. [Figure 13] FIG. 1 is a circuit diagram showing an example of a motor drive circuit implemented as a semiconductor integrated circuit. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the disclosure according to the claims. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the disclosure, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations may be omitted.

[0010] First Embodiment Next, an embodiment in which the present disclosure is applied to a multifunction peripheral according to the first embodiment will be described below.

[0011] 1(a) and 1(b) are perspective views showing the overall configuration of a multifunction peripheral equipped with a plurality of motors.

[0012] 1(a) shows a printer unit that provides the printing function of the multifunction device. The printer unit is equipped with a control board 116 that controls the entire multifunction device, including a CR motor 231, an LF motor 232, an APP motor 233, an AC adapter 113, and a motor control circuit 200 (see FIG. 2) described later.

[0013] The CR motor 131 is a motor that drives the carriage 114 that transports the print head. The LF motor 132 is a motor that drives the transport mechanism 111 that transports the recording medium. The APP motor 133 is a motor that drives the cleaning mechanism 112 that cleans the nozzles of the print head and the automatic transport mechanism 115 that picks up only the topmost sheet of multiple recording media and feeds it to the print unit.

[0014] 1(b) shows a multifunction peripheral in which an image reading unit 121 that provides the image reading function of the multifunction peripheral and a panel unit 125 that provides a user interface function are incorporated into the printer unit shown in FIG. 1(a). The image reading unit 121 includes an image reading sensor 122, an FB motor 134 that drives the image reading sensor 122, and a platen glass 124 on which a document is placed.

[0015] Next, Fig. 2 shows details of the motor control circuit 200 according to the first embodiment of the present disclosure. The motor control circuit 200 is mounted on the control board 116 and includes a processor 203, a ROM 204, and a motor drive circuit 210. The motor drive circuit 210 further includes a serial data receiving unit 202, a control signal generating unit 201, an H-bridge control unit 205, and H-bridge circuits 206 to 209. Note that Fig. 2 omits an encoder for detecting the rotation speed or rotation phase of the motor rotor and a signal line for a phase feedback signal for feeding back the rotation speed and rotation detected by the encoder to the processor 203.

[0016] The processor 203 performs the following processing based on the firmware written to the ROM 204. That is, the processor 203 transmits to the serial data receiving unit 202 signals indicating the period, pulse width, and whether or not to energize the PWM signals for PWM driving the CR motor 231, LF motor 232, APP motor 233, and FB motor 234. The signals transmitted from the processor 203 to the serial data receiving unit 202 include three signals: a chip select signal CS, a clock signal CLK, and a data signal DT. Note that while the encoder and signal lines for feedback signals between the encoder and the processor are not shown in FIG. 2, in this embodiment the processor 203 is configured to be able to process speed feedback control or phase feedback control.

[0017] The processor 203 also transmits a sleep signal SLEEP to the serial data receiving unit 202. The sleep signal SLEEP is at a LOW level when the multifunction device is in a sleep state, and is at a HIGH level while the multifunction device is printing based on a print job. Therefore, when a multifunction device in a sleep state stops printing based on a print job, the level of the sleep signal SLEEP changes from LOW to HIGH. Note that the level of the sleep signal does not necessarily change from HIGH to LOW immediately after printing ends; therefore, when printing based on two print jobs is performed consecutively, the sleep signal SLEEP remains at a HIGH level across the two prints.

[0018] The serial data receiving unit 202 has a serial interface equipped with one data signal line, and receives serial data transmitted from the processor 203. The serial data receiving unit 202 performs a parity check (described later) and decodes an address included in the data signal DT, and then writes the data into the corresponding registers 401 to 404 and 411 to 415 in the control signal generating unit 201.

[0019] The control signal generation unit 201 generates two types of motor control signals, an Enable signal (EN) and a PWM signal (PH), for each motor based on the data written in the registers 401 to 404, 411 to 415. That is, it generates two types of motor control signals, an Enable signal (ENA to END) and a PWM signal (PHA to PHD), for each of the four motors 231 to 234. In this embodiment, the control signal generation unit 201 outputs the Enable signals ENA to END and the PWM signals PHA to PHD for the four motors to the H-bridge control unit 205.

[0020] The H-bridge control unit 205 outputs PWM signals A1 to A4, B1 to B4, C1 to C4, and D1 to D4 that control the switching elements of the H-bridge circuits 206 to 209, respectively, based on the Enable signals ENA to END and the PWM signals PHA to PHD.

[0021] The H-bridge circuits 206 to 209 are current control units that drive the CR motor 231, LF motor 232, APP motor 233, and FB motor 234 by switching the direction of current flow to each of them. Each H-bridge circuit uses four switching elements to control the amount and direction of current supplied to each motor from the power supply (power supply voltage Vcc).

[0022] The serial interface protocol will now be described with reference to Figure 3. The processor 203 on the transmitting side switches the level of the sleep signal SLEEP from LOW to HIGH when printing begins. Thereafter, as shown in the figure, serial data is repeatedly transmitted in 20-bit increments. If the transmission of 20 bits is considered to be the transmission of one packet, the data transmission for one packet is as follows:

[0023] First, the chip select signal CS is lowered from HIGH to LOW to activate the serial data receiving unit 202. Next, 20 pulses of a 20 MHz clock signal CLK are output, and simultaneously, the data signal DT is output bit by bit in sequence from MSB (Most Significant Bit) to LSB (Least Significant Bit) in synchronization with the pulses. In response, the serial data receiving unit 202 latches the data signal DT at the timing of the falling edge of the clock signal CLK and takes in 20 bits of data from MSB to LSB. Furthermore, the serial data receiving unit 202 performs a parity check (described later) on the received data, and if the parity check is passed, it decodes the address included in the data signal DT and writes the data to the specified registry.

[0024] Next, FIG. 4 shows the details of the registers 401 to 404 and 411 to 415 of the control signal generating unit 201.

[0025] Some of the registers 401 to 404 are PWM period setting registers that determine the PWM periods of the CR motor 231, LF motor 232, APP motor 233, and FB motor 234. Desired PWM period data (TPA to TPD) is written to nine bits b0 to b8 of these registers 401 to 404. The PWM period is a multiplication value of the 12 MHz reference clock of the control signal generation unit 201. For example, if the PWM period is 40 μs, the PWM period data indicates a value of 40×12=480.

[0026] Other parts of the registers 401 to 404 are delay time setting registers corresponding to the CR motor 231, LF motor 232, APP motor 233, and FB motor 234, respectively. Desired delay time data (DLA to DLD) is written in five bits b9 to b13 of these registers 401 to 404. The delay time is a multiplication value of the 12 MHz reference clock of the control signal generating unit 201. For example, if the delay time is 1 μs, the delay time data indicates a value of 1 × 12 = 12.

[0027] Additionally, a unique value indicating an address for identifying each register is written in the six bits of b14 to 19. In Fig. 4, b14 to 19 are simply labeled "address."

[0028] Registers 411 to 414 are pulse width setting registers that determine the pulse width of the PWM signals for driving the CR motor 231, LF motor 232, APP motor 233, and FB motor 234, respectively. Pulse width data (DTA to DTD) is written to nine bits b4 to b12 of these registers 411 to 414. The pulse width data is a multiplication value for the 12 MHz reference clock of the control signal generation unit 201, and if the on time is 20 μs, for example, it indicates a value of 20 × 12 = 240. Furthermore, a value indicating whether or not to energize is written to b13, and addresses are written to b14 to b19.

[0029] Furthermore, parity check data is written in b0 to b3. This parity check data is used to verify, in the following manner, whether the serial signal transferred from the processor 203 has reached the serial data receiving unit 202 normally without any data corruption along the way.

[0030] 5(a) and 5(b) are conceptual diagrams illustrating a method for generating parity-check data and a data check method using the same. First, the processor 203 performs the following process on the data to be written to each of the registers 411 to 415. That is, by performing the exclusive-OR operation shown in FIG. 5(a) on the 16-bit data to be written to b4 to b19, 4-bit parity-check data (parity bits) is generated, and these are set as the data to be written to b0 to b3. In the exclusive-OR operation, b0 is the exclusive-OR of b16, b12, b8, and b4, and b1 is the exclusive-OR of b17, b13, b9, and b5. Similarly, b2 is the exclusive-OR of b18, b14, b10, and b6, and b3 is the exclusive-OR of b19, b15, b11, and b7. The processor 203 transmits the five series of data (b0 to b19) thus generated to the control signal generator 201 via the serial data receiver 202 as data to be written into the registers 411 to 415.

[0031] Next, the control signal generator 201 performs a parity check on the received 20-bit data signal DT using the exclusive OR operation shown in FIG. 5(b). In the exclusive OR operation, the exclusive OR of b16, b12, b8, b4, and b0 is set to a0, and the exclusive OR of b17, b13, b9, b5, and b1 is set to a1. Similarly, the exclusive OR of b18, b14, b10, b6, and b2 is set to a2, and the exclusive OR of b19, b15, b11, b7, and b3 is set to a3. Furthermore, the control signal generator 201 performs an exclusive OR on the four operation results a0 to a3. If the result is 0, the parity check is passed, and the transferred data signal DT of b0 to b19 is stored in a register specified by the address. On the other hand, when the exclusive OR of a0 to a3 is 1, the parity check fails, and the transferred data signal DT of b0 to b19 is discarded and not stored in the register.

[0032] The purpose of the parity check is to prevent the motor from malfunctioning due to incorrect transmission of the data signal DT caused by noise, waveform distortion in the transmission path, or the like. In this embodiment, the parity check is performed on the data signal DT for the pulse width setting registers 411 to 414, whose data is frequently updated during motor operation, and for the register 415 described below. On the other hand, the data signal DT for the PWM period setting registers 401 to 404, which only needs to be set once at the start of operation, does not contain data for parity check and is therefore not subject to the parity check. The setting at the start of operation here is performed before the sleep signal SLEEP changes from low level to high level.

[0033] Register 415 is a multiple motor simultaneous stop register for simultaneously stopping multiple motors with a single serial communication, and is used when multiple motors need to be stopped quickly when an error occurs, etc. As mentioned above, a parity check is also performed on the data signal DT for register 415, so parity check data is output to b0 to b3. Values ​​indicating whether or not to energize the CR motor 231, LF motor 232, APP motor 233, and FB motor 234 are output to b4 to b7, which are assigned enable signals ENA2 to END2. Addresses are written to b14 to b19. Note that the values ​​of b8 to b13 are not used in the data signal DT for register 415.

[0034] Next, the control signal generating unit 201 generates enable signals ENA to END and PWM signals PHA to PHD based on the data stored in the registers 401 to 404 and 411 to 415, and outputs them to the H-bridge control circuit 205, as shown in FIG.

[0035] ENA to END are enable signals that control whether or not to energize the CR motor 231, LF motor 232, APP motor 233, and FB motor 234, respectively. These enable signals ENA to END are generated by the control signal generation unit 201 based on the values ​​of ENA to END that indicate whether or not to energize and that are stored in b13 of the registers 411 to 414, respectively. The enable signals ENA to END take on one of two output voltage levels, and are controlled to HIGH when energization is enabled and LOW when energization is disabled. The H-bridge control unit 205 outputs a PWM signal to the corresponding H-bridge circuits 206 to 209 only when the voltage level of the enable signal EN is HIGH. Note that a configuration may be added in which the enable signals ENA to END are generated based on both the values ​​of ENA to END that indicate whether or not to energize and that are stored in b13 of the registers 411 to 414, respectively, and the values ​​of ENA2 to END2 that are stored in b4 to b8 of the register 415.

[0036] PHA to PHD are PWM signals for PWM controlling the CR motor 231, LF motor 232, APP motor 233, and FB motor 234. The PWM signals PHA to PHD are generated by the control signal generator 201 based on the PWM cycle data (TPA to TPD) stored in b0 to b8 of the registers 401 to 404, respectively, and the pulse width data (DTA to DTD) stored in b4 to b12 of the registers 411 to 414.

[0037] Next, FIG. 6 shows how the processor 203 changes the pulse width of a PWM signal for controlling a motor via a serial interface. The serial data signal Serial IF is a simplified version of the three signals shown in FIG. 3: the chip select signal CS, the clock signal CLK, and the data signal DT. The positions of the bold vertical lines in the serial data signal Serial IF shown in FIG. 6 indicate a single serial communication for transmitting a set of data d0 to d19. In the example shown in FIG. 6, three serial communications are performed, as indicated by Serial IFs #1 to #3. In the serial communication via Serial IF #1, the duty ratio of the PWM signal PHA for the CR motor 231 is changed from 60% to 40% by changing the pulse width. Similarly, in Serial IF #2, the duty ratio of the PWM signal PHD for the FB motor 234 is changed from 80% to 20% by changing the pulse width. In Serial IF #3, the duty ratio of the PWM signal PHB for the LF motor 233 is changed from 20% to 50% by changing the pulse width.

[0038] Setting the duty ratio of the PWM signal PHB to 50% balances the forward and reverse rotation forces of the motor, which is equivalent to stopping rotation.In addition, by fine-tuning the forward and reverse rotation forces by setting the duty ratio of the PWM signal PHB to, for example, 49% or 51% depending on the rotation situation, high-precision stopping control and ultra-low speed control are possible.

[0039] The time required for serial transfer processing between the processor and motor drive circuit is approximately 4.2 μs when the clock frequency is 5 MHz and one packet is 20 bits, as shown in Figure 3. On the other hand, the time required for reception processing by the motor drive circuit 210 is simply latching using the high-speed clock within the motor drive circuit 210, so the processing time is on the order of 10 ns.

[0040] In contrast, the speed adjustment period (servo period) for each motor is about 1 ms. Therefore, for example, if the servo period for each motor is 1 ms, speed adjustment for each period is possible if a serial transfer process of approximately 4.2 μs is carried out once during this 1 ms. In other words, if the serial interface data transmission bandwidth is 5 Mb / s, the packet length is 20 bits, and the motor speed adjustment period is 1 ms, it is possible to PWM control more than 200 motors. Note that this effect can be further reduced by increasing the clock frequency and expanding the data transmission bandwidth.

[0041] FIG. 7 is a circuit diagram showing the configuration of the PWM signal generating circuit 221 shown in FIG.

[0042] The PWM signal generating circuit 221 has four individual circuits 221A to 221D corresponding to the four motors, CR motor 231, LF motor 232, APP motor 233, and FB motor 234.

[0043] Since the individual circuits 221A to 221D have the same configuration, only the individual circuit 221A will be described, and a description of the individual circuits 221B to 221D will be omitted.

[0044] The individual circuit 221A receives the clock CLK, the sleep signal SLEEP, the delay time data DLA and PWM cycle data TPA stored in the register 401, and the pulse width data DTA stored in the register 411. Based on these received signals and data, the individual circuit 221A generates and outputs the PWM signal PHA. More specifically, the individual circuit 221A generates and outputs the PWM signal PHA from a time t+DLA·T, which is delayed from the rising edge of the sleep signal SLEEP (also referred to as the "change time") by the delay time DLA·T specified by the delay time data DLA. Here, the individual circuit 221A gives the PWM signal PHA the cycle TPA·A specified by the PWM cycle data TPA. The individual circuit 221A also gives the PWM signal PHA the pulse width DTA·T specified by the pulse width data DTA. Therefore, the individual circuit 221A gives the PWM signal PHA a duty ratio DTA / TPA. Here, T is the clock period corresponding to the frequency of the clock CLK (T=1 / CLK).

[0045] The individual circuit 221A includes a delay circuit (DLYA) 701, a counter (COUNTA) 702, a comparator (COMPA1) 703, a register (REGA1) 704, a comparator (COMPA2) 705, a register (REGA2) 706, and a logical product circuit 707.

[0046] The delay circuit 701 delays the sleep signal SLEEP by a delay time DLA·T specified by the delay time data DLA, and outputs the delayed sleep signal SLEEP as a count enable signal (ENA).

[0047] Counter 702 is a synchronous counter that starts counting when clock CLK rises while the level of the count enable signal (delayed sleep signal SLEEP) input to enable terminal EN is HIGH. Although not shown, means for setting the count value of counter 702 to zero while the level of the count enable signal is LOW is provided inside or outside counter 702.

[0048] Register 704 stores a value obtained by subtracting 1 from the PWM cycle data TPA read from b0 to b8 of register 401. Although not shown, means for subtracting 1 from the PWM cycle data TPA is provided.

[0049] Comparator 703 compares the count value CNTA of counter 702 with the value (TPA-1) stored in register 704, and when the two match, outputs a reset signal that goes HIGH to counter 702. When the clock CLK rises while the reset signal is HIGH, counter 702 sets the count value to zero.

[0050] Therefore, the counter 702 repeatedly counts from 0 to a value obtained by subtracting 1 from the PWM cycle data TPA. In other words, the counter 702 repeatedly counts at a cycle TPA·T specified by the PWM cycle data TPA.

[0051] Register 706 stores a value obtained by subtracting 1 from pulse width data DTA read from b4 to b12 of register 411. Although not shown, means for subtracting 1 from pulse width data DTA is provided.

[0052] The comparator 705 compares the count value CNTA of the counter 702 with the value (DTA-1) stored in the register 706. If CNTA is equal to or less than (DTA-1), the comparator 705 sets the level of the output signal PHAA to HIGH, and otherwise sets the level of the output signal PHAA to LOW.

[0053] Therefore, the comparator 705 repeatedly outputs the signal PHAA, which has a HIGH level during the period DTA·T and a LOW level during the period (TPA-DTA)·T, in a cycle of TPA·T. In other words, the comparator 705 repeatedly outputs the signal PHAA, which has a pulse width of DTA·T, in a cycle of TPA·T.

[0054] The AND circuit 707 masks the signal PHAA with the enable signal ENA to prevent the level of the PWM signal PHA from becoming HIGH while the enable signal ENA is LOW, thereby generating the PWM signal PHA and outputting it as the output of the individual circuit 221A.

[0055] Fig. 8 is a timing diagram showing the operation of the PWM signal generating circuit shown in Fig. 2. However, Fig. 8 shows only the operation of the individual circuit 221A and the operation of the individual circuit 221B.

[0056] The individual circuit 221A outputs a PWM signal PHA having a period TPA·T and a pulse width DTA·T. The individual circuit 221B outputs a PWM signal PHB having a period TPB·T and a pulse width DTB·T. The rising time (also referred to as the "start time") of the PWM signal PHB has a delay time of (DLB-DLA)·T relative to the rising time of the PWM signal PHA.

[0057] FIG. 9 is another timing diagram showing the operation of the PWM signal generating circuit shown in FIG.

[0058] The rising time (also called "change time") of the count enable signal ENA is delayed by a delay time T from the rising time (also called "change time") of the sleep signal SLEEP. The rising time of the count enable signal ENB is delayed by a delay time T from the rising time of the count enable signal ENA. The rising time of the count enable signal ENC is delayed by a delay time T from the rising time of the count enable signal ENB. The rising time of the count enable signal END is delayed by a delay time T from the rising time of the count enable signal ENC.

[0059] As indicated by the count value CNTA, the counter 702 starts counting a little less than one clock period after the rising edge of the count enable signal ENA, and repeatedly counts up to 1FF. As indicated by the count value CNTB, the counter 712 starts counting a little less than one clock period after the rising edge of the count enable signal ENB, and repeatedly counts up to 1FF. As indicated by the count value CNTC, the counter 722 starts counting a little less than one clock period after the rising edge of the count enable signal ENC, and repeatedly counts up to 1FF. As indicated by the count value CNTD, the counter 732 starts counting a little less than one clock period after the rising edge of the count enable signal END, and repeatedly counts up to 1FF.

[0060] As shown by the register value REGA2, 0F3 is stored as DTA-1 in the register 706. Therefore, the PWM signal PHA has a HIGH level when the count value CNTA is from 0 to 0F3, and has a LOW level when the count value CNTA is from 0F4 to 1FF.

[0061] As shown by the register value REGB2, 003 is stored as DTB-1 in the register 716. Therefore, the PWM signal PHB is at a HIGH level when the count value CNTB is between 0 and 003, and at a LOW level when the count value CNTB is between 004 and 1FF.

[0062] As indicated by the register value REGC2, 081 is stored as DTC-1 in the register 726. Therefore, the PWM signal PHC has a HIGH level when the count value CNTC is between 0 and 081, and has a LOW level when the count value CNTC is between 082 and 1FF.

[0063] As indicated by the register value REGD2, 1FC is stored as DTD-1 in the register 736. Therefore, the PWM signal PHD has a HIGH level when the count value CNTD is between 0 and 1FC, and has a LOW level when the count value CNTD is between 1FD and 1FF.

[0064] According to the first embodiment, the start timings of the PWM signals PHA to PHD can be specified by the processor 203 using the delay time data DLA to DLD, with the rising edge of the sleep signal SLEEP as a reference. Therefore, by making the values ​​of the delay time data DLA to DLD different from one another, the start timings of the PWM signals PHA to PHD can be made different from one another. If the PWM signals PHA to PHD have a common cycle, the start timings of the cycles of the PWM signals PHA to PHD can be made continuously different from one another. Therefore, it is possible to prevent the timings at which switching currents are generated in the CR motor 231, LF motor 232, APP motor 233, and FB motor 234 from overlapping with one another.

[0065] Second Embodiment In the second embodiment, the falling timings of the PWM signals PHA to PHD are prevented from overlapping with one another.

[0066] FIG. 10 is a timing chart for explaining the second embodiment.

[0067] The rising edge of PWM signal PHB at time T12 is delayed by a delay time Td from the rising edge of PWM signal PHA at time T11. The pulse width Tb1 of PWM signal PHB is shorter than the pulse width Ta1 of PWM signal PHA by time Td. In this case, the falling edges of PWM signal PHA and PHB overlap at time T13.

[0068] In the second embodiment, in order to avoid the coincidence of the fall times between the PWM signals, whether such a coincidence will occur in the future is predicted, and if so, the fall times of at least some of the PWM signals are adjusted to avoid such a coincidence. In the example shown in Figure 10, the fall time of the PWM signal PHB is adjusted by a time Tε to change it into the PWM signal PHB'. The timing of the fall of the PWM signal PHB' is shifted from the fall of the PWM signal PWA.

[0069] 11 is a flowchart illustrating a method for adjusting the pulse width of a PWM signal in the second embodiment. This method will be described as being executed by a processor (not shown) installed in the PWM signal generating circuit 221, but may also be executed by hardware, as will be described later.

[0070] In S1101, the processor waits until one of the PWM signals PHA to PHD rises, and when one of the PWM signals PHA to PHD rises, the process proceeds to S1102.

[0071] In S1102, the processor calculates the falling edge time of each of the PWM signals PHA to PHD. Specifically, the processor calculates the falling edge time for each of the PWM signals PHA to PHD based on the most recent rising edge time and pulse width. The time may be expressed by a clock number. Taking the PWM signal PHA as an example, the processor detects the clock number when the count value of the counter 702 changes from the maximum count value to zero as the rising edge timing of the PWM signal PHA. Then, Clock number + DTA is calculated as the clock number corresponding to the falling edge timing of the PWM signal PHA.

[0072] In S1203, the processor determines whether or not at least two of the four falling edge times calculated in S1102 match.

[0073] If at least two falling times do not match (if all falling times are different from one another), the processor returns the process to S1102, and if at least two falling times match, the processor proceeds to S1104.

[0074] In S1104, the processor changes at least one of the falling times so that the four falling times are shifted by changing at least one of the pulse width data (DTA to DTD).

[0075] FIG. 12 is a circuit diagram showing a configuration of the PWM signal generating circuit shown in FIG. 2 according to a second embodiment.

[0076] The PWM signal generating circuit according to the second embodiment includes a rising edge detecting unit 1201 , a rising edge time holding unit 1202 , a falling edge time calculating unit 1203 , a falling edge time agreement determining unit 1204 , and a pulse width data changing unit 1205 .

[0077] The rising edge detection unit 1201 receives the PWM signals PHA to PHD and detects their rising edges. When the rising edge detection unit 1201 detects the rising edge of the PWM signal PHA, it outputs a detection signal DETA to the rising edge time holding unit 1202. When the rising edge detection unit 1201 detects the rising edge of the PWM signal PHB, it outputs a detection signal DETB to the rising edge time holding unit 1202. When the rising edge detection unit 1201 detects the rising edge of the PWM signal PHC, it outputs a detection signal DETC to the rising edge time holding unit 1202. When the rising edge detection unit 1201 detects the rising edge of the PWM signal PHD, it outputs a detection signal DETD to the rising edge time holding unit 1202. When the rising edge detection unit 1201 detects the rising edge of any of the PWM signals PHA to PHD, it outputs a detection signal DET0 to the falling edge time calculation unit 1203, the falling edge time coincidence time determination unit 1204, and the pulse width data modification unit 1205.

[0078] When the rising edge time holder 1202 receives any of the detection signals DETA to DETD from the rising edge detection unit 1201, it holds the clock number at that time as a value indicating the rising edge time of the PWM signal whose rising edge was detected. Specifically, when the detection signal DETA is received from the rising edge detection unit 1201, the rising edge time holder 1202 holds the clock number M(DETA) at that time as a value indicating the rising edge time of the PWM signal PHA. When the detection signal DETB is received from the rising edge detection unit 1201, the rising edge time holder 1202 holds the clock number M(DETB) at that time as a value indicating the rising edge time of the PWM signal PHB. When the detection signal DETC is received from the rising edge detection unit 1201, the rising edge time holder 1202 holds the clock number M(DETC) at that time as a value indicating the rising edge time of the PWM signal PHC. When the detection signal DETD is input from the rising edge detection unit 1201, the rising edge time holding unit 1202 holds the clock number M(DETD) at that time as a value indicating the rising edge time of the PWM signal PHD.

[0079] The fall time calculation unit 1203 calculates the fall times of the PWM signals PHA to PHD when it receives the detection signal DET0 from the rise detection unit 1201. Specifically, when it receives the detection signal DET0 from the rise detection unit 1201, it holds N(DETA) = M(DETA) + DTA as the fall time of the PWM signal PHA. The fall time calculation unit 1203 also holds N(DETB) = M(DETB) + DTB as the fall time of the PWM signal PHB. The fall time calculation unit 1203 also holds N(DETC) = M(DETC) + DTC as the fall time of the PWM signal PHC. The fall time calculation unit 1203 also holds N(DETD) = M(DETD) + DTD as the fall time of the PWM signal PHB.

[0080] The fall time agreement determination unit 1204 determines whether or not at least two of the fall times of the PWM signals PHA to PHD match when the detection signal DET0 is input from the rise detection unit 1201. Specifically, when the detection signal DET0 is input from the rise detection unit 1201, the fall time agreement determination unit 1204 determines whether or not at least two of N(DETA), N(DETB), N(DETC), and N(DETD) match.

[0081] When the detection signal DET0 is input from the rising edge detection unit 1201, the pulse width data modification unit 1205 executes the following. That is, if the determination result of the falling edge time agreement determination unit 1204 is affirmative, the pulse width data modification unit 1205 modifies at least one of the pulse width data DTA to DTB stored in the registers 706, 716, 726, or 723. For example, if N(DETA) and N(DETB) match, the pulse width data modification unit 1205 modifies at least one of them so that these two do not match. However, after the modification, neither N(DETA) nor N(DETB) matches either N(DETC) or N(DETD). If N(DETA), N(DETB), and N(DETC) match, the pulse width data modification unit 1205 modifies at least two of these three so that these three do not match. However, none of the changed N(DETA), N(DETB), and N(DETC) match N(DETD). If N(DETA), N(DETB), N(DETC), and N(DETD) match, the pulse width data changing unit 1205 changes at least any three of these four so that they do not match.

[0082] According to the second embodiment, it is possible to prevent the timing of the falling edges of the PWM signals PHA to PHD from overlapping with one another, thereby preventing the timing of the switching currents generated in the CR motor 231, LF motor 232, APP motor 233, and FB motor 234 from overlapping with one another.

[0083] 7 is merely an example, and the PWM signal generation circuit 221 may have other configurations. For example, the PWM signal generation circuit 221 may include a processor for realizing at least a part of the method of the second embodiment and a memory for storing a program executed by the processor.

[0084] <Third embodiment> The third embodiment of the present disclosure is a motor drive circuit 1310 obtained by extracting the motor drive circuit 210 shown in Fig. 1 from the motor and integrating it into a semiconductor integrated circuit. An example is shown in Fig. 13. That is, this motor drive circuit includes a serial data receiving unit 202, a control signal generating unit 201, registers 401 to 404, 411 to 415, an H-bridge control unit 205, and H-bridge circuits 206 to 209. The functions and operations of these components are the same as those shown in Fig. 1, so a description thereof will be omitted here.

[0085] The motor drive circuit 1310 is a semiconductor integrated circuit that includes at least a chip select terminal CS, a clock terminal CLK, a data terminal DT as a serial interface, and four motor output terminals A / A*, B / B*, C / C*, and D / D*. Note that incidental circuit terminals such as the power supplies and GND of the H-bridge circuits 206-209 are omitted in Figure 13.

[0086] Furthermore, it is also possible to add a so-called buck converter circuit for generating the DC power supply required for the multifunction device of the first embodiment to this semiconductor integrated circuit, thereby forming a composite integrated circuit.

[0087] <Other embodiments> In the above embodiment, an example in which the delay time is different for all combinations of four motors has been described, but this is not limited to this. For example, a common delay time may be set for two or three motors. Even in such a case, the same effect as when the delay times are different for all combinations of four motors can be achieved, although the degree of this effect may vary.

[0088] Also, if the PWM signals for some motors have the same period but the PWM signals for the remaining motors have different periods, you can simply vary the delay times between the PWM signals with the same period, because the PWM signals for the remaining motors will not be synchronized with the PWM signals with the same period.

[0089] In the above embodiment, an example was described in which the start time of each PWM signal is controlled based on the sleep signal SLEEP. However, this is not limited to this, and a signal other than the sleep signal SLEEP may be used as a common reference signal to control the start time of each PWM signal. For example, unused bit b8 of register 415 may be used for the common reference signal. Alternatively, a register other than registers 401-404 and 411-415 may be provided in the control signal generator 201, and a bit for the common signal may be provided in that register. In such a case, a circuit may be provided that, when a reference signal received from processor 203 via serial communication is written to a register, immediately reads the reference signal from the register and supplies it to delay circuits 701, 711, 721, and 731.

[0090] The HIGH level / LOW level of at least some of the various signals described above may be inverted. The counters 703, 713, 723, and 733 may be down counters. In this case, the peripheral circuits and setting values ​​may be changed as appropriate. The counters 703, 713, 723, and 733 may be asynchronous counters. In this case, the peripheral circuits and setting values ​​may be changed as appropriate. The PWM signal generation circuit 221 may be entirely or partially replaced by a processor that executes a program.

[0091] In the above embodiment, a multifunction peripheral having at least an image forming unit and an image reading unit has been described as an example, but the above embodiment can also be applied to an image forming apparatus having at least an image forming unit.

[0092] Embodiments of the present invention may be implemented by a computer in a system or device that reads and executes computer-executable instructions (e.g., one or more programs) for performing one or more functions of the above-described embodiments, recorded on a storage medium (sometimes more fully referred to as a "non-transitory computer-readable storage medium"), and / or includes one or more circuits (e.g., application-specific integrated circuits (ASICs)) for performing one or more functions of the above-described embodiments, and may also be implemented by a method executed by the computer in the system or device by reading and executing the computer-executable instructions (e.g., one or more programs) for performing one or more functions of the above-described embodiments, recorded on a storage medium, and / or controlling one or more circuits (e.g., application-specific integrated circuits (ASICs)) for performing one or more functions of the above-described embodiments. The computer may include one or more processors (e.g., central processing unit (CPU), microprocessor unit (MPU)), and may include separate computers or a network of separate processors for reading and executing the computer-executable instructions. The computer-executable instructions may be provided to the computer, for example, from a network or a storage medium. The storage medium may include, for example, one or more of a hard disk, random access memory (RAM), read-only memory (ROM), storage of a distributed computing system, an optical disk (compact disk (CD), digital versatile disk (DVD), or Blu-ray disk (BD)®), a flash memory device, a memory card, and the like.

[0093] <Technical Features of the Present Disclosure> The present disclosure includes the following configurations, methods, and programs.

[0094] [Configuration 1] A PWM signal generating circuit for generating a plurality of PWM signals for PWM driving a plurality of motors, a plurality of individual circuits corresponding to the plurality of motors; Each of the individual circuits receives a reference signal common to the plurality of individual circuits and first data specifying a delay time corresponding to each motor from the outside, and generates a PWM signal for each motor, the start time of which is delayed by the delay time specified by the first data from the change time at which the reference signal changes from a first level to a second level, and the start time of the PWM signal is set to the start time of the first PWM period. PWM signal generation circuit.

[0095] [Configuration 2] the delay times differ between at least two of the motors; 2. The PWM signal generating circuit according to claim 1.

[0096] [Configuration 3] the first data for each motor is transmitted from an external device via serial communication, further comprising a register for storing the first data for each motor; 3. The PWM signal generating circuit according to configuration 1 or 2.

[0097] [Configuration 4] Each of the individual circuits further receives second data from the outside, the second data specifying the PWM period corresponding to each motor; Each of the individual circuits causes the PWM signal corresponding to each motor to have the PWM period specified by the second data. 4. The PWM signal generating circuit according to any one of configurations 1 to 3.

[0098] [Configuration 5] the delay times differ between at least two of the motors; The PWM period is common to the at least two motors having different delay times. 5. The PWM signal generating circuit according to configuration 4.

[0099] [Configuration 6] the second data for each motor is transmitted from an external device via serial communication; further comprising a register for storing the second data for each motor; 6. The PWM signal generating circuit according to configuration 4 or 5.

[0100] [Configuration 7] Each of the individual circuits further receives third data from the outside, the third data specifying a pulse width of the PWM signal corresponding to each motor; Each of the individual circuits causes the PWM signal corresponding to each motor to have the pulse width designated by the third data. 7. The PWM signal generating circuit according to any one of configurations 1 to 6.

[0101] [Configuration 8] the third data for each motor is transmitted from an external device via serial communication, further comprising a register for storing the third data for each motor; 8. The PWM signal generating circuit according to configuration 7.

[0102] [Configuration 9] Each of the individual circuits further receives from the outside second data specifying the PWM period corresponding to each motor and third data specifying the pulse width of the PWM signal corresponding to each motor; Each of the individual circuits causes the PWM signal corresponding to each motor to have the PWM period specified by the second data and the pulse width specified by the third data. 2. The PWM signal generating circuit according to claim 1.

[0103] [Claim 10] the first data, the second data, and the third data for each motor are transmitted from an external device via serial communication; further comprising a register for storing the first data, the second data, and the third data for each motor; 10. The PWM signal generating circuit according to configuration 9.

[0104] [Configuration 11] The individual circuits include: a delay circuit that delays the reference signal input from outside by the delay time indicated by the first data; a counter that starts counting from the start time obtained by delaying the reference signal using the delay circuit, and repeatedly operates at the PWM period indicated by the second data; means for generating the PWM signal based on the count value of the counter and the pulse width indicated by the third data; Equipped with 11. The PWM signal generating circuit according to configuration 9 or 10.

[0105] [Configuration 12] the PWM signal has a first level for a time corresponding to a pulse width from a start time of the PWM period in each of the PWM periods, and a second level for the remaining time; further comprising an adjusting means for adjusting a pulse width of at least one PWM signal among the plurality of PWM signals so that the timings at which the PWM signals change from the first level to the second level do not match when it is predicted that at least some of the PWM signals among the plurality of PWM signals will match with each other at the times when they change from the first level to the second level; 12. The PWM signal generating circuit according to any one of configurations 1 to 11.

[0106] [Configuration 13] A PWM signal generating circuit according to any one of configurations 1 to 12; an image forming unit; the plurality of motors used for the image forming unit; a control unit that outputs the data to the PWM signal generation circuit; Equipped with Image forming device.

[0107] [Configuration 14] A PWM signal generating circuit according to any one of configurations 1 to 12; an image forming unit; an image reading unit; the plurality of motors used for an image forming unit or an image reading unit; a control unit that outputs the data to the PWM signal generation circuit; Equipped with Multifunction machine.

[0108] [program] A program for causing a computer to function as a PWM signal generating device for generating a plurality of PWM signals for PWM driving a plurality of motors, causing a computer to function as a plurality of individual devices corresponding to the plurality of motors; Each of the individual devices receives a reference signal common to the plurality of individual devices and first data specifying a delay time corresponding to each motor from the outside, and generates a PWM signal for each motor, the start time of which is delayed by the delay time specified by the first data from the change time at which the reference signal changes from a first level to a second level, and the start time of the PWM signal is set to the start time of a first PWM period. program.

[0109] [method] A PWM signal generation method for generating a plurality of PWM signals for PWM driving a plurality of motors, comprising: a plurality of individual steps corresponding to the plurality of motors; In each of the individual steps, one reference signal common to the plurality of individual steps and first data specifying a delay time corresponding to each motor are input from the outside, and a PWM signal is generated for each motor, with the start time being delayed by the delay time specified by the first data from the change time at which the reference signal changes from a first level to a second level, and the start time being the start time of a first PWM period. PWM signal generation method. [Explanation of symbols]

[0110] 201 control signal generation unit 202 Serial data receiver 205: H-bridge control section 206-209: H-bridge circuit 210: Motor drive circuit

Claims

1. A PWM signal generating circuit for generating a plurality of PWM signals for PWM driving a plurality of motors, a plurality of individual circuits corresponding to the plurality of motors; Each of the individual circuits receives a reference signal common to the plurality of individual circuits and first data specifying a delay time corresponding to each motor from the outside, and generates a PWM signal for each motor, the start time of which is delayed by the delay time specified by the first data from the change time at which the reference signal changes from a first level to a second level, and the start time of the PWM signal is set to the start time of a first PWM period. PWM signal generation circuit.

2. the delay times differ between at least two of the motors; 2. The PWM signal generating circuit according to claim 1.

3. the first data for each motor is transmitted from an external device via serial communication, further comprising a register for storing the first data for each motor; 2. The PWM signal generating circuit according to claim 1.

4. Each of the individual circuits further receives second data from the outside, the second data specifying the PWM period corresponding to each of the motors; Each of the individual circuits causes the PWM signal corresponding to each motor to have the PWM period specified by the second data.

2. The PWM signal generating circuit according to claim 1.

5. the delay times differ between at least two of the motors; the PWM period is common to the at least two motors having different delay times; 5. The PWM signal generating circuit according to claim 4.

6. the second data for each motor is transmitted from an external device via serial communication, further comprising a register for storing the second data for each motor; 5. The PWM signal generating circuit according to claim 4.

7. each of the individual circuits further receives third data from the outside, the third data specifying a pulse width of the PWM signal corresponding to each of the motors; Each of the individual circuits causes the PWM signal corresponding to each motor to have the pulse width designated by the third data.

2. The PWM signal generating circuit according to claim 1.

8. the third data for each motor is transmitted from an external device via serial communication, further comprising a register for storing the third data for each motor; 8. The PWM signal generating circuit according to claim 7.

9. each of the individual circuits further receives from the outside second data specifying the PWM period corresponding to each of the motors and third data specifying the pulse width of the PWM signal corresponding to each of the motors; each of the individual circuits causes the PWM signal corresponding to each motor to have the PWM period designated by the second data and the pulse width designated by the third data; 2. The PWM signal generating circuit according to claim 1.

10. the first data, the second data, and the third data for each motor are transmitted from an external device via serial communication; further comprising a register for storing the first data, the second data, and the third data for each motor; 10. The PWM signal generating circuit according to claim 9.

11. The individual circuits include: a delay circuit that delays the reference signal input from outside by the delay time indicated by the first data; a counter that starts counting from the start time obtained by delaying the reference signal using the delay circuit, and repeatedly operates at the PWM period indicated by the second data; means for generating the PWM signal based on the count value of the counter and the pulse width indicated by the third data; Equipped with 10. The PWM signal generating circuit according to claim 9.

12. the PWM signal has a first level for a time corresponding to a pulse width from a start time of the PWM period in each of the PWM periods, and has a second level for the remaining time; further comprising an adjusting means for adjusting a pulse width of at least one PWM signal among the plurality of PWM signals so that the plurality of PWM signals do not match with each other at the timings at which they change from the first level to the second level, when it is predicted that at least some of the PWM signals among the plurality of PWM signals will match with each other at the timings at which they change from the first level to the second level; 2. The PWM signal generating circuit according to claim 1.

13. A PWM signal generating circuit according to any one of claims 1 to 12; an image forming unit; the plurality of motors used for the image forming unit; a control unit that outputs the data to the PWM signal generation circuit; Equipped with Image forming device.

14. A PWM signal generating circuit according to any one of claims 1 to 12; an image forming unit; an image reading unit; the plurality of motors used for an image forming unit or an image reading unit; a control unit that outputs the data to the PWM signal generation circuit; Equipped with Multifunction machine.

15. A program for causing a computer to function as a PWM signal generating device for generating a plurality of PWM signals for PWM driving a plurality of motors, comprising: causing a computer to function as a plurality of individual devices corresponding to the plurality of motors; Each of the individual devices receives a reference signal common to the plurality of individual devices and first data specifying a delay time corresponding to each motor from the outside, and generates a PWM signal for each motor, the start time of which is delayed by the delay time specified by the first data from the change time at which the reference signal changes from a first level to a second level, and the start time of the PWM signal is set to the start time of a first PWM period. program.

16. A PWM signal generation method for generating a plurality of PWM signals for PWM driving a plurality of motors, comprising: a plurality of individual steps corresponding to the plurality of motors; In each of the individual steps, one reference signal common to the plurality of individual steps and first data specifying a delay time corresponding to each motor are input from the outside, and a PWM signal is generated for each motor, with the start time of a first PWM period being set to a start time delayed by the delay time specified by the first data from the change time at which the reference signal changes from a first level to a second level. PWM signal generation method.

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