Semiconductor device and failure analysis method for semiconductor device

Abstract

To provide a semiconductor device and method capable of analyzing a failure.SOLUTION: A semiconductor device according to the present disclosure includes a central processing unit (CPU), an external terminal that receives a signal from the outside, a memory that stores an external input signal supplied via the external terminal, and a switching circuit that switches an input signal necessary for processing in the CPU from the external input signal obtained via the external terminal to the external input signal stored in the memory.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices and methods, for example, to semiconductor devices and methods that enable failure analysis. [Background technology]

[0002] Patent Document 1 discloses a microcomputer failure analysis system that estimates the clock count at the time of failure by comparing the input and output signal levels at each clock count of a faulty product and a good product, and then estimates the cause of the failure by performing an investigation using an ICE (In Circuit Emulator). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-113447 Summary of the Invention [Problem to be solved by the invention]

[0004] Not only in the system disclosed in Patent Document 1, but in semiconductor devices as well, it is required to be possible to analyze a failure that has occurred.

[0005] Other objects and novel features will become apparent from the description of this specification and the accompanying drawings. [Means for solving the problem]

[0006] A semiconductor device according to one embodiment of the present disclosure comprises a central processing unit (CPU), an external terminal for receiving a signal from the outside, a first memory for storing an external input signal supplied via the external terminal, and a switching circuit for switching an input signal required for processing by the CPU from the external input signal obtained via the external terminal to the external input signal stored in the first memory.

[0007] In a method according to one aspect of the present disclosure, a semiconductor device stores an external input signal that has passed through an external terminal of the semiconductor device that has been determined to be malfunctioning in a first memory, and based on an instruction, switches the input signal to be provided to the semiconductor device from the external input signal that has passed through the external terminal to the external input signal stored in the first memory, operates the semiconductor device using the signal stored in the first memory as the input signal, and identifies the location of the failure within the semiconductor device. [Effects of the Invention]

[0008] The present disclosure can provide a semiconductor device and method that enable failure analysis. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a block diagram showing a configuration example of a semiconductor device according to a first embodiment; [Figure 2] 4 is a flowchart showing an example of a typical process of the semiconductor device according to the first embodiment. [Figure 3] FIG. 10 is a diagram illustrating an example of a method for identifying a failure. [Figure 4] FIG. 10 is a diagram illustrating an example of a failure identification result. [Figure 5] FIG. 10 is a block diagram showing a configuration example of a semiconductor device according to a second embodiment. [Figure 6] FIG. 10 is a block diagram showing a configuration example of a semiconductor device according to a third embodiment. [Figure 7] FIG. 10 is a block diagram showing a configuration example of a semiconductor device according to a fourth embodiment. [Figure 8] FIG. 10 is a block diagram showing a configuration example of a semiconductor device according to a fifth embodiment. [Figure 9] FIG. 13 is a block diagram showing a configuration example of a semiconductor device according to a sixth embodiment. [Figure 10] 10 is a timing chart showing an operation in a normal mode. [Figure 11] 10 is a timing chart showing an operation in a recording mode. [Figure 12]10 is a timing chart showing an operation in a playback mode. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the drawings. Note that the drawings are simplified, and the technical scope of the embodiments should not be narrowly interpreted based on the description in the drawings. Furthermore, identical elements are given the same reference numerals, and duplicate explanations will be omitted. In the block diagram showing an example configuration of a semiconductor device, arrows connecting components indicate the characteristic data flows shown below. However, the data exchanged between components is not limited to those shown below.

[0011] In the following embodiments, when necessary for convenience, the description will be divided into multiple sections or embodiments. However, unless otherwise specified, they are not unrelated to each other, and one is a partial or complete modification, application example, detailed explanation, supplementary explanation, etc. of the other. Furthermore, in the following embodiments, when the number of elements (including the number, numerical value, amount, range, etc.) is mentioned, it is not limited to that specific number, and may be more or less than the specific number, unless otherwise specified or when it is clearly limited to a specific number in principle.

[0012] Furthermore, in the following embodiments, the components (including operational steps, etc.) are not necessarily essential unless otherwise specified or considered to be clearly essential in principle. Similarly, in the following embodiments, when referring to the shape, positional relationship, etc. of components, etc., it is intended to include those that are substantially similar or approximate to the shape, etc., unless otherwise specified or considered to be clearly not essential in principle. The same applies to the above numbers, etc. (including numbers, numerical values, amounts, ranges, etc.).

[0013] Furthermore, the configurations or processes shown in each embodiment can be combined with the configurations or processes shown in other embodiments as appropriate.

[0014] <Preliminary review by the inventor> Before describing the semiconductor device according to this embodiment, a failure analysis method previously studied by the present inventors will be described.

[0015] Based on the description in Patent Document 1, the following failure analysis method is considered as related technology. First, the customer confirms that a malfunction has occurred on a board on which a semiconductor device, for example, a microcontroller (hereinafter also referred to as an MCU), is mounted. Next, the customer removes the MCU from the board and re-mounts the MCU on another board to confirm whether the malfunction can be reproduced on the other board. If the malfunction occurs on both boards, it is determined that there is a fault in the MCU, and the customer provides the manufacturer with the board on which the malfunctioning MCU is mounted, or the removed MCU alone, and the board from which the MCU has been removed.

[0016] The manufacturer uses special tools (for example, a baseboard, utility board, or PC (Personal Computer)) to operate a defective MCU and a good MCU. The manufacturer compares the output signal data of the defective MCU with that of the good MCU, and investigates the clock count, program counter value, etc. that cause differences in operation between the two. Based on the results of the investigation, the manufacturer then analyzes the execution instructions and deduce the cause of the failure.

[0017] In manufacturer failure analysis, it is necessary to identify the location of the failure in order to clarify the cause of the failure. A tester for fault location identification is used to identify the location of the failure. A fault location identification program is required to reproduce the malfunction on this tester.

[0018] However, the related technologies described above have the following problems. Recently, due to the increasing number of pins on a board, BGA (Ball Grid Array) packages have become the mainstream for semiconductor device packaging. However, customers generally do not have BGA reballing equipment, and there are cases where they are unable to remove and remount the MCU. Furthermore, while it may be possible to infer the cause of a failure by analyzing the execution instructions, as in the related technologies, it is difficult to pinpoint the location of the failure. To pinpoint the location of the failure, a tester for pinpointing the failure is used. To reproduce the malfunction on the tester, the manufacturer needs a dedicated program for pinpointing the failure.

[0019] The semiconductor device described in the following embodiments can solve the above problems.

[0020] <First Embodiment> [Configuration Description] FIG. 1 is a block diagram showing a configuration example of a semiconductor device H10 according to a first embodiment. The semiconductor device H10 is mounted on a printed circuit board H, and an input signal EI1 is input thereto. The input signal EI1 is a signal provided to the semiconductor device H10 from a component H1 mounted on the printed circuit board H and provided outside the semiconductor device H10 via an external terminal H15. The semiconductor device H10 is, for example, a microcontroller (MCU) and includes a central processing unit (CPU) H12 and a memory H13. The semiconductor device H10 further includes a selector H11, a switching circuit H14, and an external terminal H15. The component H1 is, for example, a component having a communication I / F. Hereinafter, the printed circuit board H on which the semiconductor device H10 and the component H1 are mounted will also be simply referred to as the board H.

[0021] The selector H11 is connected to the CPU H12 and the memory H13 via the bus B1. The selector H11 switches the input signal (i.e., the external input signal) provided from outside the semiconductor device H10 and used in the processing of the CPU H12 from the input signal EI1 to the signal MI1 stored in the memory H13, in response to the control of the switching circuit H14. In other words, the selector H11 switches the path of the external input signal used by the CPU H12 in response to the control of the switching circuit H14.

[0022] The CPU H12 can execute a program stored in the memory H13 using the input signal EI1 or the input signal MI1 input via the selector H11 as an external input signal.

[0023] When the CPU H12 uses the input signal EI1 from the component H1 via the selector H11 as an external input signal to execute processing, the memory H13 simultaneously stores this input signal EI1. Any type of memory can be used for the memory H13. However, in order to store the input signal EI1 even after the power supply of the semiconductor device H10 is turned off, it is desirable that the memory H13 be a non-volatile memory. The memory H13 also stores programs to be executed by the CPU H12.

[0024] The switching circuit H14 controls the selector H11 based on the instruction. The switching circuit H14 switches the external input signal used in the processing of the CPU H12 between the signal MI1 stored in the memory H13 and the input signal EI1 from the component H1, depending on the instruction of the operation mode. The instruction to the switching circuit H14 may be based on an instruction signal from the outside, or may be based on information stored in the semiconductor device H10. Details of this will be described later in the second embodiment and subsequent embodiments.

[0025] The signal output from memory H13 when the signal stored in memory H13 is input to CPU H12 as an external input signal may be input signal EI1 originally stored in memory H13, or may be a signal different from input signal EI1. For example, an input signal stored in a memory of another semiconductor device having a similar configuration to semiconductor device H10 may be newly stored in memory H13 and output from memory H13. Signal MI1 output from memory H13 does not pass outside semiconductor device H10 (for example, without passing through component H1 provided on substrate H), but is input to CPU H12 as an external input signal.

[0026] The memory H13 may be included in the semiconductor device 10, or may be mounted on the printed circuit board H as a component separate from the semiconductor device 10.

[0027] [Explanation of the processing flow] 2 is a flowchart showing an example of a typical process of the semiconductor device H10, and an overview of the process of the semiconductor device H10 will be explained with reference to this flowchart. Note that the explanation of each process that has already been explained will be omitted as appropriate.

[0028] First, the memory H13 stores an input signal EI1 from the component H1 mounted on the board H (step S11). At this time, the CPU H12 can operate in accordance with the input signal EI1. By detecting the operating status of the semiconductor device H10, the user can determine whether or not there is an abnormality in the operation of the semiconductor device H10.

[0029] Here, the processing of step S11 described above is also performed for a semiconductor device mounted on another printed circuit board having the same configuration as board H. That is, the semiconductor device mounted on the other printed circuit board receives an input signal (hereinafter referred to as input signal EI2) from a component mounted on the other printed circuit board and stores this input signal. As a result, the input signal EI2 provided to the semiconductor device mounted on the other printed circuit board is stored in the memory in the semiconductor device mounted on the other printed circuit board.

[0030] After the input signal EI1 is stored in the memory H13, the user stores the input signal EI2 stored in the memory of a semiconductor device mounted on another printed circuit board in the memory H13. Here, the user may store the input signal EI1 stored in the memory H13 in the memory of a semiconductor device mounted on another printed circuit board.

[0031] Thereafter, the switching circuit H14 controls the selector H11 based on the instruction to switch the external input signal used in the processing of the CPU H12 from the input signal EI1 from the component H1 to the signal MI1 stored in the memory H13 (step S12). The CPU H12 uses the signal MI1 stored in the memory H13 as the external input signal. Here, the signal MI1 stored in the memory H13 is the input signal EI2 provided by a semiconductor device mounted on another printed circuit board from its counterpart component. Therefore, the CPU H12 executes processing using the input signal EI2. At this time, a sensor provided inside or outside the semiconductor device H10 detects the operating status of the semiconductor device H10, allowing the user to determine whether or not there is an abnormality in the operation of the semiconductor device H10.

[0032] FIG. 3 is a diagram illustrating an example of a method for identifying a fault. This example illustrates a situation in which an operational abnormality (i.e., a fault) occurs in a function implemented by a component mounted on printed circuit board A, while no operational abnormality occurs in printed circuit board B. Hereinafter, printed circuit board A will be referred to as board A, and printed circuit board B will be referred to as board B. As shown in FIG. 1, boards A and B each have the configuration of board H, which includes semiconductor device H10. Specifically, boards A and B each have components corresponding to component H1 and semiconductor device H10 shown in FIG. 1. Hereinafter, board A will be described as having component A1 and semiconductor device A10, and board B will be described as having component B1 and semiconductor device B10. Furthermore, semiconductor devices A10 and B10 will each be described as having components corresponding to semiconductor device H10 shown in FIG. 1. Specifically, semiconductor device A10 includes selector A11, CPU A12, memory A13, and switching circuit A14. Furthermore, semiconductor device B10 includes selector B11, CPU B12, memory B13, and switching circuit B14. At this time, the users of boards A and B perform the following fault identification process.

[0033] (1) First, the user executes the process of step S11 on board A. That is, the semiconductor device A10 operates using the input signal EIA from the component A1, and stores the input signal EIA in memory A13. At this time, the user monitors the operation of board A to determine whether there is an abnormality in the operation of board A. Here, it is assumed that there is an abnormality in the operation of board A.

[0034] However, at this point, the user cannot determine whether the cause of the failure is in the semiconductor device A10 or in a board A other than the semiconductor device A10 (for example, a component A1). Therefore, the user performs the following process to determine the cause of the failure.

[0035] (2) The user also executes the process of step S11 on board B. That is, the semiconductor device B10 operates using the input signal EIB from the component B1, and stores the input signal EIB in memory B13. At this time, the user monitors the operation of the functions realized by board B to determine whether there is an abnormality in the operation of board B. Here, it is assumed that it is determined that there is no abnormality in the operation of board B.

[0036] (3) Next, the user reads the input signal EIA stored in the memory A13 of the semiconductor device A10 and the input signal EIB stored in the memory B13 of the semiconductor device B10, and writes the input signal EIB to the memory A13 and the input signal EIA to the memory B13. In other words, the user swaps the input signal data stored in the memories of the respective semiconductor devices.

[0037] (4) Thereafter, the user executes the process of step S12 on board A. The selector A11 switches the path of the signal to be input as an external input signal so that the CPU A12 executes processing using the signal stored in memory A13 as the external input signal. At this time, the signal stored in memory A13 is the input signal EIB input from the component B1 on board B to the semiconductor device B10. The user also switches the path of the input signal using the selector B11 on board B so that the signal stored in memory B13 is used as the external input signal in the processing of the CPU B12. At this time, the signal stored in memory B13 is the input signal EIA input from the component A1 on board A to the semiconductor device A10. The user then checks whether there are any abnormalities in the operation of boards A and B. In this way, a cross-check is performed using a board on which a fault has occurred and a board on which a fault has not occurred.

[0038] 4 shows an example of the fault identification results. Before the recorded data (i.e., the stored input signal data) is swapped, as shown in (1) and (2), it is determined that there is an abnormality in the operation of board A, and that there is no abnormality in the operation of board B.

[0039] After the recorded data is swapped, the operating status of board A and the operating status of board B are considered to be in one of the following states. (i) A state in which the operation of board A is judged to be abnormal, and the operation of board B is judged to be normal. (ii) A state in which the operation of board A is judged to be normal and the operation of board B is judged to be abnormal. As shown in Figure 4, in case (i), the cause of the failure is assumed to be semiconductor device A10. This is because in case (i), the operation of board A becomes abnormal regardless of whether the input signal is EIA or EIB. On the other hand, in case (ii), the cause of the failure is assumed to be board A other than semiconductor device A10, for example, the wiring on board A or the opposing component A1. In case (ii), the cause of the failure is assumed to be board A other than semiconductor device A10, for example, the wiring on board A or the opposing component A1. This is because the operation becomes abnormal in both board A and board B to which the same input signal EIA is input.

[0040] In the case of (i), the user can request repair or replacement of the semiconductor device A10 by sending the semiconductor device A10 in which the failure has occurred to the manufacturer. The manufacturer operates the semiconductor device A10 on a dedicated device that identifies the location of the failure using the input signals and user programs stored in the memory A13 of the semiconductor device A10. This allows the manufacturer to identify the location of the failure in the semiconductor device A10.

[0041] [Effect description] Even if an abnormality occurs in the operation of the semiconductor device H10, the user can analyze the cause of the failure by performing the process described above. Furthermore, the use of the semiconductor device H10 also produces the following effects.

[0042] When performing the analysis, the user does not need to remove the semiconductor device H10 or the component H1 from the board H. As described above, by switching the input signals stored in the memory H13, the user can determine whether the cause of the failure is in the board or the semiconductor device.

[0043] Furthermore, the manufacturer can use the user program and input signals stored in the memory H13 when performing a failure analysis to identify the failure location using a failure location identification tester. The manufacturer does not need to create a dedicated program for identifying the failure location to be used with the failure location identification tester. In particular, in the following cases, it may be difficult to create a program for reproducing the symptoms of a semiconductor device defect: - When the problem only appears under multiple conditions If the source code of the user program is not provided In such a case, the advantage of not needing to create a program specifically for the fault location tester is particularly significant.

[0044] The following embodiments disclose specific examples of the semiconductor device H10 described in embodiment 1. However, the specific examples of the semiconductor device H10 described in embodiment 1 are not limited to those shown below. Furthermore, the configurations and processes described below are merely examples and are not limited thereto.

[0045] <Embodiment 2> [Configuration Description] 5 is a block diagram showing a configuration example of a semiconductor device H20 according to a second embodiment. The semiconductor device H20 is an MCU mounted on a printed circuit board. A counter component 9A is provided in an area on the printed circuit board that is external to the semiconductor device H20. The elements shown in FIG. 5 and the connections between the elements will be described below. Hereinafter, the printed circuit board H on which the semiconductor device H20 and the counter component 9A are mounted will also be simply referred to as the board H.

[0046] The semiconductor device H20 includes a selector 4, an I / O buffer 6, an error detection unit 13, a reset control unit 14, a CPU 15, a flash memory 16, and a RAM (Random Access Memory) 17. These components within the semiconductor device H20 are connected to one another via an internal bus B21. These elements are also connected to the recording / reproducing control circuit 2 via the internal bus B21. The semiconductor device H20 also includes a digital I / O terminal 8.

[0047] The selector 4, I / O buffer 6, digital I / O terminal 8, and opposing component 9A are connected in this order. A digital input signal (hereinafter simply referred to as an input signal) input from outside the board H passes through the opposing component 9A and digital I / O terminal 8, then passes through the selector 4 and internal bus B21, and is input to the recording / playback control circuit 2. The input signal is a digital signal that indicates the H / L state of the signal.

[0048] The selector 4 is configured as a multiplexer, and receives as input signals an input signal from the I / O buffer 6 and a signal from a data conversion circuit 22 (described later) included in the recording / reproducing control circuit 2. The selector 4 also receives as a selection signal a signal from a signal path switching circuit 23 (described later) included in the recording / reproducing control circuit 2. The selector 4 selects either the input signal from the I / O buffer 6 or the signal from the data conversion circuit 22 according to the value of the selection signal. The selector 4 outputs the selected signal to the CPU 15 and RAM 17 via the internal bus B21. In particular, the signal path switching circuit 23 outputs a selection signal so that the selector 4 outputs the input signal from the I / O buffer 6 in the recording mode, and so that the selector 4 outputs the signal from the data conversion circuit 22 in the reproduction mode.

[0049] The CPU 15 corresponds to the CPU H12 in the first embodiment. The flash memory 16 corresponds to the memory H13 in the first embodiment.

[0050] The error detection unit 13 is one of the functions provided in the semiconductor device H20. The error detection unit 13 detects an abnormality (e.g., an ECC (Error-Correcting Code) error in the RAM 17, a parity error in the data bus, etc.) during operation of the semiconductor device H20. The error detection unit 13 outputs the detected abnormality as an error detection signal to a multiplexer 20 (described later) included in the recording / reproducing control circuit 2. Note that if the recording is set to be terminated when an error is detected during recording of the input signal, the recording of the input signal is terminated when the error detection unit 13 outputs the error detection signal.

[0051] The reset control unit 14 is one of the functions provided in the semiconductor device H20. The reset control unit 14 resets each circuit in the semiconductor device H20 in response to a reset signal input to the semiconductor device H20 from outside the semiconductor device H20 via the reset I / F 10B and a reset signal generated within the semiconductor device H20. Furthermore, the reset control unit 14 outputs a reset signal to the multiplexer 20 when resetting each circuit in the semiconductor device H20.

[0052] The CPU 15 executes processing in accordance with a user program based on signals input to the semiconductor device H20. The user program is stored in the flash memory 16. The semiconductor device H20 may also include peripheral circuits (not shown). The peripheral circuits may be, for example, an interrupt control circuit or a communication control circuit.

[0053] The flash memory 16 stores input signals input via the recording / playback control circuit 2 and RAM 17, as well as user programs for operating the CPU 15. The flash memory 16 is a non-volatile memory, and the stored data is not erased but can be continuously retained even when the power supply to the semiconductor device H20 is turned off.

[0054] The RAM 17 is a volatile memory that can be written to and read from by the CPU 15 and the RAM / Flash control circuit 21. When the RAM 17 receives an input signal from a data conversion circuit 22 (described later) included in the recording / playback control circuit 2, the input signal is output to the Flash memory 16, and the input signal is written to the Flash memory 16. On the other hand, when the RAM 17 receives a signal stored in the Flash memory 16, it can also output the input signal to the data conversion circuit 22. Furthermore, the input signal stored in the Flash memory 16 is read out to the outside of the board H via the internal bus B22 and the debug I / F (Interface) 10A.

[0055] In addition, the write and read operations of the Flash memory 16 and RAM 17 are controlled in accordance with signals from a RAM / Flash control circuit 21 (described later) included in the recording / playback control circuit 2 and commands from the debug I / F 10A obtained via the internal bus B22.

[0056] The recording / reproducing control circuit 2 corresponds to the switching circuit H11 in embodiment 1. The recording / reproducing control circuit 2 has a mode terminal 19A, a reset terminal 19B, a multiplexer 20, a RAM / Flash control circuit 21, a data conversion circuit 22, a signal path switching circuit 23, and a timer 25.

[0057] The mode terminal 19A is a terminal for switching the operation mode of the recording / reproducing control circuit 2, and the user sets one of the normal mode, recording mode, and playback mode as the operation mode. When the normal mode is set, the recording / reproducing control circuit 2 does not execute any special processing. However, when either the recording mode or playback mode is set, each component of the recording / reproducing control circuit 2 executes the processing described below. Furthermore, a reset signal to the recording / reproducing control circuit 2 is input to the reset terminal 19B from outside the semiconductor device H20.

[0058] The multiplexer 20 receives as input an error detection signal from the error detection unit 13, a reset signal from the reset control unit 14, and a signal from the timer 25. The multiplexer 20 also receives as input a selection signal a signal from the signal path switching circuit 23. The multiplexer 20 selects one of the three input signals according to the value of the selection signal and outputs the selected input signal to the signal path switching circuit 23.

[0059] In recording mode / playback mode, the RAM / Flash control circuit 21 controls address signals and signals such as CE (Chip Enable) / RE (Read Enable) / WE (Write Enable) of the Flash memory 16 and RAM 17. The detailed processing is as follows.

[0060] In the recording mode, when the RAM / Flash control circuit 21 receives a RAM data write request from the data conversion circuit 22, it starts an operation to write the signal converted by the data conversion circuit 22 to the RAM 17. Specifically, in response to the RAM data write request from the data conversion circuit 22, the RAM / Flash control circuit 21 generates address signals, CE, and WE for the RAM 17. Furthermore, in response to a flash write control signal output from the signal path switching circuit 23 that receives a write command from the debug I / F 10A, the RAM / Flash control circuit 21 generates signals necessary for writing to the flash memory 16, such as address signals. In this way, the RAM / Flash control circuit 21 controls the input signal written to the RAM 17 to be written to the flash memory 16.

[0061] In playback mode, when the RAM / Flash control circuit 21 receives a RAM data read request from the data conversion circuit 22, it controls the data conversion circuit 22 to read data stored in the RAM 17. Upon receiving the RAM data read request, the RAM / Flash control circuit 21 generates address signals, CE and RE, and sends these to the RAM 17 via the internal bus B21. Data read from the RAM 17 in accordance with the address signals, CE and RE from the RAM / Flash control circuit 21 is transferred to the data conversion circuit 22 via the internal bus B21. Note that, in a previous stage, the operation of reading data stored in the Flash memory 16 into the RAM 17 is executed by outputting a read command from the debug I / F 10A to the RAM 17 before the playback operation starts.

[0062] The data conversion circuit 22 performs signal conversion processing and input / output processing in the recording mode / playback mode. The detailed processing is as follows.

[0063] In the recording mode, the data conversion circuit 22 converts the format of the input signal obtained from the I / O buffer 6 into a format for writing to the RAM 17, and writes the converted signal to the RAM 17 via the internal bus B21. In the playback mode, the data conversion circuit 22 performs format conversion on the signal read from the RAM 17 via the internal bus B21 in the reverse order to that performed in the recording mode, and outputs the converted signal to the selector 4. The format conversion in the recording mode and the reverse format conversion in the playback mode are performed based on an instruction signal from the signal path switching circuit 23.

[0064] Additionally, the data conversion circuit 22 may include compression / decompression circuitry for format conversion.

[0065] The signal path switching circuit 23 sets the trigger for ending recording in the recording mode to one of the following: output of an error detection signal, output of a reset signal, or when a time preset in the timer 25 has elapsed. The setting for the trigger for ending recording is stored in a register in the signal path switching circuit 23 and is set by the user as described below. The signal path switching circuit 23 outputs a selection signal to the multiplexer 20 based on the setting in the register. In this way, the signal path switching circuit 23 selects the signal input from the multiplexer 20 to set the trigger for ending recording.

[0066] Furthermore, the signal path switching circuit 23 switches the signal path according to the operation mode set at the mode terminal 19A, thereby controlling the selector 4 and the data conversion circuit 22. The detailed processing is as follows.

[0067] In the recording mode, when a reset signal output from outside the semiconductor device H20 via the reset terminal 19B to the semiconductor device H20 is released, the reset control unit 14 releases the reset signal that it had been outputting to the multiplexer 20 via the internal bus B21. When the input reset signal is released, the multiplexer 20 stops outputting the reset signal to the signal path switching circuit 23. In response to the release of the reset signal, the signal path switching circuit 23 instructs the data conversion circuit 22 to start format conversion. In response to this instruction, the data conversion circuit 22 converts the format of the input signal acquired from the I / O buffer 6 into a format for writing to the RAM 17, and writes the converted signal to the RAM 17 via the internal bus B21. Furthermore, when a recording end signal is input from the multiplexer 20 to the signal path switching circuit 23, the signal path switching circuit 23 instructs the data conversion circuit 22 to stop format conversion. In response, the data conversion circuit 22 stops writing the input signal to the RAM 17.

[0068] In addition, in the normal mode and the recording mode, the signal path switching circuit 23 sets the selection signal to be output to the selector 4 so that the selector 4 outputs the signal output by the I / O buffer 6 .

[0069] In the playback mode, when a reset signal input to the recording / playback control circuit 2 from outside the semiconductor device H20 via the reset terminal 19B is released, the signal path switching circuit 23 switches the selection signal to be output to the selector 4. This causes the selector 4 to switch the signal to be output from the signal output by the I / O buffer 6 to the signal output by the data conversion circuit 22.

[0070] Furthermore, in the playback mode, when the reset signal to the semiconductor device H20 is released, the reset control unit 14 releases the reset signal that it had been outputting to the multiplexer 20 via the internal bus B21. When the input reset signal is released, the multiplexer 20 stops outputting the reset signal to the signal path switching circuit 23. In response to the output of the reset signal being stopped, the signal path switching circuit 23 instructs the data conversion circuit 22 to start reverse format conversion. In response to this instruction, the data conversion circuit 22 performs format conversion on the signal read from the RAM 17 in a manner opposite to that performed in the recording mode, and outputs the converted signal to the selector 4. Furthermore, when a recording end signal is input from the multiplexer 20 to the signal path switching circuit 23, the signal path switching circuit 23 instructs the data conversion circuit 22 to stop reverse format conversion. In response to this, the data conversion circuit 22 stops reading the signal from the RAM 17.

[0071] The timer 25 is a timer for measuring time. When the trigger for ending writing (recording) of an input signal to the RAM 17 in the recording mode is set to "a preset recording time has elapsed since the start of recording," the timer 25 starts counting in response to the release of the reset signal to the semiconductor device H20. This start of counting corresponds to the start of recording. When the preset recording time has elapsed since the start of counting, the timer 25 outputs a recording end signal to the multiplexer 20. In response to the input recording end signal, the multiplexer 20 outputs the recording end signal to the signal path switching circuit 23. As a result, as described above, the signal path switching circuit 23 instructs the data conversion circuit 22 to stop format conversion or format reverse conversion.

[0072] The debug I / F 10A connects the semiconductor device H20 to the outside of the semiconductor device H20. The debug I / F 10A inputs the write command or read command to the signal path switching circuit 23 or the RAM 17 via the internal bus B22. A signal stored in the flash memory 16 may be read out to the outside of the semiconductor device H20 via the debug I / F 10A. The reset I / F 10B connects the reset control unit 14 to the outside of the semiconductor device H20. A reset signal for the semiconductor device H20 is input to the reset control unit 14 from the reset I / F 10B.

[0073] The reset signal input from outside the semiconductor device H20 to the components other than the recording / reproducing control circuit 2 included in the semiconductor device H20 and the reset signal to the recording / reproducing control circuit 2 are independent signals. Therefore, a reset I / F 10B, which is a reset terminal for the semiconductor device H20, and a reset terminal 19B, which is a reset terminal for the recording / reproducing control circuit 2, are provided separately. The recording / reproducing control circuit 2 has a power supply independent of the components other than the recording / reproducing control circuit 2 included in the semiconductor device H20, and as described below, the power supplies for the two components may be turned on or off at different times. Hereinafter, the components other than the recording / reproducing control circuit 2 included in the semiconductor device H20, such as the CPU 15, RAM 17, and reset control unit 14, are referred to as the internal circuit of the semiconductor device H20. This definition of the internal circuit also applies mutatis mutandis to the third and subsequent embodiments.

[0074] The operation of each component of the semiconductor device H20 when the recording mode or the reproducing mode is set as the operating mode of the mode terminal 19A will be described below.

[0075] (recording mode) First, the user sets the mode terminal 19A to the “recording mode.” Next, the user turns on the power supply to the recording / reproducing control circuit 2, and then releases the recording / reproducing control circuit 2 from the reset state.

[0076] Next, the user connects a computer to the recording / playback control circuit 2 via the debug I / F 10A. The user operates the computer and sets the recording end method (recording end condition) in the register in the signal path switching circuit 23 via the debug I / F 10A. As described above, the trigger for ending recording is set to one of the following: output of an error detection signal, output of a reset signal, or when a time preset in the timer 25 has elapsed.

[0077] Then, the user turns on the power supply to the internal circuit of the semiconductor device H20, thereby releasing the reset state of the internal circuit of the semiconductor device H20. This causes the CPU 15 and peripheral circuits (not shown) to start operating. Then, an input signal input from the digital I / O terminal 8 is input to the data conversion circuit 22 via the I / O buffer 6. The data conversion circuit 22 starts recording the input signal in the RAM 17 in response to an instruction from the signal path switching circuit 23. The details of this are as described above.

[0078] When the recording end condition set in the register is met, the signal path switching circuit 23 instructs the data conversion circuit 22 to stop format conversion. In response to this, the data conversion circuit 22 stops writing the input signal to the RAM 17. At this point, the input signal is stored in the RAM 17. Thereafter, in response to a write command input to the signal path switching circuit 23 from the debug I / F 10A, the signal path switching circuit 23 outputs a write control signal to the RAM / Flash control circuit 21. In response to the control signal, the RAM / Flash control circuit 21 transfers the input signal data stored in the RAM 17 to the Flash memory 16. Furthermore, the signal stored in the Flash memory 16 may be read out to an external device via the debug I / F 10A.

[0079] (Playback mode) First, the user sets the mode terminal 19A to "playback mode." Next, the user turns on the power to the recording / playback control circuit 2, thereby releasing the reset state of the recording / playback control circuit 2. In response to this, the signal path switching circuit 23 outputs a selection signal to switch the signal output by the selector 4 from the signal output by the I / O buffer 6 to the signal output by the data conversion circuit 22.

[0080] Then, the user turns on the power supply to the internal circuit of the semiconductor device H20, thereby releasing the reset state of the internal circuit of the semiconductor device H20. The user also operates the computer to output a read command to the RAM 17 via the debug I / F 10A. This causes the data stored in the Flash memory 16 to be transferred to the RAM 17. Then, a RAM data read request is output from the data conversion circuit 22. In response to this, the RAM / Flash control circuit 21 controls the data stored in the RAM 17 to be read from the data conversion circuit 22 and output to the selector 4. As described above, the selector 4 outputs the output signal from the data conversion circuit 22. This starts the playback of the data recorded in the Flash memory 16. When all the data transferred from the Flash memory 16 to the RAM 17 has been read, the data playback is completed.

[0081] In either the recording mode or the playback mode, it is preferable to power on the recording / playback control circuit 2 before powering on the internal circuits of the semiconductor device H20. This is because powering on the recording / playback control circuit 2 first ensures that the operation of the semiconductor device H20 in the normal mode can be reproduced.

[0082] [Effect description] As described above, the semiconductor device H20 includes a built-in flash memory 16 and a RAM 17 that store externally input signals during operation of the semiconductor device H20 in the recording mode. Furthermore, the semiconductor device H20 includes a recording / reproducing control circuit 2 that feeds back data stored in the flash memory 16 within the semiconductor device H20 in the reproducing mode.

[0083] This configuration makes it possible to reproduce the operation of the semiconductor device H20 in response to an input signal input from outside without removing the semiconductor device H20 from the substrate. Also, it is possible to determine whether the cause of the failure lies in the semiconductor device H20 or the substrate (including the opposing components) without removing the semiconductor device H20 from the substrate.

[0084] The semiconductor device H20 also includes a debug I / F 10A that replaces the input signal stored in the flash memory 16 with an input signal stored in another semiconductor device, thereby enabling the user to easily analyze the cause of a failure.

[0085] Furthermore, the manufacturer can receive a semiconductor device H20 that has been determined by the user to be malfunctioning and that stores the external input signal at the time the malfunction occurred. The manufacturer uses a fault location analysis tester to identify the location of the malfunction in the semiconductor device H20 received from the user. At this time, the manufacturer sets the semiconductor device H20 to playback mode using the mode terminal 19A, and causes the semiconductor device H20 to execute a user program using the input signal stored in the flash memory 16 as an external input signal. This allows the manufacturer to reproduce the malfunction of the semiconductor device H20. This eliminates the need to create a new program dedicated to use in the fault location analysis tester.

[0086] In the following embodiments, variations of the semiconductor device shown in embodiment 2 are disclosed. However, variations of the semiconductor device H20 shown in embodiment 2 are not limited to those shown below. The configurations and processes described below are examples and are not limited to these. Furthermore, hereinafter, descriptions of the configurations and processes already described in embodiment 2 will be omitted as appropriate, and differences from embodiment 2 will be particularly described.

[0087] <Third Embodiment> [Configuration Description] 6 is a block diagram showing a configuration example of a semiconductor device H30 according to embodiment 3. The semiconductor device H30 differs from the semiconductor device H20 in the following respects. The rest of the description is the same as that shown in embodiment 2, and will therefore be omitted as appropriate.

[0088] The semiconductor device H30 further includes a selector 3, an input buffer 5, and an analog I / O terminal 7. The analog I / O terminal 7 is connected to a counterpart component 9B mounted on the same substrate as the semiconductor device H30. The counterpart component 9B is, for example, a temperature sensor.

[0089] The semiconductor device H30 also includes an A / D converter 11 and an A / D conversion result register 12. The recording / playback control circuit 2 also includes a D / A converter 24. These elements are provided so that the semiconductor device H30 can handle analog signals. Each element will be described in detail below.

[0090] The selector 3 is configured as a multiplexer, and receives as input signals the analog input signal from the input buffer 5 and the signal from the data conversion circuit 22 via the D / A converter 24. The selector 3 also receives as a selection signal a signal from the signal path switching circuit 23. Depending on the value of the selection signal, the selector 3 selects either the analog input signal from the input buffer 5 or the analog signal from the D / A converter 24 and outputs it to the A / D converter 11. In detail, the signal path switching circuit 23 outputs a selection signal so that the selector 3 outputs the analog input signal from the input buffer 5 in the recording mode, and so that the selector 3 outputs the analog signal from the D / A converter 24 in the playback mode.

[0091] The A / D converter 11 converts the analog signal input from the selector 3 into a digital signal and outputs the converted digital signal to an A / D conversion result register 12. The A / D conversion result register 12 is a register that stores the digital signal value output by the A / D converter 11. The CPU 15 reads out the value stored in the A / D conversion result register 12 and performs processing.

[0092] The signal path switching circuit 23 switches the signal path according to the operation mode set at the mode terminal 19A, thereby controlling not only the selector 4 and the data conversion circuit 22 but also the selector 3. The detailed processing of the selector 3 is as follows.

[0093] In the normal mode and the recording mode, the signal path switching circuit 23 sets a selection signal for the selector 3 so that the selector 3 outputs the signal output by the input buffer 5.

[0094] In playback mode, when a reset signal input to the recording / playback control circuit 2 from outside the board is released, the signal path switching circuit 23 switches the selection signal output to the selector 3. This causes the selector 3 to switch the output signal from the signal output by the input buffer 5 to the signal output by the D / A converter 24. As a result, the data recorded in recording mode is input again to the A / D converter 11 as an analog signal. The A / D converter 11 converts the input analog signal into a digital signal and outputs the converted digital signal to the A / D conversion result register 12.

[0095] The following will describe the operation of each component of the semiconductor device H30 when the recording mode or the reproducing mode is set as the operating mode of the mode terminal 19A, focusing on analog signals.

[0096] (recording mode) First, the user sets the mode terminal 19A to the “recording mode.” Next, the user turns on the power supply to the recording / reproducing control circuit 2, and then releases the recording / reproducing control circuit 2 from the reset state.

[0097] Next, the user sets the recording termination method via the debug I / F 10A to the register in the signal path switching circuit 23. The details of this are as described in the second embodiment.

[0098] Then, the user turns on the power supply to the internal circuit of the semiconductor device H30, thereby releasing the reset state of the internal circuit of the semiconductor device H30. This causes the CPU 15 and peripheral circuits (not shown) to start operating. An analog input signal input from the analog I / O terminal 7 is input to the A / D converter 11 via the input buffer 5 and the selector 3. The analog signal input to the A / D converter 11 is converted into a digital signal. The converted digital signal, i.e., the A / D conversion result, is stored in the A / D conversion result register 12 as data consisting of multiple bits.

[0099] The A / D conversion result stored in the A / D conversion result register 12 is input to the data conversion circuit 22. Then, the A / D conversion result is recorded in the RAM 17 via the data conversion circuit 22.

[0100] (Playback mode) First, the user sets the mode terminal 19A to "playback mode." Next, the user turns on the power to the recording / playback control circuit 2, thereby releasing the reset state of the recording / playback control circuit 2. In response to this, the signal path switching circuit 23 outputs a selection signal to switch the signal output by the selector 3 from the signal output by the input buffer 5 to the signal output by the D / A converter 24.

[0101] Then, the user turns on the power supply to the internal circuit of the semiconductor device H30, thereby releasing the reset state of the internal circuit of the semiconductor device H30. As in the second embodiment, a read command is input to RAM 17 via debug I / F 10A. Then, the A / D conversion result stored in RAM 17 is read. The A / D conversion result read from RAM 17 is input to D / A converter 24 via data conversion circuit 22. D / A converter 24 converts the input digital signal (the A / D conversion result stored in RAM 17) into an analog signal and outputs it to selector 3. Selector 3 again outputs the signal output by D / A converter 24 to A / D converter 11. A / D converter 11 converts the input analog signal into a digital signal. CPU 15 performs processing using the converted digital signal. When all the data transferred from Flash memory 16 to RAM 17 has been read, data reproduction is completed.

[0102] [Effect description] As described above, the semiconductor device H30 has a configuration compatible with recording and reproducing operations of analog input signals. This allows the semiconductor device H30 to handle cases where analog signal reproduction is required to reproduce abnormal operation that has occurred in the semiconductor device. This allows the scope of application of the semiconductor device to be expanded. Furthermore, when A / D conversion is performed, the semiconductor device H30 can use the A / D converter 11 already built into the semiconductor device H30 for this purpose. Therefore, the semiconductor device H30 only needs to be newly equipped with a D / A converter 24 to support recording and reproducing operations of analog input signals, thereby reducing the cost required for this support.

[0103] <Fourth Embodiment> [Configuration Description] 7 is a block diagram showing a configuration example of a semiconductor device H40 according to embodiment 4. The semiconductor device H40 differs from the semiconductor device H30 in the following respects. The rest of the description is the same as that shown in embodiment 3, and will therefore be omitted as appropriate.

[0104] The recording / playback control circuit 2 is further provided with a RAM 27. The RAM 27 is connected to the Flash memory 16, the RAM / Flash control circuit 21, and the data conversion circuit 22, as well as to the debug I / F 10A via an internal bus B22. In the recording mode, data stored in the RAM 27 is written to the Flash memory 16. Alternatively, the data stored in the RAM 27 may be read out to the outside of the semiconductor device H40 via the debug I / F 10A. The RAM 27 is a dedicated RAM provided for recording and playing back digital signals.

[0105] The following description focuses on the operation of the RAM 27 of the semiconductor device H40 and its peripheral components when the recording mode or the playback mode is set as the operation mode of the mode terminal 19A. The rest of the description is the same as that shown in the second and third embodiments, and will be omitted as appropriate.

[0106] (recording mode) First, the user sets the mode terminal 19A to "recording mode." Next, the user turns on the power to the recording / reproducing control circuit 2 and then releases the reset state of the recording / reproducing control circuit 2. Next, the user sets the recording termination method in the register in the signal path switching circuit 23 via the debug I / F 10A.

[0107] Then, the user turns on the power supply to the internal circuit of the semiconductor device H40, thereby releasing the reset state of the internal circuit of the semiconductor device H40. This causes the CPU 15 and peripheral circuits (not shown) to start operating. Then, an input signal input from the digital I / O terminal 8 is input to the data conversion circuit 22 via the I / O buffer 6. In response to an instruction from the signal path switching circuit 23, the data conversion circuit 22 records the input signal in the RAM 27, not in the RAM 17.

[0108] When the recording end condition set in the register is met, the signal path switching circuit 23 instructs the data conversion circuit 22 to stop format conversion. In response to this, the data conversion circuit 22 stops writing the input signal to the RAM 27. At this point, the input signal is temporarily stored in the RAM 27. Thereafter, in response to a write command being input to the signal path switching circuit 23 from the debug I / F 10A, the signal path switching circuit 23 outputs a write control signal to the RAM / Flash control circuit 21. In response to the control signal, the RAM / Flash control circuit 21 transfers the input signal data stored in the RAM 27 to the Flash memory 16.

[0109] (Playback mode) First, the user sets the mode terminal 19A to "playback mode." Next, the user turns on the power to the recording / playback control circuit 2, thereby releasing the reset state of the recording / playback control circuit 2. In response to this, the signal path switching circuit 23 outputs a selection signal to switch the signal output by the selector 4 from the signal output by the I / O buffer 6 to the signal output by the data conversion circuit 22.

[0110] Then, the user turns on the power supply to the internal circuit of the semiconductor device H40, thereby releasing the reset state of the internal circuit of the semiconductor device H40. The user also operates the computer to output a read command to the RAM 27 via the debug I / F 10A. This causes the data stored in the Flash memory 16 to be transferred to the RAM 27. Then, a RAM data read request is output from the data conversion circuit 22. In response to this, the RAM / Flash control circuit 21 controls the data conversion circuit 22 to read the data temporarily stored in the RAM 27 and output it to the selector 4. As described above, the selector 4 outputs the output signal from the data conversion circuit 22. This starts the playback of the data recorded in the Flash memory 16. When all the data transferred from the Flash memory 16 to the RAM 27 has been read, the data playback is completed.

[0111] [Effect description] As described above, the semiconductor device H40 incorporates a dedicated RAM for recording and reproducing input signals as a component within the recording / reproducing control circuit 2. This allows the semiconductor device H40 to reduce accesses to the RAM 17 related to the recording / reproducing operation during the recording / reproducing operation. This reduces conflicts between accesses to the RAM 17 from the CPU 15 and accesses related to the recording / reproducing operation. Therefore, even if an abnormality occurs due to a change in the operation timing of the CPU 15, the abnormal operation can be reproduced. Furthermore, the semiconductor device H40 can accurately record input signal data in the RAM 27 even if the RAM 17 incorporated in the internal circuit of the semiconductor device H40 fails.

[0112] <Fifth Embodiment> [Configuration Description] 8 is a block diagram showing a configuration example of a semiconductor device H50 according to embodiment 5. The semiconductor device H50 differs from the semiconductor device H40 in the following respects. The rest of the description is the same as that shown in embodiment 4, and will therefore be omitted as appropriate.

[0113] The recording / playback control circuit 2 is further provided with a flash memory 26. The flash memory 26 is connected to the RAM / flash control circuit 21 and the RAM 27. In the recording mode, data stored in the RAM 27 is written to the flash memory 26. Alternatively, the data stored in the RAM 27 may be read out to the outside via the debug I / F 10A. The flash memory 26 is a dedicated flash memory provided for recording and playing back digital signals.

[0114] The following description focuses on the operation of the flash memory 26 of the semiconductor device H50 and its peripheral components when the recording mode or the playback mode is set as the operating mode of the mode terminal 19A. The rest of the description is the same as that of the second to fourth embodiments, and will therefore be omitted as appropriate.

[0115] (recording mode) First, the user sets the mode terminal 19A to "recording mode." Next, the user turns on the power to the recording / reproducing control circuit 2 and then releases the reset state of the recording / reproducing control circuit 2. Next, the user sets the recording termination method in the register in the signal path switching circuit 23 via the debug I / F 10A.

[0116] Then, the user turns on the power supply to the internal circuit of the semiconductor device H50, thereby releasing the reset state of the internal circuit of the semiconductor device H50. This causes the CPU 15 and peripheral circuits (not shown) to start operating. Then, an input signal input from the digital I / O terminal 8 is input to the data conversion circuit 22 via the I / O buffer 6. The data conversion circuit 22 records the input signal in the RAM 27 in response to an instruction from the signal path switching circuit 23.

[0117] When the recording end condition set in the register is met, the signal path switching circuit 23 instructs the data conversion circuit 22 to stop format conversion. In response to this, the data conversion circuit 22 stops writing the input signal to the RAM 27. At this point, the input signal is stored in the RAM 27. Thereafter, in response to a write command input to the signal path switching circuit 23 from the debug I / F 10A, the signal path switching circuit 23 outputs a write control signal to the RAM / Flash control circuit 21. In response to the control signal, the RAM / Flash control circuit 21 transfers the input signal data stored in the RAM 27 to the Flash memory 26, not to the Flash memory 16.

[0118] (Playback mode) First, the user sets the mode terminal 19A to "playback mode." Next, the user turns on the power to the recording / playback control circuit 2, thereby releasing the reset state of the recording / playback control circuit 2. In response to this, the signal path switching circuit 23 outputs a selection signal to switch the signal output by the selector 4 from the signal output by the I / O buffer 6 to the signal output by the data conversion circuit 22.

[0119] Then, the user turns on the power supply to the internal circuit of the semiconductor device H50, thereby releasing the reset state of the internal circuit of the semiconductor device H50. The user also operates the computer to output a read command to the RAM 27 via the debug I / F 10A. This causes the data stored in the Flash memory 26 to be transferred to the RAM 27. Then, a RAM data read request is output from the data conversion circuit 22. In response to this, the RAM / Flash control circuit 21 controls the data stored in the RAM 27 to be read from the data conversion circuit 22 and output to the selector 4. As described above, the selector 4 outputs the output signal from the data conversion circuit 22. This starts the playback of the data recorded in the Flash memory 26. When all the data transferred from the Flash memory 26 to the RAM 27 has been read, the data playback also ends.

[0120] [Effect description] As described above, the semiconductor device H50 includes a dedicated flash memory for recording and reproducing input signals as a component within the recording / reproducing control circuit 2. As described above, a user program is stored in the flash memory 16. Therefore, if the user program is large, the amount of input signal data that can be stored in the flash memory 16 may be small. However, because the semiconductor device H50 includes a dedicated flash memory 26 for recording input signal data, it can perform recording / reproducing operations without any problems even when the amount of input signal data is large. Furthermore, the semiconductor device H50 can record accurate input signal data in the flash memory 26 even if the flash memory 16 fails.

[0121] Furthermore, the Flash memory 26 may be a memory with lower performance than the Flash memory 16, such as a memory with a lower rewritable count or a slower access speed. Because the Flash memory 16 stores the source code of the user program, the CPU 15 frequently accesses the Flash memory 16. Therefore, a memory with a high rewritable count and a fast access speed is desirable. On the other hand, the frequency of recording and reproducing analog input signals is considered to be very low. Therefore, the Flash memory 26 may have a low rewritable count. Furthermore, there is little need for fast data transfer between the Flash memory 26 and the RAM 27 in the recording mode and the reproducing mode. Therefore, the Flash memory 26 may have a slower access speed. This reduces the cost of the Flash memory 26.

[0122] <Sixth Embodiment> [Configuration Description] 9 is a block diagram showing a configuration example of a semiconductor device H60 according to embodiment 6. The semiconductor device H60 differs from the semiconductor device H20 in the following respects. The rest of the description is the same as that shown in embodiment 2, and will therefore be omitted as appropriate.

[0123] The recording / playback control circuit 2 further includes a setting control circuit 28, a mode setting / decoder 29, a reset control circuit 30, a playback control circuit 31, and a power supply control circuit 32. A power supply SW (Switch) 33 is also provided outside the recording / playback control circuit 2. These elements are provided so that the semiconductor device H60 can reduce the number of dedicated terminals required for the recording / playback control circuit 2 as much as possible compared to the semiconductor device H20.

[0124] On the other hand, the semiconductor device H60 does not have a mode terminal 19A. Instead, an operation mode that can be set to one of normal mode, recording mode, and playback mode is set in a setting area of ​​the flash memory 16. By connecting the flash memory 16 to a setting control circuit 28 as described below, information on the set operation mode can be read and the set operation mode can be changed. Furthermore, as described below, the setting area of ​​the flash memory 16 stores information on various periods related to the control of playback operations. Note that a user can rewrite various pieces of information written in the setting area of ​​the flash memory 16 via the debug I / F 10A by operating a computer.

[0125] The following describes in detail the new elements of the recording / playback control circuit 2. The setting control circuit 28 reads setting information such as the operation mode that has been written in advance to a setting area in the flash memory 16. The setting control circuit 28 uses the release of the reset state of the recording / playback control circuit 2 as a trigger for reading out settings such as the operation mode. The setting control circuit 28 outputs the read setting information to the mode setting / decoder 29.

[0126] The mode setting / decoder 29 determines the operation mode and the like of the semiconductor device H60 based on the setting information read by the setting control circuit 28. The mode setting / decoder 29 outputs information on the determined operation mode and the like to the reset control circuit 30, the regeneration control circuit 31, and the power supply control circuit 32.

[0127] The reset control circuit 30 controls the reset operation of the internal circuit of the semiconductor device H60 in accordance with the information output from the mode setting / decoder 29 and the information output from the playback control circuit 31. Specifically, in the normal mode / recording mode, after determining the operation mode, the reset control circuit 30 releases the reset state of the internal circuit of the semiconductor device H60. In addition, in the playback mode, after the power supply of the internal circuit of the semiconductor device H60 is turned on for the second time, the reset control circuit 30 releases the reset state of the internal circuit of the semiconductor device H60. In this way, since the reset control circuit 30 can control the reset state of the internal circuit of the semiconductor device H60, unlike the first embodiment, there is no need to supply a reset signal to the internal circuit of the semiconductor device H60 from outside the semiconductor device.

[0128] The playback control circuit 31 is connected to the data conversion circuit 22, the mode setting / decoder 29, the reset control circuit 30, and the power control circuit 32. The playback control circuit 31 is also connected to the debug I / F 10A via an internal bus B22. The playback control circuit 31 controls the operation in playback mode.

[0129] Specifically, in playback mode, the playback control circuit 31 outputs an instruction to the internal circuit of the semiconductor device H60 to turn on the power supply for the second time. The playback control circuit 31 measures the time since the internal circuit of the semiconductor device H60 was turned on for the second time, and when a predetermined period of time has elapsed since the measurement, it releases the reset state of the internal circuit of the semiconductor device H60. This predetermined period, like the information about the operating mode, is information written in advance in the setting area of ​​the Flash memory 16. The playback control circuit 31 acquires the information about the predetermined period by referring to the Flash memory 16 and performs the above-mentioned operation. In this way, the playback control circuit 31 performs timing control related to playback.

[0130] However, the predetermined period may be set by a command input from the debug I / F 10A in the playback mode, which makes it possible to set the period from when the power is turned on until the reset state is released to the same period as during operation in the normal mode.

[0131] Furthermore, the power-off time for the internal circuits of the semiconductor device H60 before playback starts in playback mode is also information written in the setting area of ​​the flash memory 16. However, the power-off time may be set in response to a command input from the debug I / F 10A in playback mode. This allows the power-off time to be set taking into account the influence of residual charge on the chip of the semiconductor device H60.

[0132] In addition, upon receiving a command from the debug I / F 10A, the reproduction control circuit 31 controls the power on / off of the internal circuits of the semiconductor device H60. That is, upon receiving a command from the debug I / F 10A, the reproduction control circuit 31 outputs an instruction to the power control circuit 32 to turn the power of the internal circuits of the semiconductor device H60 from on to off and then on again. In this way, the reproduction control circuit 31 controls the timing at which the power of the internal circuits of the semiconductor device H60 is turned on for the second time.

[0133] It is also possible that compression / decompression is performed during format conversion / reverse conversion. In this case, it is preferable that the data conversion circuit 22 decompresses the data stored in RAM 17 while playing back the decompressed data in playback mode, rather than decompressing all of the data stored in RAM 17 before starting playback. This is because if playback is started after decompressing all of the data stored in RAM 17, a RAM 17 with a large capacity must be prepared to accommodate the decompressed data.

[0134] The power supply control circuit 32 controls the on / off of the power supply SW 33 in response to signals from the mode setting / decoder 29 and the playback control circuit 31. In response to this control, the on / off of the power supply of the internal circuit of the semiconductor device H60 is controlled. The details of this control are as follows. (A) In principle, when the substrate power supply is turned on, the power supply of the internal circuit of the semiconductor device H60 is also turned on. (B) However, in playback mode, the playback control circuit 31 outputs an instruction to the power control circuit 32 from the state of (A), so that the power SW 33 is switched off once and then switched on again. The details of this are as described above.

[0135] The power supply SW33 is provided between the internal circuit of the semiconductor device H60 and the recording / reproducing control circuit 2 and the branch point of the power supply line between the internal circuit of the semiconductor device H60 and the recording / reproducing control circuit 2, in a substrate power supply common to the internal circuit of the semiconductor device H60. The internal circuit of the semiconductor device H60 and the recording / reproducing control circuit 2 operate using a common substrate power supply. However, by providing the power supply SW33 in this position, the power supply for the internal circuit of the semiconductor device H60 can be controlled independently of the power supply for the recording / reproducing control circuit 2.

[0136] The external reset signal input to the recording / reproducing control circuit 2 via the reset terminal 19C is used as a reset signal for the recording / reproducing control circuit 2.

[0137] The following describes the operation of each component of the semiconductor device H60 when the normal mode, the recording mode, or the playback mode is set as the operating mode set in the flash memory 16. In the description, the timing charts shown in Figures 10 to 12 are used.

[0138] (Normal mode) The operation in normal mode will be described with reference to Figure 10. First, the user operates the computer to preset the operation mode written in the setting area of ​​the flash memory 16 to the default "normal mode" via the debug I / F 10A.

[0139] Next, the user turns on the substrate power supply at time t11 to supply power to the internal circuits and the recording / reproducing control circuit 2 of the semiconductor device H60.

[0140] Thereafter, at time t12, the user releases the external reset signal, thereby releasing the reset state of the recording / playback control circuit 2. This release triggers the setting control circuit 28 to read setting information such as the operating mode written in the setting area of ​​the Flash memory 16. The setting control circuit 28 transfers the read setting information to the mode setting / decoder 29.

[0141] The mode setting / decoder 29 reads the transferred setting information and determines that the normal mode is set as the operation mode. The mode setting / decoder 29 transfers information indicating that the normal mode is set to the reset control circuit 30.

[0142] At time t13, reset control circuit 30 releases the reset state of the internal circuit of semiconductor device H60 in response to receiving normal mode setting information from mode setting / decoder 29. At this time, semiconductor device H60 performs normal operation, and recording / reproduction control circuit 2 does not perform any particular operation.

[0143] (recording mode) The operation in the recording mode will be described with reference to FIG. 11. First, the user operates the computer to preset the operating mode written in the setting area of ​​the flash memory 16 to "recording mode" via the debug I / F 10A. The user also writes a recording end condition to a register in the signal path switching circuit 23 via the debug I / F 10A. The recording end condition is set to one of the following: output of an error detection signal, output of a reset signal, or the lapse of a time preset in the timer 25. The details of this are as described in the second embodiment.

[0144] Next, the user turns on the substrate power supply at time t21 to supply power to the internal circuits and the recording / reproducing control circuit 2 of the semiconductor device H60.

[0145] Thereafter, at time t22, the user releases the external reset signal, thereby releasing the reset state of the recording / playback control circuit 2. This release triggers the setting control circuit 28 to read setting information such as the operating mode written in the setting area of ​​the Flash memory 16. The setting control circuit 28 transfers the read setting information to the mode setting / decoder 29.

[0146] The mode setting / decoder 29 reads the transferred setting information and determines that the recording mode is set as the operating mode. The mode setting / decoder 29 transfers information indicating that the recording mode is set to the reset control circuit 30.

[0147] In response to receiving the recording mode setting information from the mode setting / decoder 29, the reset control circuit 30 releases the reset state of the internal circuit of the semiconductor device H60 at time t23. This causes the semiconductor device H60 to operate in the recording mode. That is, the input signal input from the digital I / O terminal 8 is input to the data conversion circuit 22 via the I / O buffer 6. The data conversion circuit 22 starts recording the input signal to the RAM 17 in response to an instruction from the signal path switching circuit 23. Thereafter, when a recording end condition set in a register within the signal path switching circuit 23 is met, the writing of the input signal to the RAM 17 is stopped. Then, the RAM / Flash control circuit 21 transfers the input signal data stored in the RAM 17 to the Flash memory 16. The signal stored in the Flash memory 16 may be read out to an external device via the debug I / F 10A. Details of this are as described in the second embodiment.

[0148] (Playback mode) The operation in the playback mode will be described with reference to Figure 12. First, the user operates the computer to set the operation mode written in the setting area of ​​the flash memory 16 to "playback mode" in advance via the debug I / F 10A. The user also writes information about various periods related to the control of the playback operation in the setting area of ​​the flash memory 16 in advance.

[0149] Next, the user turns on the substrate power supply at time t31 to supply power to the internal circuits and the recording / reproducing control circuit 2 of the semiconductor device H60.

[0150] Thereafter, at time t32, the user releases the external reset signal, thereby releasing the reset state of the recording / playback control circuit 2. This release triggers the setting control circuit 28 to read setting information such as the operating mode written in the setting area of ​​the Flash memory 16. The setting control circuit 28 transfers the read setting information to the mode setting / decoder 29.

[0151] The mode setting / decoder 29 reads the transferred setting information to determine that the playback mode is set as the operation mode and to determine information on various periods related to the control of the playback operation. The mode setting / decoder 29 outputs this setting information to the playback control circuit 31 and the power supply control circuit 32.

[0152] In response to receiving the setting information, the playback control circuit 31 waits for a command from the debug I / F 10A. Upon receiving the command from the debug I / F 10A, the playback control circuit 31 executes the playback setting and controls the data recorded in the flash memory 16 to be loaded into the RAM 17. Thereafter, the playback control circuit 31 waits for a command from the debug I / F 10A again.

[0153] When the second command is received from the debug I / F 10A at time t33, the playback control circuit 31 outputs an instruction to the power supply control circuit 32 to switch the power supply of the internal circuit of the semiconductor device H60 from on to off. In response to this instruction, the power supply control circuit 32 switches the power supply SW33 from on to off. This temporarily stops the power supply to the internal circuit of the semiconductor device H60.

[0154] The reproduction control circuit 31 starts counting using a timer from time t33. At time t34, when the power-off time of the internal circuits of the semiconductor device H60 indicated as setting information in the setting area of ​​the Flash memory 16 has elapsed, the reproduction control circuit 31 outputs an instruction to the power supply control circuit 32 to switch the power supply of the internal circuits of the semiconductor device H60 from an OFF state to an ON state. In response to this instruction, the power supply control circuit 32 switches the power supply SW33 from OFF to ON. This resumes the supply of power to the internal circuits of the semiconductor device H60.

[0155] Then, the reproduction control circuit 31 starts counting using a timer from time t34 when the power supply to the internal circuit of the semiconductor device H60 is turned on for the second time. At time t35 when a predetermined period indicated as setting information in the setting area of ​​the Flash memory 16 has elapsed, the reproduction control circuit 31 outputs an instruction to the reset control circuit 30 to release the reset state of the internal circuit of the semiconductor device H60. In response to this instruction, the reset control circuit 30 releases the reset state of the internal circuit of the semiconductor device H60. This starts the reproduction of the data recorded in the Flash memory 16. The reproduction of the data is completed when all the data transferred from the Flash memory 16 to the RAM 17 has been read. Details of the reproduction operation are as described in the second embodiment.

[0156] In the playback mode, the power supply is turned on at the same timing as the internal circuits of the semiconductor device H60 are turned on in the normal mode, so that the power supply control circuit 32 of the recording / playback control circuit 2 controls the on / off of the power supply SW33.

[0157] [Effect description] As described above, the semiconductor device H60 can use the setting area of ​​the flash memory 16 to set the operation mode, which eliminates the need to provide a mode terminal dedicated to setting the operation mode on the substrate of the semiconductor device H60.

[0158] Furthermore, since the semiconductor device H60 uses the power supply control circuit 32 and the power supply SW33 to control the power supply to the internal circuits of the semiconductor device H60, there is no need to provide separate power supplies for the internal circuits of the semiconductor device H60 and the recording / reproducing control circuit 2. This eliminates the need to provide a dedicated power supply on the board.

[0159] Furthermore, by controlling the reset of the internal circuit of the semiconductor device H60 using the reset control circuit 30, it is not necessary to separate the reset signal to the internal circuit of the semiconductor device H60 from the reset signal to the recording / reproducing control circuit 2. This makes it possible to reduce the number of terminals for reset signals provided on the substrate.

[0160] The semiconductor device described in the above embodiments can be mounted in any electronic device, for example, any MCU or dedicated memory device.

[0161] The invention made by the inventor has been specifically described above based on an embodiment, but it goes without saying that the present invention is not limited to the above embodiment and can be modified in various ways without departing from the gist of the invention. [Explanation of symbols]

[0162] H board H1 Parts H10 Semiconductor Devices H11 Selector H12 CPU H13 Memory H14 switching circuit H20 Semiconductor equipment H30 Semiconductor equipment H40 Semiconductor equipment H50 Semiconductor Devices H60 Semiconductor Devices B1 Bus B21, B22 internal bus 2 Recording / playback control circuit 3. Selectors 4 Selectors 5 Input Buffer 6 I / O Buffers 7 Analog I / O terminals 8 digital I / O terminals 9 Counterparts 10A Debug I / F 10B Reset I / F 11 A / D converter 12 A / D conversion result register 13 Error detection unit 14 Reset control section 15 CPU 16 Flash memory 17 RAM 19A mode terminal 19B Reset terminal 19C Reset terminal 20 Multiplexer 21 RAM / Flash control circuit 22 Data conversion circuit 23 Signal path switching circuit 24 D / A converter 25 Timer 26 Flash memory 27 RAM 28 Setting control circuit 29 Mode Setting / Decoder 30 Reset control circuit 31 Regeneration control circuit 32 Power supply control circuit 33 Power SW

Claims

1. a central processing unit (CPU); an external terminal for receiving an external signal; a first memory that stores an external input signal supplied via the external terminal; a switching circuit that switches an input signal required for processing by the CPU from the external input signal obtained via the external terminal to the external input signal stored in the first memory. Semiconductor device.

2. an interface for replacing the external input signal stored in the first memory with another signal supplied from outside the semiconductor device; The semiconductor device according to claim 1 .

3. an A / D converter that performs A / D conversion on an analog input signal supplied via the external terminal; a second memory for storing the digital signal output by the A / D converter; a D / A converter that D / A converts the digital signal stored in the second memory, the switching circuit causes the D / A converter to perform D / A conversion of the digital signal stored in the second memory, thereby generating a signal required for processing by the CPU; The semiconductor device according to claim 1 .

4. the switching circuit further includes a volatile memory for temporarily storing the external input signal or the signal stored in the first memory when at least one of the external input signal is stored in the first memory and the signal stored in the first memory is used as a signal required for processing by the CPU; The semiconductor device according to claim 1 .

5. the switching circuit includes the first memory as a component; The semiconductor device according to claim 1 .

6. the first memory stores information of an instruction for causing the switching circuit to switch the input signal; The semiconductor device according to claim 1 .

7. The CPU and the switching circuit are powered by a common power line, the semiconductor device further includes a power switch between the CPU and the branch point of the power line between the CPU and the switching circuit, and the CPU; the switching circuit switches the power switch on or off when the signal stored in the first memory is used as a signal required for processing by the CPU; The semiconductor device according to claim 1 .

8. the switching circuit further includes a reset control circuit that controls a reset state of the CPU when the signal stored in the first memory is used as a signal required for processing by the CPU; The semiconductor device according to claim 1 .

9. storing an external input signal passed through an external terminal of the semiconductor device determined to be malfunctioning in a first memory; based on the instruction, switching the input signal to be provided to the semiconductor device from the external input signal via the external terminal to the external input signal stored in the first memory; The semiconductor device is operated using the signal stored in the first memory as the input signal, and a fault location within the semiconductor device is identified. A failure analysis method for semiconductor devices.

10. The semiconductor device includes: replacing the external input signal stored in the first memory with another signal supplied from outside the semiconductor device via an interface; 10. The method of claim 9.

11. The semiconductor device includes: A / D converting an analog input signal supplied via the external terminal; storing a digital signal obtained by A / D converting the analog input signal in a second memory; generating a signal for operating the semiconductor device by D / A converting the digital signal stored in the second memory; 10. The method of claim 9.

12. The semiconductor device includes: When the external input signal is stored in the first memory, or when the signal stored in the first memory is used as a signal for operating the semiconductor device, the external input signal or the signal stored in the first memory is temporarily stored in a volatile memory provided in a circuit separate from a central processing unit (CPU) of the semiconductor device.

10. The method of claim 9.

13. the first memory is provided in a circuit separate from a central processing unit (CPU) of the semiconductor device; 10. The method of claim 9.

14. the first memory stores information of an instruction to switch the input signal; 10. The method of claim 9.

15. The semiconductor device includes: when the signal stored in the first memory is used as a signal for operating the semiconductor device, switching a power switch provided between a branch point of a power line between a central processing unit (CPU) of the semiconductor device and a switching circuit that switches the input signal and the CPU; 10. The method of claim 9.

16. The semiconductor device includes: controlling a reset state of a central processing unit (CPU) of the semiconductor device when the signal stored in the first memory is used as a signal for operating the semiconductor device; 10. The method of claim 9.

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