Display device

Abstract

To improve reliability in a display device having high-definition pixels.SOLUTION: Each of the plurality of pixels includes a transistor including an oxide semiconductor layer, a gate line facing the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate line, a first insulating layer provided on the transistor, a first transparent conductive layer provided on the first insulating layer and connected to the oxide semiconductor layer via a first contact hole provided in the first insulating layer and the gate insulating layer, a second insulating layer provided on the first transparent conductive layer and having a first opening exposing a part of the first transparent conductive layer, a first organic layer provided on the second insulating layer and having a second opening exposing a part of the first transparent conductive layer, and a second transparent conductive layer provided on the first organic layer and connected to the first transparent conductive layer.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] An embodiment of the present invention relates to a display device, and in particular to a display device using a transistor including an oxide semiconductor. [Background technology]

[0002] Recently, development of transistors using oxide semiconductors for the channel instead of amorphous silicon, low-temperature polysilicon, and single-crystal silicon has been progressing (see, for example, Patent Documents 1 and 2). Transistors using oxide semiconductors for the channel have a simple structure and are formed by a low-temperature process, similar to transistors using amorphous silicon for the channel. Transistors using oxide semiconductors for the channel are known to have higher mobility and a very low off-current than transistors using amorphous silicon for the channel.

[0003] In recent years, pixel sizes of display devices have been reduced. Along with this reduction in pixel size, reductions in wiring width and transistor size have been considered. However, there are limits to these reductions, and the aperture ratio is reduced due to the arrangement of metal layers and semiconductor layers that constitute pixel circuits. Therefore, development is underway to use transistors in pixel circuits that use oxide semiconductor layers for their channels, which can provide sufficient characteristics for driving pixel circuits even with small transistor sizes. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-146819 [Patent Document 2] Japanese Patent Application Laid-Open No. 2015-159315 Summary of the Invention [Problem to be solved by the invention]

[0005] As the resolution of pixels in display devices is improved, there is a concern that the layout margin of pixels will be narrowed, which may affect the reliability of the display device due to fluctuations in the characteristics of transistors using oxide semiconductor layers or poor connections of wirings or the like.

[0006] An object of one embodiment of the present invention is to improve the reliability of a display device having highly fine pixels. [Means for solving the problem]

[0007] A display device according to one embodiment of the present invention has a plurality of pixels arranged on an insulating surface, each of the plurality of pixels including a transistor having an oxide semiconductor layer, a gate wiring facing the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate wiring, a first insulating layer arranged on the transistor, a first transparent conductive layer arranged on the first insulating layer and connected to the oxide semiconductor layer via a first contact hole arranged in the first insulating layer and the gate insulating layer, a second insulating layer arranged on the first transparent conductive layer and having a first opening exposing a portion of the first transparent conductive layer, a first organic layer arranged on the second insulating layer and having a second opening exposing a portion of the first transparent conductive layer, and a second transparent conductive layer arranged on the first organic layer and connected to the first transparent conductive layer, the first contact hole being covered by the first transparent conductive layer, and a portion of an edge of the first transparent conductive layer being positioned inside the second opening. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a plan view showing an overview of a display device according to an embodiment of the present invention; [Figure 2] 1 is a block diagram showing a circuit configuration of a display device according to an embodiment of the present invention. [Figure 3] 1 is a circuit diagram showing a pixel circuit of a pixel of a display device according to an embodiment of the present invention. [Figure 4] 1 is an end view showing a configuration of a display device according to an embodiment of the present invention. [Figure 5]1 is a layout diagram of a plurality of pixels arranged in a display region of a display device according to an embodiment of the present invention. [Figure 6] 1 is a layout diagram of a plurality of pixels arranged in a display region of a display device according to an embodiment of the present invention. [Figure 7] 6 is an enlarged view of a portion of the pixels shown in FIG. 5. FIG. [Figure 8] FIG. 8 is an end view of the pixel shown in FIG. 7 taken along line A1-A2. [Figure 9] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 10] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 11] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 12] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 13] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 14] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 15] FIG. 2 is a plan view illustrating the layout of each layer in the display device according to the embodiment of the present invention. [Figure 16] 1 is a layout diagram of a plurality of pixels arranged in a display region of a display device according to an embodiment of the present invention. [Figure 17] 17 is an enlarged view of a portion of the pixels shown in FIG. 16. FIG. [Figure 18] 18 is an end view of the pixel shown in FIG. 17 taken along line B1-B2. [Figure 19] 18 is another end view of the pixel shown in FIG. 17 taken along line B1-B2. [Figure 20] 1 is a layout diagram of a plurality of pixels arranged in a display region of a display device according to an embodiment of the present invention. [Figure 21] 21 is an enlarged view of a portion of the pixels shown in FIG. 20. FIG. [Figure 22] 22 is an end view of the pixel shown in FIG. 21 taken along line C1-C2. [Figure 23] FIG. 10 is a layout diagram of pixels in a display device of a comparative example. [Figure 24] FIG. 24 is an end view of the pixel shown in FIG. 23 taken along line E1-E2. DETAILED DESCRIPTION OF THE INVENTION

[0009] Each embodiment of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that a person skilled in the art can easily arrive at by appropriately modifying the configuration of the embodiments while maintaining the gist of the invention are naturally included within the scope of the present invention. For clarity of explanation, the drawings may show the width, film thickness, shape, etc. of each part more schematically than the actual embodiment. However, the illustrated shapes are merely examples and do not limit the interpretation of the present invention. In this specification and each drawing, configurations similar to those described above with respect to the previous drawings are designated by the same reference numeral followed by an alphabet, and detailed description may be omitted as appropriate.

[0010] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as "up" or "upper." Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as "down" or "downward." For convenience of explanation, the terms "up" and "downward" are used in the following description. However, for example, the vertical relationship between the substrate and the oxide semiconductor layer may be different from that illustrated. In the following description, for example, the expression "oxide semiconductor layer on a substrate" merely describes the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other components may be disposed between the substrate and the oxide semiconductor layer. "Above" or "below" refers to the stacking order in a structure in which multiple layers are stacked. When a pixel electrode is referred to as being above a transistor, the transistor and the pixel electrode may not overlap in a planar view. On the other hand, when a pixel electrode is referred to as being vertically above a transistor, the transistor and the pixel electrode may overlap in a planar view.

[0011] The term "display device" refers to a structure that displays an image using an electro-optical layer. For example, the term "display device" may refer to a display panel including an electro-optical layer, or may refer to a structure in which other optical components (e.g., a polarizing component, a backlight, a touch panel, etc.) are attached to a display cell. The term "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, unless technically inconsistent. Therefore, although the embodiments described below will be described using a liquid crystal display device including a liquid crystal layer as an example of a display device, the structure of this embodiment can be applied to display devices including the other electro-optical layers described above.

[0012] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0013] The following embodiments can be combined with each other as long as no technical contradiction occurs.

[0014] [First embodiment] 1. Overview of the display device 10 A display device 10 according to one embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG. 1 is a plan view showing an overview of the display device 10 according to one embodiment of the present invention. As shown in FIG. 1, the display device 10 includes an array substrate 300, a sealant 400, a counter substrate 500, a flexible printed circuit board 600 (FPC 600), and an IC chip 700. The array substrate 300 and the counter substrate 500 are bonded together by the sealant 400. In a liquid crystal region 22 surrounded by the sealant 400, a plurality of pixels PIX are arranged in a matrix along a first direction D1 (row direction) and a second direction D2 (column direction) intersecting the first direction D1. The plurality of pixels PIX include red pixels R, green pixels G, and blue pixels B corresponding to color filters provided on the counter substrate. The first direction D1 and the second direction D2 may be orthogonal to each other. Although not shown in FIG. 1, a direction perpendicular to the surface of the array substrate 300 will be described as a D3 direction. The liquid crystal region 22 overlaps with a liquid crystal element LE (described later) in a planar view. In the following description, a region of the liquid crystal region 22 that includes a plurality of pixels may be referred to as a display region 23.

[0015] The display device 10 also has a backlight unit on the back of the array substrate 300, and when light emitted from the backlight unit passes through the display area 23, the transmitted light is modulated in each pixel PIX to display an image.

[0016] The sealing region 24, in which the sealing material 400 is provided, is the region surrounding the liquid crystal region 22. The FPC 600 is attached to the terminal region 26. The terminal region 26 is provided in an area where the array substrate 300 does not overlap the counter substrate 500, and is provided outside the sealing region 24. Note that the outside of the sealing region 24 means the outside of the area in which the sealing material 400 is provided and the area surrounded by the sealing material 400. The IC chip 700 is provided on the FPC 600. The IC chip 700 supplies signals to drive the pixel circuits of each pixel PIX. Note that, hereinafter, the sealing region 24, the outside of the sealing region 24, and the terminal region 26 are collectively referred to as the frame region 28. The IC chip 700 may be mounted in the frame region 28.

[0017] 2. Circuit Configuration of Display Device 10 2 is a block diagram showing the circuit configuration of a display device 10 according to one embodiment of the present invention. As shown in FIG. 2, a source driver circuit SD is provided along a first direction D1 relative to a liquid crystal region 22 in which pixels PIX are arranged, and gate driver circuits GD-1 and GD-2 are provided along a second direction D2 relative to the liquid crystal region 22. The source driver circuit SD and gate driver circuits GD-1 and GD-2 are provided in the sealing region 24. However, the region in which the source driver circuit SD and gate driver circuits GD-1 and GD-2 are provided is not limited to the sealing region 24 and may be any region outside the region in which the pixel circuits of the pixels PIX are provided. A configuration in which the source driver circuit is provided within the IC chip 700 may also be employed.

[0018] A source line 321 extends from the source driver circuit SD in the second direction D2 and is connected to the pixel circuits of the pixels PIX arranged in the second direction D2. A gate line 331 extends from the gate driver circuit GD-1 or the gate driver circuit GD-2 in the first direction D1 and is connected to the pixel circuits of the pixels PIX arranged in the first direction D1.

[0019] A terminal section 333 is provided in the terminal region 26. The terminal section 333 and the source driver circuit SD are connected by connection wiring 341. Similarly, the terminal section 333 and the gate driver circuits GD-1 and GD-2 are connected by connection wiring 341. When the FPC 600 is connected to the terminal section 333, an external device to which the FPC 600 is connected is connected to the display device 10, and pixel circuits included in each pixel PIX provided in the display device 10 are driven by signals from the external device.

[0020] 3. Pixel Circuit of Pixel PIX of Display Device 10 FIG. 3 is a circuit diagram showing a pixel circuit of a pixel PIX of a display device 10 according to an embodiment of the present invention. As shown in FIG. 3, the pixel circuit includes elements such as a transistor 800, a storage capacitor 890, and a liquid crystal element LE. As will be described in detail later, one electrode of the liquid crystal element LE is a pixel electrode, and the other electrode is a common electrode. One electrode of the storage capacitor 890 also serves as a pixel electrode, and the other electrode also serves as a common electrode. The transistor 800 has a first gate electrode 810, a first source electrode 830, and a first drain electrode 840. The first gate electrode 810 is connected to a gate wiring 331. The first source electrode 830 is connected to a source wiring 321. The first drain electrode 840 is connected to the storage capacitor 890 and the liquid crystal element LE. For ease of explanation, in this embodiment, 830B is referred to as a source electrode and 840B is referred to as a drain electrode, but the source and drain functions of each electrode may be interchangeable.

[0021] 4. Configuration of Display Device 10 The configuration of a display device 10 according to one embodiment of the present invention will be described in detail with reference to FIGS. 4 and 5. FIG. 4 is an end view illustrating the configuration of a display device 10 according to one embodiment of the present invention. FIGS. 5 and 6 are layout diagrams of a plurality of pixels arranged in a display region 23 of a display device 10 according to one embodiment of the present invention. Note that the end view shown in FIG. 4 is an end view for explaining the layer structure of the display device 10, and shows the peripheral circuit and pixel PIX adjacent to each other. In reality, the pixel PIX is provided within the display region 23, and the peripheral circuit is provided in a frame region 28 outside the display region 23, so it goes without saying that the peripheral circuit and pixel PIX are provided at a distance from each other. In particular, in the pixel PIX shown in FIG. 4, the transistor Tr1 in the pixel PIX is shown as the center, and only a portion of the aperture region (transparent region) that contributes to display is shown.

[0022] [5. Pixel circuit configuration] The display device 10 has a plurality of pixels PIX provided on an insulating surface. As shown in Fig. 4, each of the plurality of pixels PIX includes at least a transistor Tr1, a first insulating layer including a fifth insulating layer IL5 and a sixth insulating layer IL6, a connection electrode ZTCO, a seventh insulating layer IL7, an organic layer including a color filter COA and an overcoat OC1, and a pixel electrode PTCO. TCO is an abbreviation for transparent conductive oxide.

[0023] The transistor Tr1 is a transistor included in the pixel circuit of the pixel PIX of the display device 10. The transistor Tr1 (transistor 800 shown in FIG. 3) is provided on a third insulating layer IL3. The transistor Tr1 has an oxide semiconductor layer OS, a fourth insulating layer IL4, and a gate wiring GL1 (first gate electrode 810 shown in FIG. 3). The gate wiring GL1 faces the oxide semiconductor layer OS. A part of the gate wiring GL1 functions as a gate electrode. The fourth insulating layer IL4 is provided between the oxide semiconductor layer OS and the gate wiring GL1. The fourth insulating layer IL4 functions as a gate insulating layer. In this embodiment, a top-gate transistor in which the oxide semiconductor layer OS is provided closer to the array substrate SUB1 than the gate wiring GL1 is exemplified, but a bottom-gate transistor in which the positional relationship between the gate wiring GL1 and the oxide semiconductor layer OS is reversed may also be used.

[0024] The oxide semiconductor layer OS includes oxide semiconductor regions OS1 and OS2. The oxide semiconductor region OS1 is an oxide semiconductor layer in a region that overlaps with the gate wiring GL1 in a planar view. The oxide semiconductor region OS1 functions as a semiconductor and is switched between a conductive state and a non-conductive state depending on the voltage supplied to the gate wiring GL1. In other words, the oxide semiconductor region OS1 functions as a channel of the transistor Tr1. The oxide semiconductor region OS2 is doped with an impurity element and functions as a conductor.

[0025] A fifth insulating layer IL5 is provided on the gate line GL1. A line W1 (source line 321 shown in FIG. 3) is provided on the fifth insulating layer IL5. The line W1 is connected to the oxide semiconductor region OS2 via a contact hole CH1 provided in the fifth insulating layer IL5 and the fourth insulating layer IL4. A data signal related to the gradation of the pixel is transmitted to the line W1. A sixth insulating layer IL6 is provided on the fifth insulating layer IL5 and the line W1. The fifth insulating layer IL5 and the sixth insulating layer IL6 may be referred to as the first insulating layer. The fifth insulating layer IL5 and the sixth insulating layer IL6 are formed using an inorganic insulating material.

[0026] A connection electrode ZTCO (first drain electrode 840 shown in FIG. 3) is provided on the sixth insulating layer IL6. The connection electrode ZTCO is connected to the oxide semiconductor region OS2 via a contact hole CH2 provided in the fourth insulating layer IL4, the fifth insulating layer IL5, and the sixth insulating layer IL6. The connection electrode ZTCO is in contact with the oxide semiconductor region OS2 at the bottom of the contact hole CH2. The connection electrode ZTCO is made of a transparent conductive material.

[0027] The region where the connection electrode ZTCO and the oxide semiconductor region OS2 contact each other is called the contact region ZCON. The connection electrode ZTCO contacts the oxide semiconductor region OS2 in the contact region ZCON, which does not overlap with the gate wiring GL1 and the wiring W1 in a plan view. In a plan view, the contact region ZCON is included in the pixel opening region. The pixel opening region is a region surrounded by the gate wiring GL2 and the wiring W1, which extend in the first direction D1, as shown in FIG. 5.

[0028] For example, when a transparent conductive layer such as an ITO layer is formed in contact with a semiconductor layer such as a silicon layer, the surface of the semiconductor layer is oxidized by process gases and oxygen ions during ITO film formation. The oxide layer formed on the surface of the semiconductor layer has high resistance, resulting in high contact resistance between the semiconductor layer and the transparent conductive layer. As a result, poor electrical contact occurs between the semiconductor layer and the transparent conductive layer. On the other hand, even when the transparent conductive layer is formed in contact with an oxide semiconductor layer, such a high-resistance oxide layer is unlikely to form on the surface of the oxide semiconductor layer. Therefore, poor electrical contact between the oxide semiconductor layer and the transparent conductive layer is unlikely to occur.

[0029] A seventh insulating layer IL7 is provided on the connection electrode ZTCO. As shown in FIG. 5, an opening OP1 is provided in the seventh insulating layer IL7, exposing the connection electrode ZTCO and a portion of the sixth insulating layer IL6. The seventh insulating layer IL7 is formed, for example, using an inorganic insulating material that has a moisture-blocking function. This prevents moisture contained in the organic layer from penetrating into the oxide semiconductor layer OS of the transistor Tr1, even if an organic layer (described later) is formed on the transistor Tr1.

[0030] A color filter COA and an overcoat OC1 are provided on the seventh insulating layer IL7. The color filter COA and the overcoat OC1 are formed using organic materials and are therefore sometimes referred to as organic layers. For example, red, green, and blue color filters are used as the color filter COA. As the resolution of the display device 10 increases, it may become more difficult to align the color filter provided on the counter substrate SUB2 with the pixel circuit provided on the array substrate SUB1. The color filter COA does not necessarily have to be provided on the wiring W1. The area where the color filter COA is provided is a region that transmits backlight light in the pixel aperture area. Light from the backlight passes through the area where the connection electrode ZTCO and the color filter COA are provided from the array substrate SUB1 and exits from the counter substrate SUB2. The overcoat OC1 reduces steps formed by structures provided below the overcoat OC1. For this reason, the overcoat OC1 is sometimes referred to as a planarizing film. As shown in FIG. 5, an opening OP2 is provided in the overcoat OC1, and the seventh insulating layer IL7 and a part of the connection electrode ZTCO are exposed.

[0031] A pixel electrode PTCO is provided on the overcoat OC1 via an opening OP2. The pixel electrode PTCO is connected to the connection electrode ZTCO via openings OP1 and OP2. The region where the connection electrode ZTCO and the pixel electrode PTCO contact each other is called a contact region PCON. In plan view, the contact region PCON overlaps with the gate line GL1. The pixel electrode PTCO is formed using a transparent conductive material. An eighth insulating layer IL8 is provided on the pixel electrode PTCO and the overcoat OC1.

[0032] As shown in FIGS. 4 and 6 , a common auxiliary electrode CMTL and a common electrode CTCO are provided on an eighth insulating layer IL8. The common electrode CTCO is provided in contact with the common auxiliary electrode CMTL. A storage capacitor 890 is formed by the pixel electrode PTCO, the eighth insulating layer IL8, and the common electrode CTCO. The common auxiliary electrode CMTL and the common electrode CTCO have different planar patterns. In this case, a portion of the connection electrode ZTCO provided inside the opening OP2 overlaps with the common auxiliary electrode CMTL. The common auxiliary electrode CMTL is a metal layer. The common electrode CTCO is a transparent conductive layer. The electrical resistance of the common auxiliary electrode CMTL is lower than the electrical resistance of the common electrode CTCO. The common auxiliary electrode CMTL also functions as a light-shielding layer. For example, the common auxiliary electrode CMTL blocks light from adjacent pixels, thereby suppressing color mixing. In this embodiment, a configuration in which the common electrode CTCO is provided on the common auxiliary electrode CMTL is described, but a configuration in which the common auxiliary electrode CMTL is provided on the common electrode CTCO may also be described.

[0033] An overcoat OC2 is provided on the eighth insulating layer IL8 and the common electrode CTCO so as to fill the interior of an opening OP2 provided in the overcoat OC1. A spacer PS is provided on and in contact with the overcoat OC2. A portion of an edge of the connection electrode ZTCO provided inside the opening OP2 overlaps with the spacer PS. The spacer PS may be provided for some of the pixels. For example, the spacer PS may be provided for one of the red, green, and blue pixels PIX. Alternatively, the spacer PS may be provided for all of the pixels PIX.

[0034] The counter substrate SUB2 is provided with a ninth insulating layer IL9, and an overcoat OC3 on the ninth insulating layer IL9. The array substrate SUB1 and the counter substrate SUB2 are bonded together with a sealant 400 (see FIG. 1) so that the overcoat OC3 faces the eighth insulating layer IL8 and the common electrode CTCO. The cell gap between the array substrate SUB1 and the counter substrate SUB2 is determined by spacers PS. A liquid crystal layer LC is provided between the array substrate SUB1 and the counter substrate SUB2.

[0035] A gate wiring GL2 may be provided between the transistor Tr1 and the array substrate SUB1. The gate wiring GL2 can control the threshold value of the transistor Tr1. The gate wiring GL2 also functions as a light-shielding film. In plan view, the gate wiring GL2 is provided in a region where the gate wiring GL1 and the oxide semiconductor layer OS overlap. That is, in plan view, the gate wiring GL2 is provided in a region where it overlaps with the oxide semiconductor region OS1. The gate wiring GL2 prevents light incident from the array substrate SUB1 side from reaching the oxide semiconductor region OS1. In place of the gate wiring GL2, a floating conductive layer that shields the oxide semiconductor region OS1 may be provided. In plan view, the contact region ZCON is provided in a region where it does not overlap with the gate wiring GL2.

[0036] [6. Peripheral circuit configuration] The transistors Tr2-1 and Tr2-2 are transistors included in the peripheral circuits of the source driver circuit SD or the gate driver circuits GD-1 and GD-2, etc. The transistor Tr2-1 is an n-type transistor, and the transistor Tr2-2 is a p-type transistor.

[0037] The n-type transistor Tr2-1 and the p-type transistor Tr2-2 are provided on a first insulating layer IL1. Both the n-type transistor Tr2-1 and the p-type transistor Tr2-2 have a gate wiring GL3 (also referred to as a gate electrode), a second insulating layer IL2, and a semiconductor layer S. The gate wiring GL3 faces the semiconductor layer S. The second insulating layer IL2 is provided between the semiconductor layer S and the gate wiring GL3. The gate wiring GL3 is formed from the same conductive film as the gate wiring GL2. In this embodiment, a top-gate transistor in which the gate wiring GL3 is provided closer to the array substrate SUB1 than the semiconductor layer S is exemplified, but a bottom-gate transistor in which the positional relationship between the semiconductor layer S and the gate wiring GL3 is reversed may also be used.

[0038] The semiconductor layer S of the n-type transistor Tr2-1 includes semiconductor regions S1, S2, and S3. The semiconductor layer S of the p-type transistor Tr2-2 includes semiconductor regions S1 and S2. The semiconductor region S1 is a semiconductor region that overlaps with the gate wiring GL3 in a planar view. The semiconductor region S1 functions as the channel of the transistor Tr2-1. The semiconductor region S2 functions as a conductor. The semiconductor region S3 functions as a conductor with a higher resistance than the semiconductor region S2. The semiconductor region S3 suppresses hot carrier degradation by attenuating hot carriers that invade toward the semiconductor region S1.

[0039] A third insulating layer IL3 and a fourth insulating layer IL4 are provided on the gate line GL3. In transistors Tr2-1 and Tr2-2, the third insulating layer IL3 and the fourth insulating layer IL4 simply function as interlayer films. A line W2 is provided on the fourth insulating layer. The line W2 is connected to the semiconductor layer S via contact holes provided in the second insulating layer IL2, the third insulating layer IL3, and the fourth insulating layer IL4. The line W2 is formed from the same conductive film as the gate line GL1. A fifth insulating layer IL5 is provided on the line W2. A line W3 is provided on the fifth insulating layer IL5. The line W3 is formed from the same conductive film as the line W1. The line W3 is also connected to the line W2 via a contact hole provided in the fifth insulating layer IL5. A sixth insulating layer IL6 and a seventh insulating layer IL7 are provided on the fifth insulating layer IL5 and the line W3. Note that in FIG. 4, the color filter COA and the pixel electrode PTCO are not provided in the peripheral circuit, and therefore are not shown. In the peripheral circuit, a common auxiliary electrode CMTL and a common electrode CTCO may be provided.

[0040] [7. Impact of high-definition display devices] The effects of increasing the resolution of a display device will be described with reference to Figures 23 and 24. As the resolution of display devices increases, the layout of conductive layers and contact holes that form adjacent pixels becomes more restricted. For example, if the distance between the conductive layers of adjacent pixels is too close, there is a risk of short-circuiting. In order to prevent short-circuiting between adjacent conductive layers, the area of ​​the conductive layers may be reduced.

[0041] FIG. 23 is a layout diagram of a pixel of a display device of a comparative example. FIG. 24 is an end view of the pixel shown in FIG. 23 along E1-E2. Note that the common electrode, overcoat, spacer, liquid crystal layer, counter substrate, and the like are omitted from FIGS. 23 and 24 . As shown in FIGS. 23 and 24 , the connection electrode ZTCO overlaps with the gate line GL1 on the sixth insulating layer IL6 and is connected to the oxide semiconductor layer OS through a contact hole CH2 provided in the fourth to sixth insulating layers IL4 to IL6. To prevent the connection electrodes ZTCO of two adjacent pixels in the second direction D2 from being close to each other and short-circuiting, the end of the connection electrode ZTCO is provided in contact with the oxide semiconductor layer OS. When the connection electrode ZTCO is formed, the exposed region of the oxide semiconductor layer OS is exposed to an etching solution or etching gas. Because both the connection electrode ZTCO and the oxide semiconductor layer OS are made of metal oxide, the oxide semiconductor layer OS tends to be easily etched by etching the connection electrode ZTCO. If the oxide semiconductor layer OS is etched, the coverage of the connection electrode ZTCO and the oxide semiconductor layer OS will be deteriorated when the seventh insulating layer IL7 is formed on the connection electrode ZTCO. As a result, moisture from the organic layer may penetrate into the oxide semiconductor layer OS from the region where the coverage of the seventh insulating layer IL7 is deteriorated, which may cause fluctuations in the characteristics of the transistor Tr1.

[0042] Furthermore, as display devices become increasingly high-definition, they are significantly affected by misalignment of masks used to form the oxide semiconductor layer, various conductive layers, and contact holes. For example, when the oxide semiconductor layer OS and the connection electrode ZTCO are formed through the contact holes CH2 provided in the fourth to sixth insulating layers IL4 to IL6, the line width of the oxide semiconductor layer OS, the line width of the connection electrode ZTCO, and misalignment of each mask significantly affect the display. If the mask for the connection electrode ZTCO and the mask for the contact hole CH2 are misaligned relative to the mask for the oxide semiconductor layer OS, poor connection between the connection electrode ZTCO and the oxide semiconductor layer OS may occur. Furthermore, as described above, if the oxide semiconductor layer OS is exposed during processing of the connection electrode ZTCO and is etched, there is a greater concern that the connection electrode ZTCO and the oxide semiconductor layer OS may be disconnected.

[0043] As described above, there is a concern that the pixel layout margin may be narrowed as the resolution of pixels in a display device is improved, which may affect the reliability of the display device due to fluctuations in the characteristics of transistors using oxide semiconductor layers or poor connections of wirings or the like.

[0044] One of the objects of the present invention is to improve the reliability of a display device 10 having highly refined pixels.

[0045] Fig. 7 is an enlarged view of a portion of the pixels shown in Fig. 5. Fig. 8 is an end view of the pixel shown in Fig. 7 taken along line A1-A2. As shown in Fig. 5, in a plan view, the pitch1 between the gate lines GL2 of two pixels adjacent in the second direction D2 and the pitch2 between the lines W1 of two pixels adjacent in the first direction D1 are, for example, 4 μm or more and 8 μm or less. The pitch1 and pitch2 may be the same or different.

[0046] In one embodiment of the present invention, the contact hole CH2 connecting the oxide semiconductor layer OS and the connection electrode ZTCO is covered with the connection electrode ZTCO. This prevents the oxide semiconductor layer OS from being exposed when the connection electrode ZTCO is formed. Furthermore, this prevents the oxide semiconductor layer OS from being etched when the connection electrode ZTCO is formed. Therefore, when the seventh insulating layer IL7 is formed, the coverage of the connection electrode ZTCO can be improved. As a result, it is possible to prevent moisture from entering the oxide semiconductor layer OS from the organic layer. Because the contact hole CH2 is covered with the connection electrode ZTCO, it is possible to prevent poor connection between the oxide semiconductor layer OS and the connection electrode ZTCO even if mask misalignment occurs.

[0047] A portion of the end of the connection electrode ZTCO is disposed inside an opening OP2 provided in the seventh insulating layer IL7. Also, a portion of the end of the connection electrode ZTCO is disposed inside an opening OP1 provided in the seventh insulating layer IL7. Also, the pixel electrode PTCO covers a portion of the end of the opening OP1 and is in contact with the connection electrode ZTCO. This allows the organic layer to be sealed by the pixel electrode PTCO and the seventh insulating layer IL7, thereby preventing moisture from entering the organic layer into the transistor Tr1.

[0048] When the connection electrode ZTCO covers the entire contact hole CH2, if the connection electrode ZTCO is provided over the entire opening OP1, there is a risk of short-circuiting between the two connection electrodes ZTCO when the connection electrodes ZTCO are adjacent to each other in two pixels adjacent to each other in the second direction D2. Therefore, when the connection electrodes ZTCO are adjacent to each other in two pixels adjacent to each other in the second direction D2, it is preferable that a portion of the end of the connection electrode ZTCO provided inside the opening OP2 be positioned so as to overlap with the gate line GL1. A portion of the opposing end of the connection electrode ZTCO does not need to overlap with the gate line GL2 of the pixel adjacent to each other in the second direction D2. This ensures the connection between the connection electrode ZTCO and the oxide semiconductor layer OS and the connection between the connection electrode ZTCO and the pixel electrode PTCO even if the length of the connection electrode ZTCO in the second direction D2 is shortened. Furthermore, when the connection electrodes ZTCO are adjacent to each other in two pixels adjacent to each other in the second direction D2, even if the distance between the two connection electrodes ZTCO is several μm, it is possible to prevent the two connection electrodes ZTCO from shorting out. This makes it possible to bring the adjacent connection electrodes ZTCO closer to the processing limit in the second direction D2, thereby further increasing the area contributing to display in one pixel. Similarly, it is also possible to bring the adjacent pixel electrodes closer to the processing limit in the second direction D2, thereby further increasing the area contributing to display in one pixel.

[0049] In two adjacent pixels in the second direction D2, at least one of the distance between the connection electrode of one pixel and the connection electrode of the other pixel, the distance between the pixel electrode of one pixel and the pixel electrode of the other pixel, and the contact holes CH1 and CH2 can be 2 μm or less. For example, in two adjacent pixels, the distance between the connection electrode of one pixel and the connection electrode of the other pixel may be the same as the length of the contact hole in one pixel in the first direction D1. In two adjacent pixels, the distance between the connection electrode of one pixel and the connection electrode of the other pixel, the distance between the pixel electrode of one pixel and the pixel electrode of the other pixel, and the contact holes CH1 and CH2 may all be the same length. Here, "same length" does not necessarily mean that the lengths are exactly the same, but may be approximately the same length.

[0050] According to the display device 10 of one embodiment of the present invention, even if the pixel layout margin becomes narrower as pixel resolution increases, it is possible to suppress fluctuations in the characteristics of transistors using an oxide semiconductor layer. Furthermore, it is possible to suppress poor connection between the oxide semiconductor layer OS and the connection electrode ZTCO. Therefore, it is possible to improve the reliability of the display device 10 having high-resolution pixels.

[0051] 8. Planar Layout of Display Device 10 Next, the layout of each layer in the pixel circuit of the display device 10 according to one embodiment of the present invention will be described with reference to Figures 9 to 16. The layout of each layer in the pixel circuit will also be described with appropriate reference to the end view shown in Figure 4.

[0052] As shown in FIGS. 4 and 9, the gate line GL2 is provided on the second insulating layer IL2, extends in the first direction D1, and is provided commonly to the pixels arranged in the first direction D1. The oxide semiconductor layer OS is provided on the third insulating layer IL3, and extends in the second direction D2. The oxide semiconductor layer OS has a bent region. The gate line GL1 is provided on the fourth insulating layer IL4, extends in the first direction D1, and intersects with the oxide semiconductor layer OS. The pattern of the gate line GL1 is provided inside the pattern of the gate line GL2.

[0053] As shown in FIGS. 4 and 10 , the contact hole CH1 is provided near the upper end of the pattern of the oxide semiconductor layer OS in a region overlapping with the wiring W1. The contact hole CH1 is formed in the fourth insulating layer IL4 and the fifth insulating layer IL5. The wiring W1 is formed on the fifth insulating layer IL5. A main portion of the pattern of the oxide semiconductor layer OS extends in the second direction D2 between adjacent wirings W1. The wiring W1 is connected to the oxide semiconductor layer OS via the contact hole CH1. The remaining portion of the pattern of the oxide semiconductor layer OS extends from the main portion toward the region of the contact hole CH1 in a direction oblique to the first direction D1 and the second direction D2 and further bends toward the second direction D2. The multiple wirings W1 extend in the second direction D2. In this case, it can be said that the main portion of the oxide semiconductor layer OS extends in the second direction D2 between two adjacent wirings W1 and intersects with the gate wiring GL1.

[0054] As shown in FIGS. 4 and 11, the contact hole CH2 is provided near the bottom end of the pattern of the oxide semiconductor layer OS. The contact hole CH2 is formed in the fourth insulating layer IL4, the fifth insulating layer IL5, and the sixth insulating layer IL6. The contact hole CH2 is provided in a region that overlaps with the pattern of the oxide semiconductor layer OS but does not overlap with the gate wiring GL1. The connection electrode ZTCO is formed on the sixth insulating layer IL6. The connection electrode ZTCO overlaps with the gate wiring GL1 and the oxide semiconductor layer OS between two adjacent wirings W1. Therefore, the connection electrode ZTCO is in contact with the oxide semiconductor layer OS at the contact hole CH2 (contact region ZCON) that does not overlap with the gate wiring GL1. The oxide semiconductor layer OS is in contact with the wiring W1 on the side opposite to the contact hole CH2 with respect to the gate wiring GL1. The contact hole CH2 does not overlap with the gate wiring GL2.

[0055] 4 and 12, an opening OP1 is provided in the seventh insulating layer IL7. The opening OP1 is provided in a region overlapping with the gate lines GL1 and GL2. The opening OP1 is also provided above the connection electrode ZTCO so as to expose a portion of the connection electrode ZTCO.

[0056] FIG. 13 shows the layout of the color filters. The color filters include a red color filter COA(R), a green color filter (G), and a blue color filter COA(B). The color filters are arranged in the first direction D1 in the order of color filters COA(R), COA(G), and COA(B), and in the second direction D2 in the order of color filters COA(R), COA(B), and COA(G). The color filters are arranged so as not to overlap the gate wiring GL. For example, in the first direction D1, two adjacent color filters COA(R) and COA(G) overlap on the wiring W1. Furthermore, the end of the color filter COA(R) in the first direction D1 overlaps the gate wiring GL2. The color filters COA(R), COA(G), and COA(B) are arranged to fill the contact hole CH2. Moreover, the color filters COA(R), COA(G), and COA(B) are provided in an area that does not overlap with the opening OP1.

[0057] As shown in FIGS. 4 and 14, an opening OP2 is provided in the overcoat OC1. Note that a color filter COA is provided between the seventh insulating layer IL7 and the overcoat OC1, but is not shown in FIG. 14. In the opening region surrounded by the gate line GL2 and the line W1, the region where the contact hole CH2 is provided also contributes to the opening region. Therefore, as shown in FIG. 4, the color filter COA is provided inside the contact hole CH2. The opening OP2 is also provided in a region overlapping with the gate lines GL1 and GL2. The opening OP2 is provided so as to surround the opening OP1. The opening OP2 is also provided on the connection electrode ZTCO so as to expose a portion of the seventh insulating layer IL7 and a portion of the connection electrode ZTCO.

[0058] As shown in FIGS. 4 and 14 , the pixel electrode PTCO is provided on the overcoat OC1 so as to be connected to the connection electrode ZTCO through the openings OP1 and OP2. Specifically, the pixel electrode PTCO is connected to the connection electrode ZTCO inside the opening OP1 and inside the opening OP2. As shown in FIG. 4 , inside the opening OP2, the pixel electrode PTCO is in contact with the sixth insulating layer IL6. Furthermore, the thickness of the region of the sixth insulating layer IL6 that is in contact with the pixel electrode PTCO may be smaller than the thickness of the region of the sixth insulating layer IL6 that is in contact with the connection electrode ZTCO. By having the pixel electrode PTCO in contact with the sixth insulating layer IL6 inside the opening OP1, it is possible to prevent moisture originating from the organic layer from penetrating into the oxide semiconductor layer OS through the sixth insulating layer IL6. The pixel electrode PTCO overlaps with the gate wiring GL1, the oxide semiconductor layer OS, and the connection electrode ZTCO between the wirings W1 that are adjacent to each other in the first direction D1.

[0059] As shown in FIGS. 4 and 15, the common auxiliary electrode CMTL is arranged in a grid pattern extending in each of the first direction D1 and the second direction D2. A region of the common auxiliary electrode CMTL extending in the second direction D2 overlaps with the wiring W1 (not shown). A region of the common auxiliary electrode CMTL extending in the first direction D1 overlaps with the gate wiring GL1 (not shown), the gate wiring GL2, and the openings OP1 and OP2. The common electrode CTCO is provided in an island shape in the region overlapping with the wiring W1. Since the multiple common electrodes CTCO are provided on and in contact with the common auxiliary electrode CMTL, the same potential is supplied to the multiple common electrodes CTCO. In the first direction D1, a gap between two adjacent common electrodes CTCO functions as a slit SL for the FFS mode. Corners of the common electrode CTCO are arranged inside the openings OP1 and OP2.

[0060] 9. Materials of Components of Display Device 10 The array substrate SUB1 and the counter substrate SUB2 can be made of a rigid substrate that is light-transmitting and not flexible, such as a glass substrate, a quartz substrate, or a sapphire substrate.

[0061] Metallic materials can be used for the gate wiring GL1, GL2, wiring W1, W2, and W3, and the common auxiliary electrode CMTL. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), copper (Cu), or silver (Ag), or alloys or compounds thereof, can be used. The metallic materials can be used as single layers or stacked layers for the electrodes and other components.

[0062] The first insulating layer IL1 to the ninth insulating layer IL9 can be made of a general inorganic insulating material. For example, the first insulating layer IL1 to the ninth insulating layer IL9 can be made of silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum oxide (AlO x ), aluminum oxide nitride (AlO x N y ), aluminum oxide nitride (AlN x O y ), or aluminum nitride (AlN x ) or the like can be used as a single layer or a laminated layer.

[0063] The above SiO x N y and AlO x N y are silicon and aluminum compounds containing a smaller proportion (x>y) of nitrogen (N) than oxygen (O). SiN x O y and AlN x O y are silicon and aluminum compounds containing a smaller proportion of oxygen than nitrogen (x>y).

[0064] In this embodiment, the first insulating layer IL1 contains silicon nitride to prevent impurities from the array substrate SUB1 from penetrating into the semiconductor layer S. The third insulating layer IL3 may be made of a laminate of silicon nitride and silicon oxide. The fourth insulating layer IL4 may be made of silicon oxide. The seventh insulating layer IL7 and the eighth insulating layer IL8 may be made of silicon nitride to prevent moisture from penetrating from the organic layer. The second insulating layer IL2, the fifth insulating layer IL5, the sixth insulating layer IL6, and the ninth insulating layer IL9 may be made of the inorganic insulating materials described above, as appropriate.

[0065] The overcoats OC1, OC2, OC3 and the spacers PS can be made of an organic insulating material such as polyimide resin, acrylic resin, epoxy resin, silicone resin, fluorine resin, or siloxane resin.

[0066] The oxide semiconductor layer OS can be formed using an oxide semiconductor having semiconductor properties. The oxide semiconductor layer OS has light-transmitting properties. For example, an oxide semiconductor containing two or more metals including indium (In) can be used as the oxide semiconductor layer OS. For example, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) can be used as the oxide semiconductor layer OS. In particular, an oxide semiconductor having a composition ratio of In:Ga:Zn:O=1:1:1:4 can be used as the oxide semiconductor layer OS. However, the oxide semiconductor layer OS used in this embodiment is not limited to the above composition, and oxide semiconductors with compositions other than the above can also be used. For example, the ratio of In may be increased to improve mobility. Furthermore, the ratio of Ga may be increased to increase the band gap and reduce the influence of light irradiation. The oxide semiconductor layer OS may be amorphous or polycrystalline. The oxide semiconductor layer OS may be a mixed phase of amorphous and crystalline.

[0067] In the oxide semiconductor layer OS, the oxide semiconductor region OS2 is a region doped with an impurity element such as argon (Ar), phosphorus (P), or boron (B), and the oxide semiconductor region OS1 is a region not doped with the impurity element.

[0068] Low-temperature polysilicon is used as the semiconductor layer S. The semiconductor layer S includes semiconductor regions S1, S2, and S3. The semiconductor region S2 is doped with a high concentration of an impurity element, and the semiconductor region S3 is doped with a low concentration of an impurity element. The semiconductor region S1 is a region to which no impurity element is doped or a region to which a low concentration of an impurity element is doped. The semiconductor layer S of the n-type transistor Tr2-1 is doped with phosphorus, and the semiconductor layer S of the p-type transistor Tr2-2 is doped with boron.

[0069] The connection electrode ZTCO, pixel electrode PTCO, and common electrode CTCO are made of a transparent conductive material. Examples of the transparent conductive material include a mixture of indium oxide and tin oxide (ITO) and a mixture of indium oxide and zinc oxide (IZO). Materials other than those mentioned above may also be used for the transparent conductive layer.

[0070] [10. Variation 1] In this embodiment, a display device having a configuration partially different from that of the display device 10 shown in the first embodiment will be described with reference to Figs. 16 to 18. Specifically, the configuration for connecting the pixel electrode PTCO and the connection electrode ZTCO is different. Therefore, the configuration for connecting the pixel electrode PTCO and the connection electrode ZTCO will be described in detail, and other configurations will be omitted as appropriate.

[0071] In the end view illustrated in FIG. 8 , a portion of the end of the connection electrode ZTCO provided on the sixth insulating layer IL6 is located inside the opening OP1 of the seventh insulating layer IL7. That is, when forming the opening OP1 of the seventh insulating layer IL7, the sixth insulating layer IL6 exposed from the connection electrode ZTCO may be exposed to etching gas, resulting in the removal of the sixth insulating layer IL6. As a result, the thickness of the sixth insulating layer IL6 in the region in contact with the pixel electrode PTCO may be smaller than the thickness of the region in contact with the connection electrode ZTCO. For example, if the color filter COA or the overcoat CO1 contacts the exposed region of the sixth insulating layer IL6 due to mask misalignment, moisture contained in the color filter COA or the overcoat CO1 may penetrate into the oxide semiconductor layer OS through the sixth insulating layer IL6. In this case, if the thickness of the sixth insulating layer IL6 in the region in contact with the connection electrode ZTCO is sufficiently thick, moisture can be prevented from affecting the characteristics of the transistor Tr1. However, if the sixth insulating layer IL6 has a small thickness in the region in contact with the connection electrode ZTCO, moisture may affect the characteristics of the transistor Tr1.

[0072] Fig. 16 is a layout diagram of a plurality of pixels arranged in a display region of a display device 10 according to one embodiment of the present invention. Fig. 17 is an enlarged view of a portion of the plurality of pixels shown in Fig. 16. Fig. 18 is an end view of the pixel shown in Fig. 17 taken along line B1-B2.

[0073] 16 to 18, the structure from the array substrate SUB1 to the seventh insulating layer IL7 is the same as the structure described with reference to FIGS. 4 to 11. The layout of the pixel electrodes PTCO, common electrodes CTCO, and common auxiliary electrodes CMTL is also the same as that of the first embodiment, so reference may be made as appropriate. In this modification, a conductive layer CL is provided to cover the opening OP1 in the seventh insulating layer IL7 to prevent the sixth insulating layer IL6 from being exposed through the opening OP1. Since the sixth insulating layer IL6 is thereby covered by the conductive layer CL, contact between the organic layer and the sixth insulating layer IL6 can be prevented even if mask misalignment occurs. Therefore, moisture from the organic layer can be prevented from penetrating into the oxide semiconductor layer OS through the sixth insulating layer IL6. As a result, fluctuations in transistor characteristics can be suppressed, thereby improving the reliability of the display device.

[0074] The conductive layer CL is provided so as to overlap with the gate lines GL1 and GL2. Since the region where the conductive layer CL is provided is a region where light does not pass through, the conductive layer CL does not need to be light-transmitting. Therefore, the conductive layer CL may be made of the metal material described for the gate lines GL1 and GL2 and the lines W1 to W2. Alternatively, the conductive layer CL may be made of the transparent conductive material described for the connection electrode ZTCO, pixel electrode PTCO, and common electrode CTCO.

[0075] By providing a conductive layer CL on the connection electrode ZTCO and the seventh insulating layer IL7 so as to cover the opening OP1, the pixel electrode PTCO is connected to the connection electrode ZTCO via the conductive layer CL, thereby improving the connection between the pixel electrode PTCO and the connection electrode ZTCO.

[0076] FIG. 19 is another end view of the pixel shown in FIG. 17 taken along line B1-B2. This differs from the end view shown in FIG. 18 in that a conductive layer CL is provided on the connection electrode ZTCO, and a seventh insulating layer IL7 is provided on the conductive layer CL. The positions of the openings OP1 provided in the conductive layer CL and the seventh insulating layer IL7 are the same as those in FIGS. 16 and 17. Therefore, the edges of the openings OP1 are provided on the conductive layer CL. This prevents the organic layer from contacting the sixth insulating layer IL6 even if a mask misalignment occurs. This prevents moisture from penetrating the oxide semiconductor layer OS through the sixth insulating layer IL6. As a result, fluctuations in transistor characteristics can be suppressed, thereby improving the reliability of the display device.

[0077] [11. Variation 2] In this embodiment, a display device having a configuration partially different from that of the display device 10 shown in the first embodiment will be described with reference to Figs. 20 to 22. Specifically, the configuration for connecting the pixel electrode PTCO and the connection electrode ZTCO is different. Therefore, the configuration for connecting the pixel electrode PTCO and the connection electrode ZTCO will be described in detail, and other configurations will be omitted as appropriate.

[0078] Fig. 20 is a layout diagram of a plurality of pixels arranged in a display region of a display device 10 according to one embodiment of the present invention. Fig. 21 is an enlarged view of a portion of the plurality of pixels shown in Fig. 20. Fig. 22 is an end view of the pixel shown in Fig. 21 taken along line C1-C2.

[0079] 20 to 22, the structure from the array substrate SUB1 to the seventh insulating layer IL7 is the same as the structure described with reference to FIGS. 4 to 11. The layout of the pixel electrodes PTCO, common electrodes CTCO, and common auxiliary electrodes CMTL is also the same as that of the first embodiment, so reference may be made as appropriate. In this modification, the opening OP1 in the seventh insulating layer IL7 is positioned close to the contact hole CH1 to prevent the sixth insulating layer IL6 from being exposed. This allows the edge of the opening OP1 to be located above the connection electrode ZTCO, and the edge of the opening OP2 to be located above the connection electrode ZTCO and the seventh insulating layer IL7. This prevents the organic layer from contacting the sixth insulating layer IL6. This prevents moisture from penetrating from the organic layer into the oxide semiconductor layer OS through the sixth insulating layer IL6. As a result, fluctuations in transistor characteristics can be suppressed, thereby improving the reliability of the display device.

[0080] The above-described embodiments of the present invention can be combined as appropriate as long as they are not mutually inconsistent. Furthermore, even if a person skilled in the art appropriately adds or deletes components or modifies the design of a display device of each embodiment, or adds or omits processes or modifies conditions, such a display device is included in the scope of the present invention as long as it includes the gist of the present invention.

[0081] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, those that are clear from the description in this specification or that can be easily predicted by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0082] 22: liquid crystal region, 23: display region, 24: sealing region, 26: terminal region, 28: frame region, 300: array substrate, 321: source wiring, 331: gate wiring, 333: terminal section, 341: connection wiring, 400: sealing material, 500: opposing substrate, 600: flexible printed circuit board, 700: chip, 800: transistor, 810: first gate electrode, 830: first source electrode, 840: first drain electrode, 890: storage capacitor, CH1: contact hole, CH2: contact hole, CMTL: common auxiliary electrode, CO1: overcoat, CO2: overcoat, COA: color filter, CTCO: common electrode, GD-1: gate driver circuit, GD-2: gate driver circuit, GL1: gate wiring, GL2: gate wiring , GL3: gate wiring, IL1: first insulating layer, IL2: second insulating layer, IL3: third insulating layer, IL4: fourth insulating layer, IL5: fifth insulating layer, IL6: sixth insulating layer, IL7: seventh insulating layer, IL8: eighth insulating layer, IL9: ninth insulating layer, LC: liquid crystal layer, LE: liquid crystal element, OP1: opening, OP2: opening, OS: oxide semiconductor layer, OS1: oxide semiconductor region, OS2: oxide semiconductor region, PIX: pixel, PS: spacer, PTCO: pixel electrode, S: semiconductor layer, S1: semiconductor region, S2: semiconductor region, S3: semiconductor region, SD: source driver circuit, PS: spacer, SUB1: array substrate, SUB2: counter substrate, Tr1: transistor, Tr2-1: transistor, Tr2-2: transistor, W1: wiring, W2: wiring, W3: wiring

Claims

1. a plurality of pixels provided on an insulating surface; Each of the plurality of pixels is a transistor including an oxide semiconductor layer, a gate wiring facing the oxide semiconductor layer, and a gate insulating layer between the oxide semiconductor layer and the gate wiring; a first insulating layer disposed over the transistor; a first transparent conductive layer on the first insulating layer, the first transparent conductive layer being connected to the oxide semiconductor layer via a first contact hole provided in the first insulating layer and the gate insulating layer; a second insulating layer provided on the first transparent conductive layer and having a first opening exposing a portion of the first transparent conductive layer; a first organic layer on the second insulating layer, the first organic layer having a second opening exposing a portion of the first transparent conductive layer; a second transparent conductive layer on the first organic layer and connected to the first transparent conductive layer; the first contact hole is covered with the first transparent conductive layer; A display device, wherein a portion of an end of the first transparent conductive layer is disposed inside the second opening.

2. The display device according to claim 1 , wherein the first organic layer is provided inside the first contact hole.

3. The display device of claim 1 , wherein the first organic layer includes a color filter.

4. The display device according to claim 1 , wherein the second transparent conductive layer is in contact with the first insulating layer inside the second opening.

5. The display device according to claim 4 , wherein the first insulating layer has a thickness smaller in a region in contact with the second transparent conductive layer than in a region in contact with the first transparent conductive layer.

6. The display device according to claim 1 , wherein a part of an end portion of the first transparent conductive layer provided inside the second opening overlaps with the gate line.

7. a first conductive layer disposed on the second transparent conductive layer; The display device according to claim 1 , further comprising: a third transparent conductive layer provided in contact with the first conductive layer.

8. The display device according to claim 7 , wherein a part of an end portion of the first transparent conductive layer provided inside the second opening overlaps with the first conductive layer and the third transparent conductive layer in a plan view.

9. a second organic layer provided inside the second opening; a spacer provided on and in contact with the second organic layer, The display device according to claim 1 , wherein a part of an end portion of the first transparent conductive layer provided inside the second opening overlaps with the spacer in a plan view.

10. The display device according to claim 1 , wherein a part of an end of the first transparent conductive layer is disposed inside the first opening.

11. The display device according to claim 1 , wherein the first insulating layer includes a first inorganic insulating layer and a second inorganic insulating layer provided on the first inorganic insulating layer.

12. 12. The display device according to claim 11, further comprising a second conductive layer on the first inorganic insulating layer, the second conductive layer being connected to the oxide semiconductor layer via a second contact hole provided in the first inorganic insulating layer and the gate insulating layer.

13. a second conductive layer provided on the first transparent conductive layer and the second insulating layer so as to cover the second opening, The display device according to claim 1 , wherein the second transparent conductive layer is connected to the first transparent conductive layer via the second conductive layer.

14. The display device according to claim 1 , wherein the second transparent conductive layer covers a part of an edge of the first opening and is in contact with the first transparent conductive layer.

15. an edge of the first opening is provided on the first transparent conductive layer; The display device according to claim 1 , wherein an edge of the second opening is provided on the first transparent conductive layer and on the second insulating layer.

16. The plurality of pixels include a first pixel and a second pixel adjacent to the first pixel in a first direction, 2. The display device according to claim 1, wherein the distance between the first transparent conductive layer of the first pixel and the first transparent conductive layer of the second pixel is the same as the length in the first direction of the first contact hole provided in the first pixel.

Images