Fan-out wafer level packaging unit

Abstract

To provide a fan-out type wafer level packaging unit which effectively solves the problem that a conventional fan-out type package technology has a high manufacturing cost and tends to be disadvantageous to environmental protection when each conductive wire is manufactured.SOLUTION: A fan-out type wafer level packaging unit, comprising a carrier, at least one die, a first dielectric layer, a second dielectric layer, a plurality of first conductive wires, a third dielectric layer, a fourth dielectric layer, and an outer protective layer, wherein each of the first conductive wires is formed on a second surface of each of the dies by filling a metal paste into a groove and then polishing and shaping the conductive wire; Each of the second conductive lines is formed on the second dielectric layer and the plurality of first conductive lines by a technique of filling a metal paste into a groove first and then polishing and shaping the conductive line, and each of the dies can be electrically connected to the outside through each of the soldering pads around the chip area of the second surface.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a chip packaging unit, and more particularly to a fan-out type wafer level packaging unit. [Background technology]

[0002] Packaging technology that is light, thin, short, small, efficient, and reliable is a trend in the development of the semiconductor industry, and among them, fan-out wafer level packaging (FOWLP) is a conventional packaging technology.

[0003] In advanced FOWLP packaging, the redistribution layer (RDL) is the most important element. Each conductive line in the RDL provides electrical extension and interconnection in the XY plane to multiple pads on the die, resulting in multiple, more dispersed pads around each die, effectively improving the design space and reliability of each conductive line. However, the most important factor in fabricating each conductive line in the RDL is how to achieve a certain degree of lightness, thinness, and compactness while providing electrical extension and interconnection in the XY plane. However, in conventional FOWLP packaging, conductive lines are formed using chemical plating or electroplating techniques. This results in relatively high material and production costs, and the conventional processes are unsuitable for environmental protection.

[0004] In addition, when using FOWLP to meet the circuit layout requirements of various applications, two or more redistribution layers are usually installed on the FOWLP and integrated through the RDL to form a multi-die type FOWLP unit. At this time, the design space requirements for each conductive line of the RDL of the FOWLP relatively increase, and the manufacturing technology for each conductive line of the RDL also becomes relatively more important. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Special Publication No. 2023-551401 Summary of the Invention [Problem to be solved by the invention]

[0006] The objective of the present invention is to provide a fan-out wafer-level packaging unit (FOWLP) unit, which includes a carrier, at least one die, a first dielectric layer, a second dielectric layer, a plurality of first conductive lines, a third dielectric layer, a fourth dielectric layer, and an outer protective layer, wherein each of the first conductive lines is formed on a second surface of each of the dies by a technique of first filling a groove with a metal paste and then polishing and shaping the conductive line, and each of the second conductive lines is formed on the second dielectric layer and the plurality of first conductive lines by a technique of first filling a groove with a metal paste and then polishing and shaping the conductive line, and each of the dies can be electrically connected to the outside through respective welding pads around a chip area on the second surface, thereby effectively solving the problems of conventional fan-out packaging technology, which have high manufacturing costs and are prone to being unfriendly to environmental protection when fabricating each conductive line. [Means for solving the problem]

[0007] In order to achieve the above object, the present invention provides a FOWLP unit, the FOWLP unit including: a carrier; at least one die; a first dielectric layer; a second dielectric layer; a plurality of first conductive lines; a third dielectric layer; a fourth dielectric layer; a plurality of second conductive lines; at least two first welding pads; at least one first bonding wire; and an outer protective layer, wherein each of the dies is separated from a wafer and is mounted on the carrier, and has a first surface and an opposing second surface, the first surface of each of the dies is fixed on the carrier, and the second surface of each of the dies is fixed on the carrier. a surface having a plurality of pads, a vertical extent of the chip on the second surface being defined as a chip area; a first dielectric layer being disposed on the carrier and the second surface of each of the dies, the first dielectric layer having a plurality of first grooves extending horizontally, the pads of each of the dies being exposed to the outside by each of the first grooves; a second dielectric layer being disposed on the first dielectric layer, the second dielectric layer having a plurality of second grooves extending horizontally, each of the second grooves being connected to each of the first grooves; and each of the first conductive lines being filled in each of the first grooves and each of the second grooves. a third dielectric layer disposed on the second dielectric layer, the third dielectric layer having a plurality of third grooves extending horizontally, each of the third grooves communicating with a corresponding one of the second grooves; a fourth dielectric layer disposed on the third dielectric layer, the fourth dielectric layer having a plurality of fourth grooves extending horizontally, each of the fourth grooves communicating with a corresponding one of the third grooves; and each of the second conductive lines formed by the metal paste filled in each of the third grooves and each of the fourth grooves, and electrically connected to each of the first conductive lines. the outer protective layer is disposed on the fourth dielectric layer and has a plurality of openings, at least two of which are located around the chip area on the second surface of each of the dies, and each of the second conductive lines is exposed to the outside by each of the openings to form a welding pad in each of the openings, and each of the dies can be electrically connected to the outside through each of the pads, each of the first conductive lines, each of the second conductive lines, and each of the welding pads located around the chip area on the second surface of each of the dies in order to form the FOWLP unit, and a method for manufacturing the FOWLP unit includes:Step S1 of providing a carrier; Step S2 of arranging a plurality of dies separated from the same wafer or different wafers on the carrier at intervals, each of the dies having a first surface and a second surface opposite thereto, the first surface of each of the dies being placed on the carrier, the second surface of each of the dies having a plurality of pads, and a chip vertical extent of the second surface being defined as a chip area; Step S3 of forming a plurality of first conductive lines on the second surface of each of the dies by a technique of polishing and shaping conductive lines, after first filling a metal paste into a groove; a first dielectric layer is disposed on the second surface of each of the dies, and a plurality of first grooves are formed on the first dielectric layer so as to extend horizontally, and each pad of each of the dies can be exposed to the outside from each of the first grooves; a second dielectric layer is disposed on the first dielectric layer, and a plurality of second grooves are formed on the second dielectric layer so as to extend horizontally, and each of the second grooves can communicate with each of the first grooves; thereafter, a metal paste is filled into each of the first grooves and each of the second grooves, and the thickness of the metal paste is made higher than the surface of the second dielectric layer; and finally, the metal paste is polished to a thickness higher than the surface of the second dielectric layer. and a step S3 of forming a plurality of first conductive lines by flushing the surface of the metal paste with the surface of the second dielectric layer, and a step of forming a plurality of second conductive lines on the second dielectric layer and the plurality of first conductive lines by a technique of polishing and shaping a conductive line after first filling a groove with the metal paste, wherein a third dielectric layer is first disposed on the second dielectric layer, and a plurality of third grooves are formed on the third dielectric layer extending horizontally so that each of the third grooves can communicate with each of the second grooves, and then a fourth dielectric layer is disposed on the third dielectric layer, and a plurality of third grooves are formed on the fourth dielectric layer extending horizontally so that each of the third grooves can communicate with each of the second grooves. forming fourth grooves, each of which can communicate with each of the third grooves; then filling each of the third grooves and each of the fourth grooves with a metal paste, making the thickness of the metal paste higher than the surface of the fourth dielectric layer; finally polishing the metal paste higher than the surface of the fourth dielectric layer to make the surface of the metal paste flush with the surface of the fourth dielectric layer, thereby forming a plurality of second conductive lines, each of which is electrically connected to a corresponding one of the first conductive lines; and step S5 of arranging an outer protective layer on the fourth dielectric layer; and forming a plurality of openings in the outer protective layer.The method includes a step S6 of forming at least one opening around the chip region on the second surface of each of the dies, allowing each of the conductive lines to be exposed to the outside through each of the openings, and forming a welding pad in each of the openings; and a step S7 of performing a division process to form a plurality of FOWLP units by division, with one package having at least one of the dies as one unit.

[0008] In one preferred embodiment of the present invention, the FOWLP unit further includes at least two of the dies, and step S7 further performs a dividing operation to divide one package unit having at least two of the dies into one unit to form a plurality of FOWLP units.

[0009] In a preferred embodiment of the present invention, the carrier comprises a silicon carrier, a glass carrier, or a ceramic carrier.

[0010] In a preferred embodiment of the present invention, the metal paste constituting each of the first conductive wires and each of the second conductive wires includes silver paste, nanosilver paste, copper paste, or nanocopper paste.

[0011] In a preferred embodiment of the present invention, the first surface of each of the dies is further disposed on the carrier using a die attach film (DAF).

[0012] In one preferred embodiment of the present invention, each of the openings is further provided with a solder ball, each of the solder balls being electrically connectable to each of the welding pads in each of the openings, and the fan-out type wafer-level packaging unit is installed so as to be electrically connectable to a printed circuit board (PCB) using each of the solder balls. [Effects of the Invention]

[0013] The FOWLP unit 1 of the present invention has the following advantages over conventional FOWLP units. (1) Steps S3 to S4 in the manufacturing method of the FOWLP unit 1 of the present invention are all simplified and easy to perform precisely, which is particularly advantageous for reducing the thickness of the packaging unit. Therefore, the process of the present invention is simplified and can not only save costs, but also effectively improve the use efficiency and reliability of the FOWLP unit 1. (2) The plurality of first conductive wires 50 and the plurality of second conductive wires 80 of the present invention are both manufactured by first filling a metal paste into a groove, and then polishing and shaping the conductive wires. Therefore, the present invention can effectively solve the problems that the conventional fan-out packaging technology tends to increase the manufacturing cost when manufacturing each conductive wire and is unfriendly to the environment. (3) In the present invention, each die 20 is electrically connected to the outside via each pad 23, each first conductive line 50, each second conductive line 80, and each welding pad 81 located around the chip area 1a on the second surface 22 of each die 20, in that order. That is, each conductive line in the RDL generates the effect of electrical expansion and interconnection in the XY plane, and at the same time, the multi-die type FOWLP unit can achieve a certain degree of light, thin, short and small integration effect. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a cross-sectional side view of an embodiment of a FOWLP unit of the present invention mounted on a printed circuit board. [Figure 2] FIG. 1 is a side cross-sectional view of a die of the present invention mounted on a carrier. [Figure 3] FIG. 10 is a cross-sectional side view of the first dielectric layer of the present invention disposed on the carrier and the second surface of the die. [Figure 4] FIG. 2 is a cross-sectional side view of a second dielectric layer of the present invention disposed on a first dielectric layer. [Figure 5] FIG. 2 is a side cross-sectional view of the first and second grooves of the present invention filled with metal paste. [Figure 6] 6 is a side cross-sectional view of polishing the metal paste higher than the surface of the second dielectric layer of FIG. 5. [Figure 7] FIG. 2 is a cross-sectional side view of a third dielectric layer of the present invention disposed on a second dielectric layer. [Figure 8] FIG. 10 is a cross-sectional side view of the fourth dielectric layer of the present invention disposed on the third dielectric layer. [Figure 9] FIG. 2 is a side cross-sectional view of the first and second grooves of the present invention filled with metal paste. [Figure 10] 10 is a side cross-sectional view of polishing the metal paste higher than the surface of the fourth dielectric layer of FIG. 9. [Figure 11] FIG. 1 is a side cross-sectional view of an outer protective layer of the present invention having a plurality of apertures molded therein. [Figure 12] FIG. 10 is a side cross-sectional view of one embodiment of the FOWLP unit of the present invention provided with solder balls. [Figure 13] FIG. 10 is a side cross-sectional view of another embodiment of the FOWLP unit of the present invention provided with solder balls. [Figure 14] FIG. 1 is a side cross-sectional view of a FOWLP unit of the present invention mounted on a printed circuit board. DETAILED DESCRIPTION OF THE INVENTION

[0015] Referring to Figures 1 and 14, the present invention provides a fan-out wafer-level packaging unit (FOWLP) unit 1, which includes a carrier 10, at least one die 20, a first dielectric layer 30, a second dielectric layer 40, a plurality of first conductive lines 50, a third dielectric layer 60, a fourth dielectric layer 70, a plurality of second conductive lines 80, and an outer protective layer 90.

[0016] Each die 20 is separated from a wafer and placed on the carrier 10, each die 20 having a first surface 21 and an opposing second surface 22, each first surface 21 being fixed on the carrier 10, each second surface 22 having a plurality of pads 23, and the range of the second surface 22 in the chip vertical direction is defined as a chip area 1a as shown in Fig. 2. In Fig. 2, each of the pads 23 on each die 20 is described as two pads 23 as an example, but this does not limit the present invention.

[0017] The first dielectric layer 30 is disposed on the carrier 10 and the second surface 22 of each of the dies 20, and has a plurality of first grooves 31 formed to extend horizontally, as shown in Fig. 3. Each of the pads 23 of each of the dies 20 is exposed to the outside through each of the first grooves 31.

[0018] The second dielectric layer 40 is disposed on the first dielectric layer 30 and has a plurality of second grooves 41 extending horizontally, each of which is connected to each of the first grooves 31 as shown in FIG. 4.

[0019] Each of the first conductive lines 50 is formed by a metal paste 50a filled in each of the first grooves 31 and each of the second grooves 41. Each of the first conductive lines 50 is electrically connected to each of the pads 23 of each of the dies 20, as shown in FIG.

[0020] The third dielectric layer 60 is disposed on the second dielectric layer 40 and has a plurality of third grooves 61 extending horizontally, each of which is connected to each of the second grooves 41 as shown in FIG. 7.

[0021] The fourth dielectric layer 70 is disposed on the third dielectric layer 60 and has a plurality of fourth grooves 71 extending horizontally, each of which is connected to each of the third grooves 61 as shown in FIG. 8.

[0022] Each of the second conductive lines 80 is formed by a metal paste 80a filled in each of the third grooves 61 and each of the fourth grooves 71, and is electrically connected to each of the first conductive lines 50, as shown in FIG.

[0023] The outer protective layer 90 is disposed on the fourth dielectric layer 70 and has a plurality of openings 91, at least two of which are disposed around the chip region 1a on the second surface 22 of each die 20, as shown in FIG. 11. Each of the second conductive lines 80 is exposed to the outside through each of the openings 91, and a welding pad 81 is formed within each of the openings 91 (see FIGS. 11 and 13). In FIG. 11, eight openings 91 are illustrated in the outer protective layer 90, but this is not intended to limit the present invention.

[0024] Each die 20 is electrically connected to the outside via each pad 23, each first conductive wire 50, each second conductive wire 80, and each welding pad 81 located around the chip area 1a on the second surface 22 of each die 20, thereby forming the FOWLP unit 1 (see Figures 11 and 13).

[0025] The manufacturing method of the fan-out type wafer level packaging unit 1 includes the following steps. Step S1: Provide a carrier 10 as shown in FIG. Step S2: As shown in Fig. 2, a plurality of dies 20 separated from the same wafer or different wafers are arranged at intervals on the carrier 10. Each of the dies 20 has a first surface 21 and an opposing second surface 22, the first surface 21 of each of the dies 20 is arranged on the carrier 10, the second surface 22 of each of the dies 20 has a plurality of pads 23, and the range of the second surface 22 in the chip vertical direction is defined as a chip area 1a (see Fig. 2). Step S3: First, a step of forming a plurality of first conductive wires 50 on the second surface 22 of each die 20 by a technique of polishing and shaping conductive wires after filling the grooves with metal paste, in which a first dielectric layer 30 is disposed on the carrier 10 and the second surface 22 of each die 20, and a plurality of first grooves 31 are formed on the first dielectric layer 30 extending horizontally, so that each pad 23 of each die 20 can be exposed to the outside through each first groove 31 (see FIG. 3 ), and then a second dielectric layer 40 is disposed on the first dielectric layer 30, and a plurality of first grooves 31 are formed on the second surface 22 of each die 20 by polishing and shaping conductive wires. A plurality of second grooves 41 are formed on the layer 40 extending horizontally, and each of the second grooves 41 can be connected to a corresponding one of the first grooves 31 (see FIG. 4). Then, each of the first grooves 31 and each of the second grooves 41 is filled with a metal paste 50a, and the thickness of the metal paste 50a is made higher than the surface of the second dielectric layer 40 (see FIG. 5). Finally, the metal paste 50a that is higher than the surface of the second dielectric layer 40 is polished to make the surface of the metal paste 50a flush with the surface of the second dielectric layer 40, thereby forming a plurality of first conductive lines 50 (see FIG. 6). Step S4: First, a metal paste is filled into the grooves, and then a plurality of second conductive wires 80 are formed on the second dielectric layer 40 and the plurality of first conductive wires 50 by a conductive wire polishing and shaping technique. First, a third dielectric layer 60 is disposed on the second dielectric layer 40, and a plurality of third grooves 61 are formed on the third dielectric layer 60 so as to extend horizontally, and each of the third grooves 61 is allowed to communicate with each of the second grooves 41 (see FIG. 7 ). Next, a fourth dielectric layer 70 is disposed on the third dielectric layer 60, and a plurality of fourth grooves 71 are formed on the fourth dielectric layer 70 so as to extend horizontally, and each of the fourth grooves 71 is allowed to communicate with each of the second grooves 41 (see FIG. 7 ). The fourth grooves 71 can be connected to each of the third grooves 61 (see Figure 8). Then, each of the third grooves 61 and each of the fourth grooves 71 is filled with metal paste 80a, and the thickness of the metal paste 80a is made higher than the surface of the fourth dielectric layer 70 (see Figure 9). Finally, the metal paste 80a, which is higher than the surface of the fourth dielectric layer 70, is polished to make the surface of the metal paste 80a flush with the surface of the fourth dielectric layer 70, thereby forming a plurality of second conductive wires 80 (see Figure 10). Each of the second conductive wires 80 is electrically connected to each of the first conductive wires 50 (see Figure 10). Step S5: As shown in FIG. 11, an outer protective layer 90 is disposed on the fourth dielectric layer 70. Step S6: Form a plurality of openings 91 in the outer protective layer 90, at least one of which is formed around the chip area 1a on the second surface 22 of each of the dies 20, and expose each second conductive wire 80 to the outside through each opening 91 to form a welding pad 81 in each opening 91, as shown in FIG. 11. Step S7: As shown in FIG. 13, a division process is performed to divide one package unit having at least one die 20 into a single unit, thereby forming a plurality of FOWLP units 1.

[0026] The process of steps S3 to S4 can be regarded as a key step for fabricating the redistribution layer (RDL) of the FOWLP unit 1. Steps S3 to S4 are all easy to perform precisely, making the process relatively simple. While generating the electrical expansion and interconnection effects of the first conductive lines 50 and the second conductive lines 80 of the redistribution layer in the XY plane, at the same time, achieving a certain degree of the concrete effect of light, thin, short, and compact. When the FOWLP unit 1 has at least two dies 20, the effect of light, thin, short, and compact can still be achieved to a certain degree.

[0027] Referring to FIG. 2, the carrier 10 includes a silicon carrier, a glass carrier, or a ceramic carrier, which facilitates the development and application of various products.

[0028] 6, the metal paste 50a constituting each of the first conductive wires 50 and each of the second conductive wires 80 may be, but is not limited to, silver paste, nano silver paste, copper paste, nano copper paste, etc. The nano silver paste material has properties such as low cost, high conductivity, and low-temperature sintering ability.

[0029] Referring to FIG. 2, the first surface 11 of each of the dies 20 is attached to the carrier 10 using a die attach film (DAF) 100 .

[0030] 12 and 13, each of the openings 91 is further provided with a solder ball 110, and each of the solder balls 110 can be electrically connected to each of the welding pads 81 in each of the openings 91. Referring to FIGS. 1 and 14, the FOWLP unit 1 is installed on a printed circuit board (PCB) 2 using each of the solder balls 110 so as to be electrically connectable thereto.

[0031] In a preferred embodiment of the present invention, the FOWLP unit 1 further includes at least two dies 20, as shown in FIGS. 1 to 11 . The at least two dies 20 are separated from the same wafer or different wafers, and are arranged parallel to and spaced apart on the carrier 10. Each die 20 has a first surface 21 and an opposing second surface 22. The first surface 21 of each die 20 is fixed on the carrier 10, and the second surface 22 of each die 20 has a plurality of pads 23. The area of ​​the second surface 22 in the chip vertical direction is defined as a chip area 1a, as shown in FIG. 11 . Here, if the dies 20 are separated from the same wafer, the dies 20 have the same specifications, performance, or intended functions. Here, if the dies 20 are separated from different wafers, the dies 20 may have different specifications, performance, or intended functions, which is advantageous for expanding the variety of product applications. Furthermore, when the FOWLP unit 1 further includes at least two of the dies 20, the manufacturing method of the FOWLP unit 1 includes the above-mentioned steps S1 to S6, and only step S7 performs a dividing operation, and as shown in Figure 11, one package unit having at least two of the dies 20 is divided as a single unit to form multiple FOWLP units 1.

[0032] The FOWLP unit 1 of the present invention has the following advantages over conventional FOWLP units. (1) Steps S3 to S4 in the manufacturing method of the FOWLP unit 1 of the present invention are all simplified and easy to perform precisely, which is particularly advantageous for reducing the thickness of the packaging unit. Therefore, the process of the present invention is simplified and can not only save costs, but also effectively improve the use efficiency and reliability of the FOWLP unit 1. (2) The plurality of first conductive wires 50 and the plurality of second conductive wires 80 of the present invention are both manufactured by first filling a metal paste into a groove, and then polishing and shaping the conductive wires. Therefore, the present invention can effectively solve the problems that the conventional fan-out packaging technology tends to increase the manufacturing cost when manufacturing each conductive wire and is unfriendly to the environment. (3) In the present invention, each die 20 is electrically connected to the outside via each pad 23, each first conductive line 50, each second conductive line 80, and each welding pad 81 located around the chip area 1a on the second surface 22 of each die 20, in that order. That is, each conductive line in the RDL generates the effect of electrical expansion and interconnection in the XY plane, and at the same time, the multi-die type FOWLP unit can achieve a certain degree of light, thin, short and small integration effect. [Explanation of symbols]

[0033] 1 Fan-out type wafer level packaging unit 1a Chip area 10. Career 20 Die 21 Page 1 22 Side 2 23 Pad 30 First dielectric layer 31 First groove 40 Second dielectric layer 41 Second groove 50 First conductive wire 50a Metal Paste 60 Third dielectric layer 61 Third groove 70 Fourth dielectric layer 71 4th groove 80 Second conductive wire 80a Metal Paste 81 Welding Pad 90 Outer protective layer 91 Aperture 100 Die Attach Film 110 solder balls 2. Printed Circuit Board

Claims

1. 1. A fan-out wafer level packaging (FOWLP) unit, comprising: a carrier, at least one die, a first dielectric layer, a second dielectric layer, a plurality of first conductive lines, a third dielectric layer, a fourth dielectric layer, a plurality of second conductive lines, at least two first weld pads, at least one first bonding wire, and an outer protective layer; each die is separated from a wafer and mounted on the carrier, and has a first surface and an opposing second surface, the first surface of each die is fixed on the carrier, the second surface of each die has a plurality of pads, and a vertical extent of a chip on the second surface is defined as a chip area; the first dielectric layer is disposed on the carrier and the second surface of each of the dies, the first dielectric layer has a plurality of first grooves extending horizontally, and the pads of each of the dies are exposed to the outside by each of the first grooves; the second dielectric layer is disposed on the first dielectric layer, and the second dielectric layer has a plurality of second grooves formed extending in a horizontal direction, each of the second grooves communicating with each of the first grooves; Each of the first conductive lines is formed by a metal paste filled in each of the first grooves and each of the second grooves, and is electrically connected to the pad of each of the dies; the third dielectric layer is disposed on the second dielectric layer, and the third dielectric layer has a plurality of third grooves formed extending in a horizontal direction, each of the third grooves communicating with each of the second grooves; the fourth dielectric layer is disposed on the third dielectric layer, and the fourth dielectric layer has a plurality of fourth grooves extending in a horizontal direction, each of the fourth grooves communicating with each of the third grooves; each of the second conductive lines is formed by a metal paste filled in each of the third grooves and each of the fourth grooves, and is electrically connected to each of the first conductive lines; the outer protective layer is disposed on the fourth dielectric layer and has a plurality of openings, at least two of the openings being located around the chip area on the second surface of each of the dies, and each of the second conductive lines is exposed to the outside by each of the openings to form a welding pad within each of the openings; each die can be electrically connected to the outside via each pad, each first conductive line, each second conductive line, and each welding pad located around the chip area on the second surface of each die, forming the FOWLP unit; The method for manufacturing the FOWLP unit includes: Step S1: providing a carrier; Step S2: arranging a plurality of dies separated from the same wafer or different wafers on the carrier at intervals, each die having a first surface and an opposing second surface, the first surface of each die being disposed on the carrier, the second surface of each die having a plurality of pads, and a chip area in the vertical direction of the second surface being defined as a chip area; a step S3 of first filling grooves with metal paste, and then forming a plurality of first conductive lines on the second surface of each die by a technique of polishing and shaping conductive lines, the step S3 comprising: first disposing a first dielectric layer on the carrier and the second surface of each die, forming a plurality of first grooves on the first dielectric layer extending horizontally, and allowing each pad of each die to be exposed to the outside through each of the first grooves; next disposing a second dielectric layer on the first dielectric layer, and forming a plurality of second grooves on the second dielectric layer extending horizontally, each of the second grooves being capable of communicating with each of the first grooves; then filling each of the first grooves and each of the second grooves with metal paste, making the thickness of the metal paste higher than the surface of the second dielectric layer; and finally polishing the metal paste higher than the surface of the second dielectric layer to make the surface of the metal paste flush with the surface of the second dielectric layer, thereby forming a plurality of first conductive lines; a step S4 of forming a plurality of second conductive lines on the second dielectric layer and the plurality of first conductive lines by a technique of polishing and shaping conductive lines after first filling the grooves with metal paste, in which a third dielectric layer is disposed on the second dielectric layer, and a plurality of third grooves are formed on the third dielectric layer extending horizontally, so that each of the third grooves can communicate with each of the second grooves; a fourth dielectric layer is disposed on the third dielectric layer, and a plurality of fourth grooves are formed on the fourth dielectric layer extending horizontally, so that each of the fourth grooves can communicate with each of the third grooves; thereafter, a metal paste is filled into each of the third grooves and each of the fourth grooves, so that the thickness of the metal paste is higher than the surface of the fourth dielectric layer; and finally, the metal paste higher than the surface of the fourth dielectric layer is polished to make the surface of the metal paste flush with the surface of the fourth dielectric layer, so that a plurality of second conductive lines are formed, and each of the second conductive lines is electrically connected to each of the first conductive lines; Step S5 of disposing an outer protective layer on the fourth dielectric layer; Step S6: forming a plurality of openings in the outer protective layer, forming at least one opening around the chip area on the second surface of each of the dies, allowing each of the conductive lines to be exposed to the outside through each of the openings, and forming a welding pad within each of the openings; Step S7: performing a division process to divide a package having at least one die into a plurality of FOWLP units; FOWLP units, including:

2. The FOWLP unit of claim 1 , wherein the carrier comprises a silicon carrier, a glass carrier, or a ceramic carrier.

3. The FOWLP unit according to claim 1 , wherein the metal paste constituting each of the first conductive lines and each of the second conductive lines includes silver paste, nano-silver paste, copper paste, or nano-copper paste.

4. The FOWLP unit of claim 1 , wherein the first surface of each die is further disposed on the carrier using a die attach film.

5. 2. The FOWLP unit of claim 1, wherein each of the openings further includes a solder ball, each of the solder balls being electrically connectable to each of the welding pads in each of the openings, and the fan-out wafer level packaging unit is installed so as to be electrically connectable to a printed circuit board using each of the solder balls.

6. 2. The FOWLP unit according to claim 1, wherein the FOWLP unit further includes at least two of the dies, and step S7 further performs a division operation to divide one package unit having at least two of the dies into one unit to form a plurality of FOWLP units.

7. The FOWLP unit according to claim 6 , wherein at least two of the dies are formed separately from the same wafer or different wafers.

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