Liquid crystal display device and method for driving liquid crystal display device

Abstract

To provide a liquid crystal display device capable of performing a stable operation and reducing the circuit scale of a pixel circuit.SOLUTION: Each pixel 16 includes a first DRAM including a first switch and a first signal holding unit, and a second DRAM including a second switch and a second signal holding unit. The second DRAM is connected to the pixel electrode. The voltage selection circuit 144 selects the first voltage and the second voltage as the sub-frame voltage according to the value of one bit of the sub-frame and outputs the selected voltage to the column-data lines d1 to dn. The first voltage or the second voltage is written to the first signal holding unit via the first switch of the pixel 16 connected to the row scanning line selected by the vertical shift register 13. The second signal holding unit holds the first voltage or the second voltage written in the first signal holding unit in response to the input of the trigger pulse to the second switch.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a liquid crystal display device and a method for driving a liquid crystal display device. [Background technology]

[0002] Patent Document 1 describes a digitally driven liquid crystal display device having a pixel circuit including one static random access memory (SRAM) and one dynamic random access memory (DRAM). Patent Document 2 describes an analogue-driven liquid crystal display device having a pixel circuit including two DRAMs. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-92714 [Patent Document 2] Japanese Patent Application Laid-Open No. 2016-177034 Summary of the Invention [Problem to be solved by the invention]

[0004] The liquid crystal display device described in Patent Document 1 includes an SRAM, which results in a large pixel circuit size. The liquid crystal display device described in Patent Document 2 is an analog drive type, which means that its operation is prone to become unstable due to the effects of external noise or leakage current within the pixel circuit. Furthermore, analog voltage data must be retained for one frame period, which results in a large pixel circuit size even without an SRAM.

[0005] An object of the present invention is to provide a liquid crystal display device and a method for driving a liquid crystal display device that are capable of stable operation and that can reduce the circuit scale of pixel circuits. [Means for solving the problem]

[0006] The present invention provides a liquid crystal display device comprising: an image display section in which pixels are provided at each intersection of a plurality of column data lines and a plurality of row scanning lines; each frame of a video signal to be displayed on the image display section is divided into a plurality of sub-frames, each sub-frame being composed of sub-frame data with one bit of pixel data; a horizontal driver that supplies sub-frame voltage data corresponding to each line of the sub-frame data to the plurality of column data lines one line at a time in parallel; and a vertical shift register that selects a row scanning line from the plurality of row scanning lines corresponding to each line, in order to write the sub-frame voltage data corresponding to each line output from the horizontal driver into the pixels of each line of the image display section.

[0007] In the above liquid crystal display device, the pixel has a liquid crystal layer provided between a common electrode common to all pixels and a pixel electrode for each pixel, a first dynamic random access memory including a first switch connected to the column data line and a first signal holding unit connected to the first switch, and a second dynamic random access memory including a second switch and a second signal holding unit connected to the second switch, connected in series with the first dynamic random access memory, and connected to the pixel electrode.

[0008] In the above liquid crystal display device, the horizontal driver has a voltage selection circuit that selects a first voltage or a second voltage as the subframe voltage data according to the value of one bit of the subframe data and outputs the selected voltage to the plurality of column data lines, thereby writing the first voltage or the second voltage to the first signal holding unit via the first switch.

[0009] The liquid crystal display device further includes a voltage control circuit that switches between a set of a first voltage corresponding to a first mode, in which the first voltage is voltage 0, and a second voltage corresponding to a difference voltage between a saturation voltage for displaying white and a threshold voltage for displaying black in a display gray scale, and a set of a first voltage corresponding to a second mode, in which the difference voltage is the first voltage and voltage 0 is the second voltage, for each subframe, and supplies the voltage to the voltage selection circuit.In the liquid crystal display device configured as described above, the second signal holding unit holds the first voltage or the second voltage written to the first signal holding unit in response to input of a trigger pulse to the second switch.

[0010] The present invention provides a method for driving a liquid crystal display device in which pixels provided at each intersection of a plurality of column data lines and a plurality of row scanning lines in an image display section have a liquid crystal layer provided between a common electrode common to all pixels and a pixel electrode for each of the pixels, a first dynamic random access memory including a first switch connected to the column data line and a first signal holding unit connected to the first switch, and a second dynamic random access memory including a second switch and a second signal holding unit connected to the second switch, connected in series with the first dynamic random access memory, and connected to the pixel electrode.

[0011] In the above-described method for driving a liquid crystal display device, each frame of a video signal to be displayed on the image display unit is divided into a plurality of subframes, subframe voltage data corresponding to each line of subframe data, each of which has 1 bit of pixel data, is supplied line by line to the plurality of column data lines in parallel, and a row scanning line corresponding to each line is selected from the plurality of row scanning lines to write the subframe voltage data corresponding to each line to the pixels of each line of the image display unit.

[0012] In the above-mentioned method for driving a liquid crystal display device, a voltage selection circuit selects a first voltage or a second voltage as the subframe voltage data in accordance with a value of one bit of the subframe data and outputs the selected voltage to the plurality of column data lines, thereby writing the first voltage or the second voltage to the first signal holding unit via the first switch.In the above-mentioned method for driving a liquid crystal display device, a voltage control circuit switches between, for each subframe, a set of the first voltage (voltage 0) and the second voltage (a difference voltage between a saturation voltage for displaying white and a threshold voltage for displaying black in a display gray scale) corresponding to a first mode, and a set of the first voltage (voltage 0) and the second voltage (a difference voltage) corresponding to a second mode.

[0013] In the above-described method for driving a liquid crystal display device, the second signal holding unit holds the first voltage or the second voltage written to the first signal holding unit in response to input of a trigger pulse to the second switch, thereby applying the first voltage or the second voltage to the pixel electrode. [Effects of the Invention]

[0014] According to the liquid crystal display device and the method for driving the liquid crystal display device of the present invention, stable operation is possible and the circuit scale of the pixel circuit can be reduced. [Brief explanation of the drawings]

[0015] [Figure 1] FIG. 1 is a block diagram showing a liquid crystal display device according to an embodiment. [Figure 2] FIG. 2 is a block diagram showing a specific example of the configuration of the subframe data conversion device 10 of FIG. [Figure 3] FIG. 3 is a diagram showing an example of the subframe gradation table held in the subframe gradation table holding unit 103 of FIG. [Figure 4] FIG. 4 is a conceptual diagram showing an example in which one frame of a video signal is converted into 15 subframes. [Figure 5] FIG. 5 is a diagram showing a specific configuration of a pixel included in a liquid crystal display device according to an embodiment. [Figure 6] FIG. 6 is a characteristic diagram showing the relationship between the liquid crystal applied voltage applied to the liquid crystal layer of a pixel and the display gray scale. [Figure 7] FIG. 7 is a diagram for explaining how the voltages V0 and V1 supplied to the voltage selection circuit 144 in FIG. 1 and the common electrode voltage Vcom supplied to the common electrode 18 are determined. [Figure 8] FIG. 8 is a timing chart showing the operation of the liquid crystal display device according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0016] A liquid crystal display device and a method for driving a liquid crystal display device according to an embodiment will now be described with reference to the accompanying drawings. As shown in Fig. 1, a liquid crystal display device 100 according to an embodiment includes a subframe data converter 10, a timing generator 11, a data latch circuit 12, a vertical shift register 13, a horizontal driver 14, an image display unit 15, a voltage control circuit 17, and a common electrode 18. The subframe data converter 10 may be external to the liquid crystal display device 100. The liquid crystal display device 100 is a digitally driven liquid crystal display device.

[0017] The horizontal driver 14 includes a horizontal shift register 141, a latch circuit 142, a level shifter 143, and a voltage selection circuit 144. The image display unit 15 includes (n×m) pixels 16 arranged in a two-dimensional matrix, where n and m are natural numbers of 2 or greater. Each pixel 16 is provided at an intersection of n column data lines d1 to dn, each of which has one end connected to the voltage selection circuit 144 and extends in the column direction (Y direction), and m row scanning lines g1 to gm, each of which has one end connected to the vertical shift register 13 and extends in the row direction (X direction). Any column data line may be referred to as a column data line d, and any row scanning line may be referred to as a row scanning line g. There may be a plurality of column data lines d and a plurality of row scanning lines g.

[0018] In FIG. 1, the common electrode 18 is shown separated from the image display section 15, but as will be described later, the common electrode 18 is provided as a part of the pixel 16 and is common to all the pixels 16.

[0019] As shown in Fig. 2, subframe data conversion device 10 includes dither processing unit 101, subframe gradation conversion unit 102, subframe gradation table holding unit 103, data buffer 104, and subframe driver 105. A video signal to be displayed by liquid crystal display device 100 is input to subframe data conversion device 10. The video signal is assumed to have 256 8-bit gradations. Each frame input to subframe data conversion device 10 is n columns x m rows x 8 bits of data.

[0020] The dither processing unit 101 reduces the number of bits of an input 8-bit video signal to 4 bits. The dither processing unit 101 can reduce the number of bits by error diffusion, which diffuses information about each pixel data to surrounding pixels within a frame to reduce the number of gradations. The dither processing unit 101 can also reduce the number of bits by using frame rate control (FRC) technology, which diffuses information about each pixel data in the frame direction using a predetermined dither pattern.

[0021] 3 is stored in subframe gradation table storage unit 103. Subframe gradation conversion unit 102 converts the 4-bit video signal supplied from dither processing unit 101 into a 15-bit bit string in accordance with the subframe gradation table. For example, the 4-bit 0000 representing gradation 0 is converted to the 15-bit 0000000000000000, and the 4-bit 0100 representing gradation 4 is converted to the 15-bit 111100000000000.

[0022] The 15-bit bit string converted by the subframe tone converter 102 is supplied to a data buffer 104 and stored as subframe data for 15 subframes SF0 to SF14 shown in Fig. 4. Each subframe is made up of n columns x m rows x 1 bit of data. That is, each subframe is made up of subframe data in which each pixel data is 1 bit.

[0023] The subframe driver 105 transfers the subframe data to the data latch circuit 12 in Fig. 1 in the order of subframes SF0 to SF14. The subframe driver 105 supplies the vertical synchronization signal SFVS and horizontal synchronization signal SFHS of the subframe data and the basic clock CLK to the timing generator 11 in Fig. 1. The subframe driver 105 supplies the threshold voltage Vtt and saturation voltage Vsat for driving the image display unit 15 to the voltage control circuit 17 in Fig. 1.

[0024] 1, a timing generator 11 generates the following various internal signals based on the input basic clock CLK, vertical synchronization signal SFVS, and horizontal synchronization signal SFHS. The timing generator 11 generates a start pulse VST and a clock signal VCK for the vertical shift register 13 and supplies them to the vertical shift register 13. The timing generator 11 generates a start pulse HST and a clock signal HCK for the horizontal shift register 141 and supplies them to the horizontal shift register 141.

[0025] The timing generator 11 generates a latch pulse LT and supplies it to the latch circuit 142. The timing generator 11 generates a polarity inversion signal POL that inverts every subframe and supplies it to the voltage control circuit 17. The timing generator 11 generates a trigger pulse PTR and supplies the trigger pulse PTR to all pixels 16 via trigger lines TRI connected to each pixel 16.

[0026] In accordance with a clock signal VCK, the timing generator 11 transfers a start pulse VST indicating the start timing of each sub-frame to the vertical shift register 13. The vertical shift register 13 supplies row scanning signals to the row scanning lines g1 to gm in sequence, line by line, from the row scanning line g1, which is the top line, to the row scanning line gm, which is the bottom line. As a result, the row scanning lines g1 to gm in the image display unit 15 are selected in sequence, from the row scanning line g1 to the row scanning line gm, for each line of each sub-frame.

[0027] The data latch circuit 12 latches the subframe data supplied from the subframe data conversion device 10 in units of 32 bits (data D0 to D31) based on the basic clock CLK, and supplies the data to the horizontal shift register 141 in synchronization with the basic clock CLK. The horizontal shift register 141 starts shifting in the horizontal direction in response to a start pulse HST that indicates the start timing of one line from the timing generator 11, and shifts the 32-bit data in synchronization with the clock signal HCK. The horizontal shift register 141 shifts the data in units of 32 bits, thereby shifting one line's worth of data in the image display unit 15.

[0028] A latch pulse LT is supplied from the timing generator 11 to the latch circuit 142 when the horizontal shift register 141 has completed shifting one line's worth of data. The latch circuit 142 latches one line's worth of data in the horizontal shift register 141 in accordance with the input latch pulse LT and supplies the data to the level shifter 143. When the transfer of data from the horizontal shift register 141 to the latch circuit 142 is completed, a start pulse HST is supplied from the timing generator 11 to the horizontal shift register 141. This causes the horizontal shift register 141 to resume shifting data from the data latch circuit 12 in units of 32 bits, based on the basic clock CLK.

[0029] The level shifter 143 shifts the signal level of the input data for one line to the operating voltage of the subsequent voltage selection circuit 144. The level shifter 143 supplies the level-shifted data for one line to the voltage selection circuit 144. Note that if the signal level of the subframe data output from the latch circuit 142 is equal to or higher than the operating voltage of the voltage selection circuit 144, there is no need to provide the level shifter 143. Therefore, providing the level shifter 143 is not essential and may be provided as needed.

[0030] The voltage control circuit 17 generates a voltage V0 (first voltage) and a voltage V1 (second voltage) based on the threshold voltage Vtt and saturation voltage Vsat supplied from the subframe data conversion device 10 and the polarity inversion signal POL supplied from the timing generator 11, and supplies these to the voltage selection circuit 144. As will be described later, the voltages V0 and V1 have different values ​​depending on whether the polarity inversion signal POL is low (L) or high (H). The voltage control circuit 17 also generates a common electrode voltage Vcom (described later) and supplies it to the common electrode 18.

[0031] The voltage selection circuit 144 outputs n pieces of subframe voltage data corresponding to n pixels on one line in parallel to n column data lines d1 to dn based on the n pieces of subframe data level-shifted by the level shifter 143. If the subframe data is 0, the voltage selection circuit 144 outputs a voltage V0 as the subframe voltage data to the column data line d, and if the subframe data is 1, the voltage selection circuit 144 outputs a voltage V1 as the subframe voltage data to the column data line d.

[0032] The horizontal driver 14 comprises a horizontal shift register 141, a latch circuit 142, a level shifter 143, and a voltage selection circuit 144, which perform the above operations for each line, and the voltage selection circuit 144 outputs n pieces of subframe voltage data for each line in parallel to the column data lines d1 to dn all at once. The n pieces of subframe voltage data for one line supplied to the column data lines d1 to dn are written to n pixels 16 in a row selected by a row scanning signal supplied from the vertical shift register 13.

[0033] A specific circuit configuration of a pixel 16 will be described using FIG. 5. The pixel 16 includes a liquid crystal layer 20 sealed between a common electrode 18 and a pixel electrode 19. The common electrode 18 is a transparent electrode made of indium tin oxide (ITO). When the image display unit 15 is a reflective liquid crystal display element, the pixel electrode 19 is a reflective electrode provided for each pixel 16. Light from a light source (not shown) passes through the common electrode 18 and enters the liquid crystal layer 20, where it is modulated. The pixel electrode 19 reflects the light modulated by the liquid crystal layer 20. The light reflected by the pixel electrode 19 passes through the liquid crystal layer 20 and the common electrode 18, and is emitted from the common electrode 18.

[0034] A pixel circuit 22 formed on a silicon substrate 21 is connected to the pixel electrode 19. The pixel circuit 22 includes a first dynamic random access memory (first DRAM) 23 and a second dynamic random access memory (second DRAM) 24. The first DRAM 23 and the second DRAM 24 are connected in series. The first DRAM 23 includes a first switch 231 and a first signal holding unit 232 connected to the first switch 231. The second DRAM 24 includes a second switch 241 and a second signal holding unit 242 connected to the second switch 241. The first signal holding unit 232 and the second signal holding unit 242 are grounded.

[0035] The first switch 231 and the second switch 241 can be configured with field effect transistors (FETs). The first signal holding unit 232 and the second signal holding unit 242 can be configured with capacitors that function as holding capacitances. The gate of the first switch 231 is connected to the row scanning line g, the source is connected to the column data line d, and the drain is connected to the first signal holding unit 232 and the sources of the second switch 241. The gate of the second switch 241 is connected to the trigger line TRI, the source is connected to the drain of the first switch 231 and the first signal holding unit 232, and the drain is connected to the pixel electrode 19.

[0036] The subframe voltage data is written to the first signal holding unit 232 via the first switch 231. Immediately after the subframe voltage data is written to the first signal holding unit 232, a trigger pulse PTR is input to the second switch 241 via the trigger line TRI. In response to the input of the trigger pulse PTR to the second switch 241, the subframe voltage data written to the first signal holding unit 232 is transferred to the second signal holding unit 242. The second signal holding unit 242 holds the transferred subframe voltage data.

[0037] 6 shows the relationship between the liquid crystal applied voltage applied to the liquid crystal layer 20 and the displayed gray scale. If the voltage applied to the liquid crystal layer 20 is the threshold voltage Vtt, black is displayed on the image display section 15, and if the voltage applied to the liquid crystal layer 20 is the saturation voltage Vsat, white is displayed on the image display section 15.

[0038] 7, how the voltages V0 and V1 supplied to the voltage selection circuit 144 and the common electrode voltage Vcom supplied to the common electrode 18 are determined will be described. When the polarity inversion signal POL is L, the voltages V0 and V1 are voltages in the positive polarity mode (first mode), with voltage V0 being the ground voltage GND (i.e., voltage 0) and voltage V1 being voltage (Vsat-Vtt). As a result, positive polarity mode subframe voltage data is written to the first signal holding unit 232. In response to input of a trigger pulse PTR to the second switch 241, the positive polarity mode subframe voltage data written to the first signal holding unit 232 is transferred to and held by the second signal holding unit 242. The polarity inversion signal POL is also inverted in response to the trigger pulse PTR, so that when the polarity inversion signal POL is H, the common electrode voltage Vcom is voltage (-Vtt) in the positive polarity mode (first mode).

[0039] When the subframe voltage data is 0, a voltage (GND-(-Vtt)) = voltage Vtt is applied to the liquid crystal layer 20, which is obtained by subtracting the common electrode voltage Vcom from the voltage V0. When the subframe voltage data is 1, a voltage ((Vsat-Vtt)-(-Vtt)) = voltage Vsat is applied to the liquid crystal layer 20, which is obtained by subtracting the common electrode voltage Vcom from the voltage V1.

[0040] When the polarity inversion signal POL is H, the voltages V0 and V1 are voltages in the negative polarity mode (second mode), with the voltage V0 being the ground voltage (Vsat-Vtt) and the voltage V1 being the voltage GND (i.e., voltage 0). This causes the negative polarity mode subframe voltage data to be written to the first signal holding unit 232. In response to the input of a trigger pulse PTR to the second switch 241, the negative polarity mode subframe voltage data written to the first signal holding unit 232 is transferred to and held in the second signal holding unit 242. The polarity inversion signal POL is also inverted in response to the trigger pulse PTR, so that when the polarity inversion signal POL is L, the common electrode voltage Vcom is the negative polarity mode (second mode) voltage (Vsat).

[0041] When the subframe voltage data is 0, a voltage ((Vsat-Vtt)-Vsat)=voltage (-Vtt) is applied to the liquid crystal layer 20, which is obtained by subtracting the common electrode voltage Vcom from the voltage V0. When the subframe voltage data is 1, a voltage (GND-Vsat)=voltage (-Vsat) is applied to the liquid crystal layer 20, which is obtained by subtracting the common electrode voltage Vcom from the voltage V1.

[0042] When the polarity inversion signal POL is L, the voltage control circuit 17 switches between a set of voltage 0 in the positive mode as voltage V0 and a difference voltage between the saturation voltage Vsat in the positive mode and the threshold voltage Vtt as voltage V1, and when the polarity inversion signal POL is H, a set of voltage 0 in the negative mode as voltage V0 and a difference voltage between the saturation voltage Vsat in the negative mode and the threshold voltage Vtt as voltage V1, and supplies these voltages to the voltage selection circuit 144. When the polarity inversion signal POL is L, the voltage control circuit 17 switches between a set of voltage 0 in the positive mode and a difference voltage between the saturation voltage Vsat in the negative mode and the threshold voltage Vtt in the positive mode as voltage V1, and supplies these voltages to the common electrode 18, switching between these voltages for each subframe.

[0043] The operation of the liquid crystal display device 100 will be further explained using the timing chart shown in Figure 8. In Figure 8, (a) shows subframe data transferred from the subframe data converter 10 to the horizontal driver 14 via the data latch circuit 12. Here, the subframe data of consecutive subframes SF0 to SF3 is shown. The top end of the subframes SF0 to SF3 is the most significant line and the bottom end is the least significant line, and the most significant line and the least significant line are shifted in the time direction because data transfer takes time. The difference between the start timing of the most significant line and the start timing of the least significant line is the data transfer period.

[0044] In FIG. 8, (b) is a polarity inversion signal POL that inverts between L and H every subframe. The voltage control circuit 17 generates two types of voltages V0 and V1 synchronized with the polarity inversion signal POL based on a threshold voltage Vtt for displaying black and a saturation voltage Vsat for displaying white. In FIG. 8, (c) shows voltage V0, and (d) shows voltage V1. Voltage V0 is the voltage for applying to pixel electrode 19 a voltage for displaying black. Voltage V1 is the voltage for applying to pixel electrode 19 a voltage for displaying white.

[0045] In the period from time t0 to time t1 shown in Figure 8, the polarity inversion signal POL is L and in positive mode, so voltage V0 is voltage GND and voltage V1 is voltage (Vsat-Vtt). In the period from time t1 to time t2, the polarity inversion signal POL is H and in negative mode, so voltage V0 is voltage (Vsat-Vtt) and voltage V1 is voltage GND. Voltage V0 inverts in synchronization with the inversion of polarity inversion signal POL. Voltage V1, inverted from voltage V0, inverts in synchronization with the inversion of polarity inversion signal POL.

[0046] In the positive polarity mode, a voltage is applied to the liquid crystal layer 20 so that the pixel electrodes 19 have a positive potential compared to the potential of the common electrode 18. In the negative polarity mode, a voltage is applied to the liquid crystal layer 20 so that the pixel electrodes 19 have a negative potential compared to the potential of the common electrode 18.

[0047] In Fig. 8, (e) shows a write operation to pixel circuit 22. As in (a) of Fig. 8, the top line and bottom line of subframes SF0 to SF3 are shifted in the time direction because it takes time to write data. The difference between the start timing of the top line and the start timing of the bottom line is the data write period.

[0048] One of the row scanning lines g1 to gm is selected by a row scanning signal supplied from the vertical shift register 13. A voltage V0 or a voltage V1 is written as subframe voltage data corresponding to the value of one bit of the subframe data via the first switch 231 to each of the first signal holding units 232 in the pixel circuits 22 of the n pixels 16 connected to the selected row scanning line g.

[0049] 8(e), the polarity inversion signal POL is L during the period from time t0 to time t1, and the subframe voltage data written to the first signal holding unit 232 during that period is represented as SF0+ to indicate that it is positive polarity mode subframe voltage data. The polarity inversion signal POL is H during the period from time t1 to time t2, and the subframe voltage data written to the first signal holding unit 232 during that period is represented as SF1- to indicate that it is negative polarity mode subframe voltage data. Similarly, the subframes SF2 and SF3 are represented as SF2+ and SF3-, respectively.

[0050] In FIG. 8, (f) shows a trigger pulse PTR output from the timing generator 11. The trigger pulse PTR is output in synchronization with the timing at which the polarity inversion signal POL is inverted. The trigger pulse PTR is supplied to the second switch 241 in the pixel circuit 22 of all pixels 16 via a trigger line TRI. When the trigger pulse PTR becomes H, the second switch 241 is turned on and becomes conductive. The subframe voltage data written in the first signal holding unit 232 is transferred to the second signal holding unit 242 via the second switch 241 and written therein.

[0051] 8, (g) shows the subframe voltage data written to the second signal holding unit 242. Immediately before the trigger pulse PTR changes to H at time t1, the positive polarity mode subframe voltage data is written to the first signal holding unit 232, and when the trigger pulse PTR changes to H at time t1, the positive polarity mode subframe voltage data (SF0+) is transferred to the second signal holding unit 242. During the period from time t1 to time t2, the positive polarity mode subframe voltage data (SF0+) is applied to the pixel electrode 19.

[0052] Similarly, from time t2 to time t3, negative polarity mode subframe voltage data (SF1-) is applied to the pixel electrode 19. From time t3 to time t4, positive polarity mode subframe voltage data (SF2+) is applied to the pixel electrode 19. From time t4 to time t5, negative polarity mode subframe voltage data (SF3-) is applied to the pixel electrode 19.

[0053] In Figure 8, (h) shows the common electrode voltage Vcom. In (h) of Figure 8, the polarity inversion signal POL is L from time t0 to time t1, and the common electrode voltage Vcom is in negative polarity mode, so it is voltage Vsat. From time t1 to time t2, the polarity inversion signal POL is H, and the common electrode voltage Vcom is in positive polarity mode, so it is voltage (-Vtt). Similarly, from time t2 to time t3, from time t3 to time t4, and from time t4 to time t5, the common electrode voltage Vcom is voltage Vsat, (-Vtt), and Vsat, respectively.

[0054] In Fig. 8, (i) shows the state of the voltage applied to the liquid crystal layer 20. In (i) of Fig. 8, during the period from time t1 to time t2, positive polarity mode subframe voltage data is applied to the pixel electrodes 19, and a positive polarity mode voltage (-Vtt) is applied to the common electrode voltage Vcom. Therefore, when the subframe voltage data is 0, the voltage Vtt is applied to the liquid crystal layer 20, and when the subframe voltage data is 1, the voltage Vsat is applied.

[0055] During the period from time t2 to time t3, negative polarity mode subframe voltage data is applied to the pixel electrodes 19, and negative polarity mode voltage Vsat is applied to the common electrode voltage Vcom. Therefore, when the subframe voltage data is 0, a voltage (-Vtt) is applied to the liquid crystal layer 20, and when the subframe voltage data is 1, a voltage (-Vsat) is applied.

[0056] Similarly, during the period from time t3 to time t4, positive polarity mode subframe voltage data is applied to the pixel electrodes 19, and a positive polarity mode voltage (-Vtt) is applied to the common electrode voltage Vcom. Therefore, when the subframe voltage data is 0, voltage Vtt is applied to the liquid crystal layer 20, and when the subframe voltage data is 1, voltage Vsat is applied to the liquid crystal layer 20.

[0057] As described above, the liquid crystal display device 100 has a configuration in which the pixel circuit 22 includes two DRAMs, the first DRAM 23 and the second DRAM 24, thereby enabling the circuit scale of the pixel circuit 22 to be reduced. Furthermore, the liquid crystal display device 100 is a digitally driven device in which each frame is divided into a plurality of subframes and the gray scale of each pixel 16 is expressed by pulse width modulation, which varies the time for which the voltage Vsat or the voltage (-Vsat) is applied to the liquid crystal layer 20 within each subframe. Therefore, the liquid crystal display device 100 can operate stably.

[0058] The present invention is not limited to the above-described embodiment, and various modifications are possible without departing from the gist of the present invention. [Explanation of symbols]

[0059] 10 Subframe data conversion device 11 Timing Generator 12 Data latch circuit 13 Vertical Shift Register 14 Horizontal driver 15 Image display section 16 pixels 17 Voltage control circuit 18 Common electrode 19 Pixel electrode 20 Liquid crystal layer 21 Silicon substrate 22 Pixel circuit 23 First Dynamic Random Access Memory 24 Second Dynamic Random Access Memory 100 LCD display device 141 Horizontal shift register 142 Latch Circuit 143 Level Shifter 144 Voltage selection circuit 231 First Switch 232 first signal holding unit 241 Second Switch 242 Second signal holding unit

Claims

1. an image display section in which pixels are provided at each intersection of a plurality of column data lines and a plurality of row scanning lines; a horizontal driver for supplying subframe voltage data corresponding to each line of the subframe data to the plurality of column data lines in parallel, line by line; a vertical shift register that selects a row scanning line corresponding to each of the lines from among the plurality of row scanning lines in order to write the subframe voltage data corresponding to each of the lines output from the horizontal driver to pixels of each of the lines of the image display unit; Equipped with The pixel is a liquid crystal layer provided between a common electrode common to all pixels and a pixel electrode for each pixel; a first dynamic random access memory including a first switch connected to the column data line and a first signal holding unit connected to the first switch; a second dynamic random access memory including a second switch and a second signal holding unit connected to the second switch, connected in series with the first dynamic random access memory, and connected to the pixel electrode; and the horizontal driver includes a voltage selection circuit that selects a first voltage or a second voltage as the subframe voltage data in accordance with a value of one bit of the subframe data and outputs the selected voltage to the plurality of column data lines, thereby writing the first voltage or the second voltage into the first signal holding unit via the first switch; a voltage control circuit that switches between a set of voltage 0 as the first voltage and a differential voltage between a saturation voltage for displaying white of a display gray scale and a threshold voltage for displaying black of the display gray scale as the second voltage, corresponding to a first mode, and a set of the differential voltage as the first voltage and voltage 0 as the second voltage, corresponding to a second mode, for each subframe, and supplies the voltage to the voltage selection circuit; The second signal holding unit holds the first voltage or the second voltage written to the first signal holding unit in response to input of a trigger pulse to the second switch. LCD display device.

2. 2. The liquid crystal display device according to claim 1, wherein the voltage control circuit switches between a voltage corresponding to the first mode, the polarity of which is the inverse of the threshold voltage, and the saturation voltage corresponding to the second mode, and supplies the voltage to the common electrode every subframe.

3. The pixels provided at each intersection of a plurality of column data lines and a plurality of row scanning lines in the image display section are a liquid crystal layer provided between a common electrode common to all pixels and a pixel electrode for each pixel; a first dynamic random access memory including a first switch connected to the column data line and a first signal holding unit connected to the first switch; a second dynamic random access memory including a second switch and a second signal holding unit connected to the second switch, connected in series with the first dynamic random access memory, and connected to the pixel electrode; It has Dividing each frame of a video signal to be displayed on the image display unit into a plurality of subframes; supplying subframe voltage data corresponding to each line of subframe data, each pixel data being one bit, constituting each of the plurality of subframes to the plurality of column data lines one line at a time in parallel; selecting a row scanning line corresponding to each of the lines from among the plurality of row scanning lines in order to write subframe voltage data corresponding to each of the lines to pixels of the line of the image display unit; a voltage selection circuit, in accordance with a value of one bit of the subframe data, selecting a first voltage or a second voltage as the subframe voltage data and outputting the selected voltage to the plurality of column data lines, thereby writing the first voltage or the second voltage into the first signal holding unit via the first switch; a voltage control circuit switches between a set of voltage 0 as the first voltage and a differential voltage between a saturation voltage for displaying white of a display gray scale and a threshold voltage for displaying black of the display gray scale as the second voltage, corresponding to a first mode, and a set of the differential voltage as the first voltage and voltage 0 as the second voltage, corresponding to a second mode, and supplies the voltage to the voltage selection circuit, The second signal holding unit holds the first voltage or the second voltage written in the first signal holding unit in response to input of a trigger pulse to the second switch, thereby applying the first voltage or the second voltage to the pixel electrode. A method for driving a liquid crystal display device.

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