Transmission driver IC, device including the same, and bus system
The transmission driver IC with a bypass circuit and control mechanism addresses impedance mismatch issues in bus systems by redirecting excess current, enhancing signal integrity and reducing waveform distortions.
Patent Information
- Application Number
- JP2024102146
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Filing Date
- 2024-06-25
- Publication Date
- 2026-01-14
AI Technical Summary
Conventional bus systems that transmit differential signals via a pair of wires face issues with impedance mismatch, leading to communication line current flowing into termination resistors, which generates voltage distortions and can cause communication failures.
The implementation of a transmission driver IC with a bypass circuit and control circuit that redirects communication line current through a bypass path using an internal signal as a trigger, reducing excess current flow into termination resistors.
This approach suppresses communication waveform distortion and reduces communication failures by minimizing excess current flow into termination resistors, thereby improving signal integrity.
Smart Images
Figure 2026003991000001_ABST
Abstract
Description
[Technical Field]
[0001] The present disclosure relates to a transmission driver IC, a device including the same, and a bus system. [Background technology]
[0002] BACKGROUND ART Conventionally, a bus system that transmits differential signals via a pair of wires is known (see, for example, Patent Document 1). [Prior art documents] [Patent documents]
[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-107660 Summary of the Invention [Problem to be solved by the invention]
[0004] In conventional bus systems that transmit differential signals via a pair of wires, if impedance matching is not achieved between the signal transmitter and receiver, the current (communication line current) generated in the pair of wires due to communication delays, reflections, etc. flows into the termination resistor connected between the pair of wires. When the communication line current flows into the termination resistor, a voltage is generated across the termination resistor, which can distort the communication waveform transmitted through the pair of wires. Distorted communication waveforms can lead to communication failures.
[0005] An object of the present disclosure is to suppress distortion of communication waveforms. [Means for solving the problem]
[0006] The present disclosure provides: a first transmission driver IC; a second transmission driver IC; a first communication line and a second communication line connecting the first transmission driver IC and the second transmission driver IC; a termination resistor connected between the first communication line and the second communication line, The first transmission driver IC and the second transmission driver IC each include: a transmitter circuit for transmitting a differential signal to the first communication line and the second communication line; a receiving circuit that converts differential signals received from the first communication line and the second communication line into internal signals; a bypass circuit connected to the first communication line or the second communication line; and a control circuit that operates the bypass circuit using the internal signal as a trigger so that a communication line current flowing through the first communication line or the second communication line flows through the bypass circuit.
[0007] The present disclosure provides: a transmission circuit that transmits a differential signal to a first communication line and a second communication line having a termination resistor therebetween; a receiving circuit that converts differential signals received from the first communication line and the second communication line into internal signals; A bypass circuit; and a control circuit that operates the bypass circuit connected to the first communication line or the second communication line using the internal signal as a trigger so that the communication line current flowing through the first communication line or the second communication line flows to the bypass circuit connected to the first communication line or the second communication line.
[0008] The present disclosure provides: an input / output circuit that outputs a transmission signal and receives a reception signal; a transmission driver IC; The transmission driver IC a transmission circuit that converts the transmission signal into a differential signal to be transmitted to a first communication line and a second communication line having a termination resistor therebetween; a receiving circuit that converts differential signals received from the first communication line and the second communication line into internal signals; A bypass circuit; and a control circuit that uses the internal signal as a trigger to operate the bypass circuit connected to the first communication line or the second communication line so that the communication line current flowing through the first communication line or the second communication line flows to the bypass circuit connected to the first communication line or the second communication line. [Effects of the Invention]
[0009] According to the present disclosure, it is possible to suppress the distortion of communication waveforms. [Brief explanation of the drawings]
[0010] [Figure 1] 1 is a diagram illustrating a bus system to which a transmission driver IC according to the present disclosure can be applied; [Figure 2] 4 is a timing chart illustrating waveforms at various parts of the bus system; [Figure 3] FIG. 1 is a diagram illustrating a bus system including a transmission driver IC according to a first comparative example. [Figure 4] 10A to 10C are diagrams illustrating waveforms at various parts of a bus system including a transmission driver IC according to a first comparative example. [Figure 5] 1 is a diagram illustrating a bus system including a transmission driver IC according to a first embodiment; [Figure 6] 3A to 3C are diagrams illustrating waveforms at various parts of a bus system including a transmission driver IC according to a first embodiment. [Figure 7] 4 is a timing chart for explaining an example of a configuration and a method in which the transmission driver IC according to the first embodiment controls a bypass circuit. [Figure 8] FIG. 10 is a diagram illustrating a bus system including a transmission driver IC according to a second embodiment. [Figure 9] 10 is a timing chart for explaining an example of a configuration and a method in which a transmission driver IC according to a second embodiment controls a bypass circuit. [Figure 10] FIG. 10 is a diagram illustrating a bus system including a transmission driver IC according to a third embodiment. [Figure 11] 10A and 10B are diagrams illustrating an example of the suppression effect of waveform distortion of an AMI signal at a communication speed of 9.6 kbps. [Figure 12] FIG. 10 is a diagram showing an example of the suppression effect of waveform distortion of an AMI signal at a communication speed of 300 kbps. DETAILED DESCRIPTION OF THE INVENTION
[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings.
[0012] Fig. 1 is a diagram illustrating a bus system to which the transmission driver IC of the present disclosure can be applied. The bus system 1000 shown in Fig. 1 is a communication system including a plurality of transmission driver ICs (Integrated Circuits) that are balanced-connected to one another via a pair of communication lines A and B. Fig. 1 illustrates five drivers 211, 212, 213, 214, and 215 (hereinafter also referred to as "drivers 211, etc.") as the plurality of transmission driver ICs. The drivers 211, etc. are circuits that include the same communication interface circuit and communicate with one another using differential signals transmitted over the pair of communication lines A and B.
[0013] Fig. 1 illustrates an example in which a bus system 1000 is applied to communication between air conditioning devices. The bus system 1000 includes a plurality of air conditioning devices that are balanced-connected to each other via a pair of communication lines A and B. Fig. 1 illustrates an indoor unit 201, a remote control terminal 202, an indoor unit 203, a remote control terminal 204, and an outdoor unit 205 as examples of the plurality of air conditioning devices.
[0014] The indoor unit 201 has a driver 211 and an input / output circuit 221, and conditions the air in a room 241. The remote control terminal 202 has a driver 212 and an input / output circuit 222, and is an operation terminal for remotely controlling the indoor unit 201. The indoor unit 203 has a driver 213 and an input / output circuit 223, and conditions the air in a room 242. The remote control terminal 204 has a driver 214 and an input / output circuit 224, and is an operation terminal for remotely controlling the indoor unit 203. The outdoor unit 205 has a driver 215 and an input / output circuit 225, and discharges air that has exchanged heat with the refrigerant circulating between the indoor units 201 and 203 to the outside.
[0015] Specific examples of the input / output circuits 221, 223 include a processor such as an MPU (Micro Processing Unit), and a power controller that controls the air conditioning operation of the indoor units 201, 203. Specific examples of the input / output circuits 222, 224 include an MPU, a display device such as an LCD (Liquid Crystal Display), and a switch (SW). Specific examples of the input / output circuit 225 include an MPU, and a power controller that controls the refrigerant compression operation in the outdoor unit 205.
[0016] The drivers 211 etc. are compliant with the home bus system (HBS), but may be compliant with a bus system different from the HBS. Each of the drivers 211 etc. includes a transmission terminal OUTA connected to the communication line A via a capacitor (not shown) and a transmission terminal OUTB connected to the communication line B via a capacitor (not shown).
[0017] 2 is a timing chart illustrating waveforms at various components of the bus system. The bus system 1000 employs, for example, the AMI (Alternate Mark Inversion) method for signal waveforms transmitted between multiple devices. The driver 211 and other components have a transmitting circuit that converts a square wave signal received at an input terminal DIN from a microcomputer such as an MPU into a pair of differential AMI signals and transmits them from transmitting terminals OUTA and OUTB. The driver 211 and other components have a receiving circuit that converts a pair of differential AMI signals received from a pair of communication lines A and B into square wave signals and transmits them from an output terminal DOUT to the microcomputer such as an MPU. The AMI signal propagating through communication line A and the AMI signal propagating through communication line B are in opposite phase to each other.
[0018] FIG. 3 illustrates a bus system including a transmission driver IC according to a first comparative example. The bus system 300 illustrated in FIG. 3 is a communication system for transmitting and receiving differential signals between a plurality of devices. For simplicity of explanation, FIG. 3 illustrates two devices 231 and 232 connected to each other by a pair of communication lines A and B. The bus system 300 includes devices 231 and 232, communication lines A and B. The device 231 includes an MPU 15, a transmission driver IC1, capacitors 31, 32, 33, and 34, and a termination resistor 30. The termination resistor 30 is connected between communication lines A and B. The device 232 includes an MPU 25, a transmission driver IC2, and capacitors 35, 36, 37, and 38.
[0019] The transmission driver IC1 includes a transmitter circuit 11 and a receiver circuit 12. The transmitter circuit 11 converts a square wave signal Din received at an input terminal DIN from the MPU 15 into a pair of differential AMI signals and transmits them from transmitter terminals OUTA and OUTB to communication lines A and B. The transmitter terminal OUTA is electrically connected to communication line A via a capacitor 31. The transmitter terminal OUTB is electrically connected to communication line B via a capacitor 32. The receiver circuit 12 converts a pair of differential AMI signals received at receiver terminals INA and INB from the pair of communication lines A and B into a square wave signal Dout and transmits it to the MPU 15 from an output terminal DOUT. The receiver terminal INA is electrically connected to communication line A via a capacitor 34. The receiver terminal INB is electrically connected to communication line B via a capacitor 33.
[0020] The transmission driver IC2 includes a transmitter circuit 21 and a receiver circuit 22. The transmitter circuit 21 converts a square wave signal Din received at an input terminal DIN from the MPU 25 into a pair of differential AMI signals and transmits them from transmitter terminals OUTA and OUTB to communication lines A and B. The transmitter terminal OUTA is electrically connected to communication line A via a capacitor 35. The transmitter terminal OUTB is electrically connected to communication line B via a capacitor 36. The receiver circuit 22 converts a pair of differential AMI signals received at receiver terminals INA and INB from the pair of communication lines A and B into a square wave signal Dout and transmits it to the MPU 25 from an output terminal DOUT. The receiver terminal INA is electrically connected to communication line A via a capacitor 38. The receiver terminal INB is electrically connected to communication line B via a capacitor 37.
[0021] In the bus system 300, a termination resistor 30 is provided in the device 231, but a termination resistor is not provided in the device 232. Therefore, the longer the communication lines A and B between the devices 231 and 232, the more difficult it becomes to achieve impedance matching between the devices 231 and 232. If impedance matching is not achieved between the devices 231 and 232, part or all of the current (communication line current Itrans) generated in the pair of communication lines A and B due to communication delays, reflections, etc. flows into the termination resistor 30 as the current Iterm. When the communication line current Itrans flows into the termination resistor 30, a voltage Vtrans is generated across the termination resistor 30, which may distort the communication waveform propagated by the pair of communication lines A and B. Distorted communication waveforms can lead to communication failures.
[0022] 4 is a diagram illustrating waveforms at various parts of a bus system including a transmission driver IC according to the first comparative example. "H" means a high level, and "L" means a low level (the same applies to waveforms in other drawings).
[0023] The transmitter circuit 11 converts the square wave signal Din received at the input terminal DIN from the MPU 15 into a pair of differential AMI signals and transmits them from the transmission terminals OUTA and OUTB to the communication lines A and B. The voltage Vtrans is a voltage generated across the terminals of the termination resistor 30, and is a differential voltage obtained by subtracting the potential of the communication line B from the potential of the communication line A.
[0024] If impedance matching is not achieved between the device 231 and the device 232, a communication line current Itrans flows through the pair of communication lines A and B due to communication delays, reflections, and the like. Part or all of the communication line current Itrans flows into the termination resistor 30 as the current Iterm. Fluctuations in the current Iterm cause the voltage Vtrans to ring, distorting the communication waveform (in this case, the voltage Vtrans) transmitted through the pair of communication lines A and B. The ringing of the communication waveform may cause chattering in the reception signal Dout output from the receiving circuit 22 to the MPU 25 via the output terminal DOUT, potentially resulting in poor reception by the MPU 25. If excess current Iterm flows into the termination resistor 30 and distorts the communication waveform, communication between the device 231 and the device 232 may become unstable.
[0025] 5, the bus system 301 according to the first embodiment suppresses the distortion of the communication waveform by reducing the excess current Iterm flowing into the termination resistor 30. Next, the bus system 301 according to the first embodiment will be described.
[0026] FIG. 5 is a diagram illustrating a bus system including a transmission driver IC according to the first embodiment. The bus system 301 shown in FIG. 5 is a communication system that transmits and receives differential signals between multiple devices. For simplicity of explanation, FIG. 5 illustrates two devices 231 and 232 connected to each other by a pair of communication lines A and B. The number of devices connected to the pair of communication lines A and B is not limited to two, and may be three or more. The devices 231 and 232 may be, for example, any of the multiple air conditioning devices described above.
[0027] 5, a bus system 301 includes a device 231, a device 232, a communication line A, and a communication line B. The device 231 includes an MPU 15, a transmission driver IC 10, capacitors 31, 32, 33, and 34, and a termination resistor 30. The termination resistor 30 is connected between the communication line A and the communication line B. The device 232 includes an MPU 25, a transmission driver IC 20, and capacitors 35, 36, 37, and 38.
[0028] The termination resistor 30 is a resistor interposed between the communication line A and the communication line B. In the illustrated example, the termination resistor 30 is provided only in the device 231, but it may be provided only in the device 232, or in both the devices 231 and 232. Even if the termination resistor 30 is provided in both the devices 231 and 232, the longer the communication lines A and B are, the more difficult it may be to achieve impedance matching between the devices 231 and 232 due to the impedances of the communication lines A and B, etc. The termination resistor 30 may be built into one or both of the transmission driver ICs 10 and 20, or may be provided outside the devices 231 and 232, as long as it is electrically connected between the communication line A and the communication line B.
[0029] The MPUs 15 and 25 are each an example of an input / output circuit that outputs a transmission signal and receives a reception signal. The MPUs 15 and 25 may each be any of the input / output circuits provided in the air conditioning equipment. The MPU 15 outputs a square wave signal Din as a transmission signal to the transmission driver IC 10 and receives a square wave signal Dout as a reception signal from the transmission driver IC 10. The MPU 25 outputs the square wave signal Din as a transmission signal to the transmission driver IC 20 and receives the square wave signal Dout as a reception signal from the transmission driver IC 20.
[0030] The transmission driver IC10 is an example of a first transmission driver IC. The transmission driver IC10 is a semiconductor integrated circuit including a transmission circuit 11, a reception circuit 12, bypass circuits 13A and 13B, and a control circuit 14. In this example, the transmission driver IC10 further includes a plurality of terminals including a transmission terminal OUTA, a transmission terminal OUTB, a reception terminal INA, and a reception terminal INB. The transmission terminal OUTA is an example of a first transmission terminal. The transmission terminal OUTB is an example of a second transmission terminal. The reception terminal INA is an example of a first reception terminal. The reception terminal INB is an example of a second reception terminal.
[0031] The transmitter circuit 11 converts a square wave signal Din received at an input terminal DIN from the MPU 15 into a pair of differential AMI signals and transmits them from transmission terminals OUTA and OUTB to communication lines A and B. The transmission terminal OUTA is electrically connected to the communication line A via a capacitor 31. The transmission terminal OUTB is electrically connected to the communication line B via a capacitor 32.
[0032] The receiving circuit 12 converts a pair of differential AMI signals received from a pair of communication lines A and B via receiving terminals INA and INB into an internal signal RO and outputs it to the control circuit 14. The receiving terminal INA is electrically connected to the communication line A via a capacitor 34. The receiving terminal INB is electrically connected to the communication line B via a capacitor 33.
[0033] The communication lines A and B are wirings that connect the transmission driver IC10 and the transmission driver IC20. The communication line A is an example of a first communication line. The communication line A is connected to the transmitting terminal OUTA via a capacitor 31 and to the receiving terminal INA via a capacitor 34. The communication line B is an example of a second communication line. The communication line B is connected to the transmitting terminal OUTB via a capacitor 32 and to the receiving terminal INB via a capacitor 33.
[0034] The capacitors 31 and 34 may be combined into a single capacitor, thereby combining the transmission terminal OUTA and the reception terminal INA into a single transmission / reception terminal. This single transmission / reception terminal is connected to the transmission circuit 11 and the reception circuit 12 in a branched manner within the transmission driver IC 10. Similarly, the capacitors 32 and 33 may be combined into a single capacitor, thereby combining the transmission terminal OUTB and the reception terminal INB into a single transmission / reception terminal. This single transmission / reception terminal is connected to the transmission circuit 11 and the reception circuit 12 in a branched manner within the transmission driver IC 10.
[0035] The bypass circuit 13A is connected to the communication line A. In this example, the transmission driver IC10 has a bypass terminal BPA, and the bypass circuit 13A is electrically connected to the communication line A via the bypass terminal BPA. The bypass circuit 13A has the ability to sink and source current via the bypass terminal BPA. In the case of FIG. 5, the bypass circuit 13A has a buffer 13Aa having the ability to sink and source current. The buffer 13Aa has an output terminal connected to the bypass terminal BPA, an inverting input terminal to which the output terminal is connected, and a non-inverting input terminal to which a constant voltage (VCC / 2) is input. VCC is the power supply voltage of the transmission driver IC10.
[0036] The bypass circuit 13B is connected to the communication line B. In this example, the transmission driver IC10 includes a bypass terminal BPB, and the bypass circuit 13B is electrically connected to the communication line B via the bypass terminal BPB. The bypass circuit 13B has the ability to sink and source current via the bypass terminal BPB. In the case of FIG. 5, the bypass circuit 13B includes a buffer 13Ba having the ability to sink and source current. The buffer 13Ba has an output terminal connected to the bypass terminal BPB, an inverting input terminal to which the output terminal is connected, and a non-inverting input terminal to which a constant voltage (VCC / 2) is input.
[0037] The control circuit 14 operates the bypass circuit 13A in response to an internal signal RO output from the receiving circuit 12 so that the communication line current Itrans flowing through the communication line A flows through the bypass circuit 13A. Similarly, the control circuit 14 operates the bypass circuit 13B in response to an internal signal RO output from the receiving circuit 12 so that the communication line current Itrans flowing through the communication line B flows through the bypass circuit 13B. The control circuit 14 outputs an enable signal EN that operates the bypass circuits 13A and 13B.
[0038] In this example, the enable signal EN generated by the control circuit 14 is input to the buffers 13Aa and 13Ba. When the enable signal EN is active, the buffers 13Aa and 13Ba output (VCC / 2), and when the enable signal EN is inactive, they output high impedance.
[0039] For example, the control circuit 14 includes a signal generating circuit 14a that activates the enable signal EN in response to the internal signal RO as a trigger. The signal generating circuit 14a may determine the time for which the enable signal EN is activated based on the time it takes to charge the capacitor 16, which is connected via the connection terminal CDF of the transmission driver IC 10, to a predetermined first voltage. The control circuit 14 includes a logic circuit 14b that outputs the logical product of the enable signal EN and the internal signal RO. The logic circuit 14b generates a reception signal Dout that is output to the MPU 15 based on the logical product.
[0040] The transmission driver IC 20 is an example of a second transmission driver IC. The transmission driver IC 20 is a semiconductor integrated circuit including a transmitting circuit 21, a receiving circuit 22, bypass circuits 23A and 23B, and a control circuit 24. The transmission driver IC 20 has the same configuration and function as the transmission driver IC 10, and therefore the above description will be used to simplify the description.
[0041] The transmitter circuit 21 converts a square wave signal Din received from the MPU 25 at an input terminal DIN into a pair of differential AMI signals and transmits them from transmission terminals OUTA and OUTB to communication lines A and B. The receiver circuit 22 converts the pair of differential AMI signals received from the pair of communication lines A and B via reception terminals INA and INB into an internal signal RO and outputs it to the control circuit 24. The bypass circuit 23A has the ability to sink and source current via a bypass terminal BPA. In the case of FIG. 5, the bypass circuit 23A has a buffer 23Aa having the ability to sink and source current. The bypass circuit 23B has the ability to sink and source current via a bypass terminal BPB. In the case of FIG. 5, the bypass circuit 23B has a buffer 23Ba having the ability to sink and source current.
[0042] The control circuit 24 operates the bypass circuit 23A in response to an internal signal RO output from the receiving circuit 22 so that the communication line current Itrans flowing through the communication line A flows through the bypass circuit 23A. Similarly, the control circuit 24 operates the bypass circuit 23B in response to an internal signal RO output from the receiving circuit 22 so that the communication line current Itrans flowing through the communication line B flows through the bypass circuit 23B. The control circuit 24 outputs an enable signal EN that operates the bypass circuits 23A and 23B.
[0043] In this example, the enable signal EN generated by the control circuit 24 is input to the buffers 23Aa and 23Ba. When the enable signal EN is active, the buffers 23Aa and 23Ba output (VCC / 2), and when the enable signal EN is inactive, they output high impedance.
[0044] For example, the control circuit 24 includes a signal generating circuit 24a that activates the enable signal EN using the internal signal RO as a trigger. The signal generating circuit 24a may determine the time for which the enable signal EN is activated based on the time it takes to charge the capacitor 26, which is connected via the connection terminal CDF of the transmission driver IC 20, to a predetermined first voltage. The control circuit 24 includes a logic circuit 24b that outputs the logical product of the enable signal EN and the internal signal RO. The logic circuit 24b generates the reception signal Dout that is output to the MPU 25 based on the logical product.
[0045] The control circuit 14 operates the bypass circuits 13A and 13B in response to an internal signal RO output from the receiving circuit 12 as a trigger so that the communication line current Itrans flowing through the communication lines A and B flows through the bypass circuits 13A and 13B. Similarly, the control circuit 24 operates the bypass circuits 23A and 23B in response to an internal signal RO output from the receiving circuit 22 as a trigger so that the communication line current Itrans flowing through the communication lines A and B flows through the bypass circuits 23A and 23B.
[0046] The control circuit 14 operates the bypass circuits 13A and 13B as described above, and the control circuit 24 operates the bypass circuits 23A and 23B as described above. As a result, part or all of the excess communication line current Itrans, which is generated due to impedance mismatch between the device 231 and the device 232, flows to the bypass circuits 13A, 13B, 23A, and 23B without flowing to the termination resistor 30. Since the bypass current Ibyps flows through the bypass circuits 13A, 13B, 23A, and 23B, the excess current Iterm flowing into the termination resistor 30 is reduced, and the excess voltage Vtrans generated across the termination resistor 30 is reduced. Therefore, distortion of the communication waveform propagated by the pair of communication lines A and B is suppressed, reducing the occurrence of communication failures.
[0047] 5, the bypass current Ibyps flowing through the bypass circuit 13A flows bidirectionally through a bypass path that passes through the capacitor 31, the resistor 41, the bypass terminal BPA, and the buffer 13Aa. The bypass current Ibyps flowing through the bypass circuit 13B flows bidirectionally through a bypass path that passes through the capacitor 32, the resistor 42, the bypass terminal BPB, and the buffer 13Ba. The bypass current Ibyps flowing through the bypass circuit 23A flows bidirectionally through a bypass path that passes through the capacitor 35, the resistor 43, the bypass terminal BPA, and the buffer 23Aa. The bypass current Ibyps flowing through the bypass circuit 23B flows bidirectionally through a bypass path that passes through the capacitor 36, the resistor 44, the bypass terminal BPB, and the buffer 23Ba.
[0048] 6 is a diagram illustrating waveforms at various parts of a bus system including a transmission driver IC according to the first embodiment. The transmitter circuit 11 converts a rectangular wave signal Din received at an input terminal DIN from the MPU 15 into a pair of differential AMI signals and transmits them from transmission terminals OUTA and OUTB to communication lines A and B. The voltage Vtrans is a voltage generated across the termination resistor 30, and is a differential voltage obtained by subtracting the potential of communication line B from the potential of communication line A.
[0049] When impedance matching is not achieved between the device 231 and the device 232, a communication line current Itrans flows through the pair of communication lines A and B due to communication delays, reflections, and the like. The control circuit 14 activates an enable signal EN that operates the bypass circuits 13A and 13B, triggered by a rising or falling edge of the internal signal RO generated by the receiving circuit 12, so that the communication line current Itrans flows through the bypass circuits 13A and 13B. Similarly, the control circuit 24 activates an enable signal EN that operates the bypass circuits 23A and 23B, triggered by a rising or falling edge of the internal signal RO generated by the receiving circuit 22, so that the communication line current Itrans flows through the bypass circuits 23A and 23B. When the bypass current Ibyps flows through the bypass circuits 13A, 13B, 23A, and 23B, the excess current Iterm flowing into the termination resistor 30 is reduced, and the excess voltage Vtrans generated across the termination resistor 30 is reduced. Therefore, the distortion of the communication waveform propagated through the pair of communication lines A and B is suppressed, and the occurrence of communication failures is reduced.
[0050] As shown in FIG. 6, the control circuit 14 causes the communication line current Itrans to flow through the bypass circuits 13A and 13B during the off period of the differential signals transmitted through the communication lines A and B (in this example, the period when the voltage of the AMI signal (corresponding to the voltage Vtrans in FIG. 6) is zero). Similarly, as shown in FIG. 6, the control circuit 24 causes the communication line current Itrans to flow through the bypass circuits 23A and 23B during the off period of the differential signals transmitted through the communication lines A and B. This improves the accuracy of the timing for suppressing distortion of the communication waveform that occurs during the off period of the differential signals.
[0051] As shown in Fig. 6, the control circuit 14 causes the communication line current Itrans to flow through the bypass circuits 13A and 13B during a first half period Tm of the off period, and stops the communication line current Itrans from flowing through the bypass circuits 13A and 13B during a second half period Tn of the off period. Similarly, as shown in Fig. 6, the control circuit 24 causes the communication line current Itrans to flow through the bypass circuits 23A and 23B during a first half period Tm of the off period, and stops the communication line current Itrans from flowing through the bypass circuits 23A and 23B during a second half period Tn of the off period. This improves the accuracy of the timing for suppressing distortion of the communication waveform that occurs during the first half period Tm of the off period.
[0052] As shown in Fig. 6, the control circuit 14 masks the output of the internal signal RO to the outside during the first half period Tm, and releases the masking of the output of the internal signal RO to the outside during the second half period Tn. As a result, the control circuit 14 does not transmit the internal signal RO directly to the MPU 15 via the output terminal DOUT as the reception signal Dout during the first half period Tm, but transmits the internal signal RO directly to the MPU 15 via the output terminal DOUT as the reception signal Dout during the second half period Tn. As a result, even if a disturbance in the internal signal RO occurs during the first half period Tm, the disturbance in the internal signal RO does not affect the reception signal Dout, thereby reducing reception errors in the MPU 15. The control circuit 24 also operates in the same manner as the control circuit 14, thereby reducing reception errors in the MPU 25.
[0053] 5, for example, the bypass circuit 13A has a lower impedance than the termination resistor 30 (for example, a resistance value 10% or less of that of the termination resistor 30). As a result, excess communication line current Itrans generated due to impedance mismatch is more likely to flow through the bypass circuit 13A than through the termination resistor 30, and the bypass current Ibyps flowing through the bypass circuit 13A increases. This improves the effect of suppressing waveform distortion. Like the bypass circuit 13A, the bypass circuits 13B, 23A, and 23B each have an impedance lower than that of the termination resistor 30 (for example, a resistance value 10% or less of that of the termination resistor 30), thereby improving the effect of suppressing waveform distortion.
[0054] 5, the bypass circuit 13A may include a resistive element 41 having a resistance value lower than that of the termination resistor 30 (for example, the resistive element 41 having a resistance value 10% or less of that of the termination resistor 30). The resistive element 41 functions as an auxiliary termination resistor. By changing the resistance value of the resistive element 41, it is possible to fine-tune the impedance matching between the device 231 and the device 232. Similarly to the bypass circuit 13A, the bypass circuits 13B, 23A, and 23B may also include resistive elements 42, 43, and 44 having a resistance value lower than that of the termination resistor 30 (for example, the resistive elements 42, 43, and 44 having a resistance value 10% or less of that of the termination resistor 30). By changing the resistance values of some or all of the resistive elements 41, 42, 43, and 44, it is possible to fine-tune the impedance matching between the device 231 and the device 232.
[0055] The resistive element 41 may be provided outside the transmission driver IC 10. This allows the resistance value of the resistive element 41 to be changed more easily than when the resistive element 41 is provided inside the transmission driver IC 10, making it easier to fine-tune the impedance matching (the same applies to the resistive element 42). The resistive element 43 may be provided outside the transmission driver IC 20. This allows the resistance value of the resistive element 43 to be changed more easily than when the resistive element 43 is provided inside the transmission driver IC 20, making it easier to fine-tune the impedance matching (the same applies to the resistive element 44).
[0056] 7 is a timing chart illustrating an example of a configuration and a method in which the transmission driver IC according to the first embodiment controls the bypass circuit. The control circuit 14 flows excess communication line current Itrans through the bypass circuits 13A and 13B when triggered by a change in the internal signal RO corresponding to an on-to-off change of the differential signal (in this example, the AMI signal) transmitted through the communication lines A and B. Similarly, the control circuit 24 flows excess communication line current Itrans through the bypass circuits 23A and 23B when triggered by a change in the internal signal RO corresponding to an on-to-off change of the differential signal (in this example, the AMI signal) transmitted through the communication lines A and B. In the case of FIG. 7, the on-to-off change of the AMI signal corresponds to the edge where the voltage Vtrans level falls from 1 to zero and the edge where the voltage Vtrans level rises from -1 to zero.
[0057] As shown in Figure 7, the internal signal RO may also ring in response to the ringing behavior of the AMI signal waveform. In this case, if the control circuits 14 and 24 activate the enable signal EN using a change in the internal signal RO corresponding to the AMI signal changing from on to off (a rising edge in Figure 7), as a trigger, the enable signal EN may become unstable. This is because the ringing of the internal signal RO occurs immediately after the trigger timing.
[0058] 7, when the control circuits 14 and 24 detect a change in the internal signal RO corresponding to a change from on to off of the AMI signal (a rising edge in the case of FIG. 7), they latch the enable signal EN. This keeps the enable signal EN active even if the internal signal RO becomes unstable. The control circuits 14 and 24 release the latch on the enable signal EN after the first half period Tm has elapsed, thereby making the enable signal EN inactive during the second half period Tn.
[0059] 8 is a diagram illustrating a bus system including a transmission driver IC according to the second embodiment. In the bus system 302 according to the second embodiment, the same configuration, operation, and effects as those of the bus system 301 according to the first embodiment will not be described by citing the above description. The control circuits 14 and 24 of the transmission driver ICs 10 and 20 according to the second embodiment differ from the control circuits 14 and 24 of the transmission driver ICs 10 and 20 according to the first embodiment in that they further include delay circuits 14c and 24c that generate a delay time D.
[0060] The delay circuit 14c may generate a delay time D according to the time required to charge the capacitor 17 connected via the connection terminal CT of the transmission driver IC10 to a predetermined second voltage. The signal generation circuit 14a changes the enable signal EN from inactive to active after the delay time D has elapsed from the edge of the internal signal RO. The delay circuit 24c may generate a delay time D according to the time required to charge the capacitor 27 connected via the connection terminal CT of the transmission driver IC20 to a predetermined second voltage. The signal generation circuit 24a changes the enable signal EN from inactive to active after the delay time D has elapsed from the edge of the internal signal RO.
[0061] 9 is a timing chart illustrating an example of a configuration and a method for controlling a bypass circuit by a transmission driver IC according to the second embodiment. The control circuit 14 is triggered by a change in the internal signal RO corresponding to an OFF-to-ON change of a differential signal (in this example, the AMI signal) transmitted through the communication lines A and B, and then, after a delay time D has elapsed, causes an excess communication line current Itrans to flow through the bypass circuits 13A and 13B. Similarly, the control circuit 24 is triggered by a change in the internal signal RO corresponding to an OFF-to-ON change of a differential signal (in this example, the AMI signal) transmitted through the communication lines A and B, and then, after a delay time D has elapsed, causes an excess communication line current Itrans to flow through the bypass circuits 23A and 23B. In the case of FIG. 9, the OFF-to-ON change of the AMI signal corresponds to an edge where the voltage Vtrans rises from zero to one and an edge where the voltage Vtrans falls from zero to -1.
[0062] As shown in Figure 9, the internal signal RO may also ring in response to the ringing of the AMI signal waveform. In this case, if the control circuits 14 and 24 activate the enable signal EN using the change in the internal signal RO corresponding to the AMI signal changing from on to off (the rising edge in Figure 7), as a trigger, the enable signal EN may become unstable. This is because the ringing of the internal signal RO occurs immediately after the trigger timing.
[0063] In the case of FIG. 9, when the control circuits 14 and 24 detect a change in the internal signal RO corresponding to a change from off to on of the AMI signal (a falling edge in the case of FIG. 7), they can maintain the enable signal EN inactive until the delay time D has elapsed, and then transition the enable signal EN to active after the delay time D has elapsed. The signal generating circuit 14a may determine the time to activate the enable signal EN based on the time it takes to charge the capacitor 16 connected via the connection terminal CDF of the transmission driver IC10 to a predetermined first voltage. This allows the enable signal EN to be maintained active even if the internal signal RO becomes unstable. The control circuits 14 and 24 deactivate the enable signal EN after the first half period Tm has elapsed.
[0064] 10 is a diagram illustrating a bus system including a transmission driver IC according to the third embodiment. In the bus system 303 according to the third embodiment, the same configuration, operation, and effects as those of the bus system 301 according to the first embodiment will not be described by citing the above description. The bypass circuits 13 and 23 of the transmission driver ICs 10 and 20 according to the third embodiment differ from the bypass circuits of the transmission driver ICs 10 and 20 according to the first embodiment in that they include switches 13a and 23a that electrically connect communication lines A and B.
[0065] In this example, the enable signal EN generated by the control circuit 14 is input to the switch 13a, and the enable signal EN generated by the control circuit 24 is input to the switch 23a. When the enable signal EN is active, the switches 13a and 23a electrically connect (turn on) the communication lines A and B, and when the enable signal EN is inactive, they cut off (turn off) the electrical connection between the communication lines A and B. As in FIG. 6, turning on the switches 13a and 23a reduces the excess current Iterm flowing into the termination resistor 30, thereby reducing the excess voltage Vtrans generated across the termination resistor 30. Therefore, distortion of the communication waveform propagated by the pair of communication lines A and B is suppressed, reducing the occurrence of communication failures.
[0066] Fig. 11 is a diagram showing an example of the effect of suppressing waveform collapse of an AMI signal at a communication speed of 9.6 kbps. Fig. 12 is a diagram showing an example of the effect of suppressing waveform collapse of an AMI signal at a communication speed of 300 kbps. In the legends of Figs. 11 and 12, "comparative embodiment" refers to the first comparative embodiment shown in Fig. 3, and "embodiment" refers to the first embodiment shown in Fig. 5. As shown in Figs. 11 and 12, by using internal signal RO as a trigger to pass current through the bypass circuit, collapse of the communication waveform is suppressed, thereby enabling an increase in communication speed.
[0067] Although the embodiments have been described above, they are presented as examples and the present invention is not limited to the above embodiments. The above embodiments can be implemented in various other forms, and various combinations, omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as set forth in the claims.
[0068] For example, the communication method may be a method different from the AMI method.
[0069] The device equipped with the transmission driver IC is not limited to air conditioning equipment, but may be other devices such as telephone equipment, security equipment, audio equipment, video equipment, and communication equipment. [Explanation of symbols]
[0070] 1,2,10,20 Transmission driver IC 11,21 Transmitter circuit 12,22 Receiver circuit 13, 13A, 13B, 23, 23A, 23B Bypass circuit 13Aa, 23Aa, 23Aa, 23Ba buffer 13a,23a switch 14,24 Control circuit 14a,24a Signal generation circuit 14b, 24b logic circuit 14c,24c delay circuit 15,25 MPU 16,17,26,27,31,32,32,33,34,35,36,37,38 Capacitors 30 Termination Resistor 41, 42, 43, 44 Resistive elements 201,203 Indoor unit 202,204 Remote control terminal 205 Outdoor unit 211,212,213,214,215 drivers 221, 222, 223, 224, 225 Input / output circuits 231,232 equipment 241,242 rooms 300, 301, 302, 303, 1000 bus systems A,B communication line BPA,BPB Bypass terminals CDF, CT connection terminal INA, INB receiving terminals OUTA, OUTB transmission terminals
Claims
1. a first transmission driver IC; a second transmission driver IC; a first communication line and a second communication line connecting the first transmission driver IC and the second transmission driver IC; a termination resistor connected between the first communication line and the second communication line, The first transmission driver IC and the second transmission driver IC each include: a transmitter circuit for transmitting a differential signal to the first communication line and the second communication line; a receiving circuit that converts differential signals received from the first communication line and the second communication line into internal signals; a bypass circuit connected to the first communication line or the second communication line; a control circuit that operates the bypass circuit using the internal signal as a trigger so that a communication line current flowing through the first communication line or the second communication line flows through the bypass circuit.
2. 2. The bus system according to claim 1, wherein the control circuit causes the communication line current to flow through the bypass circuit during an OFF period of the differential signal.
3. 3. The bus system according to claim 2, wherein the control circuit causes the communication line current to flow through the bypass circuit during a first half of the off period, and stops the communication line current from flowing through the bypass circuit during a second half of the off period.
4. 4. The bus system according to claim 3, wherein said control circuit masks the output of said internal signal to the outside during said first half period, and releases the masking of said output during said second half period.
5. 5. The bus system according to claim 2, wherein the control circuit causes the communication line current to flow through the bypass circuit when triggered by a change in the internal signal corresponding to a change from on to off of the differential signal.
6. the control circuit includes a delay circuit that generates a delay time; 5. The bus system according to claim 2, wherein the control circuit is triggered by a change in the internal signal corresponding to a change from off to on of the differential signal, and causes the communication line current to flow through the bypass circuit after the delay time has elapsed.
7. 5. The bus system according to claim 1, wherein the bypass circuit has an impedance lower than that of the termination resistor.
8. 8. The bus system according to claim 7, wherein the bypass circuit has a resistive element having a resistance value lower than that of the termination resistor.
9. 9. The bus system according to claim 8, wherein the resistive element is provided outside the first transmission driver IC or the second transmission driver IC.
10. 5. The bus system according to claim 1, wherein the bypass circuit has current sink and source capabilities.
11. 5. The bus system according to claim 1, wherein the bypass circuit includes a switch that electrically connects the first communication line and the second communication line.
12. a transmission circuit that transmits a differential signal to a first communication line and a second communication line having a termination resistor therebetween; a receiving circuit that converts differential signals received from the first communication line and the second communication line into internal signals; A bypass circuit; a control circuit that operates the bypass circuit connected to the first communication line or the second communication line using the internal signal as a trigger so that the communication line current flowing through the first communication line or the second communication line flows to the bypass circuit connected to the first communication line or the second communication line.
13. further comprising a plurality of terminals including a first transmitting terminal, a second transmitting terminal, a first receiving terminal, and a second receiving terminal; the transmission circuit transmits a differential signal to the first communication line and the second communication line via the first transmission terminal and the second transmission terminal; 13. The transmission driver IC according to claim 12, wherein the receiving circuit receives differential signals from the first communication line and the second communication line via the first receiving terminal and the second transmitting terminal.
14. an input / output circuit that outputs a transmission signal and receives a reception signal; a transmission driver IC; The transmission driver IC includes: a transmission circuit that converts the transmission signal into a differential signal to be transmitted to a first communication line and a second communication line having a termination resistor therebetween; a receiving circuit that converts differential signals received from the first communication line and the second communication line into internal signals; A bypass circuit; a control circuit that operates the bypass circuit using the internal signal as a trigger so that a communication line current flowing through the first communication line or the second communication line flows to the bypass circuit connected to the first communication line or the second communication line.