Adaptive resolution for single reference motion vector difference

Abstract

To provide methods and systems for providing adaptive resolution for motion vector difference in inter-prediction of video blocks.SOLUTION: The method includes receiving a video stream, extracting an inter-prediction syntax element from the video stream to determine whether an ADAPTM mode is signaled for one or more video blocks, determining a current MVD pixel resolution associated with the one or more video blocks based on whether the ADAPTM mode is signaled in the inter-prediction syntax element, and extracting and decoding one or more MVD-related syntax elements associated with the one or more video blocks based on whether the ADAPTM mode is signaled in the inter-prediction syntax element and the current MVD pixel resolution.SELECTED DRAWING: Figure 18

Description

[Technical Field]

[0001] [Incorporated by reference] This application is based on and claims the benefit of priority to U.S. Non-Provisional Patent Application No. 17 / 824,248, entitled "Adaptive Resolution for Single-Reference Motion Vector Difference," filed May 25, 2022, which in turn claims the benefit of priority to U.S. Provisional Patent Application No. 63 / 282,549, entitled "Adaptive MVD for Single Reference," filed November 23, 2021, both of which are incorporated herein by reference in their entireties.

[0002] [Technical field] FIELD This disclosure relates generally to video coding, and more particularly to methods and systems that provide adaptive resolution for motion vector differentials in inter prediction of video blocks. [Background technology]

[0003] This background discussion provided herein is intended to generally present the context for the present disclosure. The work of the presently named inventors, to the extent that that work is described in this background section, is not admitted expressly or impliedly as prior art to the present disclosure, as are aspects of the description that are not admitted as prior art at the time of the filing of this application.

[0004] Video coding and decoding can be performed using inter-picture prediction with motion compensation. Uncompressed digital video can include a series of pictures, each with spatial dimensions of, for example, 1920 x 1080 luminance samples and associated full or subsampled chrominance samples. The series of pictures can have a fixed or variable picture rate (alternatively called a frame rate), for example, 60 pictures / second or 60 frames / second. Uncompressed video has specific bitrate requirements for streaming or data processing. For example, a video with a pixel resolution of 1920 x 1080, a frame rate of 60 frames / second, and chroma subsampling of 4:2:0 with 8 bits / pixel per color channel requires a bandwidth approaching 1.5 Gbit / second. One hour of such video requires over 600 gigabytes of storage space.

[0005] One goal of video coding and decoding can be to reduce redundancy in an uncompressed input video signal through compression. Compression can help reduce the aforementioned bandwidth and / or storage space requirements by more than two orders of magnitude, in some cases. Both lossless and lossy compression, and combinations of these, can be employed. Lossless compression refers to techniques in which an exact copy of the original signal can be reconstructed from the compressed original signal through the decoding process. Lossy compression refers to a coding / decoding process in which the original video information is not fully preserved during coding and is not fully recoverable during decoding. When using lossy compression, the reconstructed signal may not be identical to the original signal, but the distortion between the original and reconstructed signal is small enough to make the reconstructed signal useful for its intended application, despite some information loss. For video, lossy compression is widely adopted in many applications. The amount of acceptable distortion depends on the application. For example, users of a particular consumer video streaming application may tolerate higher distortion than users of a movie or television broadcast application. The compression ratio achievable by a particular coding algorithm can be selected or adjusted to reflect different distortion tolerances. Higher tolerable distortion generally allows for coding algorithms that result in higher loss and higher compression ratios.

[0006] Video encoders and decoders can utilize techniques from several broad categories and steps, including, for example, motion compensation, Fourier transforms, quantization, and entropy coding.

[0007] Video codec technology can include a technique known as intra-coding. In intra-coding, sample values ​​are represented without reference to samples or other data from previously reconstructed reference pictures. In some video codecs, a picture is spatially subdivided into blocks of samples. When all blocks of samples are coded in intra-mode, the picture may be called an intra-picture. Intra-pictures and their derivatives, such as independent decoder refresh pictures, can be used to reset the decoder state and thus can be used as the first picture in a coded video bitstream and video session, or as a still image. The samples of the block after intra-prediction can then undergo a transform to the frequency domain, and the transform coefficients so generated can be quantized before entropy coding. Intra-prediction refers to a technique that minimizes sample values ​​in the pre-transform domain. In some cases, the smaller the DC value and the smaller the AC coefficients after the transform, the fewer bits are required at a given quantization step size to represent the block after entropy coding.

[0008] For example, traditional intra-coding, such as that known from MPEG-2 generation coding techniques, does not use intra-prediction. However, some newer video compression techniques include techniques that attempt to code / decode a block based on surrounding sample data and / or metadata obtained during the encoding and / or decoding of its spatial neighbors and that precede the block of data being intra-coded or decoded in decoding order. Such techniques are hereinafter referred to as "intra-prediction" techniques. Note that, at least in some cases, intra-prediction uses only reference data from the current picture being reconstructed, and not reference data from other reference pictures.

[0009] Intra prediction can take many different forms. When two or more such techniques are available in a given video coding technique, the technique in use may be referred to as an intra prediction mode. A particular codec may provide one or more intra prediction modes. In certain cases, a mode may have sub-modes and / or may be associated with various parameters, and mode / sub-mode information and intra-coding parameters for a block of video may be coded individually or collectively included in a mode codeword. Which codeword to use for a given mode, sub-mode, and / or parameter combination may affect the coding efficiency gain from intra prediction, and therefore may also affect the entropy coding technique used to convert the codeword into a bitstream.

[0010] Certain modes of intra prediction were introduced in H.264, refined in H.265, and further refined in newer coding techniques such as joint search model (JEM), versatile video coding (VVC), and benchmark set (BMS). In general, for intra prediction, a predictor block may be formed using neighboring sample values ​​that become available. For example, available values ​​of a particular set of neighboring samples along a particular direction and / or line may be copied into the predictor block. A reference to the direction in use may be codeable in the bitstream or may itself be predicted.

[0011] Referring to FIG. 1A, shown at the bottom right is a subset of the nine predictor directions defined in the 33 possible intra-predictor directions of H.265 (corresponding to the 33 angle modes of the 35 intra-modes defined in H.265). The point where the arrows converge (101) represents the sample being predicted. The arrows represent the direction in which neighboring samples are used to predict sample 101. For example, arrow (102) indicates that sample (101) is predicted to the upper right and at a 45-degree angle from horizontal from one or more neighboring samples. Similarly, arrow (103) indicates that sample (101) is predicted to the lower left and at a 22.5-degree angle from horizontal from one or more neighboring samples.

[0012] Continuing with FIG. 1A, a square block (104) of 4×4 samples (indicated by a thick dashed line) is shown in the upper left. The square block (104) contains 16 samples, each labeled with "S" and its position in the Y dimension (e.g., row index) and its position in the X dimension (e.g., column index). For example, sample S21 is the second sample (from the top) in the Y dimension and the first sample (from the left) in the X dimension. Similarly, sample S44 is the fourth sample in the block (104) in both the Y and X dimensions. Because the block is 4×4 samples in size, S44 is located in the lower right. Also shown are exemplary reference samples that follow a similar numbering scheme. The reference samples are labeled R and their Y position (e.g., row index) and X position (column index) relative to the block (104). In both H.264 and H.265, predicted samples neighboring the block being reconstructed are used.

[0013] Intra-picture prediction of block 104 may begin by copying reference sample values ​​from neighboring samples according to the signaled prediction direction. For example, assume that the coded video bitstream includes signaling for this block 104 indicating the prediction direction of the arrow (102), i.e., the sample is predicted from one or more prediction samples at a 45-degree angle from the horizontal, to the upper right. In such a case, samples S41, S32, S23, and S14 are predicted from the same reference sample R05. And sample S44 is predicted from reference sample R08.

[0014] In certain cases, especially when the direction is not evenly divisible by 45 degrees, the values ​​of multiple reference samples may be combined, for example by interpolation, to calculate the reference sample.

[0015] As video coding technology continues to develop, the number of possible directions is increasing. For example, in H.264 (2003), nine different directions are available for intra prediction. This increased to 33 in H.265 (2013), and as of the time of this disclosure, JEM / VVC / BMS can support up to 65 directions. Experimental studies have been conducted to help identify the most appropriate intra prediction directions, and certain techniques in entropy coding can be used to encode these most appropriate directions with fewer bits while accepting certain bit penalties for the directions. Furthermore, the directions themselves can be predicted from neighboring directions used in the intra prediction of decoded neighboring blocks.

[0016] FIG. 1B shows a schematic diagram (180) illustrating 65 intra prediction directions according to JEM to illustrate the increasing number of prediction directions in various coding techniques developed over time.

[0017] Methods for mapping bits representing intra-prediction directions to prediction directions in a coded video bitstream may vary from video coding technique to technique, ranging, for example, from simple direct mapping of prediction directions to intra-prediction modes to codewords, complex adaptive schemes involving most-probable modes, and similar techniques. However, in all cases, there may be certain directions for intra-prediction that are statistically less likely to occur in the video content than certain other directions. Because the goal of video compression is to reduce redundancy, these less likely directions may be represented by more bits than more likely directions in a well-designed video coding technique.

[0018] Inter-picture prediction or inter-prediction may be based on motion compensation. In motion compensation, sample data from a previously reconstructed picture or part thereof (reference picture) may be used to predict a newly reconstructed picture or picture part (e.g., block) after being spatially shifted in a direction indicated by a motion vector (hereinafter, MV). In some cases, the reference picture may be the same as the picture currently being reconstructed. The MV may have two dimensions, X and Y, or three dimensions, with the third dimension indicating the reference picture in use (similar to the temporal dimension).

[0019] In some video compression techniques, the current MV applicable to a particular area of ​​sample data can be predicted from other MVs, e.g., from other MVs related to other areas of sample data that are spatially adjacent to the area being reconstructed and precede the current MV in decoding order. Doing so can substantially reduce the overall amount of data required to code the MV by relying on removing redundancy in the correlated MVs, thereby increasing compression efficiency. MV prediction can work effectively because, for example, when coding an input video signal derived from a camera (known as natural video), there is a statistical possibility that an area larger than the area to which a single MV is applicable will move in a similar direction in the video sequence, and therefore, in some cases, it can be predicted using similar motion vectors derived from MVs of neighboring areas. As a result, the actual MV of a given area will be similar or identical to the MV predicted from the surrounding MVs. Such an MV can be represented, after entropy coding, with fewer bits than would be used if the MV were coded directly rather than predicted from neighboring MV(s). In some cases, MV prediction can be an example of lossless compression of a signal (i.e., an MV) derived from the original signal (i.e., a sample stream). In other cases, the MV prediction itself may be lossy, for example due to rounding errors when computing the predictor from several surrounding MVs.

[0020] H.265 / HEVC (ITU-T Rec. H.265, “High Efficiency Video Coding”, December 2016) describes various MV prediction mechanisms. Among the many MV prediction mechanisms specified by H.265, the one described below is a technique called “spatial merging” hereinafter.

[0021] Specifically, referring to Figure 2, a current block (201) contains samples that the encoder discovered during the motion search process to be predictable from a spatially shifted previous block of the same size. Instead of coding its MV directly, the MV may be derived from metadata associated with one or more reference pictures, e.g., the most recent reference picture (in decoding order), using the MV associated with any one of five surrounding samples, denoted A0, A1, and B0, B1, B2 (202-206, respectively). In H.265, MV prediction can use predictors from the same reference picture as neighboring blocks. Summary of the Invention

[0022]

[0001] This disclosure relates generally to video coding, and more particularly to methods and systems for providing and signaling adaptive resolution for motion vector differentials in inter prediction of video blocks. In an example implementation, a method for decoding one or more video blocks of a video stream is disclosed. The method may include receiving a video stream; extracting an inter prediction syntax element from the video stream to determine whether an ADAPTMV mode is signaled for one or more video blocks, where the ADAPTMV mode is a single-reference inter prediction mode with adaptive motion vector differential (MVD) pixel resolution; determining a current MVD pixel resolution associated with the one or more video blocks based on whether the ADAPTMV mode is signaled in the inter prediction syntax element; and extracting and decoding one or more MVD-related syntax elements associated with the one or more video blocks based on whether the ADAPTMV mode is signaled in the inter prediction syntax element and further based on the current MVD pixel resolution.

[0023] In the above example implementations, inter-prediction syntax elements are signaled in the video stream after inter-prediction reference frame indexes associated with one or more video blocks are signaled.

[0024] In any of the above example implementations, the inter prediction syntax element is configured to indicate one of the following single-reference inter prediction modes: ADAPTMV mode, NEWMV mode, which is a single-reference inter prediction mode with non-adaptive MVD pixel resolution, NEARMV mode, which is a single-reference inter prediction mode in which motion vectors are predicted directly without motion vector differentials, and GLOBALMV mode, which is a single-reference inter prediction mode in which motion vectors are predicted using a set of global motion parameters.

[0025] In any of the above example implementations, the context for decoding the ADAPTMV mode in the inter prediction syntax element is shared with the decoding of the NEWMV mode, the NEARMV mode, and the GLOBALMV mode.

[0026] In any of the above example implementations, the method further includes deriving one or more contexts for decoding one or more MVD-related syntax elements based on whether ADAPTMV mode is signaled in the inter-prediction syntax element.

[0027] In any of the above example implementations, the one or more MVD-related syntax elements include a first MVD syntax element for indicating which MVD components are non-zero, and at least one of a second MVD syntax element for specifying an MVD code, a third MVD syntax element for specifying an MVD magnitude range, a fourth MVD syntax element for specifying an integer MVD magnitude offset within the MVD magnitude range, or a fifth MVD syntax element for specifying an MVD pixel resolution.

[0028] In any of the above example implementations, when one or more video blocks are coded in ADAPTMV mode, a first context is derived to decode the first MVD syntax element or the third MVD syntax element, and when one or more video blocks are coded in an inter-prediction mode other than ADAPTMV mode, a second context different from the first context is derived to decode the first MVD syntax element or the third MVD syntax element.

[0029] In any of the above example implementations, the current MVD pixel resolution associated with one or more video blocks is 2 n Pell (2 n pixels), where n is an integer between -6 and 11, inclusive.

[0030] In any of the above example implementations, the method further includes deriving an MVD magnitude range associated with one or more video blocks from the video stream, and fractional MVD pixel resolution is allowed only when the MVD magnitude is less than or equal to a predetermined threshold MVD magnitude.

[0031] In any of the above example implementations, the allowed MVD pixel resolutions correspond to different MVD magnitudes in non-ascending order.

[0032] In any of the above example implementations, the method further includes obtaining, from the video stream, an MVD class index for specifying an MVD magnitude range associated with one or more video blocks.

[0033] In any of the above example implementations, fractional MVD pixel resolution is allowed only when the MVD class index is less than or equal to a predetermined threshold MVD class index.

[0034] In any of the above example implementations, MVD class indices greater than or equal to a predetermined threshold MVD class index are each associated with a single allowed integer MVD pixel resolution value.

[0035] In any of the above example implementations, the allowed MVD pixel resolutions correspond to different MVD class indices in non-ascending order.

[0036] In any of the above example implementations, the MVD pixel resolutions associated with different MVD class indices are distinct.

[0037] Aspects of the present disclosure also provide a video encoding or decoding device or apparatus that includes circuitry configured to perform any of the above method implementations.

[0038] Aspects of the present disclosure also provide a non-transitory computer-readable medium storing instructions that, when executed by a computer, cause the computer to perform a method for video decoding and / or encoding. [Brief explanation of the drawings]

[0039] Further features, nature and various advantages of the disclosed subject matter will become more apparent from the following detailed description and accompanying drawings. [Figure 1A] 1 shows a schematic diagram of an exemplary subset of intra-prediction direction modes. [Figure 1B] 1 shows a diagram of exemplary intra-prediction directions. [Figure 2] 1 illustrates a schematic diagram of a current block and its surrounding spatial merge candidates for motion vector prediction in one example. [Figure 3] 1 shows a simplified block diagram schematic of a communication system (300) according to an exemplary embodiment. [Figure 4] 4 shows a simplified block diagram of a communication system (400) according to an exemplary embodiment. [Figure 5] 1 shows a simplified block diagram schematic of a video decoder according to an example embodiment; [Figure 6] 1 shows a simplified block diagram schematic of a video encoder according to an example embodiment; [Figure 7] 1 shows a block diagram of a video encoder according to another example embodiment. [Figure 8] 10 shows a block diagram of a video decoder according to another example embodiment. [Figure 9] 1 illustrates a coding block partitioning scheme according to an exemplary embodiment of the present disclosure. [Figure 10] 10 illustrates another scheme for coding block partitioning according to an exemplary embodiment of the present disclosure. [Figure 11] 10 illustrates another scheme for coding block partitioning according to an exemplary embodiment of the present disclosure. [Figure 12] 1 illustrates an exemplary partitioning of a base block into coding blocks according to an exemplary partitioning scheme. [Figure 13] 1 illustrates an exemplary ternary partitioning scheme. [Figure 14] 1 illustrates an exemplary quadtree / binary tree coding block partitioning scheme. [Figure 15] 1 illustrates a scheme for partitioning a coding block into multiple transform blocks and a coding order of the transform blocks, according to an example embodiment of this disclosure. [Figure 16] 1 illustrates another scheme for partitioning a coding block into multiple transform blocks and the coding order of the transform blocks, according to an example embodiment of this disclosure. [Figure 17] 10 illustrates another scheme for partitioning a coding block into multiple transform blocks, according to an example embodiment of the present disclosure. [Figure 18] 1 shows a flowchart of a method according to an exemplary embodiment of the present disclosure. [Figure 19] 1 shows a schematic diagram of a computer system according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0040] Throughout this specification and claims, terms may have nuanced meanings suggested or implied in context beyond their explicitly stated meanings. The phrases "in one embodiment" or "in some embodiments" used herein do not necessarily refer to the same embodiment, and the phrases "in another embodiment" or "in other embodiments" used herein do not necessarily refer to different embodiments. Similarly, the phrases "in one implementation" or "in some implementations" used herein do not necessarily refer to the same implementation, and the phrases "in another implementation" or "in other implementations" used herein do not necessarily refer to different implementations. For example, the claimed subject matter is intended to include, in whole or in part, a combination of example embodiments / implementations.

[0041] Generally, terms can be understood at least in part from their usage in context. For example, terms such as "and," "or," or "and / or" used herein can include a variety of meanings that may depend, at least in part, on the context in which such terms are used. Typically, when "or" is used to relate a list, such as A, B, or C, it is intended to mean A, B, and C (used here in an inclusive sense) as well as A, B, or C (used here in an exclusive sense). Additionally, the terms "one or more" or "at least one" used herein may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a combination of features, structures, or characteristics in a plural sense, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" may be understood to convey a singular sense or to convey a plural sense, again depending, at least in part, on the context. Additionally, it may be understood that the terms "based on" or "determined by" are not intended to convey an exclusive set of factors, but instead may allow for the existence of additional factors not necessarily explicitly described, again depending at least in part on the context. FIG. 3 illustrates a simplified block diagram of a communication system (300) according to one embodiment of the present disclosure. The communication system (300) includes multiple terminal devices capable of communicating with each other, e.g., via a network (350). For example, the communication system (300) includes a first pair of terminal devices (310) and (320) interconnected via the network (350). In the example of FIG. 3, the first pair of terminal devices (310) and (320) may perform unidirectional transmission of data. For example, the terminal device (310) may code video data (e.g., of a stream of video pictures captured by the terminal device (310)) for transmission to the other terminal device (320) via the network (350).The encoded video data may be transmitted in the form of one or more coded video bitstreams. The terminal device (320) may receive the coded video data from the network (350), decode the coded video data to recover video pictures, and display the video pictures according to the recovered video data. The unidirectional data transmission may be implemented in a media serving application, etc.

[0042] In another example, the communication system (300) includes a second pair of terminal devices (330) and (340) performing bidirectional transmission of coded video data, which may be implemented, for example, in a videoconferencing application. For the bidirectional transmission of data, in one example, each of the terminal devices (330) and (340) may code video data (e.g., of a stream of video pictures captured by the terminal device) for transmission to the other of the terminal devices (330) and (340) over the network (350). Each of the terminal devices (330) and (340) may also receive coded video data transmitted by the other of the terminal devices (330) and (340), decode the coded video data to recover the video pictures, and display the video pictures on an accessible display device according to the recovered video data.

[0043] In the example of FIG. 3 , the terminal devices (310), (320), (330), and (340) may be implemented as a server, a personal computer, and a smartphone, but the applicability of the underlying principles of the present disclosure need not be so limited. Embodiments of the present disclosure may be implemented in desktop computers, laptop computers, tablet computers, media players, wearable computers, dedicated videoconferencing equipment, and / or the like. The network (350) represents any number or type of network that conveys coded video data between the terminal devices (310), (320), (330), and (340), including, for example, wireline and / or wireless communication networks. The communication network (350) may exchange data over circuit-switched, packet-switched, and / or other types of channels. Exemplary networks include telecommunications networks, local area networks, wide area networks, and / or the Internet. For purposes of this description, the architecture and topology of the network (350) may not be important to the operation of the present disclosure unless explicitly described herein.

[0044] 4 illustrates the arrangement of a video encoder and a video decoder in a video streaming environment as an example of an application of the disclosed subject matter. The disclosed subject matter may be equally applicable to other video applications, including, for example, video conferencing, digital TV broadcasting, gaming, virtual reality, storage of compressed video on digital media including CDs, DVDs, memory sticks, etc.

[0045] A video streaming system may include a video source (401), such as a video capture subsystem (413), which may include a digital camera, for creating a stream of uncompressed video pictures or images (402). In one example, the stream of video pictures (402) includes samples recorded by the digital camera of the video source 401. The stream of video pictures (402), shown in bold to emphasize its high data volume compared to the encoded video data (404) (or coded video bitstream), may be processed by an electronic device (420) including a video encoder (403) coupled to the video source (401). The video encoder (403) may include hardware, software, or a combination thereof for enabling or implementing aspects of the disclosed subject matter, as described in more detail below. The coded video data (404) (or coded video bitstream (404)), shown with thin lines to emphasize its low data volume compared to the stream of uncompressed video pictures (402), may be stored on the streaming server (405) for future use or directly stored on a downstream video device (not shown). One or more streaming client subsystems, such as the client subsystems (406) and (408) of FIG. 4, can access the streaming server (405) to retrieve copies (407) and (409) of the coded video data (404). The client subsystem (406) may include a video decoder (410), for example, within the electronic device (430). The video decoder (410) decodes the incoming copy of the coded video data (407) and creates an outgoing stream of video pictures (411) that is uncompressed and can be rendered on a display (412) (e.g., a display screen) or other rendering device (not shown). Video decoder 410 may be configured to perform some or all of the various functions described in this disclosure.In some streaming systems, the encoded video data (404), (407), and (409) (e.g., video bitstreams) may be encoded according to a particular video coding / compression standard. Examples of such standards include ITU-T Recommendation H.265. In one example, a video coding standard under development is informally known as Versatile Video Coding (VVC). The disclosed subject matter may be used in the context of VVC and other video coding standards.

[0046] It should be noted that the electronic devices (420) and (430) may include other components (not shown). For example, the electronic device (420) may include a video decoder (not shown), and similarly, the electronic device (430) may include a video encoder (not shown).

[0047] 5 shows a block diagram of a video decoder (510) according to any of the following embodiments of the present disclosure. The video decoder (510) may be included in an electronic device (530). The electronic device (530) may include a receiver (531) (e.g., a receiving circuit). The video decoder (510) may be used in place of the video decoder (410) in the example of FIG. 4.

[0048] The receiver (531) may receive one or more coded video sequences to be decoded by the video decoder (510). In the same or another embodiment, one coded video sequence may be decoded at a time, where the decoding of each coded video sequence is independent of the other coded video sequences. Each video sequence may be associated with multiple video frames or images. The coded video sequences may be received from a channel (501), which may be a hardware / software link to a storage device that stores the coded video data or a streaming source that transmits the coded video data. The receiver (531) may receive the coded video data along with other data, such as coded audio data and / or auxiliary data streams, which may be forwarded to their respective processing circuits (not shown). The receiver (531) may separate the coded video sequences from other data. To combat network jitter, a buffer memory (515) may be disposed between the receiver (531) and the entropy decoder / parser (520) (hereinafter, "parser (520)"). In certain applications, the buffer memory (515) may be implemented as part of the video decoder (510). In other applications, it may be external to and separate from the video decoder (510) (not shown). In still other applications, there may be a buffer memory (not shown) external to the video decoder (510), for example, to combat network jitter, and there may be another additional buffer memory (515) internal to the video decoder (510), for example, to handle playback timing. When the receiver (531) is receiving data from a storage / forwarding device with sufficient bandwidth and controllability or from an isochronous network, the buffer memory (515) may not be needed or may be small. For use on a best-effort packet network such as the Internet, a sufficiently sized buffer memory (515) may be needed, and its size may be relatively large.Such a buffer memory may be implemented with an adaptive size and may be implemented at least in part in an operating system or similar element (not shown) external to the video decoder (510).

[0049] The video decoder (510) may include a parser (520) for reconstructing symbols (521) from the coded video sequence. These symbol categories include information used to manage the operation of the video decoder (510) and, in some cases, information for controlling a rendering device, such as a display (512) (e.g., a display screen), which may or may not be an integral part of the electronic device (530) but may be coupled to the electronic device (530), as shown in FIG. 5. The control information for the rendering device(s) may be in the form of supplemental enhancement information (SEI messages) or video usability information (VUI) parameter set fragments (not shown). The parser (520) may parse / entropy decode the coded video sequence received by the parser (520). The entropy coding of the coded video sequence may follow a video coding technique or standard and may follow various principles, including variable length coding, Huffman coding, arithmetic coding with or without context sensitivity, etc. The parser (520) may extract, from the coded video sequence, a set of subgroup parameters for at least one of the subgroups of pixels in the video decoder based on at least one parameter corresponding to the subgroup. The subgroup may include a group of pictures (GOP), a picture, a tile, a slice, a macroblock, a coding unit (CU), a block, a transform unit (TU), a prediction unit (PU), etc. The parser (520) may also extract information from the coded video sequence, such as transform coefficients (e.g., Fourier transform coefficients), quantizer parameter values, motion vectors, etc.

[0050] The parser (520) may perform entropy decoding / parsing operations on the video sequence received from the buffer memory (515) to create symbols (521).

[0051] The reconstruction of the symbols (521) may involve several different processing or functional units, depending on the type of coded video picture or portion thereof (e.g., inter-picture and intra-picture, inter-block and intra-block, etc.), as well as other factors. The units involved and how they are included may be controlled by subgroup control information parsed from the coded video sequence by the parser (520). The flow of such subgroup control information between the parser (520) and the following several processing or functional units is not shown for simplicity.

[0052] Beyond the functional blocks already mentioned, the video decoder (510) may be conceptually subdivided into several functional units, as described below. In actual implementations operating under commercial constraints, many of these functional units may interact closely with each other and may be at least partially integrated with each other. However, for purposes of clearly describing the various functions of the disclosed subject matter, the following disclosure employs a conceptual subdivision into functional units.

[0053] The first unit may include a scalar / inverse transform unit (551). The scalar / inverse transform unit (551) may receive quantized transform coefficients and control information, including information indicating which type of inverse transform to use, block size, quantization factors / parameters, quantization scaling matrices, and lines as symbol(s) (521) from the parser (520). The scalar / inverse transform unit (551) may output blocks containing sample values ​​that may be input to an aggregator (555).

[0054] In some cases, the output samples of the scaler / inverse transform unit (551) may relate to intra-coded blocks, i.e., blocks that do not use prediction information from a previously reconstructed picture but can use prediction information from a previously reconstructed portion of the current picture. Such prediction information may be provided by the intra-picture prediction unit (552). In some cases, the intra-picture prediction unit (552) may generate blocks of the same size and shape as the block being reconstructed using surrounding block information already reconstructed and stored in the current picture buffer (558). The current picture buffer (558), for example, buffers partially reconstructed and / or fully reconstructed current pictures. In some implementations, the aggregator (555) may add, on a sample-by-sample basis, the prediction information generated by the intra-picture prediction unit (552) to the output sample information provided by the scaler / inverse transform unit (551).

[0055] In other cases, the output samples of the scalar / inverse transform unit (551) may relate to an inter-coded, possibly motion-compensated, block. In such cases, the motion-compensated prediction unit (553) may access a reference picture memory (557) to fetch samples used for inter-picture prediction. After motion-compensating the fetched samples according to the symbols (521) associated with the block, these samples may be added by an aggregator (555) to the output of the scalar / inverse transform unit (551) (the output of unit 551 may be referred to as a residual sample or residual signal) to generate output sample information. The addresses in the reference picture memory (557) from which the motion-compensated prediction unit (553) fetches prediction samples may be controlled by motion vectors available to the motion-compensated prediction unit (553), for example, in the form of symbols (521) that may have X and Y components (shift), and a reference picture component (time). Motion compensation may also include interpolation of sample values ​​as fetched from a reference picture memory (557) when sub-sample accurate motion vectors are used, and may also be associated with a motion vector prediction mechanism, etc.

[0056] The output samples of the aggregator (555) may undergo various loop filtering techniques in the loop filter unit (556). Video compression techniques may include in-loop filter techniques controlled by parameters contained in the coded video sequence (also called a coded video bitstream) and made available to the loop filter unit (556) as symbols (521) from the parser (520), but may also respond to meta-information obtained during decoding of a previous portion (in decoding order) of the coded picture or coded video sequence, or may respond to previously reconstructed and loop-filtered sample values. Several types of loop filters may be included as part of the loop filter unit 556, in various orders, as described in further detail below.

[0057] The output of the loop filter unit (556) can be a sample stream that can be output to a rendering device (512) and stored in a reference picture memory (557) for use in future inter-picture prediction.

[0058] Once a particular coded picture is fully reconstructed, it can be used as a reference picture for future inter-picture prediction. For example, once the coded picture corresponding to the current picture is fully reconstructed and the coded picture is identified as a reference picture (e.g., by the parser (520)), the current picture buffer (558) can become part of the reference picture memory (557), and a new current picture buffer can be reallocated before beginning reconstruction of the next coded picture.

[0059] The video decoder (510) may perform decoding operations according to a predetermined video compression technique adopted in a standard such as ITU-T Rec. H.265. A coded video sequence may conform to the syntax specified by the video compression technique or standard being used, in the sense that the coded video sequence conforms to both the syntax of the video compression technique or standard and the profile documented in the video compression technique or standard. Specifically, a profile may select a specific tool from all tools available in the video compression technique or standard as the only tool available for use under that profile. To comply with a standard, the complexity of the coded video sequence may be within a range defined by the level of the video compression technique or standard. In some cases, the level limits the maximum picture size, maximum frame rate, maximum reconstruction sample rate (e.g., measured in megasamples per second), maximum reference picture size, etc. The limits set by the level may, in some cases, be further restricted through a hypothetical reference decoder (HRD) specification and metadata for HRD buffer management signaled in the coded video sequence.

[0060] In some exemplary embodiments, the receiver (531) may receive additional (redundant) data along with the encoded video. The additional data may be included as part of the coded video sequence(s). The additional data may be used by the video decoder (510) to properly decode the data and / or to more accurately reconstruct the original video data. The additional data may be in the form of, for example, temporal, spatial, or signal-to-noise ratio (SNR) enhancement layers, redundant slices, redundant pictures, forward error correction codes, etc.

[0061] 6 shows a block diagram of a video encoder (603) according to an exemplary embodiment of the present disclosure. The video encoder (603) may be included in an electronic device (620). The electronic device (620) may further include a transmitter (640) (e.g., a transmitting circuit). The video encoder (603) may be used in place of the video encoder (403) in the example of FIG. 4.

[0062] The video encoder (603) may receive video samples from a video source (601) (which is not part of the electronic device (620) in the example of FIG. 6) that may capture video image(s) to be coded by the video encoder (603). In another example, the video source (601) may be implemented as part of the electronic device (620).

[0063] The video source (601) may provide a source video sequence to be coded by the video encoder (603) in the form of a digital video sample stream, which may be of any suitable bit depth (e.g., 8-bit, 10-bit, 12-bit, ...), any color space (e.g., BT.601 YCrCb, RGB, XYZ, ...), and any suitable sampling structure (e.g., YCrCb 4:2:0, YCrCb 4:4:4). In a media serving system, the video source (601) may be a storage device capable of storing previously prepared video. In a video conferencing system, the video source (601) may be a camera that captures local image information as a video sequence. The video data may be provided as multiple individual pictures or images that, when viewed sequentially, impart motion. The picture itself may be organized as a spatial array of pixels, where each pixel may contain one or more samples depending on the sampling structure, color space, etc., being used. Those skilled in the art can readily understand the relationship between pixels and samples. The following description focuses on samples.

[0064] According to some example embodiments, the video encoder (603) may code and compress pictures of a source video sequence into a coded video sequence (643) in real time or under any other time constraints required by the application. Implementing an appropriate coding rate constitutes one function of the controller (650). In some embodiments, the controller (650) may be functionally coupled to and control other functional units, as described below. Coupling is not shown for simplicity. Parameters set by the controller (650) may include rate control-related parameters (picture skip, quantizer, lambda value for rate-distortion optimization techniques, ...), picture size, group-of-picture (GOP) layout, maximum motion vector search range, etc. The controller (650) may be configured with other appropriate functions associated with the video encoder (603) optimized for a particular system design.

[0065] In some exemplary embodiments, the video encoder (603) may be configured to operate in a coding loop. As an oversimplified explanation, in one example, the coding loop may include a source coder (630) (e.g., responsible for creating symbols, such as a symbol stream, based on an input picture to be coded and reference picture(s)) and a (local) decoder (633) embedded in the video encoder (603). The decoder (633) reconstructs the symbols to create sample data in a manner similar to that created by a (remote) decoder, even if the embedded decoder 633 processed the coded video stream by the source coder 630 without entropy coding (because any compression between the symbols and the coded video bitstream in entropy coding may be lossless in the video compression techniques considered in the disclosed subject matter). The reconstructed sample stream (sample data) is input to a reference picture memory (634). Because decoding the symbol stream yields bit-exact results regardless of the location of the decoder (local or remote), the contents in the reference picture memory (634) are also bit-exact between the local and remote encoders. In other words, the predictive portion of the encoder "sees" the exact same sample values ​​as the reference picture samples that the decoder will "see" when using prediction during decoding. This fundamental principle of reference picture synchrony (and the resulting drift if synchrony cannot be maintained, for example, due to channel errors) is used to improve coding quality.

[0066] The operation of the "local" decoder (633) may be the same as that of a "remote" decoder, such as the video decoder (510) already described in detail above in connection with Figure 5. However, with brief reference also to Figure 5, because symbols are available and the encoding / decoding of symbols into a coded video sequence by the entropy coder (645) and parser (520) may be lossless, the entropy decoding portion of the video decoder (510), including the buffer memory (515) and parser (520), may not be fully implemented in the local decoder (633) within the encoder.

[0067] An observation that can be made at this point is that any decoder technology, with the exception of parsing / entropy decoding, which may only be present in the decoder, may necessarily also need to be present in the corresponding encoder in substantially identical functional form. For this reason, the disclosed subject matter may sometimes focus on decoder operations related to the decoding portion of the encoder. Therefore, descriptions of encoder technology may be omitted, as they are the reverse of the decoder technology described generically. Only in certain areas or aspects is a more detailed description of the encoder provided below.

[0068] During operation in some example implementations, the source coder (630) may perform motion-compensated predictive coding, which predictively codes an input picture with reference to one or more previously coded pictures from a video sequence designated as “reference pictures.” In this manner, the coding engine (632) codes differences (or residuals) in color channels between pixel blocks of the input picture and pixel blocks of reference picture(s) that may be selected as predictive reference(s) to the input picture. The terms “residue” and its adjective form “residual” may be used interchangeably.

[0069] The local video decoder (633) may decode coded video data of pictures that may be designated as reference pictures based on symbols created by the source coder (630). The operation of the coding engine (632) may advantageously be a lossy process. When the coded video data is decoded in a video decoder (not shown in FIG. 6), the reconstructed video sequence may typically be a replica of the source video sequence with some errors. The local video decoder (633) may replicate the decoding process that may be performed by the video decoder on the reference pictures and store the reconstructed reference pictures in a reference picture cache (634). In this way, the video encoder (603) may locally store copies of reconstructed reference pictures that have common content with reconstructed reference pictures obtained by a far-end (remote) video decoder (without transmission errors).

[0070] The predictor (635) may perform the predictive search of the coding engine (632). That is, for a new picture to be coded, the predictor (635) may search the reference picture memory (634) for sample data (as candidate reference pixel blocks) or specific metadata, such as reference picture motion vectors, block shapes, etc., that may serve as appropriate prediction references for the new picture. The predictor (635) may operate on a sample block-by-pixel block basis to find appropriate prediction references. In some cases, as determined by the search results obtained by the predictor (635), the input picture may have prediction references drawn from multiple reference pictures stored in the reference picture memory (634).

[0071] The controller (650) may manage the coding operations of the source coder (630), including, for example, setting parameters and subgroup parameters used to encode the video data.

[0072] The output of all the aforementioned functional units may undergo entropy coding in entropy coder 645. The entropy coder (645) converts the symbols produced by the various functional units into a coded video sequence by losslessly compressing the symbols according to techniques such as Huffman coding, variable length coding, or arithmetic coding.

[0073] The transmitter (640) may buffer the coded video sequence(s) created by the entropy coder (645) in preparation for transmission over a communication channel (660), which may be a hardware / software link to a storage device that stores the coded video data. The transmitter (640) may merge the coded video data from the video encoder (603) with other data to be transmitted, such as coded audio data and / or auxiliary data streams (sources not shown).

[0074] The controller (650) may manage the operation of the video encoder (603). During coding, the controller (650) may assign a particular coded picture type to each coded picture, which may affect the coding technique that may be applied to the respective picture. For example, pictures may often be assigned as one of the following picture types:

[0075] An intra picture (I-picture) may be one that can be coded and decoded without using other pictures in a sequence as a source of prediction. Some video codecs allow different types of intra pictures, including, for example, independent decoder refresh ("IDR") pictures. Those skilled in the art are aware of these variations of I-pictures, as well as their respective uses and characteristics.

[0076] A predicted picture (P picture) may be one that can be coded and decoded using intra- or inter-prediction, which uses at most one motion vector and reference index to predict the sample values ​​of each block.

[0077] Bidirectionally predicted pictures (B-pictures) may be those that can be coded and decoded using intra- or inter-prediction, which uses at most two motion vectors and reference indices to predict the sample values ​​of each block. Similarly, multiple-predictive pictures can use more than two reference pictures and associated metadata for the reconstruction of a single block.

[0078] A source picture is generally spatially subdivided into multiple sample coding blocks (e.g., blocks of 4x4, 8x8, 4x8, or 16x16 samples each) and may be coded block-by-block. Blocks may be predictively coded with reference to other (already coded) blocks, as determined by the coding assignment applied to the block's respective picture. For example, blocks of an I-picture may be non-predictively coded or predictively coded with reference to already coded blocks of the same picture (spatial prediction or intra-prediction). Pixel blocks of a P-picture may be predictively coded via spatial prediction or temporal prediction with reference to one previously coded reference picture. Blocks of a B-picture may be predictively coded via spatial prediction or temporal prediction with reference to one or two previously coded reference pictures. Source pictures or intermediate processed pictures may be subdivided into other types of blocks for other purposes. The division of coding blocks and other types of blocks may or may not follow the same method, as described in more detail below.

[0079] The video encoder (603) may perform coding operations according to a predetermined video coding technique or standard, such as ITU-T Rec. H.265. In doing so, the video encoder (603) may perform various compression operations, including predictive coding operations that exploit temporal and spatial redundancy in the input video sequence. Thus, the coded video data may conform to a syntax specified by the video coding technique or standard being used.

[0080] In some exemplary embodiments, the transmitter (640) may transmit additional data along with the coded video. The source coder (630) may include such data as part of the coded video sequence. The additional data may include temporal / spatial / SNR enhancement layers, other forms of redundant data such as redundant pictures and slices, SEI messages, VUI parameter set fragments, etc.

[0081] Video may be captured as multiple source pictures (video pictures) in a time sequence. Intra-picture prediction (often abbreviated as intra-prediction) exploits spatial correlation within a given picture, while inter-picture prediction exploits temporal or other correlation between pictures. For example, a particular picture being encoded / decoded, called the current picture, may be partitioned into blocks. When a block in the current picture is similar to a reference block in a previously coded and still buffered reference picture in the video, it may be coded by a vector called a motion vector. A motion vector points to a reference block in a reference picture and may have a third dimension that identifies the reference picture when multiple reference pictures are used.

[0082] In some exemplary embodiments, a bi-prediction technique may be used for inter-picture prediction. According to such a bi-prediction technique, two reference pictures, such as a first reference picture and a second reference picture, are used, both of which precede the current picture in the video in decoding order (but may be past or future, respectively, in display order). A block in the current picture may be coded by a first motion vector pointing to a first reference block in the first reference picture and a second motion vector pointing to a second reference block in the second reference picture. A block may be jointly predicted by a combination of the first reference block and the second reference block.

[0083] In addition, a merge mode technique may be used in inter-picture prediction to improve coding efficiency.

[0084] According to some exemplary embodiments of the present disclosure, prediction, such as inter-picture prediction and intra-picture prediction, is performed on a block-by-block basis. For example, a picture in a sequence of video pictures is partitioned into coding tree units (CTUs) for compression, and the CTUs in a picture may have the same size, such as 64x64 pixels, 32x32 pixels, or 16x16 pixels. In general, a CTU may include three parallel coding tree blocks (CTBs), i.e., one luma CTB and two chroma CTBs. Each CTU may be recursively quadtree-decomposed into one or more coding units (CUs). For example, a 64x64 pixel CTU may be divided into one CU of 64x64 pixels or four CUs of 32x32 pixels. One or more of the 32x32 blocks may each be further divided into four CUs of 16x16 pixels. In some exemplary embodiments, each CU may be analyzed during encoding to determine its prediction type from various prediction types, such as inter prediction or intra prediction. A CU may be divided into one or more prediction units (PUs) according to temporal and / or spatial predictability. Generally, each PU includes one luma prediction block (PB) and two chroma PBs. In one embodiment, prediction operations during coding (encoding / decoding) are performed on a prediction block-by-prediction block basis. The division of a CU into PUs (or PBs of different color channels) may be performed in various spatial patterns. For example, a luma or chroma PB may include a matrix of sample values ​​(e.g., luma values), such as 8x8 pixels, 16x16 pixels, 8x16 pixels, 16x8 samples, etc.

[0085] 7 shows a diagram of a video encoder (703) according to another exemplary embodiment of this disclosure. The video encoder (703) is configured to receive a processed block (e.g., a predictive block) of sample values ​​in a current video picture in a sequence of video pictures and encode the processed block into a coded picture that is part of a coded video sequence. The exemplary video encoder (703) may be used in place of the video encoder (403) in the example of FIG. 4.

[0086] For example, the video encoder (703) receives a matrix of sample values ​​for a processing block, such as a predictive block of 8x8 samples. The video encoder (703) then determines whether the processing block is best coded using intra-mode, inter-mode, or bi-predictive mode, e.g., using rate-distortion optimization (RDO). When it is determined that the processing block is coded in intra-mode, the video encoder (703) may encode the processing block into a coded picture using intra-prediction techniques, and when it is determined that the processing block is coded in inter-mode or bi-predictive mode, the video encoder (703) may encode the processing block into a coded picture using inter-prediction techniques or bi-prediction techniques, respectively. In some exemplary embodiments, merge mode may be used as a sub-mode of inter-picture prediction, in which a motion vector is derived from one or more motion vector predictors without the aid of coded motion vector components outside the predictors. In some other exemplary embodiments, there may be motion vector components applicable to the current block. Thus, the video encoder (703) may include components not explicitly shown in FIG. 7, such as a mode decision module, to determine the prediction mode of a processing block.

[0087] In the example of Figure 7, the video encoder (703) includes an inter-encoder (730), an intra-encoder (722), a residual calculator (723), a switch (726), a residual encoder (724), an overall controller (721), and an entropy encoder (725), coupled to each other as shown in the exemplary configuration of Figure 7.

[0088] The inter-encoder (730) is configured to receive samples of a current block (e.g., a processing block), compare the block with one or more reference blocks in a reference picture (e.g., blocks in previous and subsequent pictures in display order), generate inter-prediction information (e.g., a description of redundant information due to inter-coding techniques, motion vectors, merge mode information), and calculate an inter-prediction result (e.g., a predicted block) based on the inter-prediction information using any suitable technique. In some examples, the reference picture is a decoded reference picture decoded based on the coded video information using a decoding unit 633 embedded in the example encoder 603 of FIG. 6 (shown as residual decoder 728 of FIG. 7, as described in further detail below).

[0089] The intra encoder (722) is configured to receive samples of a current block (e.g., a processing block), compare the block with previously coded blocks in the same picture, generate transformed quantized coefficients, and possibly generate intra prediction information (e.g., intra prediction direction information according to one or more intra encoding techniques). The intra encoder (722) may calculate intra prediction results (e.g., predicted blocks) based on the intra prediction information and reference blocks in the same picture.

[0090] The overall controller (721) may be configured to determine overall control data and control other components of the video encoder (703) based on the overall control data. In one example, the overall controller (721) determines a prediction mode for a block and provides a control signal to the switch (726) based on the prediction mode. For example, if the prediction mode is intra-mode, the overall controller (721) controls the switch (726) to select an intra-mode result for use by the residual calculator (723) and controls the entropy encoder (725) to select intra-prediction information and include the intra-prediction information in the bitstream. If the prediction mode for the block is inter-mode, the overall controller (721) controls the switch (726) to select an inter-prediction result for use by the residual calculator (723) and controls the entropy encoder (725) to select inter-prediction information and include the inter-prediction information in the bitstream.

[0091] The residual calculator (723) may be configured to calculate a difference (residual data) between a received block and a prediction result for a block selected from the intra-encoder (722) or the inter-encoder (730). The residual encoder (724) may be configured to encode the residual data to generate transform coefficients. For example, the residual encoder (724) may be configured to transform the residual data from the spatial domain to the frequency domain to generate the transform coefficients. The transform coefficients then undergo a quantization process to obtain quantized transform coefficients. In various exemplary embodiments, the video encoder (703) also includes a residual decoder (728). The residual decoder (728) is configured to perform an inverse transform and generate decoded residual data. The decoded residual data can be used appropriately by the intra-encoder (722) and the inter-encoder (730). For example, the inter-encoder (730) can generate decoded blocks based on the decoded residual data and inter-prediction information, and the intra-encoder (722) can generate decoded blocks based on the decoded residual data and intra-prediction information. The decoded blocks are processed appropriately to generate decoded pictures, which can be buffered in a memory circuit (not shown) and used as reference pictures.

[0092] The entropy encoder (725) may be configured to format a bitstream to include the encoded blocks and perform entropy coding. The entropy encoder (725) may be configured to include various information in the bitstream. For example, the entropy encoder (725) may be configured to include overall control data, selected prediction information (e.g., intra-prediction information or inter-prediction information), residual information, and other appropriate information in the bitstream. When coding a block in a merged sub-mode of either an inter mode or a bi-prediction mode, the residual information may be absent.

[0093] 8 shows a diagram of an exemplary video decoder (810) according to another embodiment of the present disclosure. The video decoder (810) is configured to receive coded pictures that are part of a coded video sequence and decode the coded pictures to generate reconstructed pictures. In one example, the video decoder (810) may be used in place of the video decoder (410) in the example of FIG. 4.

[0094] In the example of Figure 8, the video decoder (810) includes an entropy decoder (871), an inter-decoder (880), a residual decoder (873), a reconstruction module (874), and an intra-decoder (872), coupled to each other as shown in the exemplary configuration of Figure 8.

[0095] The entropy decoder (871) may be configured to reconstruct, from a coded picture, certain symbols representing syntax elements that make up the coded picture. Such symbols may include, for example, prediction information (e.g., intra- or inter-prediction information) that may identify the mode in which the block is coded (e.g., intra-mode, inter-mode, bi-prediction mode, merged sub-mode, or another sub-mode), certain samples or metadata used for prediction by the intra decoder (872) or inter decoder (880), residual information in the form of quantized transform coefficients, etc. In one example, if the prediction mode is an inter-mode or bi-prediction mode, the inter-prediction information is provided to the inter decoder (880), and if the prediction type is an intra-prediction type, the intra-prediction information is provided to the intra decoder (872). The residual information may undergo inverse quantization and be provided to the residual decoder (873).

[0096] The inter decoder (880) may be configured to receive inter prediction information and generate inter prediction results based on the inter prediction information.

[0097] The intra decoder (872) may be configured to receive intra prediction information and generate a prediction result based on the intra prediction information.

[0098] The residual decoder (873) may be configured to perform inverse quantization to extract dequantized transform coefficients and process the dequantized transform coefficients to transform the residual from the frequency domain to the spatial domain. The residual decoder (873) may also utilize certain control information (to include quantizer parameters (QP)), which may be provided by the entropy decoder (871) (data path not shown, as this may be only low-data-volume control information).

[0099] The reconstruction module (874) may be configured to combine, in the spatial domain, the residual output by the residual decoder (873) with the prediction results (output by the inter-prediction module or the intra-prediction module, as the case may be) to form reconstructed blocks that form part of the reconstructed picture as part of the reconstructed video. It should be noted that other appropriate operations, such as deblocking operations, may also be performed to improve visual quality.

[0100] It should be noted that the video encoders (403), (603), and (703) and the video decoders (410), (510), and (810) may be implemented using any suitable technique. In some exemplary embodiments, the video encoders (403), (603), and (703) and the video decoders (410), (510), and (810) may be implemented using one or more integrated circuits. In another embodiment, the video encoders (403), (603), and (703) and the video decoders (410), (510), and (810) may be implemented using one or more processors executing software instructions.

[0101] Turning to block partitioning for coding and decoding, general partitioning may start from a base block and may follow a predefined set of rules, a specific pattern, a partition tree, or any partition structure or scheme. The partitioning may be hierarchical and recursive. After dividing or partitioning the base block according to the exemplary partitioning procedure or any of the other procedures described below, or a combination thereof, a final set of partitions or coding blocks may be obtained. Each of these partitions may be at one of various partitioning levels in the partitioning hierarchy and may be of various shapes. Each partition may be referred to as a coding block (CB). For various exemplary partitioning implementations described further below, each resulting CB may be of any of the allowed sizes and partitioning levels. Such partitions are referred to as coding blocks because they may form the unit at which some basic coding / decoding decisions may be made, coding / decoding parameters may be optimized, determined, and signaled in the coded video bitstream. The highest or deepest level of the final partition represents the depth of the coding block partitioning structure in the tree. The coding block may be a luma coding block or a chroma coding block. The CB tree structure for each color may be referred to as a coding block tree (CBT).

[0102] The coding blocks of all color channels may be collectively referred to as a coding unit (CU). The hierarchical structure of all color channels may be collectively referred to as a coding tree unit (CTU). The partitioning pattern or structure for various color channels in a CTU may or may not be the same.

[0103] In some implementations, the partition tree scheme or structure used for the luma channel and the chroma channel may not be the same. In other words, the luma channel and the chroma channel may have separate coding tree structures or patterns. Furthermore, whether the luma channel and the chroma channel use the same or different coding partition tree structures, and the actual coding partition tree structure to be used, may depend on whether the slice being coded is a P slice, a B slice, or an I slice. For example, for an I slice, the chroma channel and the luma channel may have separate coding partition tree structures or coding partition tree structure modes, while for a P or B slice, the luma channel and the chroma channel may share the same coding partition tree scheme. When separate coding partition tree structures or modes are applied, the luma channel may be partitioned into CBs by one coding partition tree structure, and the chroma channel may be partitioned into chroma CBs by another coding partition tree structure.

[0104] In some example implementations, a predetermined partitioning pattern may be applied to the base block. As shown in FIG. 9, an example four-way partition tree may start at a first predefined level (e.g., a 64x64 block level or other size as the base block size), and the base block may be partitioned hierarchically down to a predefined lowest level (e.g., a 4x4 level). For example, the base block may receive four predefined partitioning options or patterns indicated by 902, 904, 906, and 908, and a partition designated as R allows recursive partitioning in that the same partitioning option shown in FIG. 9 may be repeated at a lower scale down to the lowest level (e.g., a 4x4 level). In some implementations, additional restrictions may be applied to the partitioning scheme of FIG. 9. In the implementation of FIG. 9, rectangular partitions (e.g., 1:2 / 2:1 rectangular partitions) may be allowed, but they may not be allowed to be recursive, whereas square partitions are allowed to be recursive. Partitioning according to FIG. 9 with recursion generates a final set of coding blocks, if necessary. A coding tree depth may be further defined to indicate the division depth from the root node or root block. For example, the coding tree depth for a root node or root block, e.g., a 64×64 block, may be set to 0, and after the root block is further divided according to FIG. 9, the coding tree depth is increased by 1. The maximum or deepest level from the 64×64 base block to the smallest 4×4 partition is 4 (starting from level 0) in the above scheme. Such a partitioning scheme may be applied to one or more of the color channels. Each color channel may be partitioned independently according to the scheme of FIG. 9 (e.g., partitioning patterns or options among predefined patterns may be determined independently for each of the color channels at each hierarchical level).Alternatively, two or more of the color channels may share the same hierarchical pattern tree as in FIG. 9 (e.g., the same partitioning pattern or options between predefined patterns may be chosen for two or more color channels at each hierarchical level).

[0105] FIG. 10 illustrates another exemplary predefined partitioning pattern that allows recursive partitioning to form a partitioning tree. As shown in FIG. 10, an exemplary 10-way partitioning structure or pattern may be predefined. A root block may start at a predefined level (e.g., from a base block at the 128×128 level or the 64×64 level). The exemplary partitioning structure of FIG. 10 includes various 2:1 / 1:2 and 4:1 / 1:4 rectangular partitions. A partition type with three subpartitions, indicated by 1002, 1004, 1006, and 1008 in the second row of FIG. 10, may be referred to as a “T” partition. The “T” partitions 1002, 1004, 1006, and 1008 may be referred to as a left T, an upper T, a right T, and a lower T. In some exemplary implementations, none of the rectangular partitions of FIG. 10 allow further subdivision. A coding tree depth may be further defined to indicate the division depth from the root node or root block. For example, the coding tree depth for a root node or root block, e.g., a 128x128 block, may be set to 0, and after the root block is further divided according to FIG. 10, the coding tree depth is increased by 1. In some implementations, only the full square partition at 1010 may be allowed for recursive partitioning to the next level of the partitioning tree according to the pattern of FIG. 10. In other words, recursive partitioning may not be allowed for square partitions within the T-shaped patterns 1002, 1004, 1006, and 1008. The partitioning procedure according to FIG. 10 with recursion generates a final set of coding blocks as needed. Such a scheme may be applied to one or more of the color channels. In some implementations, more flexibility may be added to the use of partitions below the 8x8 level. For example, 2x2 chroma inter prediction may be used in certain cases.

[0106] In some other example implementations for coding block partitioning, a quadtree structure may be used to divide a base block or an intermediate block into quadtree partitions. Such quadtree division may be applied hierarchically and recursively to any square partition. Whether a base block or an intermediate block or partition is further quadtree divided may be adapted to various local characteristics of the base block or intermediate block / partition. Quadtree partitioning at picture boundaries may be further adapted. For example, implicit quadtree division may be performed at picture boundaries so that blocks continue to be quadtree divided until their size fits into the picture boundaries.

[0107] In some other example implementations, hierarchical binary partitioning from a base block may be used. In such a scheme, a base block or an intermediate-level block may be partitioned into two partitions. The binary partitioning may be either horizontal or vertical. For example, horizontal binary partitioning may divide a base block or an intermediate block into equal right and left partitions. Similarly, vertical binary partitioning may divide a base block or an intermediate block into equal upper and lower partitions. Such binary partitioning may be hierarchical and recursive. At each base block or intermediate block, a decision may be made as to whether the binary partitioning scheme should continue, and if the scheme continues further, whether horizontal or vertical binary partitioning should be used. In some implementations, further partitioning may stop at a predefined minimum partition size (in one or both dimensions). Alternatively, further partitioning may stop upon reaching a predefined partitioning level or depth from the base block. In some implementations, the aspect ratio of the partitions may be limited. For example, the aspect ratio of a partition will not be smaller than 1:4 (or larger than 4:1), so a vertical strip partition with a 4:1 vertical-to-horizontal aspect ratio may be further binary partitioned vertically only into an upper partition and a lower partition, each with a 2:1 vertical-to-horizontal aspect ratio.

[0108] In yet some other examples, a ternary partitioning scheme may be used to partition the base block or any intermediate blocks, as shown in FIG. 13 . The ternary pattern may be implemented vertically, as shown at 1302 in FIG. 13 , or horizontally, as shown at 1304 in FIG. 13 . The exemplary division ratio in FIG. 13 is shown as 1:2:1 vertically or horizontally, but other ratios may be predefined. In some implementations, two or more different ratios may be predefined. While quadtrees and binary trees always divide along block centers, resulting in objects being divided into separate partitions, such ternary partitioning schemes may be used to complement quadtree or binary tree partitioning structures in that such ternary tree partitioning can capture objects located at block centers within one contiguous partition. In some implementations, the width and height of the exemplary ternary tree partitions are always powers of two to avoid additional transformations.

[0109] The above partitioning schemes may be combined in any manner at different partitioning levels. As an example, the quadtree and binary partitioning schemes described above may be combined to partition a base block into a quadtree-binary tree (QTBT) structure. In such a scheme, the base block or intermediate blocks / partitions, if specified, may be either quadtree-partitioned or binary-partitioned according to a set of predefined conditions. A specific example is shown in FIG. 14. In the example of FIG. 14, the base block is first quadtree-partitioned into four partitions, as shown by 1402, 1404, 1406, and 1408. Each of the resulting partitions is then either quadtree-partitioned into four further partitions (such as 1408), binary-partitioned into two further partitions at the next level (e.g., 1402 or 1406, both symmetrical, horizontally or vertically), or not partitioned (1404). Binary or quadtree partitioning may be recursively allowed for square partitions, as shown by the overall exemplary partition pattern in 1410 and the corresponding tree structure / representation in 1420, where solid lines represent quadtree partitioning and dashed lines represent binary partitioning. A flag may be used for each binary partition node (non-leaf binary partition) to indicate whether the binary partitioning is horizontal or vertical. For example, as shown in 1420, consistent with the partitioning structure in 1410, a flag "0" may represent a horizontal binary partition and a flag "1" may represent a vertical binary partition. For quadtree partitioned partitions, there is no need to indicate the partition type, since quadtree partitioning always divides a block or partition both horizontally and vertically to generate four sub-blocks / partitions of equal size. In some implementations, a flag "1" may represent a horizontal binary partition and a flag "0" may represent a vertical binary partition.

[0110] In some example implementations of QTBT, the quadtree and binary splitting rule sets may be represented by the following predefined parameters and their associated corresponding functions: - CTU size: quadtree root node size (base block size) - MinQTSize: Minimum allowed quadtree leaf node size - MaxBTSize: Maximum allowed binary tree root node size - MaxBTDepth: Maximum allowed binary tree depth - MinBTSize: The minimum allowable binary tree leaf node size In some example implementations of the QTBT partitioning structure, the CTU size may be set as 128x128 luma samples with two corresponding 64x64 blocks of chroma samples (when considering and using example chroma subsampling), MinQTSize may be set as 16x16, MaxBTSize may be set as 64x64, MinBTSize (both width and height) may be set as 4x4, and MaxBTDepth may be set as 4. Quadtree partitioning may first be applied to the CTU to generate quadtree leaf nodes. The quadtree leaf nodes may have sizes from its minimum allowed size of 16x16 (i.e., MinQTSize) to 128x128 (i.e., CTU size). If a node is 128x128, it will not be initially split by the binary tree because its size exceeds MaxBTSize (i.e., 64x64). Otherwise, nodes that do not exceed MaxBTSize may be partitioned by binary tree. In the example of Figure 14, the base block is 128x128. The base block can only be quadtree partitioned according to a predefined set of rules. The base block has a partitioning depth of 0. Each of the resulting four partitions is 64x64, does not exceed MaxBTSize, and can be further quadtree or binary tree partitioned at level 1. The process continues. When the binary tree depth reaches MaxBTDepth (i.e., 4), no further partitions will be considered. When a binary tree node has a width equal to MinBTSize (i.e., 4), no further horizontal partitions will be considered. Similarly, when the height of a binary tree node is equal to MinBTSize, no further vertical partitions will be considered.

[0111] In some example implementations, the above QTBT scheme may be configured to support flexibility for luma and chroma to have the same or separate QTBT structures. For example, for P slices and B slices, the luma CTB and chroma CTB in one CTU may share the same QTBT structure. However, for I slices, the luma CTB may be partitioned into CBs by a QTBT structure, and the chroma CTB may be partitioned into chroma CBs by a different QTBT structure. This means that CUs may be used to refer to different color channels in an I slice; for example, an I slice may consist of one luma component coding block or two chroma component coding blocks, and a CU in a P slice or B slice may consist of all three color component coding blocks.

[0112] In some other implementations, the QTBT scheme may be supplemented with the ternary scheme described above. Such implementations may be referred to as multi-type tree (MTT) structures. For example, in addition to binary partitioning of nodes, one of the ternary partition patterns in FIG. 13 may be chosen. In some implementations, only square nodes may be subject to ternary partitioning. An additional flag may be used to indicate whether the ternary partitioning is horizontal or vertical.

[0113] The design of two-level or multi-level trees, such as QTBT implementations and QTBT implementations supplemented by ternary partitioning, may be primarily motivated by complexity reduction. In theory, the complexity of traversing a tree is reduced by T D where T denotes the number of split types and D is the depth of the tree. Trade-offs can be made by using multiple types (T) while reducing the depth (D).

[0114] In some implementations, the CB may be further partitioned. For example, the CB may be further partitioned into multiple prediction blocks (PBs) for the purpose of intra- or inter-frame prediction during the coding and decoding process. In other words, the CB may be further divided into different subpartitions at which individual prediction decisions / configurations may be made. In parallel, the CB may be further partitioned into multiple transform blocks (TBs) for the purpose of delineating the level at which a transform or inverse transform of video data is performed. The partitioning scheme of the CB into PBs and TBs may be the same or different. For example, each partitioning scheme may be performed using its own procedure, for example, based on various characteristics of the video data. The PB and TB partitioning schemes may be independent in some exemplary implementations. The PB and TB partitioning schemes and boundaries may be correlated in some other exemplary implementations. In some implementations, for example, the TB may be partitioned into PB partitions, and in particular, the PB may be further partitioned into one or more TBs after being determined according to the partitioning of the coding blocks. For example, in some implementations, the PB may be divided into one, two, four, or some other number of TBs.

[0115] In some implementations, the luma channel and the chroma channels may be treated differently for partitioning base blocks into coding blocks and further partitioning into prediction blocks and / or transform blocks. For example, in some implementations, partitioning of coding blocks into prediction blocks and / or transform blocks may be allowed for the luma channel, but such partitioning of coding blocks into prediction blocks and / or transform blocks may not be allowed for the chroma channel(s). In such implementations, transform and / or prediction of luma blocks may thus be performed only at the coding block level. In another example, the minimum transform block sizes for the luma channel and the chroma channel(s) may be different, e.g., coding blocks for the luma channel may be allowed to be partitioned into smaller transform and / or prediction blocks than the chroma channels. As yet another example, the maximum depth of partitioning of a coding block into transform blocks and / or prediction blocks may differ between the luma channel and the chroma channels; for example, a coding block for a luma channel may be allowed to be partitioned into deeper transform and / or prediction blocks than a chroma channel(s). In a specific example, a luma coding block may be partitioned into transform blocks of multiple sizes, which can be expressed with recursive partitions down up to two levels, and transform block shapes such as square, 2:1 / 1:2, and 4:1 / 1:4, as well as transform block sizes from 4×4 to 64×64, may be allowed. However, for chroma blocks, only the largest possible transform block specified for the luma block may be allowed.

[0116] In some example implementations for dividing a coding block into PBs, the depth, shape, and / or other characteristics of the PB partitioning may depend on whether the PB is intra-coded or inter-coded.

[0117] Partitioning of coding blocks (or prediction blocks) into transform blocks may be implemented in various exemplary manners, including, but not limited to, recursive or non-recursive quadtree partitioning and predefined pattern partitioning, with additional consideration of transform blocks at coding block or prediction block boundaries. In general, the resulting transform blocks may be at different partitioning levels, may not be the same size, and may not need to be square in shape (e.g., they may be rectangular with some allowed size and aspect ratio). Further examples are described in more detail below with respect to Figures 15, 16, and 17.

[0118] However, in some other implementations, the CB obtained through any of the above partitioning schemes may be used as a basic or minimum coding block for prediction and / or transform. In other words, no further partitioning is performed for inter-prediction / intra-prediction and / or transform purposes. For example, the CB obtained from the above QTBT scheme may be directly used as a unit for performing prediction. Specifically, such a QTBT structure eliminates the concept of multiple partition types, i.e., it eliminates the separation of CUs, PUs, and TUs, and supports more flexibility for CU / CB partition shapes as described above. In such a QTBT block structure, the CUs / CBs can have either square or rectangular shapes. The leaf nodes of such a QTBT are used as units for prediction and transform processing without further partitioning. This means that the CUs, PUs, and TUs have the same block size in such an exemplary QTBT coding block structure.

[0119] The various CB partitioning schemes described above, as well as further partitioning of the CB into PBs and / or TBs (including no PB / TB partitioning), may be combined in any manner. The following specific implementations are provided as non-limiting examples.

[0120] Specific exemplary implementations of coding block and transform block partitioning are described below. In such exemplary implementations, a base block may be divided into coding blocks using recursive quadtree partitioning or predefined partitioning patterns described above (such as those in FIGS. 9 and 10). At each level, whether to continue further quadtree partitioning of a particular partition may be determined by local video data characteristics. The resulting CBs may be at various quadtree partition levels and various sizes. A decision on whether to code a picture area using inter-picture (temporal) prediction or intra-picture (spatial) prediction may be made at the CB level (or at the CU level for all three color channels). Each CB may be further divided into one, two, four, or other numbers of PBs according to a predefined PB partition type. Within one PB, the same prediction process may be applied, and related information may be transmitted to the decoder for each PB. After obtaining residual blocks by applying a prediction process based on the PB partition type, the CBs may be partitioned into TBs according to another quadtree structure similar to the coding tree for the CBs. In this particular implementation, the CB or TB may be limited to a square, but need not be so limited. Furthermore, in this particular example, the PB may be square or rectangular for inter prediction, and may only be square for intra prediction. A coding block may be divided into, for example, four square TBs. Each TB may be further recursively divided (using quadtree partitioning) into smaller TBs called residual quadtrees (RQTs).

[0121] Another exemplary implementation for partitioning a base block into CBs, PBs, and / or TBs is further described below. For example, rather than using multiple partition unit types such as those shown in FIG. 9 or FIG. 10, a quadtree with nested multi-type trees using a binary and ternary partition segmentation structure (e.g., the QTBT or QTBT with ternary partitioning described above) may be used. The separation of CBs, PBs, and TBs (i.e., partitioning the CB into PBs and / or TBs and the PB into TBs) may be abandoned except when required for CBs with sizes too large for the maximum transform length, and such CBs may require further partitioning. This exemplary partitioning scheme may be designed to support more flexibility for CB partition shapes, so that both prediction and transformation can be performed at the CB level without further partitioning. In such a coding tree structure, the CBs may have either a square or rectangular shape. Specifically, the coding tree blocks (CTBs) may first be partitioned by a quadtree structure. The quadtree leaf nodes can then be further partitioned by a nested multitype tree structure. An example of a nested multitype tree structure using binary or ternary partitioning is shown in FIG. 11. Specifically, the exemplary multitype tree structure in FIG. 11 includes four partition types: vertical binary partitioning (SPLIT_BT_VER) (1102), horizontal binary partitioning (SPLIT_BT_HOR) (1104), vertical ternary partitioning (SPLIT_TT_VER) (1106), and horizontal ternary partitioning (SPLIT_TT_HOR) (1108). And, CB corresponds to the leaf of the multitype tree. In this exemplary implementation, as long as CB is not too large relative to the maximum transform length, this segmentation is used for both prediction and transform processing without further partitioning. This means that in most cases, CB, PB, and TB have the same block size in a quadtree with a nested multitype tree coding block structure.An exception occurs when the maximum supported transform length is smaller than the width or height of the color components of the CB. In some implementations, in addition to binary or ternary partitioning, the nested pattern of Figure 11 may further include quadtree partitioning.

[0122] One specific example for a quadtree with nested multitype tree coding block structure of block partitions (including quadtree, binary, and ternary partitioning options) for one base block is shown in FIG. 12. More specifically, FIG. 12 shows a base block 1200 being quadtree partitioned into four square partitions 1202, 1204, 1206, and 1208. A decision to further use the multitype tree structure and quadtree of FIG. 11 for further partitioning is made for each quadtree partitioned partition. In the example of FIG. 12, partition 1204 is not further partitioned. Partitions 1202 and 1208 each employ a different quadtree partitioning. For partition 1202, the second-level quadtree partitioned upper-left, upper-right, lower-left, and lower-right partitions employ the third-level partitioning of quadtree, horizontal binary partitioning 1104 of FIG. 11, no partitioning, and horizontal ternary partitioning 1108 of FIG. 11, respectively. Partition 1208 employs another quadtree partitioning, and the second-level quadtree-divided upper-left, upper-right, lower-left, and lower-right partitions employ third-level partitioning of vertical ternary partitioning 1106 in FIG. 11 , no partitioning, no partitioning, and horizontal binary partitioning 1104 in FIG. 11 , respectively. Two of the subpartitions of the third-level upper-left partition of 1208 are further divided according to horizontal binary partitioning 1104 and horizontal ternary partitioning 1108 in FIG. 11 , respectively. Partition 1206 employs a division pattern according to vertical binary partitioning 1102 in FIG. 11 at the second level to create two partitions, and these partitions are further divided according to horizontal ternary partitioning 1108 and vertical binary partitioning 1102 in FIG. 11 at the third level. A fourth-level division is further applied to one of them according to horizontal binary partitioning 1104 in FIG. 11 .

[0123] In the specific example above, the maximum luma transform size may be 64x64, and the maximum supported chroma transform size may differ, for example, luma at 32x32. The above example CB in Figure 12 is generally not further divided into smaller PBs and / or TBs, but when the width or height of a luma coding block or chroma coding block is larger than the maximum transform width or height, the luma coding block or chroma coding block may be automatically divided horizontally and / or vertically to meet the transform size constraint in that direction.

[0124] In a specific example for partitioning the above base blocks into CBs, as described above, the coding tree scheme may support the ability for luma and chroma to have separate block tree structures. For example, in the case of P slices and B slices, the luma CTB and chroma CTB in one CTU may share the same coding tree structure. In the case of an I slice, for example, the luma and chroma may have separate coding block tree structures. When separate block tree structures are applied, the luma CTB may be partitioned into luma CBs by one coding tree structure, and the chroma CTB may be partitioned into chroma CBs by another coding tree structure. This means that a CU in an I slice may be composed of one luma component coding block or two chroma component coding blocks, and a CU in a P or B slice is always composed of coding blocks for all three color components unless the video is monochrome.

[0125] When a coding block is further partitioned into multiple transform blocks, the transform blocks therein may be ordered in the bitstream according to various orders or scanning methods. Exemplary implementations for partitioning coding or predictive blocks into transform blocks and the coding order of the transform blocks are described in further detail below. In some exemplary implementations, as described above, transform partitioning may support transform blocks of multiple shapes, e.g., 1:1 (square), 1:2 / 2:1, and 1:4 / 4:1, with transform block sizes ranging from 4×4 to 64×64, for example. In some implementations, when a coding block is 64×64 or smaller, transform block partitioning may be applied only to the luma component, and thus, for chroma blocks, the transform block size is the same as the coding block size. Otherwise, if the coding block width or height is greater than 64, both the luma coding block and the chroma coding block may be implicitly divided into multiples of min(W,64)×min(H,64) and min(W,32)×min(H,32) transform blocks, respectively.

[0126] In some example implementations of transform block partitioning, for both intra-coded and inter-coded blocks, the coding block may be further partitioned into multiple transform blocks at a partition depth up to a predefined number of levels (e.g., two levels). The transform block partition depth and size may be related. For some example implementations, the mapping from the transform size of the current depth to the transform size of the next depth is shown in Table 1 below. [Table 1]

[0127] Based on the example mapping in Table 1, for a 1:1 square block, the next-level transform partitioning may create four 1:1 square sub-transform blocks. The transform partition may stop at, for example, 4x4. So, a transform size of 4x4 at the current depth corresponds to the same size of 4x4 at the next depth. In the example of Table 1, for a 1:2 / 2:1 non-square block, the next-level transform partitioning may create two 1:1 square sub-transform blocks, while for a 1:4 / 4:1 non-square block, the next-level transform partitioning may create two 1:2 / 2:1 sub-transform blocks.

[0128] In some example implementations, additional restrictions may be applied to transform block partitioning for the luma component of an intra-coded block. For example, for each level of transform partitioning, all sub-transform blocks may be constrained to have equal sizes. For example, for a 32x16 coding block, level 1 transform partitioning creates two 16x16 sub-transform blocks, and level 2 transform partitioning creates eight 8x8 sub-transform blocks. In other words, second-level partitioning must be applied to all first-level sub-blocks to keep the transform units equal in size. An example of transform block partitioning for an intra-coded square block according to Table 1 is shown in FIG. 15, with the coding order indicated by the arrows. Specifically, 1502 indicates a square coding block. The first-level partitioning into four equal-sized transform blocks according to Table 1 is shown in 1504, with the coding order indicated by the arrows. The second-level partitioning of all first-level equal-sized blocks according to Table 1 into 16 equal-sized transform blocks is shown in 1506, with the coding order indicated by the arrows.

[0129] In some example implementations, the above restrictions for intra-coding may not apply to the luma component of an inter-coded block. For example, after the first level of transform partitioning, any one of the sub-transform blocks may be further partitioned independently at another level. Thus, the resulting transform blocks may or may not be of the same size. An example partitioning of an inter-coded block into transform blocks, along with their coding order, is shown in Figure 16. In the example of Figure 16, an inter-coded block 1602 is partitioned into transform blocks at two levels according to Table 1. At the first level, the inter-coded block is partitioned into four transform blocks of equal size. Then, as indicated by 1604, only one of the four transform blocks (but not all of them) is further partitioned into four sub-transform blocks, resulting in a total of seven transform blocks with two different sizes. An example coding order of these seven transform blocks is indicated by the arrows at 1604 in Figure 16.

[0130] In some example implementations, for chroma component(s), some additional restrictions for transform blocks may apply. For example, for chroma component(s), the transform block size can be the same size as the coding block size, but cannot be smaller than a predefined size, e.g., 8x8.

[0131] In some other example implementations, for coding blocks with either width (W) or height (H) greater than 64, both the luma coding block and the chroma coding block may be implicitly divided into multiples of min(W,64)×min(H,64) and min(W,32)×min(H,32) transform units, respectively, where, in this disclosure, "min(a,b)" may return the smaller of a and b.

[0132] Figure 17 further illustrates another alternative exemplary scheme for partitioning coding blocks or predictive blocks into transform blocks. As shown in Figure 17, instead of using recursive transform partitioning, a predefined set of partitioning types may be applied to a coding block according to the transform type of the coding block. In the particular example shown in Figure 17, one of six exemplary partitioning types may be applied to divide the coding block into various numbers of transform blocks. Such a scheme for generating transform block partitioning may be applied to either coding blocks or predictive blocks.

[0133] More specifically, the partitioning scheme of FIG. 17 provides up to six exemplary partition types for any given transform type (transform type refers to the type of primary transform, such as ADST, for example). In this scheme, every coding block or predictive block may be assigned a transform partition type based, for example, on a rate-distortion cost. In one example, the transform partition type assigned to a coding block or predictive block may be determined based on the transform type of the coding block or predictive block. A particular transform partition type may correspond to a transform block partition size and pattern, as illustrated by the six transform partition types shown in FIG. 17. Correspondence between various transform types and various transform partition types may be predefined. An example is shown below, with capitalized labels indicating transform partition types that may be assigned to a coding block or predictive block based on a rate-distortion cost: PARTITION_NONE: Allocate a transformation size equal to the block size. · PARTITION_SPLIT: Allocate a transformation size that is 1 / 2 the width of the block size and 1 / 2 the height of the block size. PARTITION_HORZ: Allocates a transformation size with width equal to the block size and height half the block size. · PARTITION_VERT: Allocates a transformation size with a width half the block size and a height equal to the block size. PARTITION_HORZ4: Allocates a transformation size with the same width as the block size and 1 / 4 the height of the block size. PARTITION_VERT4: Allocates a transformation size with a width of 1 / 4 of the block size and a height equal to the block size.

[0134] In the above example, all transform partition types include a uniform transform size for the partitioned transform blocks, as shown in Figure 17. This is by way of example only and not limitation. In some other implementations, mixed transform block sizes may be used for the partitioned transform blocks in a particular partition type (or pattern).

[0135] The PBs (or CBs, also called PBs when not further partitioned into predictive blocks) obtained from any of the above partitioning schemes can then become individual blocks for coding via either intra-prediction or inter-prediction. In the case of inter-prediction for the current PB, a residual between the current block and the predictive block can be generated, coded, and included in the coded bitstream.

[0136] Inter prediction may be implemented, for example, in single-reference mode or mixed-reference mode. In some implementations, a skip flag may be initially included in the (or higher-level) bitstream for the current block to indicate whether the current block is inter-coded and should not be skipped. If the current block is inter-coded, another flag may be further included as a signal in the bitstream to indicate whether a single-reference mode or a mixed-reference mode is used to predict the current block. In the single-reference mode, one reference block may be used to generate a predictive block for the current block. In the mixed reference mode, two or more reference blocks may be used to generate a predictive block, for example, by weighted averaging. The mixed reference mode may be referred to as a more-than-one-reference mode, two-reference mode, or multiple-reference mode. One or more reference blocks may be identified using one or more reference frame indices and, additionally, one or more corresponding motion vectors indicating the location, e.g., the shift(s), between the reference block(s) and the current block in horizontal and vertical pixels. For example, in a single reference mode, an inter-predicted block for a current block may be generated from a single reference block identified as the predictive block by one motion vector in a reference frame, while in a mixed reference mode, the predictive block may be generated by a weighted average of two reference blocks in two reference frames indicated by two reference frame indices and two corresponding motion vectors. The motion vector(s) may be coded and included in the bitstream in various ways.

[0137] In some implementations, an encoding or decoding system may maintain a decoded picture buffer (DPB). Some images / pictures are maintained in the DPB waiting to be displayed (in the decoding system), and some images / pictures in the DPB may be used as reference frames to enable inter-prediction (in the decoding system or encoding system). In some implementations, reference frames in the DPB may be tagged as either short-term or long-term references for the current image being encoded or decoded. For example, short-term reference frames may include frames used for inter-prediction for blocks in the current frame or in a predefined number (e.g., two) subsequent video frames closest to the current frame in decoding order. Long-term reference frames may include frames in the DPB that can be used to predict image blocks of frames that are more than a predefined number away from the current frame in decoding order. Information regarding such tags for short-term and long-term reference frames may be referred to as a reference picture set (RPS) and may be added to the header of each frame in the encoded bitstream. Each frame in the encoded video stream may be identified by a picture order counter (POC), which is numbered according to the playback sequence, either in an absolute manner or relative to a group of pictures starting, for example, from an I-frame.

[0138] In some example implementations, one or more reference picture lists including identification of short-term and long-term reference frames for inter prediction may be formed based on information in the RPS. For example, for unidirectional inter prediction, a single picture reference list denoted as L0 reference (or reference list 0) may be formed, and for bidirectional inter prediction, two picture reference lists denoted as L0 (or reference list 0) and L1 (or reference list 1) may be formed for each of the two prediction directions. The reference frames included in the L0 and L1 lists may be ordered in various predetermined manners. The lengths of the L0 and L1 lists may be signaled in the video bitstream. Unidirectional inter prediction may be either a single reference mode or a mixed reference mode when multiple references for generating a predictive block by weighted averaging in a mixed prediction mode are on the same side of the block to be predicted. Bidirectional inter prediction may be a mixed mode only in that bidirectional inter prediction involves at least two reference blocks.

[0139] In some implementations, a merge mode (MM) for inter prediction may be implemented. Generally, in the merge mode, one or more of the motion vectors in single reference prediction or mixed reference prediction for the current PB may be derived from other motion vector(s) rather than being calculated and signaled independently. For example, in an encoding system, current motion vector(s) for the current PB may be represented by difference(s) between the current motion vector(s) and one or more other already coded motion vectors (referred to as reference motion vectors). Such difference(s) of the motion vector(s) rather than the entire current motion vector(s) may be coded and included in the bitstream, and may be linked to the reference motion vector(s). Correspondingly, in a decoding system, the motion vector(s) corresponding to the current PB may be derived based on the decoded motion vector difference(s) and the decoded reference motion vector(s) linked thereto. As a specific form of general merge mode (MM) inter prediction, such inter prediction based on motion vector differential(s) may be referred to as merge mode with motion vector differential (MMVD). Thus, general MM or MMVD in particular may be implemented to exploit the correlation between motion vectors associated with different PBs to improve coding efficiency. For example, adjacent PBs may have similar motion vectors, so that MVD may be small and may be coded efficiently. In another example, motion vectors may be correlated temporally (between frames) for similarly located / positioned blocks in space.

[0140] In some example implementations, an MM flag may be included in the bitstream during the encoding process to indicate whether the PB is currently in merge mode. Additionally or alternatively, an MMVD flag may be included and signaled in the bitstream during the encoding process to indicate whether the PB is currently in MMVD mode. The MM flag and / or MMVD flag or indicator may be provided at the PB level, CB level, CU level, CTB level, CTU level, slice level, picture level, sequence level, etc. For a particular example, both an MM flag and an MMVD flag may be included for the current CU, and the MMVD flag may be signaled immediately after the skip flag and MM flag to specify whether the MMVD mode is used for the current CU.

[0141] In some example implementations of MMVD, a list of merge candidates for motion vector prediction may be formed for a block being predicted. The list of merge candidates may include a predetermined number (e.g., two) of MV predictor candidate blocks whose motion vectors can be used to predict the current motion vector. MVD candidate blocks may include blocks selected from neighboring blocks in the same frame and / or temporal blocks (e.g., similarly located blocks in a frame preceding or following the current frame). These options represent blocks at spatial or temporal locations relative to the current block that are likely to have similar or identical motion vectors to the current block. The size of the list of MV predictor candidates may be predetermined. For example, the list may include two candidates. To be on the list of merge candidates, a candidate block may, for example, be required to have the same reference frame(s) as the current block, must exist (e.g., a boundary check needs to be performed when the current block is near the edge of a frame), have already been coded during the coding process, and / or have already been decoded during the decoding process. In some implementations, the list of merge candidates may be first filled with spatially adjacent blocks (scanned in a specific predefined order) if they are available and satisfy the above conditions, and then filled with temporal blocks if there is still space available in the list. The adjacent candidate blocks may be selected, for example, from the left and above blocks of the current block. The list of merge MV predictor candidates may be signaled in the bitstream.

[0142] In some implementations, the actual merge candidate used as the reference motion vector for predicting the motion vector of the current block may be signaled. When the merge candidate list includes two candidates, a one-bit flag called a merge candidate flag may be used to indicate the selection of the reference merge candidate. For a current block being predicted in combined mode, each of the multiple motion vectors predicted using the MV predictor may be associated with a reference motion vector from the merge candidate list.

[0143] In some exemplary implementations of MMVD, after a merge candidate is selected and used as a base motion vector predictor for a motion vector to be predicted, a motion vector differential (MVD or delta MV, representing the difference between the motion vector to be predicted and a reference candidate motion vector) may be calculated in the coding system. Such an MVD may include information representing the magnitude and direction of the MV differential, both of which may be signaled in the bitstream. The magnitude and direction of the motion vector differential may be signaled in various ways.

[0144] In some exemplary implementations of MMVD, a distance index may be used to specify magnitude information of the motion vector differential and to indicate one of a set of predefined offsets representing a predefined motion vector differential from a starting point (reference motion vector). The MV offset according to the signaled index may then be added to either the horizontal or vertical component of the starting (reference) motion vector. Whether the horizontal or vertical component of the reference motion vector should be offset may be determined by the direction information of the MVD. An exemplary predefined relationship between the distance index and the predefined offsets is set forth in Table 2. [Table 2]

[0145] In some example implementations of MMVD, a direction index may be further signaled and used to represent the direction of the MVD relative to the reference motion vector. In some implementations, the direction may be limited to either the horizontal or vertical direction. An example 2-bit direction index is shown in Table 3. In the example of Table 3, the interpretation of the MVD may change according to the information of the starting / reference MV. For example, when the starting / reference MV corresponds to a uni-predictive block or a bi-predictive block where both reference frame lists point to the same side of the current picture (i.e., the POCs of the two reference pictures are both greater than or both less than the POC of the current picture), the code in Table 3 may specify the sign (direction) of the MV offset added to the starting / reference MV. When the start / reference MV corresponds to a bi-predictive block having two reference pictures on different sides of the current picture (i.e., the POC of one reference picture is larger than the POC of the current picture and the POC of the other reference picture is smaller than the POC of the current picture), and the difference between the reference POC in picture reference list 0 and the current frame is larger than the difference between the reference POC in picture reference list 1 and the current frame, the code in Table 3 may specify the sign of the MV offset to be added to the reference MV corresponding to the reference picture in picture reference list 0, and the sign of the offset of the MV corresponding to the reference picture in picture reference list 1 may have the opposite value (opposite sign of the offset). Otherwise, when the difference between the reference POC in picture reference list 1 and the current frame is larger than the difference between the reference POC in picture reference list 0 and the current frame, the code in Table 3 may specify the sign of the MV offset to be added to the reference MV associated with picture reference list 1, and the sign of the offset to the reference MV associated with picture reference list 0 has the opposite value. [Table 3]

[0146] In some example implementations, the MVD may be scaled according to the POC difference in each direction. If the POC difference in both lists is the same, no scaling is required. Otherwise, if the POC difference in reference list 0 is larger than that of reference list 1, the MVD for reference list 1 is scaled. If the POC difference in reference list 1 is larger than list 0, the MVD for list 0 may be scaled in the same manner. If the starting MV is uni-predicted, the MVD is added to the available or reference MV.

[0147] In some example implementations of MVD coding and signaling for bidirectional mixed prediction, in addition to or as an alternative to separately coding and signaling two MVDs, symmetric MVD coding may be implemented such that only one MVD needs to be signaled and the other MVD can be derived from the signaled MVD. In such implementations, motion information including reference picture indices for both list 0 and list 1 is signaled. However, for example, only the MVD associated with reference list 0 is signaled, and the MVD associated with reference list 1 is derived rather than signaled. Specifically, at the slice level, a flag called "mvd_l1_zero_flag" may be included in the bitstream to indicate whether reference list 1 is not signaled in the bitstream. If this flag is 1, indicating that reference list-1 is equal to 0 (and therefore not signaled), a bidirectional prediction flag called "BiDirPredFlag" may be set to 0, signifying no bidirectional prediction. Otherwise, if mvd_l1_zero_flag is 0, and the closest reference picture in list 0 and the closest reference picture in list 1 form a forward-backward pair of reference pictures or a backward-forward pair of reference pictures, BiDirPredFlag may be set to 1, and the reference pictures in list 0 and list 1 are both short-term reference pictures. Otherwise, BiDirPredFlag is set to 0. A BiDirPredFlag of 1 may indicate that a symmetric mode flag is additionally signaled in the bitstream. A decoder may extract the symmetric mode flag from the bitstream when BiDirPredFlag is 1. The symmetric mode flag may be signaled, for example, at the CU level (if necessary) and may indicate whether symmetric MVD coding mode is used for the corresponding CU.When the symmetric mode flag is 1, it indicates the use of symmetric MVD coding mode and that only the reference picture indexes of both list 0 and list 1 (called "mvp_l0_flag" and "mvp_l1_flag") are signaled along with the MVD associated with list 0 (called "MVD0"), and the other motion vector differential, "MVD1," should be derived rather than signaled. For example, MVD1 may be derived as -MVD0. Thus, only one MVD is signaled in the exemplary symmetric MVD mode. In some other exemplary implementations for MV prediction, a harmonized scheme may be used to implement general merge mode, MMVD, and some other types of MV prediction for both single-reference and mixed-reference mode MV prediction. Various syntax elements may be used to signal how the MV for the current block is predicted.

[0148] For example, for single reference modes, the following MV prediction modes may be signaled: NEARMV - Use one of the motion vector predictors (MVP) in the list indicated by the DRL (Dynamic Reference List) index directly without MVD. NEWMV - Use one of the motion vector predictors (MVPs) in the list signaled by the DRL index as a reference and apply a delta to the MVP (eg, using MVD). GLOBALMV - Use motion vectors based on frame-level global motion parameters.

[0149] Similarly, for mixed reference inter prediction modes using two reference frames corresponding to the two MVs to be predicted, the following MV prediction modes may be signaled: NEAR_NEARMV - For each of two of the MVs to be predicted, use one of the motion vector predictors (MVPs) in the list signaled by the DRL index without the MVD. NEAR_NEWMV - To predict the first of two motion vectors, one of the motion vector predictors (MVP) in the list signaled by the DRL index is used as a reference MV without MVD, and to predict the second of two motion vectors, one of the motion vector predictors (MVP) in the list signaled by the DRL index is used as a reference MV with an additionally signaled delta MV (MVD). NEW_NEARMV - To predict the second of two motion vectors, one of the motion vector predictors (MVP) in the list signaled by the DRL index is used as a reference MV without MVD, and to predict the first of two motion vectors, one of the motion vector predictors (MVP) in the list signaled by the DRL index is used as a reference MV with an additionally signaled delta MV (MVD). NEW_NEWMV - Use one of the motion vector predictors (MVPs) in the list signaled by the DRL index as a reference MV and use it together with the additionally signaled delta MV to predict for each of the two MVs. GLOBAL_GLOBALMV - Use the MV from each reference based on their frame-level global motion parameters.

[0150] Thus, the term "NEAR" above refers to MV prediction using a reference MV without an MVD, as in the general merge mode, and the term "NEW" refers to MV prediction using a reference MV and offsetting it with a signaled MVD, as in the MMVD mode. In the case of hybrid inter prediction, both the reference-based motion vector and the motion vector delta may generally differ or be independent between the two references, even though, for example, they may be correlated and such correlation may be exploited to reduce the amount of information required to signal the two motion vector deltas. In such a situation, joint signaling of the two MVDs may be implemented and indicated in the bitstream, as described in more detail below.

[0151] The dynamic reference list (DRL) described above is dynamically maintained and can be used to hold a set of indexed motion vectors that are considered as candidate motion vector predictors.

[0152] In some example implementations, a predefined resolution for the MVD may be allowed. For example, a motion vector precision (or accuracy) of 1 / 8 pixel may be allowed. The above-described MVD in various MV prediction modes may be configured and signaled in various ways. In some implementations, various syntax elements may be used to signal the above motion vector differential(s) in reference frame list 0 or list 1.

[0153] For example, a syntax element called "mv_joint" may specify which components of its associated motion vector differential are non-zero. In the case of MVD, this is signaled jointly for all non-zero components. For example, A mv_joint with a value of 0 may indicate that there is no non-zero MVD in either the horizontal or vertical direction. A mv_joint with a value of 1 may indicate that there is non-zero MVD only along the horizontal direction. A mv_joint with a value of 2 may indicate that there is non-zero MVD only along the vertical direction. A mv_joint with a value of 3 may indicate that there is non-zero MVD along both the horizontal and vertical directions.

[0154] When the "mv_joint" syntax element for MVD signals that there are no non-zero MVD components, no further MVD information may be signaled. However, if the "mv_joint" syntax signals that there are one or two non-zero components, additional syntax elements may be further signaled for each of the non-zero MVD components, as described below.

[0155] For example, a syntax element called "mv_sign" may be used to additionally specify whether the corresponding motion vector differential component is positive or negative.

[0156] In another example, a syntax element called "mv_class" may be used to specify a class of motion vector difference among a predefined set of classes for the corresponding non-zero MVD component. The predefined classes for motion vector difference may be used, for example, to divide the continuous magnitude space of motion vector difference into non-overlapping ranges, with each range corresponding to an MVD class. Thus, the signaled MVD class indicates the magnitude range of the corresponding MVD component. In the example implementation shown in Table 4 below, higher classes correspond to motion vector difference with a larger magnitude range. In Table 4, the symbol (n,m] is used to represent a range of motion vector difference that is greater than n pixels and less than or equal to m pixels. [Table 4]

[0157] In some other examples, a syntax element called "mv_bit" may be further used to specify the integer portion of the offset between a non-zero motion vector differential component and the starting magnitude of the correspondingly signaled MV class magnitude range. The number of bits required in "mv_bit" to signal the full range of each MVD class may vary as a function of the MV class. As an example, MV_CLASS 0 and MV_CLASS 1 in the implementation of Table 4 may only require a single bit to indicate an integer pixel offset of 1 or 2 from a starting MVD of 0, and each higher MV_CLASS in the example implementation of Table 4 may require progressively one more bit for "mv_bit" than the previous MV_CLASS.

[0158] In some other examples, a syntax element called “mv_fr” may be further used to specify the first two fractional bits of the motion vector differential for the corresponding non-zero MVD component, and a syntax element called “mv_hp” may be used to specify the third fractional bit (high-resolution bit) of the motion vector differential for the corresponding non-zero MVD component. The two “mv_fr” bits may essentially provide ¼ pixel MVD resolution, and the “mv_hp” bits may further provide ⅛ pixel resolution. In some other implementations, two or more “mv_hp” bits may be used to provide MVD pixel resolution finer than ⅛ pixel. In some example implementations, additional flags may be signaled at one or more of various levels to indicate whether ⅛ pixel or finer MVD resolutions are supported. If MVD resolutions do not apply to a particular coding unit, the above syntax elements for the corresponding unsupported MVD resolutions may not be signaled.

[0159] In some example implementations described above, fractional resolution may be independent of different classes of MVD. In other words, similar options for motion vector resolution may be provided using a predefined number of "mv_fr" and "mv_hp" bits to signal fractional MVD of non-zero MVD components, regardless of the magnitude of the motion vector differential.

[0160] However, in some other exemplary implementations, the resolution for motion vector differentials in various MVD magnitude classes may be differentiated. Specifically, a high-resolution MVD for a large MVD magnitude of a higher MVD class may not statistically result in a significant improvement in compression efficiency. Therefore, the MVD may be coded with reduced resolution (integer pixel resolution or fractional pixel resolution) for a larger MVD magnitude range corresponding to a higher MVD magnitude class. Similarly, the MVD may generally be coded with reduced resolution (integer pixel resolution or fractional pixel resolution) for a larger MVD value. Such MVD class-dependent or MVD magnitude-dependent MVD resolution may generally be referred to as adaptive MVD resolution. Adaptive MVD resolution may be implemented in various situations, as described by the following exemplary implementations, to achieve better overall compression efficiency. In particular, the reduction in the number of signaling bits by targeting a less accurate MVD may be greater than the additional bits required to code the inter-prediction residual as a result of such a less accurate MVD, which is due to the statistical observation that treating the MVD resolution for a large magnitude or high class MVD at the same level as the MVD resolution for a small magnitude or low class MVD in a non-adaptive manner cannot significantly improve the inter-prediction residual coding efficiency of blocks with a large magnitude or high class MVD. In other words, using a higher MVD resolution for a large magnitude or high class MVD may not result in more coding gain than using a lower MVD resolution.

[0161] In some typical example implementations, the pixel resolution or precision for the MVD may decrease or not increase as the MVD class increases. Decreasing the pixel resolution for the MVD corresponds to a coarser MVD (or a larger step from one MVD level to the next). In some implementations, the correspondence between MVD pixel resolution and MVD class may be specified, predefined, or preset, and thus would not need to be signaled in the encoded bitstream.

[0162] In some example implementations, each of the MV classes in Table 3 may be associated with a different MVD pixel resolution.

[0163] In some example implementations, each MVD class may be associated with a single allowed resolution. In some other implementations, one or more MVD classes may be associated with two or more optional MVD pixel resolutions. Thus, a signal in the bitstream for a current MVD component having such an MVD class may be followed by additional signaling to indicate which optional pixel resolution is selected for the current MVD component.

[0164] In some example implementations, adaptively allowed MVD pixel resolutions may include, but are not limited to, (in descending order of resolution) 1 / 64 pel (pixel), 1 / 32 pel, 1 / 16 pel, 1 / 8 pel, 1 / 4 pel, 1 / 2 pel, 1 pel, 2 pel, 4 pel... As such, each ascending MVD class may be associated with one of these resolutions in a non-ascending manner. In some implementations, an MVD class may be associated with two or more of the above resolutions, with a higher resolution being equal to or less than the lower resolution for the preceding MVD class. For example, if MV_CLASS_3 in Table 4 may be associated with optional 1-pel and 2-pel resolutions, then the highest resolution to which MV_CLASS_4 in Table 4 may be associated would be 2-pel. In some other implementations, the highest allowed resolution for an MV class may be higher than the lowest allowed resolution of the preceding (lower) MV class. However, the average of allowed resolutions for ascending MV classes may only be in non-ascending order.

[0165] In some implementations, if fractional pixel resolution higher than 1 / 8 pel is allowed, the "mv_fr" and "mv_hp" signaling may be extended to accommodate a total of more than three fractional bits.

[0166] In some example implementations, fractional pixel resolution may be allowed only for MVD classes equal to or less than the threshold MVD class. For example, fractional pixel resolution may be allowed only for MV_CLASS_0 and not for all other MV classes in Table 4. Similarly, fractional pixel resolution may be allowed only for MVD classes equal to or less than any one of the other MV classes in Table 4. For other MVD classes above the threshold MVD class, only integer pixel resolution for the MVD is allowed. In such a manner, fractional resolution signaling, such as one or more of the “mv_fr” and / or “mv_hp” bits, may not need to be signaled for MVDs signaled in MVD classes equal to or greater than the threshold MVD class. For MVD classes with resolutions less than one pixel, the number of bits in the “mv_bit” signaling may be further reduced. For example, for MV_CLASS_5 in Table 4, the range of MVD pixel offset is (32,64], so 5 bits are required to signal the entire range at 1 pel resolution. However, if MV_CLASS_5 is associated with 2 pel MVD resolution (lower than 1 pixel resolution), 4 bits may be required for "mv_bit" instead of 5 bits, and neither "mv_fr" nor "mv_hp" need to be signaled following the signaling of "mv_class" as MV_CLASS_5.

[0167] In some example implementations, fractional pixel resolution may be allowed only for MVDs with integer values ​​below a threshold integer pixel value. For example, fractional pixel resolution may be allowed only for MVDs with less than 5 pixels. Corresponding to this example, fractional resolution would be allowed for MV_CLASS_0 and MV_CLASS_1 in Table 4, but not for all other MV classes. In another example, fractional pixel resolution may be allowed only for MVDs with less than 7 pixels. Corresponding to this example, fractional resolution may be allowed for MV_CLASS_0 and MV_CLASS_1 in Table 4 (which have a range below 5 pixels), but not for MV_CLASS_3 and above (which have a range above 5 pixels). For MVDs belonging to MV_CLASS_2, whose pixel range includes 5 pixels, fractional pixel resolution for the MVD may or may not be allowed depending on the “mv_bit” value. If the 'mv_bit' value is signaled as 1 or 2 (the integer part of the signaled MVD, calculated as the start of the pixel range for MV_CLASS_2 with offset 1 or 2 indicated by 'mv_bit', is 5 or 6), fractional pixel resolution may be allowed. Otherwise, if the 'mv_bit' value is signaled as 3 or 4 (the integer part of the signaled MVD is 7 or 8), fractional pixel resolution may not be allowed.

[0168] In some other implementations, for MV classes equal to or greater than the threshold MV class, only a single MVD value may be allowed. For example, such a threshold MV class may be MV_CLASS 2. Thus, MV_CLASS_2 and above may only be allowed to have a single MVD value and have no fractional pixel resolution. The single allowed MVD value for these MV classes may be predefined. In some examples, the allowed single value may be the upper end value of the respective range for these MV classes in Table 4. For example, MV_CLASS_2 through MV_CLASS_10 may be equal to or greater than the threshold class of MV_CLASS 2, and the allowed single MVD values ​​for these classes may be predefined as 8, 16, 32, 64, 128, 256, 512, 1024, and 2048, respectively. In some other examples, the allowed single value may be the middle value of the respective range for these MV classes in Table 4. For example, MV_CLASS_2 through MV_CLASS_10 may exceed the class threshold, and the allowed single MVD values ​​for these classes may be predefined as 3, 6, 12, 24, 48, 96, 192, 384, 768, and 1536, respectively. Any other value within the range may also be defined as the single allowed resolution for the respective MVD class.

[0169] In the above implementation, when the signaled "mv_class" is equal to or greater than the predefined MVD class threshold, only the "mv_class" signaling is sufficient to determine the MVD value. The magnitude and direction of the MVD will then be determined using "mv_class" and "mv_sign."

[0170] Therefore, when an MVD is signaled for only one reference frame (from either reference frame list 0 or list 1, but not both) or jointly for two reference frames, the accuracy (or resolution) of the MVD may depend on the associated class of motion vector differential in Table 3 and / or the magnitude of the MVD.

[0171] In some other implementations, the pixel resolution or precision for the MVD may decrease or not increase as the MVD magnitude increases. For example, the pixel resolution may depend on the integer portion of the MVD magnitude. In some implementations, fractional pixel resolution may be allowed only for MVD magnitudes below an amplitude threshold. For a decoder, first, the integer portion of the MVD magnitude may be extracted from the bitstream. Then, the pixel resolution may be determined, and then a determination may be made as to whether any fractional MVD is present in the bitstream and needs to be parsed (e.g., if fractional pixel resolution is not allowed for a particular extracted MVD integer magnitude, no fractional MVD bits will be included in the bitstream requiring extraction). The exemplary implementations described above related to MVD class-dependent adaptive MVD pixel resolution apply to MVD magnitude-dependent adaptive MVD pixel resolution. In a particular example, MVD classes above or encompassing a magnitude threshold may be allowed to have only one predefined value.

[0172] The various exemplary implementations described above apply to single-reference modes. These implementations also apply to exemplary NEW_NEARMV, NEAR_NEWMV, and / or NEW_NEWMV modes in combined prediction under MMVD. These implementations generally apply to adaptive resolution for any MVD.

[0173] In some example implementations, MVD with adaptive resolution may be treated as a separate inter-prediction single-reference mode, referred to herein as "ADAPTMV," "ADAPTIVEMV," or "ADVANCEDMV" mode. Similar to regular intra- or inter-prediction modes, such adaptive single-reference inter-coding modes may be determined and specified at the frame level, picture level, coding block level, and other levels. The specification of such a mode indicates that (1) the corresponding coding block is inter-coded, (2) the coding block is predicted by a predictive block in a single reference frame, (3) the corresponding motion vector is also predicted via a reference motion vector and MVD, and (4) adaptive resolution is applied for coding the MVD. For example, the MVD pixel resolution may depend on the MVD class and / or MVD magnitude, as described above.

[0174] In some examples, such single-reference inter prediction modes with adaptive pixel resolution may be implemented as sub-prediction modes of normal inter prediction modes and therefore may be signaled after the normal inter prediction flag. In some particular implementations, the flag for signaling the ADAPTMV mode may follow a frame index for a reference frame for inter prediction in the bitstream.

[0175] As explained above, under the single-reference inter prediction mode, MVs may be predicted or constructed in various ways, with or without MVD. For example, in the NEWMV mode, MVs are predicted by a reference MV together with MVD, while in the NEARMV mode, MVs are predicted directly by a reference MV without MVD. Furthermore, in the GLOBALMV mode, MVs are based on frame-level global motion parameters rather than any reference MV or MVD. In some exemplary implementations, an additional ADAPTMV mode may be implemented in parallel with these three modes. Therefore, the following four sub-modes may be implemented under the single-reference inter prediction umbrella: ADAPTMV - Use one of the motion vector predictors (MVPs) in the list signaled by the DRL index as a reference and apply a delta to the MVP (e.g., using MVD) with adaptive pixel resolution or precision; NEWMV - Use one of the motion vector predictors (MVPs) in the list signaled by the DRL index as a reference and apply a delta to the MVP (e.g., using MVD) at a fixed or non-adaptive pixel resolution; NEARMV - Use one of the motion vector predictors (MVP) in the list indicated by the DRL (Dynamic Reference List) index directly without MVD. GLOBALMV - Use motion vectors based on frame-level global motion parameters.

[0176] Therefore, these four single-reference inter-prediction modes may be signaled in the bitstream using one syntax among other MVD and MV-related syntax as described above.

[0177] In some example implementations, the context assignment for signaling the ADAPTMV mode may be the same as that for NEWMV, NEARMV, and GLOBALMV. In other words, regardless of whether these modes are signaled under the same syntax, they may be coded using the same probability model during entropy coding, for example, using the context-based adaptive binary arithmetic coding (CABAC) algorithm.

[0178] In some example implementations, context derivation for signaling various MVD-related syntaxes may depend on whether the MVD pixel resolution is adaptive. Examples of MVD-related syntaxes may include, but are not limited to, the mv_joint, mv_bit, mv_sign, mv_class, mv_fr, and mv_hp described above, as well as other MVD-related syntaxes. As such, these MVD syntaxes may be signaled after signaling the ADAPTMV mode, and the context or probability model may be derived by considering whether the ADAPTMV mode is signaled in the bitstream. Thus, such implementations take into account differences in the probability distribution of symbols for these MVD-related syntaxes in ADAPTMV mode or non-ADAPTMV mode.

[0179] For example, the probability distribution for mv_joint or mv_class may differ between when ADAPTMV mode is used and when ADAPTMV mode is not used. In a specific example, for mv_class, a distribution that is less concentrated in the lower classes of Table 4 may be more likely to be coded with adaptive resolution and associated with ADAPTMV mode. Thus, in some example implementations, if the current block is coded in ADAPTMV mode, one context may be derived to be used to signal mv_joint (or mv_class). Otherwise, another one or more different contexts may be used to signal mv_joint (or mv_class).

[0180] Figure 18 shows a flowchart 1800 of an example method according to the principles underlying the above-described implementations for adaptive MVD resolution and its signaling. The example decoding method flow starts at S1801. At S1810, a video stream is received. At S1820, an inter-prediction syntax element is extracted from the video stream to determine whether an ADAPTMV mode is signaled for one or more video blocks, the ADAPTMV mode being a single-reference inter-prediction mode with adaptive motion vector differential (MVD) pixel resolution. At S1830, a current MVD pixel resolution associated with one or more video blocks is determined based on whether the ADAPTMV mode is signaled in the inter-prediction syntax element. At S1840, one or more MVD-related syntax elements associated with one or more video blocks are extracted and decoded based on whether the ADAPTMV mode is signaled in the inter-prediction syntax element and further based on the current MVD pixel resolution.

[0181] In the embodiments and implementations of the present disclosure, any steps and / or operations may be combined or arranged in any quantity or order as needed. Two or more of the steps and / or operations may be performed in parallel. The embodiments and implementations of the present disclosure may be used separately or combined in any order. Furthermore, each of the method (or embodiment), encoder, and decoder may be implemented by a processing circuit (e.g., one or more processors or one or more integrated circuits). In one example, the one or more processors execute a program stored on a non-transitory computer-readable medium. The embodiments of the present disclosure may apply to a luma block or a chroma block. The term block may be interpreted as a prediction block, a coding block, or a coding unit, i.e., a CU. The term block in this specification may also be used to refer to a transform block. In the following sections, when referring to a block size, it may refer to either the width or height of the block, the maximum value of the width and height, the minimum value of the width and height, the area size (width * height), or the aspect ratio of the block (width:height or height:width).

[0182] The techniques described above may be implemented as computer software using computer-readable instructions and physically stored on one or more computer-readable media. For example, Figure 19 illustrates a computer system (1900) suitable for implementing certain embodiments of the disclosed subject matter.

[0183] Computer software may be coded using any suitable machine code or computer language that may be subject to assembly, compilation, linking, or similar mechanisms to create code containing instructions that may be executed by one or more computer central processing units (CPUs), graphics processing units (GPUs), etc., directly, or through interpretation, microcode execution, etc.

[0184] The instructions may be executed on various types of computers or components thereof, including, for example, personal computers, tablet computers, servers, smartphones, gaming devices, Internet of Things devices, and the like.

[0185] 19 for computer system (1900) are exemplary in nature and are not intended to suggest any limitation as to the scope of use or functionality of the computer software implementing embodiments of the present disclosure, nor should the arrangement of components be interpreted as having any dependency or requirement regarding any one or combination of components shown in the exemplary embodiment of computer system (1900).

[0186] The computer system 1900 may include certain human interface input devices. Such human interface input devices may respond to input by one or more human users through, for example, tactile input (e.g., keystrokes, swipes, data glove movements), audio input (e.g., voice, clapping), visual input (e.g., gestures), and olfactory input (not shown). Human interface devices may also be used to capture certain media that do not necessarily involve direct conscious human input, such as audio (e.g., speech, music, ambient sounds), images (e.g., scanned images, photographic images obtained from a still image camera), and video (e.g., two-dimensional video, three-dimensional video including stereoscopic video).

[0187] The input human interface devices may include one or more (only one of each is shown) of a keyboard (1901), a mouse (1902), a trackpad (1903), a touchscreen (1910), a data glove (not shown), a joystick (1905), a microphone (1906), a scanner (1907), and a camera (1908).

[0188] The computer system (1900) may also include certain human interface output devices. Such human interface output devices may stimulate one or more human user senses, for example, through tactile output, sound, light, and smell / taste. Such human interface output devices may include haptic output devices (e.g., haptic feedback via a touchscreen (1910), data gloves (not shown), or joystick (1905), although haptic feedback devices that do not function as input devices may also be present), audio output devices (such as speakers (1909), headphones (not shown)), visual output devices (such as screens (1910), including CRT screens, LCD screens, plasma screens, and OLED screens, each with or without touchscreen input capability and each with or without haptic feedback capability, some of which may be capable of outputting two-dimensional visual output or output in more than three dimensions by means of stereographic output, virtual reality glasses (not shown), holographic displays, and smoke tanks (not shown)), and printers (not shown).

[0189] The computer system (1900) may also include human-accessible storage devices and their associated media, such as optical media including CD / DVD ROM / RW (1920) with CD / DVD or similar media (1921), thumb drives (1922), removable hard drives or solid state drives (1923), legacy magnetic media (not shown) such as tape and floppy disks, and dedicated ROM / ASIC / PLD-based devices (not shown) such as security dongles.

[0190] Those skilled in the art should also understand that the term "computer-readable medium" as used in connection with the subject matter of this disclosure does not encompass transmission media, carrier waves, or other transitory signals.

[0191] The computer system (1900) may also include an interface (1954) to one or more communication networks (1955). The networks may be, for example, wireless, wireline, or optical. The networks may further be local, wide area, metropolitan, vehicular, and industrial, real-time, delay-tolerant, and the like. Examples of networks include local area networks such as Ethernet; wireless LANs; cellular networks including GSM, 3G, 4G, 5G, LTE, and the like; TV wireline or wireless wide area digital networks including cable TV, satellite TV, and terrestrial broadcast TV; vehicular and industrial networks including CANBus; and the like. Certain networks generally require an external network interface adapter attached to a particular general-purpose data port or peripheral bus (1949) (e.g., a USB port on the computer system (1900)); others are generally integrated into the core of the computer system (1900) by attaching to a system bus (e.g., an Ethernet interface to a PC computer system or a cellular network interface to a smartphone computer system), as described below. Using any of these networks, the computer system 1900 can communicate with other entities. Such communications may be one-way receive-only (e.g., broadcast TV), one-way transmit-only (e.g., CANbus to a specific CANbus device), or two-way to other computer systems using, for example, local or wide-area digital networks. Specific protocols and protocol stacks may be used with each of these networks and network interfaces, as described above.

[0192] The aforementioned human interface devices, human-accessible storage devices, and network interfaces may be attached to the core (1940) of the computer system (1900).

[0193] The core (1940) may include one or more central processing units (CPUs) (1941), graphics processing units (GPUs) (1942), dedicated programmable processing units in the form of field programmable gate arrays (FPGAs) (1943), hardware accelerators for specific tasks (1944), graphics adapters (1950), etc. These devices may be connected through a system bus (1948), along with read-only memory (ROM) (1945), random access memory (1946), and internal mass storage devices (1947) such as non-user-accessible internal hard drives or SSDs. In some computer systems, the system bus (1948) may be accessible in the form of one or more physical plugs to allow expansion with additional CPUs, GPUs, etc. Peripheral devices may be connected directly to the core's system bus (1948) or through a peripheral bus (1949). In one example, a screen (1910) may be connected to the graphics adapter (1950). Peripheral bus architectures include PCI, USB, etc.

[0194] The CPU (1941), GPU (1942), FPGA (1943), and accelerator (1944) can execute specific instructions that, in combination, can constitute the aforementioned computer code. That computer code can be stored in ROM (1945) or RAM (1946). Transient data can also be stored in RAM (1946), and persistent data can be stored, for example, in internal mass storage (1947). Fast storage and retrieval to any of the memory devices can be enabled through the use of cache memory, which can be closely associated with one or more of the CPU (1941), GPU (1942), mass storage (1947), ROM (1945), RAM (1946), etc.

[0195] The computer-readable medium may bear computer code for performing various computer-implemented operations. The medium and computer code may be specially designed and constructed for the purposes of the present disclosure, or they may be of the kind well known and available to those skilled in the computer software arts.

[0196] By way of example and not limitation, a computer system (1900) having the architecture, and specifically the core (1940), can provide functionality as a result of a processor(s) (including a CPU, GPU, FPGA, accelerator, etc.) executing software embodied in one or more tangible computer-readable media. Such computer-readable media can be user-accessible mass storage devices, as introduced above, as well as media associated with specific storage devices of the core (1940) that are non-transitory in nature, such as the core's internal mass storage device (1947) or ROM (1945). Software implementing various embodiments of the present disclosure can be stored in such devices and executed by the core (1940). The computer-readable media can include one or more memory devices or chips, according to particular needs. The software can cause the core (1940) and specifically the processors therein (including CPUs, GPUs, FPGAs, etc.) to perform particular processes or particular portions of particular processes described herein, including defining data structures stored in RAM (1946) and modifying such data structures according to processes defined by the software. Additionally or alternatively, the computer system can provide functionality as a result of hardwired or otherwise embodied logic in circuitry (e.g., accelerators (1944)), which can operate in place of or in conjunction with software to perform particular processes or particular portions of particular processes described herein. References to software can encompass logic, where appropriate, and vice versa. References to computer-readable media can encompass circuitry (such as integrated circuits (ICs)) that stores software for execution, circuitry that embodies logic for execution, or both, where appropriate. The present disclosure encompasses any suitable combination of hardware and software.

[0197] While this disclosure has described several exemplary embodiments, there are alterations, permutations, and various substitute equivalents that fall within the scope of this disclosure. It will thus be appreciated that those skilled in the art will be able to devise numerous systems and methods that, although not explicitly shown or described herein, embody the principles of the present disclosure and are therefore within its spirit and scope. [Appendix A: Acronyms] JEM: joint exploration model VVC: versatile video coding BMS:benchmark set MV: Motion Vector HEVC: High Efficiency Video Coding SEI: Supplementary Enhancement Information VUI: Video Usability Information GOPs: Groups of Pictures TUs: Transform Units PUs: Prediction Units CTUs: Coding Tree Units CTB: Coding Tree Blocks PB: Prediction Blocks HRD: Hypothetical Reference Decoder SNR: Signal-to-Noise Ratio CPUs: Central Processing Units GPUs: Graphics Processing Units CRT:Cathode Ray Tube LCD: Liquid-Crystal Display OLED: Organic Light-Emitting Diode CD: Compact Disc DVD: Digital Video Disc ROM: Read-Only Memory RAM: Random Access Memory ASIC: Application-Specific Integrated Circuit PLD: Programmable Logic Device LAN: Local Area Network GSM: Global System for Mobile communications LTE: Long-Term Evolution CANBus: Controller Area Network Bus USB: Universal Serial Bus PCI: Peripheral Component Interconnect FPGA: Field Programmable Gate Areas SSD: solid-state drive IC: Integrated Circuit HDR: high dynamic range SDR: standard dynamic range JVET: Joint Video Exploration Team MPM: Most probable mode WAIP: Wide-Angle Intra Prediction CU: Coding Unit PU: Prediction Unit TU: Transform Unit CTU: Coding Tree Unit PDPC: Position Dependent Prediction Combination ISP: Intra Sub-Partitions SPS: Sequence Parameter Set PPS: Picture Parameter Set APS: Adaptation Parameter Set VPS: Video Parameter Set DPS: Decoding Parameter Set ALF: Adaptive Loop Filter SAO: Sample Adaptive Offset CC-ALF: Cross-Component Adaptive Loop Filter CDEF: Constrained Directional Enhancement Filter CCSO: Cross-Component Sample Offset LSO:Local Sample Offset LR: Loop Restoration Filter AV1:AOMedia Video 1 AV2: AOMedia Video 2 MVD: Motion Vector Difference CfL: Chroma from Luma SDT: Semi-Decoupled Tree SDP: Semi Decoupled Partitioning SST: Semi-Separate Tree SB: Super Block IBC (or IntraBC): Intra Block Copy CDF: Cumulative Density Function SCC: Screen Content Coding GBI: Generalized Bi-prediction BCW: Bi-prediction with CU-level Weights CIIP: Combined intra-inter prediction POC: Picture Order Counter RPS: Reference Picture Set DPB: Decoded Picture Buffer MMVD: Merge Mode with Motion Vector Difference

Claims

[Claim 1] 1. A method for decoding one or more video blocks of a video stream, comprising: receiving the video stream; extracting an inter prediction syntax element from the video stream to determine whether an ADAPTMV mode is signaled for the one or more video blocks, the ADAPTMV mode being a single-reference inter prediction mode with adaptive motion vector differential (MVD) pixel resolution; determining a current MVD pixel resolution associated with the one or more video blocks based on whether the ADAPTMV mode is signaled in the inter prediction syntax element; extracting and decoding one or more MVD-related syntax elements associated with the one or more video blocks based on whether the ADAPTMV mode is signaled in the inter-prediction syntax element and further based on the current MVD pixel resolution; A method comprising:

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