Parallel processing system

Abstract

To accelerate a calculation speed in the structure analysis of a building by parallel processing by a plurality of information processors.SOLUTION: A parallel processing system including a plurality of information processing devices 210 sets a load vector = an entire rigidity matrix * a displacement vector (an analysis target expression) for a building to be analyzed by a finite element method. The load vector and the total stiffness matrix are known, and the displacement vector is unknown. The whole rigidity matrix is divided into N pieces, and an individual information processor is allocated to processing related to each matrix. The LU decomposition process is applied to each of the N matrices in parallel. Next, the forward substitution process is sequentially performed on the divided N matrices from the top to the bottom. When the processing of the lowermost matrix is completed, the backward substitution processing is sequentially performed on the N divided matrices from the bottom to the top. When the results of all the backward substitution processes are integrated, the value of the displacement vector which is initially unknown is calculated.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This relates to technology for a parallel processing system that uses multiple information processing devices to perform structural analysis of buildings. [Background technology]

[0002] Structural analysis of buildings is generally carried out using the finite element method with the aid of a computer.

[0003] There has long been a need to shorten the time required for structural analysis, but the time required for structural analysis by computer depends on the information processing speed of the computer.

[0004] Against this background, many technical proposals have been made to shorten the time required for computer-based structural analysis. For example, Patent Document 1 proposes an FEM analysis method for structures that allows for reasonable parallel calculations, and Patent Document 2 proposes a structural calculation device for buildings that reduces the time and effort required for structural calculations of buildings. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2020-173185 [Patent Document 2] Japanese Patent Application Laid-Open No. 2003-233640 Summary of the Invention [Problem to be solved by the invention]

[0006] In the above-mentioned conventional technology, in order to shorten the time required for structural analysis, it is necessary to improve the information processing speed of the computer used, but there is a problem in that using a computer with a high information processing speed increases costs.

[0007] In view of the above problems, the present invention aims to provide a parallel processing system that increases the calculation speed in structural analysis of buildings by having multiple information processing devices perform relatively light-load calculations in parallel. [Means for solving the problem]

[0008] One embodiment of the disclosed parallel processing system includes a plurality of information processing devices, and is characterized in that it performs processing in the following procedure to perform structural analysis of a building using the finite element method. (1) For the building to be analyzed using the finite element method, set the load vector = overall stiffness matrix x displacement vector (analysis target equation).

[0009] (2) Divide the overall stiffness matrix in (1) above into N pieces. The matrices divided into N pieces will be referred to as the first matrix, the second matrix, ..., the Nth matrix from the top. The method for dividing into N pieces is predetermined when the overall stiffness matrix is ​​created. (3) The first matrix, the second matrix, . . . , the Nth matrix are each subjected to LU decomposition in parallel using different information processing devices 210 (CPUs 410).

[0010] Here, the following information processing (4) to (6) is executed sequentially in the order of i=1, 2, 3, ..., N-1. For example, the following information processing (4) to (6) is executed for i=1, then the following information processing (4) to (6) is executed for i=2, and so on, so that the following information processing (4) to (6) is executed sequentially N-1 times.

[0011] (4) The information processing device 210 (CPU 410) in charge of the i-th matrix finds the part of the expression to be analyzed that corresponds to the i-th matrix by forward substitution, and generates the i-th intermediate result. (5) The information processing device 210 (CPU 410) in charge of the i-th matrix modifies the i-th intermediate result and generates the i-th intermediate result dash.

[0012] (6) The information processing device 210 (CPU 410) in charge of the i-th matrix passes the i-th intermediate result dash to the information processing device 210 (CPU 410) in charge of the (i+1)-th matrix.

[0013] (7) The information processing device 210 (CPU 410) in charge of the Nth matrix uses the (N-1)th intermediate result dash to find the part of the expression to be analyzed that corresponds to the Nth matrix by forward substitution, and generates the Nth intermediate result.

[0014] (8) The information processing device 210 (CPU 410) in charge of the Nth matrix uses the Nth intermediate result to apply back substitution to the part of the expression to be analyzed that corresponds to the Nth matrix, thereby generating the first second intermediate result.

[0015] (9) The information processing device 210 (CPU 410) in charge of the Nth matrix passes the first second intermediate result to the information processing device 210 (CPU 410) in charge of the (N-1)th matrix.

[0016] *Here, the information processing of (10) and (11) below is executed sequentially in the order of j=N-1, N-2, N-3, ..., 2. For example, the information processing of (10) and (11) below is executed for j=N-1, then the information processing of (10) and (11) below is executed for i=N-2, and so on, so that the information processing of (10) and (11) below is executed sequentially N-2 times.

[0017] (10) The information processing device 210 (CPU 410) responsible for the jth matrix uses the (Nj)th second intermediate result to apply a back-substitution process to the part of the expression to be analyzed that corresponds to the jth matrix, thereby generating the (N-j+1)th second intermediate result.

[0018] (11) The information processing device 210 (CPU 410) in charge of the j-th matrix passes the (N-j+1)-th second intermediate result to the information processing device 210 (CPU 410) in charge of the (j-1)-th matrix.

[0019] (12) The information processing device 210 (CPU 410) responsible for the first matrix uses the (N-1)th second intermediate result to apply a back-substitution process to the part of the expression to be analyzed that corresponds to the first matrix, thereby generating the Nth second intermediate result.

[0020] (13) After the information processing device 210 (CPU 410) in charge of the first matrix has finished processing, the results of all the backward substitution processes are integrated to calculate the value of the displacement vector that was initially unknown. [Effects of the Invention]

[0021] The disclosed parallel processing system aims to increase the calculation speed in structural analysis of buildings by having multiple information processing devices perform relatively light-load calculations in parallel. [Brief explanation of the drawings]

[0022] [Figure 1] 1 is a diagram illustrating an overview of a parallel processing system according to an embodiment of the present invention. [Figure 2] 1 is a diagram illustrating an example of a hardware configuration of an information processing device that constitutes a parallel processing system according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0023] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. (Operational principle of the parallel processing system according to this embodiment)

[0024] A parallel processing system 100 according to this embodiment (hereinafter simply referred to as "this system") includes a plurality of information processing devices 210, and performs structural analysis of buildings using the finite element method. This system 100 then performs information processing according to the following procedure.

[0025] (1) For a building to be analyzed using the finite element method, the load vector = overall stiffness matrix x displacement vector (analysis target equation) is set. At this time, the load vector and overall stiffness matrix are known, but the displacement vector is unknown, so the purpose of this system 100 is to find the unknown displacement vector.

[0026] (2) Divide the overall stiffness matrix in (1) above into N pieces. The matrices divided into N pieces will be referred to as the first matrix, the second matrix, ..., the Nth matrix from the top. The method for dividing into N pieces is predetermined when the overall stiffness matrix is ​​created. (3) The first matrix, the second matrix, . . . , the Nth matrix are each subjected to LU decomposition in parallel using different information processing devices 210 (CPUs 410).

[0027] Here, the following information processing (4) to (6) is executed sequentially in the order of i=1, 2, 3, ..., N-1. For example, the following information processing (4) to (6) is executed for i=1, then the following information processing (4) to (6) is executed for i=2, and so on, so that the following information processing (4) to (6) is executed sequentially N-1 times.

[0028] (4) The information processing device 210 (CPU 410) in charge of the i-th matrix finds the part of the expression to be analyzed that corresponds to the i-th matrix by forward substitution, and generates the i-th intermediate result. (5) The information processing device 210 (CPU 410) in charge of the i-th matrix modifies the i-th intermediate result and generates the i-th intermediate result dash.

[0029] (6) The information processing device 210 (CPU 410) in charge of the i-th matrix passes the i-th intermediate result dash to the information processing device 210 (CPU 410) in charge of the (i+1)-th matrix.

[0030] (7) The information processing device 210 (CPU 410) in charge of the Nth matrix uses the (N-1)th intermediate result dash to find the part of the expression to be analyzed that corresponds to the Nth matrix by forward substitution, and generates the Nth intermediate result.

[0031] (8) The information processing device 210 (CPU 410) in charge of the Nth matrix uses the Nth intermediate result to apply back substitution to the part of the expression to be analyzed that corresponds to the Nth matrix, thereby generating the first second intermediate result.

[0032] (9) The information processing device 210 (CPU 410) in charge of the Nth matrix passes the first second intermediate result to the information processing device 210 (CPU 410) in charge of the (N-1)th matrix.

[0033] *Here, the information processing of (10) and (11) below is executed sequentially in the order of j=N-1, N-2, N-3, ..., 2. For example, the information processing of (10) and (11) below is executed for j=N-1, then the information processing of (10) and (11) below is executed for i=N-2, and so on, so that the information processing of (10) and (11) below is executed sequentially N-2 times.

[0034] (10) The information processing device 210 (CPU 410) responsible for the jth matrix uses the (Nj)th second intermediate result to apply a back-substitution process to the part of the expression to be analyzed that corresponds to the jth matrix, thereby generating the (N-j+1)th second intermediate result.

[0035] (11) The information processing device 210 (CPU 410) in charge of the j-th matrix passes the (N-j+1)-th second intermediate result to the information processing device 210 (CPU 410) in charge of the (j-1)-th matrix.

[0036] (12) The information processing device 210 (CPU 410) responsible for the first matrix uses the (N-1)th second intermediate result to apply a back-substitution process to the part of the expression to be analyzed that corresponds to the first matrix, thereby generating the Nth second intermediate result.

[0037] (13) After the information processing device 210 (CPU 410) in charge of the first matrix has finished processing, the results of all the backward substitution processes are integrated, and the value of the displacement vector that was initially unknown is calculated.

[0038] The present system 100 aims to increase the calculation speed in the structural analysis of buildings by having a plurality of information processing devices 210 perform relatively light-load calculations in parallel. (Hardware Configuration of Parallel Processing System According to the Present Embodiment)

[0039] An example of the hardware configuration of the information processing device 210 constituting the present system 100 will be described using Fig. 2. Fig. 2 is a diagram showing an example of the hardware configuration of the information processing device 210. As shown in Fig. 2, the information processing device 210 has a CPU (Central Processing Unit) 410, a ROM (Read-Only Memory) 420, a RAM (Random Access Memory) 430, an auxiliary storage device 440, a communication I / F 450, an input device 460, an output device (display device) 470, and a storage medium I / F 480.

[0040] The CPU 410 is a device that executes programs stored in the ROM 420, performs arithmetic processing on data loaded into the RAM 430 in accordance with instructions from the programs, and controls the entire information processing device 210. The ROM 420 stores the programs and data to be executed by the CPU 410. When the CPU 410 executes a program stored in the ROM 420, the programs and data to be executed are loaded into the RAM 430, and the RAM 430 temporarily holds the arithmetic data during the calculation.

[0041] The auxiliary storage device 440 is a device that stores the basic software, such as the OS (Operating System), and the application program according to this embodiment, together with related data, and is, for example, an HDD (Hard Disk Drive) or flash memory.

[0042] The communication I / F 450 is an interface for connecting to a communication network 310 such as a wired or wireless LAN (Local Area Network) or the Internet, and for transmitting and receiving data to and from other devices that provide communication functions.

[0043] The input device 460 is a device such as a keyboard or a touch panel for inputting data to the information processing device 210. The output device 470 is a device configured with an LCD (Liquid Crystal Display) or the like, and functions as a user interface when the user uses the functions of the information processing device 210 or when making various settings. The storage medium I / F 480 is an interface for transmitting and receiving data to and from a storage medium 490 such as a CD-ROM, a DVD-ROM, or a USB memory.

[0044] Each means of the information processing device 210 may be realized by the CPU 410 executing a program corresponding to each means stored in the ROM 420 or the auxiliary storage device 440. Each means of the information processing device 210 may also be realized by hardware that performs the processing of each means. Alternatively, the information processing device 210 may be caused to execute the program by reading the program according to the present invention from an external server device via the communication I / F 450 or by reading the program according to the present invention from the storage medium 490 via the storage medium I / F 480.

[0045] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as defined in the claims. [Explanation of symbols]

[0046] 100 Parallel Processing Systems 210 Information processing equipment 310 Communication Network 410 CPU 420 ROM 430 RAM 440 Auxiliary storage 450 communication interface 460 Input Device 470 Output Device 480 Storage Media Interface 490 Memory Media

Claims

[Claim 1] A parallel processing system including a plurality of information processing devices, which performs processing in the following procedure to perform structural analysis of a building using the finite element method. (1) For the building to be analyzed using the finite element method, set the load vector = overall stiffness matrix x displacement vector (analysis target equation). (2) Divide the overall stiffness matrix of (1) above into N pieces. The N pieces of the matrix will be referred to as the first matrix, the second matrix, ..., the Nth matrix from the top. The method for dividing into N pieces is determined in advance when the overall stiffness matrix is ​​created. (3) The first matrix, the second matrix, . . . , the Nth matrix are subjected to LU decomposition in parallel using different information processing devices 210 (CPUs 410). Here, the following information processing (4) to (6) is executed sequentially in the order of i = 1, 2, 3, ..., N-1. For example, the following information processing (4) to (6) is executed for i = 1, then the following information processing (4) to (6) is executed for i = 2, and so on, with the following information processing (4) to (6) being executed sequentially N-1 times. (4) The information processing device 210 (CPU 410) in charge of the i-th matrix determines the part of the expression to be analyzed that corresponds to the i-th matrix by forward substitution, and generates the i-th intermediate result. (5) The information processing device 210 (CPU 410) in charge of the i-th matrix modifies the i-th intermediate result and generates the i-th intermediate result dash. (6) The information processing device 210 (CPU 410) in charge of the i-th matrix passes the i-th intermediate result dash to the information processing device 210 (CPU 410) in charge of the (i+1)-th matrix. (7) The information processing device 210 (CPU 410) in charge of the Nth matrix uses the (N-1)th intermediate result dash to find the part of the expression to be analyzed that corresponds to the Nth matrix by forward substitution, and generates the Nth intermediate result. (8) The information processing device 210 (CPU 410) in charge of the Nth matrix uses the Nth intermediate result to apply back substitution processing to the part of the expression to be analyzed that corresponds to the Nth matrix, thereby generating the first second intermediate result. (9) The information processing device 210 (CPU 410) in charge of the Nth matrix passes the first second intermediate result to the information processing device 210 (CPU 410) in charge of the (N-1)th matrix. *Here, the information processing of (10) and (11) below is executed sequentially in the order of j = N-1, N-2, N-3, ..., 2. For example, the information processing of (10) and (11) below is executed for j = N-1, then the information processing of (10) and (11) below is executed for i = N-2, and so on, so that the information processing of (10) and (11) below is executed sequentially N-2 times. (10) The information processing device 210 (CPU 410) responsible for the jth matrix uses the (N-j)th second intermediate result to apply a back-substitution process to the part of the expression to be analyzed that corresponds to the jth matrix, thereby generating the (N-j+1)th second intermediate result. (11) The information processing device 210 (CPU 410) in charge of the j-th matrix passes the (N-j+1)-th second intermediate result to the information processing device 210 (CPU 410) in charge of the (j-1)-th matrix. (12) The information processing device 210 (CPU 410) responsible for the first matrix uses the (N-1)th second intermediate result to apply a back-substitution process to the part of the expression to be analyzed that corresponds to the first matrix, thereby generating the Nth second intermediate result. (13) After the information processing device 210 (CPU 410) in charge of the first matrix has finished processing, the results of all the backward substitution processes are integrated to calculate the value of the displacement vector that was initially unknown.

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