Current generating circuit

Abstract

To provide a current generation circuit capable of improving the accuracy of a current value.SOLUTION: The current generation circuit includes a first current mirror circuit that generates a second current obtained by subtracting a first current from an input current, a second current mirror circuit that generates a third current obtained by subtracting the second current from the input current, and an output terminal that outputs the third current.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to a current generating circuit. [Background technology]

[0002] A current generating circuit that generates current even at a low power supply voltage is known (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 11-506860 Summary of the Invention [Problem to be solved by the invention]

[0004] The current generating circuit of Patent Document 1 can generate a current with a negative temperature characteristic at a power supply voltage of 0.9 V. However, the accuracy of the current value is low due to the influence of manufacturing variations in the elements and the temperature characteristics of the elements.

[0005] The present disclosure provides a current generating circuit that can improve the accuracy of the current value. [Means for solving the problem]

[0006] An embodiment of the present disclosure is a current generating circuit including a first current mirror circuit that generates a second current by subtracting a first current from an input current, a second current mirror circuit that generates a third current by subtracting the second current from the input current, and an output terminal that outputs the third current. [Effects of the Invention]

[0007] According to the present disclosure, the accuracy of the current value can be improved. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is an example of a circuit diagram of a current generating circuit according to a comparative example. [Figure 2] FIG. 2 is an example of a circuit diagram of the current generating circuit according to the first embodiment. [Figure 3] FIG. 3 is an example of a circuit diagram of a current generating circuit according to a first modification of the first embodiment. [Figure 4] FIG. 4 is an example of a circuit diagram of a current generating circuit according to the second modification of the first embodiment. [Figure 5] FIG. 5 is an example of a circuit diagram of a current generating circuit according to a third modification of the first embodiment. [Figure 6] FIG. 6 is an example of a circuit diagram showing a current source and a current generating circuit according to the third modification of the first embodiment. [Figure 7] FIG. 7 is a diagram showing an example of temperature characteristics of current in the third modification of the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. The following embodiments are examples for embodying the technical ideas of the invention, and the present disclosure is not limited to the described configurations and numerical values. In each drawing, the same components are denoted by the same reference numerals, and duplicate explanations may be omitted as appropriate.

[0010] In the current generating circuit of Patent Document 1, the current value of the generated current varies due to variations in elements, resulting in low accuracy of the current value. A comparative example will be described as a current generating circuit with low accuracy of the current value.

[0011] (Comparative form) FIG. 1 is an example circuit diagram of a current generating circuit according to a comparative example. As shown in FIG. 1, a current generating circuit 110 according to the comparative example includes bipolar transistors N10 and N11, resistors R10 and R11, and a current mirror circuit 12F. The bipolar transistors N10 and N11 are NPN bipolar transistors. The current mirror circuit 12F includes FETs (Field Effect Transistors) M10 and M11. The FETs M10 and M11 are P-channel FETs.

[0012] The bipolar transistor N10 has an emitter electrically connected to the ground line 21, a base electrically connected to a node N10A, and a collector electrically connected to a node N10B. The bipolar transistor N11 has an emitter electrically connected to the node N10A, a base electrically connected to the node N10B, and a collector electrically connected to the power supply line 20 via the FET M10. The resistor element R10 has one end electrically connected to the node N10A and the other end electrically connected to the ground line 21. The resistor element R11 has one end electrically connected to the node N10B and the other end electrically connected to the power supply line 20. The node N10A is a node between the bipolar transistor N11 and the resistor element R10. The node N10B is a node between the resistor element R11 and the bipolar transistor N10.

[0013] FETM10 has a source electrically connected to power supply line 20, a gate electrically connected to the drain, and a drain electrically connected to the collector of bipolar transistor N11. The drain and gate are electrically connected in common. FETM11 has a source electrically connected to power supply line 20, a gate electrically connected to the gate of FETM10, and a drain electrically connected to output terminal OUT.

[0014] The current I10 flowing through the resistor element R10 is Vbe / R10, where Vbe is the base-emitter voltage of the bipolar transistor N10, and R10 is the resistance value of the resistor element R10. The collector current of the bipolar transistor N11 and the drain current of the FET M10 are I10. Due to the current mirror circuit 12F, the current I11, which is the drain current of the FET M11, has the same current value as the current I10. As a result, the current I10 is output from the output terminal OUT.

[0015] However, the current generating circuit 110 is provided with a bipolar transistor N11. The bipolar transistor N11 functions as an impedance conversion element. Without the bipolar transistor N11, the current I10 would change due to the impedance relationship between the FET M10, the resistor element R10, and the bipolar transistor N10, making constant current operation impossible.

[0016] In the current generating circuit 110, a resistor R10, a bipolar transistor N11, and an FET M10 are electrically connected in series between a power supply line 20 and a ground line 21. The voltage between the power supply line 20 and the ground line 21 is divided into a base-emitter voltage Vbe of the bipolar transistor N10, a collector-emitter voltage Vce of the bipolar transistor N11, and a gate-source voltage Vgs of the FET M10. In order for the current generating circuit 110 to generate a constant current, the bipolar transistors N10 and N11 must operate in their active regions, and the FET M10 must operate in its saturation region. Therefore, Vbe + Vce + Vgs is approximately 1.5 V.

[0017] Therefore, to operate the current generating circuit 110, the power supply voltage VCC must be 1.5V or higher. If the power supply voltage VCC is less than 1.5V, the current I10 will be small and it will not be possible to generate a desired constant current. In the following embodiment, a current generating circuit will be described that operates at a low power supply voltage of about 1.0V and can generate a current whose value changes little in response to manufacturing variations and temperature characteristics of elements, as well as fluctuations in the power supply voltage VCC.

[0018] (First embodiment) Fig. 2 is an example of a circuit diagram of a current generating circuit according to the first embodiment. As shown in Fig. 2, a current generating circuit 100 according to the first embodiment includes current mirror circuits 12A and 12B and current sources 14A and 14B.

[0019] The current mirror circuit 12A includes bipolar transistors N3 and N4 and a resistor R1. The bipolar transistors N3 and N4 are NPN bipolar transistors. The bipolar transistor N3 has an emitter electrically connected to the ground line 21, a base electrically connected to a node N1A, and a collector electrically connected to a node N1B. The nodes N1A and N1B are at the same potential, and the collector and base are electrically connected in common. The bipolar transistor N4 has an emitter electrically connected to the ground line 21, a base electrically connected to the node N1A, and a collector electrically connected to a node N2B. The resistor R1 has one end electrically connected to the node N1A and the other end electrically connected to the ground line 21. The other end of the resistor R1 is electrically connected to the emitter of the bipolar transistor N3 via the ground line 21.

[0020] The current mirror circuit 12B includes FETs M7 and M8. FETs M7 and M8 are N-channel FETs. FET M7 has a source electrically connected to ground line 21, a gate electrically connected to node N2A, and a drain electrically connected to node N2B. Nodes N2A and N2B are at the same potential, and the drain and gate are electrically connected in common. FET M8 has a source electrically connected to ground line 21, a gate electrically connected to node N2A, and a drain electrically connected to output terminal OUT. Current source 14A is electrically connected between power supply line 20 and node N1B. Current source 14B is electrically connected between power supply line 20 and node N2B. Current sources 14A and 14B generate currents I0 with the same current value.

[0021] Because one end of resistor R1 is electrically connected to the base of bipolar transistor N3, current I1 flowing through resistor R1 is Vbe / R1. Vbe is the base-emitter voltage of bipolar transistor N3, and R1 is the resistance of resistor R1. Current I0 generated by current source 14A is branched into a current flowing from the collector to the emitter of bipolar transistor N3 and current I1 flowing through resistor R1. As a result, the current flowing from the collector to the emitter of bipolar transistor N3 is I0-I1. Because the current flowing through bipolar transistor N4 is a copy of current I0-I1 flowing through bipolar transistor N3, current I2 flowing from the collector to the emitter of bipolar transistor N4 is I0-I1.

[0022] The current I0 generated by current source 14B is branched into current I2, which flows from the collector to the emitter of bipolar transistor N4, and current, which flows from the drain to the source of FET M7. As a result, the current flowing from the drain to the source of FET M7 is I0-I2. The current flowing through FET M8 is a copy of the current I0-I2 flowing through FET M7, so the current I3 flowing from the drain to the source of FET M8 is I0-I2. Since I2=I0-I1, I3=I0-(I0-I1)=I1. Therefore, the current flowing through the output terminal OUT is I3=I1. In this way, the current I3 at the output terminal OUT has the same value as current I1, regardless of the current values ​​of current sources 14A and 14B.

[0023] According to the first embodiment, the current mirror circuit 12A (first current mirror circuit) generates a current I2 (second current) by subtracting the current I1 (first current) from the input current I0 (input current). The current mirror circuit 12B (second current mirror circuit) generates a current I3 (third current) by subtracting the current I2 from the current I0. The output terminal OUT outputs the current I3. As a result, even if the current I0 fluctuates due to manufacturing variations and temperature characteristics of the elements of the current sources 14A and 14B and fluctuations in the power supply voltage VCC, the current I3 is less susceptible to the influence of the current I0. Therefore, if the current I1 is designed to have a desired current value and temperature characteristics, the current I3 can be designed to have a desired current value and temperature characteristics without being influenced by the current I0.

[0024] In the current mirror circuit 12A, a current I0 is input to the collector of a bipolar transistor N3 (first bipolar transistor). One end of a resistor R1 (first resistor) is electrically connected to the base of the bipolar transistor N3, and the other end is connected to the emitter of the bipolar transistor N3. This allows the base-emitter voltage Vbe of the bipolar transistor N3 to be determined by the resistance value of the resistor R1. The current value of the current I1 is Vbe / R1.

[0025] The base of the bipolar transistor N3 is electrically connected to the base of the bipolar transistor N4 (second bipolar transistor), so that a current I2=I0-I1 flows between the collector and emitter of the bipolar transistor N4.

[0026] The drain of FET M7 (first transistor) receives current I0 and is electrically connected to the collector of bipolar transistor N4. This causes current I0-I2 to flow through FET M7. Current I0-I2 is replicated, and current I3=I0-I2 flows between the drain and source of FET M8 (second transistor). Therefore, current I3 flowing through output terminal OUT is I1=Vbe / R1. Therefore, current I3 can be set to Vbe / R regardless of current I0. In other words, to improve the accuracy of current I1, it is necessary to suppress the element variations of only bipolar transistor N3 and resistor R1. As a result, the accuracy of current I1 flowing through output terminal OUT can be improved.

[0027] Although the first and second transistors of the current mirror circuit 12B have been described as FETs, the first and second transistors may be bipolar transistors. When the transistor is an FET, the source, drain, and gate correspond to the input terminal, output terminal, and control terminal, respectively. When the transistor is a bipolar transistor, the emitter, collector, and base correspond to the input terminal, output terminal, and control terminal, respectively. Note that the input terminal and output terminal are not limited to inputting and outputting currents having positive current values, and may also input and output currents having negative current values.

[0028] (Modification 1 of the first embodiment) Fig. 3 is an example of a circuit diagram of a current generating circuit according to Modification 1 of the first embodiment. As shown in Fig. 3, a current generating circuit 102 according to Modification 1 of the first embodiment includes current mirror circuits 12A, 12B, and 12C, and current sources 14A and 14B. A subsequent circuit 16 is connected to an output terminal OUT.

[0029] The configurations of the current mirror circuits 12A, 12B and the current sources 14A and 14B are the same as those of the current generating circuit 100 of the first embodiment, except that the drain of the FET M8 is electrically connected to the node N3B, and therefore a description thereof will be omitted.

[0030] The current mirror circuit 12C includes FETs M5 and M6. FETs M5 and M6 are P-channel FETs. FET M5 has a source electrically connected to the power supply line 20, a gate electrically connected to a node N3A, and a drain electrically connected to a node N3B. Nodes N3A and N3B are at the same potential, and the drain and gate are electrically connected in common. FET M6 has a source electrically connected to the power supply line 20, a gate electrically connected to a node N2A, and a drain electrically connected to the output terminal OUT.

[0031] The subsequent circuit 16 is, for example, a reference voltage generating circuit and includes a bipolar transistor N5 (third bipolar transistor) and a resistor R3 (second resistor) as a start-up circuit. The bipolar transistor N5 is an NPN bipolar transistor and has an emitter electrically connected to a ground line 21, a base electrically connected to the output terminal OUT, and a collector electrically connected to the subsequent circuit. The resistor R3 has one end electrically connected to the output terminal OUT and the other end electrically connected to the ground line 21. The other end of the resistor R3 is electrically connected to the emitter of the bipolar transistor N5 via the ground line 21. Note that a circuit element may be provided between the resistor R3 and the ground line 21. Alternatively, a circuit element may be provided between the bipolar transistor N5 and the ground line 21.

[0032] In the first modification of the first embodiment, the current mirror circuit 12C (third current mirror circuit) receives the current I3 generated by the current mirror circuit 12B and outputs the current I3 to the output terminal OUT. This makes it possible to reverse the direction of the current I3 at the output terminal OUT in the first embodiment (in FIG. 2, the current I3 is drawn into the output terminal OUT) from the direction of the current I3 at the output terminal OUT in the first modification of the first embodiment (in FIG. 3, the current I3 is output from the output terminal OUT). Furthermore, by setting the magnitudes of the FETs M5 and M6, the current I3 output at the output terminal OUT can be set to any multiple of I1.

[0033] In the current mirror circuit 12C, the source and gate of FETM5 (third transistor) are electrically connected in common. The gate of FETM5 is electrically connected to the gate of FETM6 (fourth transistor). The source of FETM6 is electrically connected to the output terminal OUT. As a result, a current I3 generated by the current mirror circuit 12A flows between the source and drain of FETM5. A current I3 that is a copy of the current I3 that flows between the source and drain of FETM5 flows between the source and drain of FETM6.

[0034] Although the third and fourth transistors of the current mirror circuit 12C are FETs in the above example, the third and fourth transistors may be bipolar transistors.

[0035] The subsequent circuit 16 is activated when the base-emitter voltage Vbe of the bipolar transistor N5 becomes greater than the product of the current I3 and the resistance value of the resistor R3. When the activation voltage of the subsequent circuit 16 is about 1 V, if a current generating circuit with a power supply voltage of 1.5 V is used as in the comparative example, the subsequent circuit will not operate.

[0036] In current generating circuit 102, the sum of the drain-source voltage Vds of FET M8 and the gate-source voltage Vgs of FET M5 is the power supply voltage VCC. When FETs M5 and M8 are operated in their saturation regions, a forward current flows through the gate and source of FET M5. For example, Vds = 0.8 V and Vgs = 0.2 V, allowing the power supply voltage VCC to be approximately 1 V. Thus, the power supply voltage VCC is preferably less than 1.5 V, and more preferably 1.2 V or less.

[0037] If the current I3 differs from the startup conditions of the subsequent-stage circuit 16, the subsequent-stage circuit 16 may not start or the startup time may differ. When bipolar transistors N3, N4, and N5 are NPN bipolar transistors as in Variation 1 of the first embodiment, the Vbe of the bipolar transistors N3, N4, and N5 is approximately the same even with manufacturing variations. Furthermore, the temperature characteristics of the Vbe of the bipolar transistors N3, N4, and N5 are approximately the same. For example, if the Vbe of the bipolar transistor N5 increases due to manufacturing variations or temperature changes, the current I3 also increases. This reduces startup failures and changes in startup time of the subsequent-stage circuit 16. Furthermore, by using resistor elements R1 and R3 with the same structure, such as diffused resistors or polysilicon resistors, the manufacturing variations and temperature fluctuations of the resistor elements R1 and R2 can be approximately the same. To reduce manufacturing variations, the current generating circuit 102 and the subsequent-stage circuit 16 are preferably provided on the same semiconductor substrate.

[0038] (Modification 2 of the first embodiment) 4 is an example of a circuit diagram of a current generating circuit according to Modification 2 of the first embodiment. As shown in FIG. 4, in a current generating circuit 104 according to Modification 2 of the first embodiment, bipolar transistors N3, N4, and N5 are PNP bipolar transistors. FETs M5 and M6 are N-channel FETs, and FETs M7 and M8 are P-channel FETs.

[0039] The emitters of bipolar transistors N3, N4, and N5, the sources of FETs M7 and M8, and the other ends of resistors R1 and R3 are electrically connected to a power supply line 20. The sources of FETs M5 and M6 are electrically connected to a ground line 21. Current source 14A is connected between node N1B and the ground line 21, and current source 14B is connected between node N2B and the ground line 21. The other connections are the same as those in the first modification of the first embodiment.

[0040] The current I1 flowing through resistor element R1 is Vbe / R1, where Vbe is the base-emitter voltage of bipolar transistor N3, and R1 is the resistance value of resistor element R1. The current flowing through bipolar transistor N3 is I0-I1. The current I2 flowing through bipolar transistor N4 is I0-I1. The current flowing through FET M7 is I0-I2, and the current I3 flowing through FET M8 is I0-I2=I1. As a result, the output terminal OUT outputs a current I3=I1. Since the power supply voltage VCC is determined by the Vds of FET M8 and the Vgs of FET M3, the power supply voltage VCC can be made smaller than 1.5V.

[0041] As in Modification 2 of the first embodiment, when the bipolar transistor N5 in the subsequent circuit 16 is a PNP bipolar transistor, it is preferable that the bipolar transistors N3 and N4 are PNP bipolar transistors. This makes the Vbe of the bipolar transistors N3, N4, and N5 approximately the same, and also makes the temperature characteristics of Vbe approximately the same.

[0042] (Modification 3 of the first embodiment) 5 is an example of a circuit diagram of a current generating circuit according to Modification 3 of the first embodiment. As shown in FIG. 5, a current generating circuit 106 according to Modification 3 of the first embodiment includes a current source 18 and a current generating circuit 19. The current source 18 includes bipolar transistors N1 and N2 and a resistor element R2. The bipolar transistors N1 and N2 are NPN bipolar transistors. The current generating circuit 19 includes FETs M1, M2, M3, and M4. The FETs M1 to M4 are P-channel FETs.

[0043] 6 is an example of a circuit diagram showing a current source and a current generating circuit according to Modification 3 of the first embodiment. The symbols "x1," "x2," and "xN" shown near each transistor indicate the size of the transistor. For example, a "xN" transistor indicates that it is N times larger than a "x1" transistor, and corresponds to N transistors of the same size connected in parallel.

[0044] 6, in the current source 18, the bipolar transistor N1 has an emitter electrically connected to the ground line 21, a base electrically connected to a node N4A, and a collector electrically connected to a node N4B. The nodes N4A and N4B are at the same potential, and the collector and base are electrically connected in common. The bipolar transistor N2 has an emitter electrically connected to the ground line 21 via a resistor R2, a base electrically connected to the node N4A, and a collector electrically connected to the power supply line 20 via an FET M2. The resistor R2 has one end electrically connected to the emitter of the bipolar transistor N2 and the other end electrically connected to the ground line 21.

[0045] If the base-emitter voltages of bipolar transistors N1 and N2 are Vbe(N1) and Vbe(N2), respectively, and the resistance of resistor element R2 is R2, then the current flowing through resistor element R2 is IG = [Vbe(N1) - Vbe(N2)] / R2. For example, if the size of bipolar transistor N2 is twice the size of bipolar transistor N1, then IG = [Vbe(N1) - Vbe(N2)] / R2 = VT x ln2 / R2, where VT is the thermal voltage and ln is the natural logarithm. Any circuit other than the one mentioned above can be used to generate current IG.

[0046] In the current generating circuit 19, FETM1 has a source electrically connected to the power supply line 20, a gate electrically connected to a node N5A, and a drain electrically connected to a node N4B. FETM2 has a source electrically connected to the power supply line 20, a gate electrically connected to a node N5A, and a drain electrically connected to the collector of bipolar transistor N4. FETM3 has a source electrically connected to the power supply line 20, a gate electrically connected to a node N5B, and a drain electrically connected to a node N1B. FETM4 has a source electrically connected to the power supply line 20, a gate electrically connected to a node N5B, and a drain electrically connected to a node N2B. Nodes N5A and N5B are at the same potential, and the gates of FETM1 to FETM4 are electrically connected in common.

[0047] A current I G flows through FETs M1 and M2. If the magnitudes of FETs M3 and M4 are N times larger than those of FETs M1 and M2, then the current I O flowing through FETs M3 and M4 is I O = N × I G. As an example, N = 3. The current I O of current sources 14A and 14B in the first embodiment and its first and second modifications can be set to the same current value.

[0048] 2 to 5, if the current I0 is smaller than the current I1, the current I1 cannot be generated. Therefore, the current I0 is made larger than the current I1. The current I0 is preferably 1.5 times or more, more preferably 2 times or more, the current I1.

[0049] In order to increase the current I0, in the third modification of the first embodiment, the current source 18 generates a current I G (reference current). The current generating circuit 19 generates a current I0 larger than the current I G from the current I G. This allows a large current I0 to be generated.

[0050] More specifically, a current IG flows between the source and drain of FET M1 and M2 (fifth transistor). The gate of FET M3 (sixth transistor) is electrically connected to the gates of FET M1 and M2. As a result, a current I0 that is N times the current IG flows between the source and drain of FET M3. The gate of FET M4 (seventh transistor) is electrically connected to the gates of FET M1 and M2. As a result, a current I0 that is N times the current IG flows between the source and drain of FET M4. As a result, the current I0 input to the current mirror circuits 12A and 12B can be N times the current IG. Therefore, the current I0 can be made larger than the current I1.

[0051] Although the fifth, sixth, and seventh transistors are FETs in the above description, they may be bipolar transistors. If the transistor is a FET, the source, drain, and gate correspond to the input terminal, output terminal, and control terminal, respectively. If the transistor is a bipolar transistor, the emitter, collector, and base correspond to the input terminal, output terminal, and control terminal, respectively.

[0052] FIG. 7 is a graph showing an example of the temperature characteristic of current in Modification 3 of the first embodiment. The horizontal axis represents the ambient temperature of the current generating circuit 104, and the vertical axis represents the current I3 output from the output terminal OUT. As shown in FIG. 7, the current I3 has a negative temperature coefficient with respect to temperature. The temperature coefficient is approximately −2800 ppm / °C. The temperature coefficient of Vbe of a bipolar transistor is generally −2 mV / °C, and it is believed that the output current also has a negative temperature coefficient due to the temperature coefficient of Vbe. Furthermore, because a resistor element with a positive temperature coefficient of resistance is used as the resistor element R1, the temperature coefficient of the output current is more negative. The temperature coefficient of current I3 is mainly determined by the temperature coefficient of Vbe of the bipolar transistor N3 and the temperature coefficient of resistor element R1, and is not easily affected by other elements. Therefore, the temperature characteristic of current I3 can be adjusted to the desired temperature characteristic.

[0053] As in Modification 2 of the first embodiment, P-channel FETs may be used as FETs M1 to M4, and PNP bipolar transistors may be used as bipolar transistors N1 and N2. In this case, the sources of FETs M1 to M4 are connected to the ground line 21, and the emitters of bipolar transistors N1 and N2 are connected to the power supply line 20. In this way, it is sufficient that the sources of FETs M1 to M4 are electrically connected to either the power supply line 20 or the ground line 21, and the emitters of bipolar transistors N1 and N2 are electrically connected to the other of the power supply line 20 and the ground line 21.

[0054] As in the first and second modifications of the first embodiment, the bipolar transistor N3 and the bipolar transistor N5 of the subsequent circuit are of the same type (NPN or PNP), and the resistive elements R1 and R3 have the same structure (diffused resistor or polysilicon resistor). This allows the current generating circuit and the subsequent circuit 16 to have the same temperature coefficient.

[0055] Although the embodiments have been described above, they are presented as examples and the present invention is not limited to the above embodiments. The above embodiments can be implemented in various other forms, and various combinations, omissions, substitutions, modifications, etc. can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as set forth in the claims. [Explanation of symbols]

[0056] 12A, 12B, 12C, 12F current mirror circuit 14A, 14B, 18 current source 16 Subsequent circuit 19 Current generation circuit 20 Power line 21 Ground wire

Claims

1. a first current mirror circuit that generates a second current by subtracting the first current from an input current; a second current mirror circuit that generates a third current by subtracting the second current from the input current; an output terminal for outputting the third current; A current generating circuit comprising:

2. The first current mirror circuit comprises: a first bipolar transistor having a collector to which the input current is input and a base electrically connected to the collector; a first resistor element having one end electrically connected to the base of the first bipolar transistor; a second bipolar transistor having a base electrically connected to the base of the first bipolar transistor; and the first current is determined by the base-emitter voltage of the first bipolar transistor and the resistance value of the first resistor element; 2. The current generating circuit according to claim 1.

3. 3. The current generating circuit according to claim 2, wherein said second current flows between the emitter and collector of said second bipolar transistor.

4. The second current mirror circuit comprises: a first transistor having an output terminal to which the input current is input and electrically connected to the collector of the second bipolar transistor, and a control terminal electrically connected to the output terminal; a second transistor having a control terminal electrically connected to the control terminal of the first transistor; and the third current flows between the input terminal and the output terminal of the second transistor; 4. The current generating circuit according to claim 3.

5. 5. The current generating circuit according to claim 4, further comprising a third current mirror circuit that receives the third current generated by the second current mirror circuit and outputs the third current to the output terminal.

6. The third current mirror circuit comprises: a third transistor having an input terminal to which the third current generated by the second current mirror circuit is input, and a control terminal connected to the input terminal; a fourth transistor having an input terminal electrically connected to the output terminal and a control terminal electrically connected to the control terminal of the third transistor; and the third current generated by the second current mirror circuit flows between the input terminal and the output terminal of the third transistor; a current that is a copy of the third current that flows between the input terminal and the output terminal of the third transistor flows between the input terminal and the output terminal of the fourth transistor; 6. The current generating circuit according to claim 5.

7. The current generating circuit of claim 1 , wherein the input current is greater than the first current.

8. a current source for generating a reference current; a current generating circuit that generates the input current larger than the reference current from the reference current; 8. The current generating circuit of claim 7, comprising:

9. 3. The current generating circuit according to claim 2, further comprising a subsequent circuit electrically connected to the output terminal, the subsequent circuit including a third bipolar transistor and a second resistive element.

10. the third bipolar transistor has a base electrically connected to the output terminal; the second resistor element has one end electrically connected to the base of the third bipolar transistor; the subsequent stage circuit is activated when the base-emitter voltage of the third bipolar transistor becomes greater than the product of the third current and the resistance value of the second resistor element.

10. The current generating circuit according to claim 9.

11. the second transistor and the third transistor operate in a saturation region; the sum of the voltage between the input terminal and the output terminal of the second transistor and the voltage between the control terminal and the output terminal of the third transistor is less than 1.5 V; 7. The current generating circuit according to claim 6.

12. the first bipolar transistor, the second bipolar transistor, and the third bipolar transistor are NPN bipolar transistors; or the first bipolar transistor, the second bipolar transistor, and the third bipolar transistor are PNP bipolar transistors; 10. The current generating circuit according to claim 9.

13. The power line and A ground wire and Equipped with The current generating circuit includes: a fifth transistor having an input terminal electrically connected to either the power supply line or the ground line, the reference current flowing between the input terminal and an output terminal; a sixth transistor having an input terminal electrically connected to one of the lines, an output terminal electrically connected to the first current mirror circuit, and a control terminal electrically connected to the control terminal of the fifth transistor, the input current flowing between the input terminal and the output terminal; a seventh transistor having an input terminal electrically connected to one of the lines, an output terminal electrically connected to the second current mirror circuit, and a control terminal electrically connected to the control terminal of the fifth transistor, and through which the input current flows between the input terminal and the output terminal; The current generating circuit of claim 8 , comprising:

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