Power supply control device and DC / DC converter

Abstract

To provide a power supply control device capable of reducing power consumption with an effective configuration.SOLUTION: A power supply control device (2) includes an internal power supply circuit (4) including a switching unit (41) configured to switch between an output regeneration function OFF state in which an internal power supply output voltage (Vreg) is generated based on an input voltage (Vin) input to a DC / DC converter (1) and an output regeneration function ON state in which the internal power supply output voltage is generated based on an output voltage (Vout) of the DC / DC converter, and a switching control unit (43) configured to control switching by the switching unit according to the output voltage. The switching control unit controls the switching unit so as to temporarily maintain a valid state of the output regeneration function OFF state when transitioning from the output regeneration function OFF state to the output regeneration function ON state.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to a power supply control device. [Background technology]

[0002] BACKGROUND ART Conventionally, a power supply control device having a function of controlling a DC / DC converter may be provided with an internal power supply circuit (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-82752

[0004] [overview] In the above-mentioned power supply control device, there is a demand for reduction in power consumption.

[0005] In view of the above circumstances, an object of the present disclosure is to provide a power supply control device that can achieve a reduction in power consumption with an effective configuration.

[0006] One aspect of the present disclosure is a power supply control device configured to control a step-down DC / DC converter, a switching unit configured to switch between an output regeneration function OFF state in which an internal power supply output voltage is generated based on an input voltage input to the DC / DC converter and an output regeneration function ON state in which the internal power supply output voltage is generated based on an output voltage of the DC / DC converter; a switching control unit configured to control switching by the switching unit in response to the output voltage; an internal power supply circuit having The switching control unit is configured to control the switching unit so as to temporarily maintain the effective state of the output regeneration function off state when transitioning from the output regeneration function off state to the output regeneration function on state.

[0007] Another aspect of the present disclosure is a power supply control device configured to control a step-down DC / DC converter, a switching unit configured to switch between an output regeneration function OFF state in which an internal power supply output voltage is generated based on an input voltage input to the DC / DC converter and an output regeneration function ON state in which the internal power supply output voltage is generated based on an output voltage of the DC / DC converter; a switching control unit configured to control switching by the switching unit in response to the output voltage; an error amplifier configured to receive a feedback voltage based on the internal power supply output voltage and a reference voltage; a gain boost circuit configured to increase the gain of the error amplifier; an internal power supply circuit having The gain boost circuit is configured to temporarily increase the gain when the output regeneration function transitions from an ON state to an OFF state. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a diagram showing the overall configuration of a DC / DC converter. [Figure 2] FIG. 2 is a perspective view of the external appearance of the power supply IC (power supply control device). [Figure 3] FIG. 3 is a diagram showing a configuration of an internal power supply circuit according to a comparative example. [Figure 4] FIG. 4 is a timing chart showing an example of operation of the internal power supply circuit according to the comparative example. [Figure 5] FIG. 5 is a diagram showing a configuration of an internal power supply circuit according to an embodiment of the present disclosure. [Figure 6] FIG. 6 is a diagram showing a transition operation from the output regeneration function OFF state ST1 to the output regeneration function ON state ST2. [Figure 7] FIG. 7 is a timing chart showing an example of operation in the internal power supply circuit according to the comparative example and an example of operation in the internal power supply circuit according to the present disclosure. [Figure 8]FIG. 8 is a diagram showing a specific example of the configuration of the delay circuit. [Figure 9] FIG. 9 is a diagram showing the transition operation from the output regeneration function ON state ST2 to the output regeneration function OFF state ST1. [Figure 10] FIG. 10 is a diagram showing a specific example of the configuration of the gain boost circuit.

[0009] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0010] <Power supply control device> FIG. 1 is an overall configuration diagram of a DC / DC converter 1. The DC / DC converter 1 in FIG. 1 includes a power supply IC2 as a power supply control device and multiple discrete components externally connected to the power supply IC2. These multiple discrete components include a capacitor C1 as an output capacitor, a capacitor C2 as a boot capacitor, resistors R1 and R2 as feedback resistors, and an inductor L1. The DC / DC converter 1 is configured as a step-down DC / DC converter that generates a desired output voltage Vout from an externally supplied input voltage Vin. The DC / DC converter 1 is configured as a switching regulator. The output voltage Vout is generated at an output terminal OUT. In other words, the output terminal OUT is the application terminal of the output voltage Vout (the terminal to which the output voltage Vout is applied). The output voltage Vout is supplied to a load (not shown) connected to the output terminal OUT.

[0011] The input voltage Vin and the output voltage Vout are positive DC voltages, and the output voltage Vout is lower than the input voltage Vin. For example, when the input voltage Vin is 12 V, the output voltage Vout can be stabilized at a desired target voltage (e.g., 5 V) less than 12 V by adjusting the resistance values ​​of the resistors R1 and R2.

[0012] FIG. 2 shows a perspective view of the power supply IC2 (power control device). The power supply IC2 is an electronic component that includes a semiconductor chip with a semiconductor integrated circuit, a housing (package) that houses the semiconductor chip, and multiple external terminals that are exposed from the housing to the outside of the power supply IC2. The power supply IC2 is formed by encapsulating the semiconductor chip in a housing (package) made of resin. Note that the number of external terminals of the power supply IC2 and the type of housing for the power supply IC2 shown in FIG. 2 are merely examples and can be designed as desired. The output stage circuit MM, main control block 3, rectifier element D1, and internal power supply circuit 4 shown in FIG. 1 are included in the semiconductor integrated circuit. Note that the output stage circuit MM may be provided external to the power supply IC2.

[0013] In FIG. 1, only the input terminal VIN, the output voltage detection terminal VOUT_SNS, the boot terminal BST, the switch terminal SW, the feedback terminal FB, and the ground terminal GND are shown as some of the external terminals provided on the power supply IC2, but other external terminals (such as a power good terminal) may also be provided on the power supply IC2.

[0014] The external configuration of power supply IC2 will now be described. An input voltage Vin is supplied to the input terminal VIN from outside power supply IC2. An inductor L1 is connected in series between the switch terminal SW and the output terminal OUT. One end of inductor L1 is connected to the switch terminal SW, and the other end of inductor L1 is connected to the output terminal OUT. The output terminal OUT is connected to the ground terminal (the terminal to which the ground potential is applied) via capacitor C1. One end of capacitor C1 is connected to the output terminal OUT, and the other end of capacitor C1 is connected to the ground terminal. The output terminal OUT is connected to one end of resistor R1, and the other end of resistor R1 is connected to the ground terminal via resistor R2. The connection node between resistors R1 and R2 is connected to the feedback terminal FB. The output voltage detection terminal VOUT_SNS is connected to the output terminal OUT. Therefore, the output voltage Vout is applied to the output voltage detection terminal VOUT_SNS. The ground terminal GND is connected to the ground terminal. Capacitor C2 is provided between the boot terminal BST and the switch terminal SW. That is, one end of the capacitor C2 is connected to the boot terminal BST, and the other end of the capacitor C2 is connected to the switch terminal SW. The current flowing through the inductor L1 is referred to as an inductor current IL.

[0015] The following describes the internal configuration of the power supply IC 2. The power supply IC 2 includes an output stage circuit MM, a main control block 3 for controlling the output stage circuit MM, a rectifier element D1, and an internal power supply circuit 4.

[0016] The output stage circuit MM includes a high-side transistor HQ and a low-side transistor LQ. Here, the transistors HQ and LQ are each assumed to be an N-channel metal oxide semiconductor field effect transistor (MOSFET). The transistors HQ and LQ are a pair of switching elements connected in series between the input terminal VIN and the ground terminal GND. When these transistors are switched, the input voltage Vin is switched and a square-wave switching voltage Vsw appears at the switch terminal SW. Specifically, the drain of the transistor HQ is connected to the input terminal VIN, which is the application terminal of the input voltage Vin, and the source of the transistor HQ and the drain of the transistor LQ are commonly connected to the switch terminal SW. The source of the transistor LQ is connected to the ground terminal GND.

[0017] The high-side transistor HQ functions as an output transistor, and the low-side transistor LQ functions as a synchronous rectifier transistor. Inductor L1 and capacitor C1 form a rectifying and smoothing circuit that rectifies and smoothes the square-wave switching voltage Vsw that appears at the switch terminal SW to generate the output voltage Vout. Resistors R1 and R2 form a voltage divider circuit that divides the output voltage Vout, and a feedback voltage Vfb, which is the divided voltage of the output voltage Vout, is generated at the connection node between resistors R1 and R2. When the connection node between resistors R1 and R2 is connected to the feedback terminal FB, the feedback voltage Vfb is input to the feedback terminal FB.

[0018] Gate signals G1 and G2 are supplied to the gates of transistors HQ and LQ, respectively. Transistors HQ and LQ are turned on and off in response to gate signals G1 and G2. When gate signal G1 is at a high level, the high-side transistor HQ is on, and when gate signal G1 is at a low level, the high-side transistor HQ is off. Similarly, when gate signal G2 is at a high level, the low-side transistor LQ is on, and when gate signal G2 is at a low level, the low-side transistor LQ is off. Essentially, transistors HQ and LQ are switched complementarily. However, a simultaneous off period (dead time) during which both transistors HQ and LQ are off may be provided.

[0019] The main control block 3 is connected to the gates of the transistors HQ and LQ, the switch terminal SW, the feedback terminal FB, the rectifier element D1, and the boot terminal BST. The main control block 3 controls the on / off states of the transistors HQ and LQ by controlling the levels of the gate signals G1 and G2 based on the feedback voltage Vfb, thereby generating an output voltage Vout at the output terminal OUT that corresponds to the feedback voltage Vfb.

[0020] The power supply IC2 is provided with an internal power supply circuit 4 that generates an internal power supply output voltage Vreg based on the input voltage Vin. The internal power supply circuit 4 is configured as a series regulator. The internal power supply output voltage Vreg has a predetermined positive DC voltage value. In the example of Figure 1, the rectifier element D1 is a diode. In this case, the anode of the rectifier element D1 is connected to the application terminal of the internal power supply output voltage Vreg, and the cathode is connected to the boot terminal BST. The rectifier element D1 may also be a switching element that is turned on during the on period of the transistor LQ. The rectifier element D1 and capacitor C2 form a bootstrap circuit. The voltage applied to the boot terminal BST is called the boot voltage Vboot. The main control block 3 can be driven based on the internal power supply voltage Vreg or the boot voltage Vboot.

[0021] When the output stage circuit MM is in the output low state (high-side transistor HQ is off and low-side transistor LQ is on), capacitor C2 is charged through rectifier element D1 based on the internal power supply output voltage Vreg, causing the boot voltage Vboot to be higher than the switching voltage Vsw by the voltage across capacitor C2. Thereafter, even when the output stage circuit MM is switched to the output high state (high-side transistor HQ is on and low-side transistor LQ is off), the boot voltage Vboot remains higher than the switching voltage Vsw by the voltage across capacitor C2.

[0022] The gate signal G1 is a signal based on the potential of the switch terminal SW. Specifically, a low-level gate signal G1 has the potential of the switch terminal SW, and a high-level gate signal G1 is higher than the potential of the switch terminal SW by the difference between voltages Vboot and Vsw. The main control block 3 can generate a high-level gate signal G1 based on the boot voltage Vboot. On the other hand, the gate signal G2 is a signal based on the ground potential. Specifically, a low-level gate signal G2 has the ground potential, and a high-level gate signal G2 is higher than the ground potential by a predetermined voltage (e.g., the internal power supply output voltage Vreg).

[0023] <Internal power supply circuit according to comparative example> 1, in addition to the input voltage Vin, the output voltage Vout can be input to the internal power supply circuit 4 via the output voltage detection terminal VOUT_SNS. In the internal power supply circuit 4, power consumption increases as the input voltage Vin becomes larger compared to the internal power supply output voltage Vreg. Therefore, in a DC / DC converter 1 with a large step-down ratio, power consumption can be reduced by using an output regeneration function that switches the power supply of the internal power supply circuit 4 from the power supply of the DC / DC converter 1 (i.e., the input voltage Vin) to the output voltage Vout of the DC / DC converter 1.

[0024] 3 is a diagram showing the configuration of an internal power supply circuit 4X according to a comparative example for comparison with the present disclosure. The internal power supply circuit 4X shown in FIG. 3 includes a switching unit 41, a switching control unit 42, output transistors M1 and M2, an error amplifier AP, and voltage-dividing resistors Rd1 and Rd2.

[0025] The switching unit 41 includes switches SW1 and SW2. The switch SW1 includes switches S1A and S1B. The switch SW2 includes switches S2A and S2B.

[0026] The output transistors M1 and M2 are both configured as P-channel MOSFETs. However, the output transistors are not limited to P-channel MOSFETs and may be configured as N-channel MOSFETs. The source of the output transistor M1 is connected to the terminal to which the input voltage Vin is applied. The drain of the output transistor M1 is connected to the output terminal Tout and one terminal of a voltage-dividing resistor Rd1 via a switch S2A. The other terminal of the voltage-dividing resistor Rd1 is connected to the ground terminal via a voltage-dividing resistor Rd2. The connection node between the voltage-dividing resistors Rd1 and Rd2 is connected to the non-inverting input terminal (+) of the error amplifier AP. As a result, the feedback voltage Vf generated at the connection node is input to the non-inverting input terminal of the error amplifier AP. The inverting input terminal (-) of the error amplifier AP is connected to the terminal to which the reference voltage Vref is applied. The output terminal of the error amplifier AP is connected to the gate of the output transistor M1 via a switch S1A.

[0027] The source of the output transistor M2 is connected to the application terminal of the output voltage Vout. The drain of the output transistor M2 is connected to the output terminal Tout and one terminal of the voltage dividing resistor Rd1 via a switch S2B. The output terminal of the error amplifier AP is connected to the gate of the output transistor M2 via a switch S1B.

[0028] When switches S1A and S2A are in the on state (S1B and S2B are in the off state), the error amplifier AP controls the gate of the output transistor M1 so that the voltage (feedback voltage Vf) obtained by dividing the internal power supply output voltage Vreg generated at the output terminal Tout using voltage dividing resistors Rd1 and Rd2 matches the reference voltage Vref, and the output regeneration function is turned off, where the internal power supply output voltage Vreg is generated based on the input voltage Vin.

[0029] On the other hand, when switches S1B and S2B are in the on state (S1A and S2A are in the off state), the error amplifier AP controls the gate of the output transistor M2 so that the voltage obtained by dividing the internal power supply output voltage Vreg generated at the output terminal Tout by the voltage dividing resistors Rd1 and Rd2 matches the reference voltage Vref, and the output regeneration function is turned on, where the internal power supply output voltage Vreg is generated based on the input voltage Vout.

[0030] In this way, the switching unit 41 can switch between an output regeneration function OFF state and an output regeneration function ON state. Here, the switching control unit 42 is configured to control the switching unit 41, and specifically has a comparator CP. An application terminal for the output voltage Vout is connected to a non-inverting input terminal of the comparator CP. An application terminal for the threshold voltage Vth is connected to an inverting input terminal of the comparator CP. The comparator CP compares the output voltage Vout with the threshold voltage Vth and outputs a selection signal SL.

[0031] When the output voltage Vout is equal to or lower than the threshold voltage Vth, the selection signal SL goes low, and in this case, the switches S1A and S2A are turned on and the switches S1B and S2B are turned off. That is, the output regeneration function is turned off. On the other hand, when the output voltage Vout is higher than the threshold voltage Vth, the selection signal SL goes high, and in this case, the switches S1A and S2A are turned off and the switches S1B and S2B are turned on. That is, the output regeneration function is turned on.

[0032] 4 is a timing chart showing an example of operation of the internal power supply circuit 4X according to the comparative example having the above-described configuration. Note that in FIG. 4 (and FIG. 7, which will be described later), the output voltage Vout, the gate voltage GM1 of the output transistor M1, the gate voltage GM2 of the output transistor M2, and the internal power supply output voltage Vreg are shown in this order from the top.

[0033] First, at timing t1, the output voltage Vout is below the threshold voltage Vth, and the selection signal SL sets the output regeneration function off state ST1. The internal power supply output voltage Vreg is output by controlling the gate voltage GM1 of the output transistor M1. Then, at timing t2, when the output voltage Vout exceeds the threshold voltage Vth, the selection signal SL switches the output regeneration function off state ST1 to the output regeneration function on state ST2. The gate voltage GM2 of the output transistor M2 falls, and the output voltage Vout is output by controlling the gate voltage GM2. Meanwhile, the gate voltage GM1 of the output transistor M1 rises, disabling the output transistor M1. The gates of the output transistors M1 and M2 are pulled up by resistors (not shown). However, when transitioning from the output regeneration function off state ST1 to the output regeneration function on state ST2, both the output regeneration function off state ST1 and the output regeneration function on state ST2 are disabled. At this time, the internal power supply output voltage Vreg temporarily drops, as indicated by VA in FIG. 4.

[0034] Then, at time t3, when the output voltage Vout falls below the threshold voltage Vth, the selection signal SL switches from the output regeneration function on state ST2 to the output regeneration function off state ST1, the gate voltage GM1 of the output transistor M1 falls, and the output voltage Vout is output under the control of the gate voltage GM1. Meanwhile, the gate voltage GM2 of the output transistor M2 rises, and the output transistor M2 is disabled. However, when transitioning from the output regeneration function on state ST2 to the output regeneration function off state ST1, both the output regeneration function off state ST1 and the output regeneration function on state ST2 become disabled, and at this time the internal power supply output voltage Vreg temporarily drops as shown by VB in FIG. 4.

[0035] In order to suppress such a drop in the internal power supply output voltage Vreg that occurs during transition between the output regeneration function OFF state and the output regeneration function ON state, the following embodiment is implemented.

[0036] <Internal power supply circuit according to the present disclosure> <<Internal circuit configuration>> 5 is a diagram showing the configuration of an internal power supply circuit 4 according to an embodiment of the present disclosure. The internal power supply circuit 4 differs from the internal power supply circuit 4X according to the comparative example in that it has a switching control unit 43 instead of the switching control unit 42. The switching control unit 43 differs from the switching control unit 42 in that it has a delay circuit DLY in addition to a comparator CP. The internal power supply circuit 4 shown in FIG. 5 also has a gain boost circuit 44.

[0037] <<Transition from output regeneration function OFF state to ON state>> Fig. 6 is a diagram showing the transition operation from the output regeneration function off state ST1 to the output regeneration function on state ST2 in the internal power supply circuit 4 configured as shown in Fig. 5. As shown in Fig. 6, first, the output voltage Vout is equal to or lower than the threshold voltage Vth, and in the output regeneration function off state ST1 (the output regeneration function on state is invalid), the switches S1A and S2A are on and the switches S1B and S2B are off, and the internal power supply output voltage Vreg is output by controlling the gate voltage of the output transistor M1.

[0038] When the output voltage Vout becomes higher than the threshold voltage Vth, the selection signal SL switches from low to high, and the switches S1B and S2B immediately switch from off to on, but the switches S1A and S2A are switched from on to off after a delay time due to the delay of the selection signal SL caused by the delay circuit DLY. That is, the on state of the switches S1A and S2A is maintained during the delay time (transient state ST2_A immediately after state S1).

[0039] When the delay time has elapsed, the delay circuit DLY switches the switches S1A and S2A from the on state to the off state, and the output regeneration function transitions to the on state ST2 (the output regeneration function off state is invalid).

[0040] FIG. 7 is a timing chart showing an example of operation of an internal power supply circuit 4X according to a comparative example (similar to FIG. 4) on the left side, and an example of operation of the internal power supply circuit 4 according to the present disclosure on the right side.

[0041] In the internal power supply circuit 4 according to the present disclosure, when the output voltage Vout becomes higher than the threshold voltage Vth at timing t11, the switches S1A and S2A are maintained in the on state for the delay time Td. As a result, the gate voltage GM1 of the output transistor M1 remains controlled, while the gate voltage GM2 falls. This results in a state in which the output regeneration function off state is enabled and the output regeneration function on state is disabled, and a state in which both the output regeneration function off state and the output regeneration function on state are enabled. Therefore, a state in which both the output regeneration function off state and the output regeneration function on state are disabled is eliminated, and a temporary drop in the internal power supply output voltage Vreg can be suppressed (VC (solid line) compared to VA (dashed line) shown in FIG. 7).

[0042] 8 is a diagram showing a specific configuration example of the delay circuit DLY. The delay circuit DLY has a counter CT and a NAND circuit NAD. The counter CT counts the clock CLK. The output of the counter CT and a selection signal SL are input to the NAND circuit NAD. The on / off of the switches S1A and S2A is controlled by the output of the NAND circuit NAD.

[0043] When the output voltage Vout is equal to or lower than the threshold voltage Vth and the selection signal SL is at a low level, the output of the NAND circuit NAD is at a high level, and the switches S1A and S2A are turned on. When the output voltage Vout becomes higher than the threshold voltage Vth and the selection signal SL is switched from a low level to a high level, the counter CT starts counting the clock CLK. Until the clock CLK is counted a number of times corresponding to the delay time, the output of the counter CT is at a low level, the output of the NAND circuit NAD is at a high level, and the switches S1A and S2A are maintained in an on state. Then, when the clock CLK is counted a number of times corresponding to the delay time, the counter CT outputs a high level, and both inputs of the NAND circuit NAD are at a high level. Therefore, the output of the NAND circuit NAD is at a low level, and the switches S1A and S2A are switched off.

[0044] <<Transition from output regeneration function ON state to OFF state>> Fig. 9 is a diagram showing the transition operation from the output regeneration function on state ST2 to the output regeneration function off state ST1 in the internal power supply circuit 4 configured as shown in Fig. 5. As shown in Fig. 9, first, the output voltage Vout is higher than the threshold voltage Vth, and in the output regeneration function on state ST2 (the output regeneration function off state is invalid), the switches S1A and S2A are in the off state and the switches S1B and S2B are in the on state, and the internal power supply output voltage Vreg is output by controlling the gate voltage of the output transistor M2.

[0045] When the output voltage Vout becomes equal to or lower than the threshold voltage Vth, the selection signal SL switches from high to low, and the switches S1B and S2B immediately switch from on to off. At this time, the delay by the delay circuit DLY is disabled, and the switches S1A and S2A immediately switch from off to on (transient state ST1_A immediately after state ST2). As shown in Figure 8, when the selection signal SL switches to low, the output of the NAND circuit NAD becomes high, and the switches S1A and S2A immediately switch to on.

[0046] At this time, the gain boost circuit 44 starts operating, the gain of the error amplifier AP is increased for a predetermined time, and the circuit that outputs the internal power supply output voltage Vreg based on the input voltage Vin is restored quickly. After that, the operation of the gain boost circuit 44 is stopped, the increased gain state of the error amplifier AP is released, and the output regeneration function is turned off (the output regeneration function is turned on).

[0047] Referring to FIG. 7, when the output voltage Vout falls below the threshold voltage Vth at time t12, the selection signal SL switches from high to low, the switches S1B and S2B are immediately switched off, the gate voltage GM2 of the output transistor M2 rises, and the output transistor M2 is disabled. At this time, the switches S1A and S2A are immediately switched on, and the gain of the error amplifier AP is increased by the operation of the gain boost circuit 44. Because the gain remains increased for a predetermined time Tg, the gate voltage GM1 of the output transistor M1 falls quickly. This suppresses the decrease in the output voltage Vreg (VD (solid line) compared to VB (dashed line) shown in FIG. 7).

[0048] Fig. 10 is a diagram showing a specific example of the configuration of the gain boost circuit 44. Note that Fig. 10 also shows an example of the configuration of the error amplifier AP.

[0049] The gain boost circuit 44 includes an inverter 44A, a counter 44B, an AND circuit 44C, an NMOS transistor 44D, a resistor 44E, and a current mirror 44F. The inverter 44A inverts the selection signal SL and outputs it to one input terminal of the AND circuit 44C. The counter 44B counts the clock CLK. The output of the counter 44B is input to the other input terminal of the AND circuit 44C. The NMOS transistor 44D is an N-channel MOSFET. The output of the AND circuit 44C is applied to the gate of the NMOS transistor 44D. The source of the NMOS transistor 44D is connected to the ground terminal. The drain of the NMOS transistor 44D is connected to one terminal of the resistor 44E.

[0050] The current mirror 44F has an input transistor PM1 and an output transistor PM2. Both the input transistor PM1 and the output transistor PM2 are configured by P-channel MOSFETs. The drain of the input transistor PM1 is connected to the other end of the resistor 44E. The drain and gate of the input transistor PM1 are shorted. The source of the input transistor PM1 and the source of the output transistor PM2 are connected to the application terminal of the power supply voltage Vcc.

[0051] The internal power supply circuit 4 is provided with a constant current source CI. The constant current source CI is connected between the application terminal of the power supply voltage Vcc and the drain of the output transistor PM2. The error amplifier AP has PMOS transistors MP and MN and resistors RP and RN. An input signal INp is applied to the gate of the PMOS transistor MP. An input signal INn is applied to the gate of the PMOS transistor MP, and the sources of the PMOS transistors MP and MN are connected to the drain of the output transistor PM2. The drain of the PMOS transistor MP is connected to the ground terminal via the resistor RP. The drain of the PMOS transistor MN is connected to the ground terminal via the resistor RN. An error amplifier output AOUT is generated at the drain of the PMOS transistor MN.

[0052] With this configuration, when the output voltage Vout is higher than the threshold voltage Vth and the selection signal SL is at a high level, the output of the inverter 44A is at a low level, and the output of the AND circuit 44C is also at a low level, so that the NMOS transistor 44D is turned off, no current flows through the current mirror 44F, and the current I1 from the constant current source CI is supplied to the error amplifier AP, i.e., the gain of the error amplifier AP is at a normal state.

[0053] On the other hand, when the output voltage Vout falls below the threshold voltage Vth and the selection signal SL switches from high to low, the output of the inverter 44A goes high. The counter 44B starts counting the clock CLK and outputs a high signal. This causes the output of the AND circuit 44C to go high, turning on the NMOS transistor 44D. Then, the current I2' flowing through the input transistor PM1 is mirrored to become the current I2 flowing through the output transistor PM2, and the error amplifier AP is supplied with a current I1 plus I2. This increases the gain of the error amplifier AP.

[0054] After that, when the counter 44B counts the number of clocks CLK corresponding to a predetermined time, the counter 44B outputs a low level. This turns off the NMOS transistor 44D, stops the current I2 from flowing, and supplies the current I1 to the error amplifier AP. Therefore, the gain of the error amplifier AP returns to the normal state.

[0055] <Modification> As a modified example, when transitioning from the output regeneration function off state to the output regeneration function on state, the switches S1A and S2A may be immediately switched to the off state without delay, and the gain of the error amplifier AP may be temporarily increased by the gain boost circuit. However, as described above, when transitioning from the output regeneration function on state to the output regeneration function off state, the output voltage Vout is lower, so it is necessary to immediately switch the switches S1B and S2B to the off state, and therefore increasing the gain of the error amplifier AP is more significant.

[0056] <Other> In addition to the above-described embodiments, various modifications can be made to the various technical features disclosed in this specification without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present disclosure should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0057] <Additional Notes> As described above, one aspect of the present disclosure is a power supply control device (2) configured to control a step-down DC / DC converter (1), a switching unit (41) configured to switch between an output regeneration function OFF state in which an internal power supply output voltage (Vreg) is generated based on an input voltage (Vin) input to the DC / DC converter, and an output regeneration function ON state in which the internal power supply output voltage is generated based on an output voltage (Vout) of the DC / DC converter; a switching control unit (43) configured to control switching by the switching unit in accordance with the output voltage; an internal power supply circuit (4) having The switching control unit is configured to control the switching unit so as to temporarily maintain the enabled state of the output regeneration function off state when transitioning from the output regeneration function off state to the output regeneration function on state (first configuration).

[0058] In addition, in the above first configuration, the switching unit (41) may be configured to have a first switch (S1A, S2A) configured to switch between enabling and disabling the output regeneration function OFF state, and a second switch (S1B, S2B) configured to switch between enabling and disabling the output regeneration function ON state (second configuration).

[0059] In the second configuration, the switching control unit (43) includes a comparator (CP) configured to compare the output voltage (Vout) with a threshold voltage (Vth); The third configuration may also include a delay circuit (DLY) configured to delay the selection signal (SL) and input it to the first switch when the output voltage becomes higher than the threshold voltage and the level of the selection signal (SL) output from the comparator changes.

[0060] In the third configuration, the delay circuit (DLY) includes a counter (CT) configured to start counting clocks (CLK) when the output voltage becomes higher than the threshold voltage and the level of the selection signal output from the comparator is switched, and to switch the level and output the clocks when the number of clocks corresponding to a predetermined delay time is counted; A logic gate (NAD) configured to receive the selection signal and the output of the counter and to output to the first switch may be provided (fourth configuration).

[0061] In addition, in the third or fourth configuration, the delay circuit may be configured to disable the delay of the selection signal when the output voltage becomes equal to or lower than the threshold voltage and the level of the selection signal output from the comparator changes (fifth configuration).

[0062] Another aspect of the present disclosure is a power supply control device (2) configured to control a step-down DC / DC converter (1), a switching unit (41) configured to switch between an output regeneration function OFF state in which an internal power supply output voltage (Vreg) is generated based on an input voltage (Vin) input to the DC / DC converter, and an output regeneration function ON state in which the internal power supply output voltage is generated based on an output voltage (Vout) of the DC / DC converter; a switching control unit (43) configured to control switching by the switching unit in accordance with the output voltage; an error amplifier (AP) configured to receive a feedback voltage (Vf) based on the internal power supply output voltage and a reference voltage (Vref); a gain boost circuit (44) configured to increase the gain of the error amplifier; an internal power supply circuit (4) having The gain boost circuit is configured to temporarily increase the gain when the output regeneration function transitions from the on state to the off state (sixth configuration).

[0063] In addition, in the sixth configuration, the switching unit (41) may be configured to include a first switch (S1A, S2A) configured to switch between enabling and disabling the output regeneration function OFF state, and a second switch (S1B, S2B) configured to switch between enabling and disabling the output regeneration function ON state (seventh configuration).

[0064] In addition, in the seventh configuration, the switching control unit (43) may be configured to have a comparator (CP) configured to compare the output voltage (Vout) with a threshold voltage (Vth) and output a selection signal (SL) for controlling the first switch and the second switch (eighth configuration).

[0065] In the eighth configuration, the internal power supply circuit has a constant current source (CI), The gain boost circuit (44) includes a current generating unit (44F) configured to generate a second current (I2) to be added to the first current (I1) generated by the constant current source and supplied to the error amplifier, The gain boost circuit may be configured to enable the current generating unit for a predetermined time when the output voltage becomes equal to or lower than the threshold voltage and the level of the selection signal changes, and to disable the current generating unit after the predetermined time has elapsed (ninth configuration).

[0066] In any one of the first to ninth configurations, the DC / DC converter may be configured as a switching regulator, and the internal power supply circuit may be configured as a series regulator (tenth configuration).

[0067] Moreover, a DC / DC converter (1) according to an aspect of the present disclosure includes a power supply control device (2) having any one of the first to tenth configurations (eleventh configuration). [Industrial Applicability]

[0068] The present disclosure can be used in DC / DC converters for various applications. [Explanation of symbols]

[0069] 1 DC / DC converter 2 Power IC 3 Main Control Block 4, 4X internal power circuit 41 Switching section 42, 43 Switching control section 44 Gain boost circuit 44A inverter 44B Counter 44C AND circuit 44D NMOS transistor 44E Resistance 44F Current Mirror AP Error Amplifier BST Boot terminal C1 and C2 capacitors CI constant current source CP Comparator CT counter D1 rectifier element DLY delay circuit FB Feedback terminal GND Ground terminal L1 inductor HQ High-side transistor M1, M2 output transistors LQ low-side transistor MM output stage circuit MP, MN PMOS transistors NAD NAND circuit OUT output terminal PM1 input transistor PM2 output transistor R1, R2 resistance RN, RP resistance Rd1, Rd2 voltage dividing resistors S1A, S1B switches S2A, S2B switches SW Switch terminal SW1, SW2 switch section Tout output end VIN input terminal VOUT_SNS Output voltage detection pin

Claims

1. A power supply control device configured to control a step-down DC / DC converter, a switching unit configured to switch between an output regeneration function OFF state in which an internal power supply output voltage is generated based on an input voltage input to the DC / DC converter and an output regeneration function ON state in which the internal power supply output voltage is generated based on an output voltage of the DC / DC converter; a switching control unit configured to control switching by the switching unit in response to the output voltage; an internal power supply circuit having A power supply control device, wherein the switching control unit controls the switching unit to temporarily maintain the enabled state of the output regeneration function off state when transitioning from the output regeneration function off state to the output regeneration function on state.

2. 2. The power supply control device according to claim 1, wherein the switching unit has a first switch configured to switch between enabling and disabling the output regeneration function off state, and a second switch configured to switch between enabling and disabling the output regeneration function on state.

3. The switching control unit a comparator configured to compare the output voltage with a threshold voltage; a delay circuit configured to delay the selection signal and input it to the first switch when the output voltage becomes higher than the threshold voltage and the level of the selection signal output from the comparator changes; The power supply control device according to claim 2 , further comprising:

4. The delay circuit a counter configured to start counting clocks when the output voltage becomes higher than the threshold voltage and the level of the selection signal output from the comparator is switched, and to switch the level and output the selection signal when the number of clocks corresponding to a predetermined delay time is counted; a logic gate configured to receive the selection signal and the output of the counter and to output to the first switch; The power supply control device according to claim 3 , further comprising:

5. 5. The power supply control device according to claim 3, wherein the delay circuit disables the delay of the selection signal when the output voltage becomes equal to or lower than the threshold voltage and the level of the selection signal output from the comparator is switched.

6. A power supply control device configured to control a step-down DC / DC converter, a switching unit configured to switch between an output regeneration function OFF state in which an internal power supply output voltage is generated based on an input voltage input to the DC / DC converter and an output regeneration function ON state in which the internal power supply output voltage is generated based on an output voltage of the DC / DC converter; a switching control unit configured to control switching by the switching unit in response to the output voltage; an error amplifier configured to receive a feedback voltage based on the internal power supply output voltage and a reference voltage; a gain boost circuit configured to increase the gain of the error amplifier; an internal power supply circuit having The gain boost circuit temporarily increases the gain when transitioning from the output regeneration function on state to the output regeneration function off state.

7. 7. The power supply control device according to claim 6, wherein the switching unit has a first switch configured to switch between enabling and disabling the output regeneration function off state, and a second switch configured to switch between enabling and disabling the output regeneration function on state.

8. 8. The power supply control device according to claim 7, wherein the switching control unit includes a comparator configured to compare the output voltage with a threshold voltage and output a selection signal for controlling the first switch and the second switch.

9. the internal power supply circuit has a constant current source; the gain boost circuit has a current generating unit configured to generate a second current to be added to a first current from the constant current source and supplied to the error amplifier; 9. The power supply control device according to claim 8, wherein the gain boost circuit enables the current generation unit for a predetermined time when the output voltage becomes equal to or lower than the threshold voltage and the level of the selection signal is switched, and disables the current generation unit after the predetermined time has elapsed.

10. the DC / DC converter is configured as a switching regulator; 7. The power supply control device according to claim 1, wherein the internal power supply circuit is configured as a series regulator.

11. A DC / DC converter comprising the power supply control device according to claim 1 or 6.

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