Analog-to-digital conversion apparatus and analog-to-digital conversion

Abstract

To shorten a voltage measuring time as a whole device.SOLUTION: An analog-to-digital conversion device having a multiplexer that selectively switches a channel to be output from among a plurality of channels to be input includes acquisition means for acquiring respective voltage values of the plurality of channels, and control means for performing control to change an order of switching the channel to be output from among the plurality of channels so that magnitudes of the respective voltage values become ascending order.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This disclosure relates to analog-to-digital conversion. [Background technology]

[0002] There is known an analog-to-digital conversion device (hereinafter referred to as "AD conversion device") that measures voltage by converting an analog voltage supplied from an analog voltage terminal into a digital value. The AD conversion device includes a multiplexer, the input side of which is connected to a plurality of analog voltage terminals via a plurality of channels, and the output side of which is connected to a capacitor. By switching between the channels using the multiplexer, the AD conversion device charges a capacitor with the input analog voltage, converts it to a digital value, and then discharges the analog voltage charged to the capacitor, for each channel. Patent Document 1 describes an AD conversion device in which the settling time can be set for each channel. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-197384 Summary of the Invention [Problem to be solved by the invention]

[0004] However, since charging and discharging a capacitor each requires time, there is a demand for shortening the voltage measurement time of the entire device. [Means for solving the problem]

[0005] An analog-to-digital conversion device according to one aspect of the present disclosure is an analog-to-digital conversion device having a multiplexer that selectively switches an output channel from among a plurality of input channels, and is equipped with an acquisition means that acquires the voltage values ​​of each of the plurality of channels, and a control means that controls the switching order of the output channels from among the plurality of channels so that the magnitudes of each of the voltage values ​​are in ascending order. [Effects of the Invention]

[0006] According to the present disclosure, it is possible to shorten the voltage measurement time of the entire device. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 2 is a block diagram showing the internal configuration of the AD conversion device. [Figure 2] 2 is a flowchart illustrating processing performed by the AD conversion device of FIG. 1. [Figure 3] 2 is a flowchart illustrating processing performed by the AD conversion device of FIG. 1. [Figure 4] 3 is a flowchart illustrating the process of S202 in FIG. 2. [Figure 5] 3 is a flowchart illustrating the process of S202 in FIG. 2. [Figure 6] FIG. 4 is a diagram showing measurement results in the first embodiment. [Figure 7] FIG. 3 is a diagram showing the measurement results of S202 in FIG. 2. [Figure 8] 10 is a flowchart illustrating processing of an AD conversion device according to the second embodiment. [Figure 9] 10 is a flowchart illustrating processing of an AD conversion device according to the second embodiment. [Figure 10] 10 is a flowchart illustrating processing of an AD conversion device according to the second embodiment. [Figure 11] FIG. 10 is a diagram showing measurement results in the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the present disclosure, and not all combinations of features described in the following embodiments are necessarily essential to the solutions of the present disclosure. Note that the same reference numerals are used to designate the same components.

[0009] <Summary> AD conversion devices are known that measure voltages by converting analog voltages supplied from analog voltage terminals into digital values. The AD conversion device includes a multiplexer. Multiple analog voltage terminals are connected to the input side of the multiplexer via multiple channels. A capacitor, functioning as a voltage holding circuit, is connected to the output side of the multiplexer. Because the multiplexer can switch between channels, the AD conversion device can measure the analog voltages supplied from the analog voltage terminals for each channel. When measuring the analog voltage, the AD conversion device charges a capacitor with the supplied analog voltage and then converts it to a digital value. The AD conversion device then discharges the analog voltage charged in the capacitor after converting it to a digital value. If the magnitude of the load connected to each analog voltage terminal differs, the time required to charge the capacitor also differs for each channel. Furthermore, as the load connected to the terminal increases, the time required to charge the capacitor with the analog voltage (hereinafter referred to as the charging time) increases, and the time required to discharge the charged analog voltage from the capacitor (hereinafter referred to as the discharging time) also increases. Therefore, if the connected load is large but the charging time is short, the digital conversion occurs while the capacitor is charging, resulting in an incorrect digital value. Furthermore, if the connected load is small but the charging time is long, additional time is spent converting the digital value. Therefore, to appropriately set the charging time, there is a technique for setting a settling time, which is the time elapsed from the start of charging the capacitor until the capacitor voltage stabilizes. However, even with this technique, a charging time and a discharging time are required for each channel. Therefore, as the number of channels increases or as the number of channels with large connected loads increases, the overall period required to convert the analog voltage supplied from each channel to a digital value becomes longer. Therefore, in the present disclosure, control is performed to selectively switch the output channel from among multiple input channels so that the measured voltage values ​​are in ascending order. This control can eliminate the process of discharging the voltage charged in the capacitor.Furthermore, with this control, the charging of the capacitor after switching channels is further charging a capacitor that is already charged to a certain extent, thereby shortening the charging time. As a result, it is possible to shorten the voltage measurement time for the entire device. Next, details of this disclosure will be described using the figures.

[0010] <Overall structure> 1 is a block diagram showing the internal configuration of an AD conversion device, which includes a multiplexer 100, a switch (hereinafter referred to as SW) 101, a capacitor 102, a voltage comparison circuit 103, and a selector 104.

[0011] (Multiplexer 100) The multiplexer 100 has a function of selectively switching an output channel from among multiple input channels. A plurality of analog voltage terminals are connected to the input side of the multiplexer 100 via multiple channels. FIG. 1 shows an example in which four analog voltage terminals (not shown) are connected to the input side of the multiplexer 100 via four channels Ch1, Ch2, Ch3, and Ch4. The multiple analog voltage terminals may be configured as a terminal block separate from the analog-to-digital conversion device. Alternatively, the multiple analog voltage terminals may be configured as a terminal block separate from the analog-to-digital conversion device. Alternatively, the multiple analog voltage terminals may be integrally provided at one of both ends of each channel.

[0012] Each of the multiple analog voltage terminals is connected to multiple different elements or circuits. Examples of elements connected to the analog voltage terminals include thermistors, photoelectric conversion elements, and output terminals. Thermistors measure ambient temperatures, such as room temperature. For ambient temperatures, thermistors only need to detect changes in ambient temperature over a period of a few minutes. When photoelectric conversion elements are used to detect the position of a measurement target by sensing changes in light, as in an interrupter, measurements must be taken at high-speeds of less than a few microseconds. Therefore, in this case, AD conversion is controlled to enable measurements at the fastest possible period among the multiple connected circuits. The output terminal is the output destination for the current measured by, for example, a circuit current measurement circuit after amplification. Examples of circuits connected to the analog voltage terminals include power supply voltage monitor circuits. Power supply voltage monitor circuits are designed to maintain a nearly constant voltage except under abnormal conditions.

[0013] (Capacitor 102; SW101; voltage comparator circuit 103; selector 104) A capacitor 102 is connected to the output side of the multiplexer 100 via a switch (SW) 101. The capacitor 102 functions as a voltage holding circuit. Therefore, the switch (SW) 101 can control whether or not the analog voltage supplied from the output side of the multiplexer 100 is supplied to the capacitor 102. The analog voltage is supplied to a voltage comparison circuit 103 via the capacitor 102 as an analog input signal supplied from an analog voltage terminal. The voltage comparison circuit 103 is connected between the capacitor 102 and a selector 104. The voltage comparison circuit 103 converts the analog voltage into a digital value based on the deviation between the analog voltage held by the capacitor 102 and a preset reference voltage. The voltage comparison circuit 103 can supply the converted digital value to the outside as the voltage value of each of channels Ch1 to Ch4. The voltage comparison circuit 103 is connected to the input side of the selector 104. AD conversion result registers 1 to 4 are connected to the output side of the selector 104. The AD conversion result registers 1 to 4 of the selector 104 are registers corresponding to the channels Ch1 to Ch4. Therefore, the digital value input from the voltage comparator circuit 103 to the selector 104 is output to one of the AD conversion result registers 1 to 4 and stored.

[0014] The AD conversion device includes a control circuit 105 , a timer 106 , a multiplexer switching counter 107 , an EEPROM 108 , a magnitude determination unit 109 , a switching order determination unit 110 , and an arithmetic circuit 111 .

[0015] (Control circuit 105) The control circuit 105 includes a ROM (Read Only Memory), a RAM (Random Access Memory), and a CPU (Central Processing Unit). The ROM stores various programs and data. The RAM functions as a working memory for the CPU. The control circuit 105 controls the multiplexer 100, the switch 101, the voltage comparator circuit 103, and the selector 104. The control circuit 105 can reset the multiplexer switching counter 107 by incrementing the count value by one and can read the current count value. The control circuit 105 can reset or start the timer 106. The control circuit 105 can read the current time. The control circuit 105 has a function of acquiring digital values ​​converted as voltage values ​​for each of the multiple channels in the voltage comparator circuit 103 by the CPU executing a predetermined program. The control circuit 105 has a function of changing the order in which the multiple channels are switched so that the voltage values ​​of the multiple channels are in ascending order by the CPU executing a predetermined program.

[0016] (Timer 106) The timer 106 has a function of measuring the settling time. The settling time is the time measured when the following operations are performed while the output side of the multiplexer 100 and the capacitor 102 are connected by SW101. In other words, the settling time is the time until the voltage of the capacitor 102 stabilizes. Therefore, the settling time does not include the discharge time. Furthermore, if the time elapsed since the analog voltage supplied from the analog voltage terminal to the capacitor 102 started to charge exceeds the settling time, the CPU controls SW101 as follows. That is, the CPU controls SW101 to change the state between the output side of the multiplexer 100 and the capacitor 102 from a conductive state to a non-conductive state.

[0017] (Multiplexer Switching Counter 107) The multiplexer switching counter 107 has a function of incrementing a count value by 1 each time the channel of the multiplexer 100 is switched. For example, in this embodiment, the count value starts from 1, and the switching order of the channels of the multiplexer 100 is determined so that the voltage value of the analog input signal increases each time the count value is incremented.

[0018] (EEPROM108) EEPROM 108 stores settling times, voltage values ​​for each channel, the magnitude relationship between the voltage values ​​for each channel, or the order in which the channels are switched. For example, control circuit 105 reads the voltage values ​​for each channel from EEPROM 108 and transmits them to magnitude determination unit 109. Control circuit 105 also reads the order in which the channels are switched from EEPROM 108. Control circuit 105 also reads data on the magnitude relationship between the voltage values ​​for each channel obtained by magnitude determination unit 109 from EEPROM 108 and transmits it to switching order determination unit 110.

[0019] (Size determination unit 109; Switching order determination unit 110; Arithmetic circuit 111) The magnitude judgment unit 109 judges the magnitude relationship of the voltage values ​​in each channel based on the voltage values ​​of the channels stored in EEPROM 108 or the values ​​of the AD conversion result register, and stores the judgment result in EEPROM 108. The switching order determination unit 110 determines the order in which the channels are switched based on the magnitude relationship of the voltage values ​​of the channels stored in EEPROM 108, and stores the determination result in EEPROM 108. The arithmetic circuit 111 has a function of calculating the average value of the voltage values ​​for each channel or the difference between the maximum and minimum voltage values ​​for the digital values ​​stored in EEPROM 108. Details of the arithmetic circuit 111 will be described later in the second embodiment.

[0020] (Discharge circuit 121) The AD conversion device includes a discharge circuit 121. The discharge circuit 121 is provided between SW101 and capacitor 102, and has a function of discharging the voltage charged in capacitor 102. The discharge circuit 121 is composed of, for example, a resistor. One end of the resistor is connected between SW101 and capacitor 102, and the other end of the resistor is connected to chassis ground 122.

[0021] (First embodiment) Next, using the flowcharts of FIGS. 2 to 5, a measurement method for changing the channel switching order in an AD conversion device connected to multiple analog signals, capable of acquiring highly accurate voltage values ​​in a short period of time, will be described. In the first embodiment, the channel switching order is changed so that the channel voltage values ​​are in ascending order, and if the magnitude of the voltage value has already been acquired, a process is executed to set a shorter settling time compared to when the voltage value is unknown. FIG. 2 is a flowchart explaining the process of the AD conversion device of FIG. 1. FIG. 3 is a flowchart explaining the process of the AD conversion device of FIG. 1. FIG. 4 is a flowchart explaining the process of S202 of FIG. 2. FIG. 5 is a flowchart explaining the process of S202 of FIG. 2. The processes shown in FIGS. 2 to 5 are realized in the control circuit 105 by the CPU reading a program stored in the ROM into the RAM and executing it. Specifically, the processes shown in FIGS. 2 to 5 are realized by the CPU reading and executing the program 21. More specifically, the processes shown in FIGS. 2 to 5 are executed as follows after the AD conversion device is powered on and initialization is executed. That is, the AD conversion device is executed at the timing when the conduction state between the analog voltage terminal and the multiplexer 100 is recognized via channels Ch1 to Ch4. Note that some or all of the functions of the steps in Figures 2 to 5 may be realized by hardware such as an ASIC or electronic circuit. The symbol "S" in the explanation of each process indicates a step in the flowchart.

[0022] In S201, the CPU sets settling time 1 and settling time 2 and stores them in the EEPROM 108. Settling time 1 is the settling time when the count value of the multiplexer switching counter 107 is 1. When the count value is 1, this is the timing at which measurement of the voltages of multiple channels begins. On the other hand, settling time 2 is the settling time when the count value of the multiplexer switching counter 107 is 2 or greater. Therefore, when the voltage of the channel being measured first is measured, the potential of the capacitor 102 is 0 V, and charging of the capacitor 102 begins from 0 V. Therefore, since it is expected that it will take some time for the voltage of the capacitor 102 to stabilize, settling time 1 is set to a settling time that is sufficiently longer than settling time 2. On the other hand, it is expected that the potential difference between the channels is small and the time it takes for the voltage value to stabilize is shorter than settling time 1. For this reason, settling time 2 is set to a value shorter than settling time 1.

[0023] In S202, the CPU acquires the voltage value of each channel and stores it in EEPROM 108. That is, in S202, the CPU acquires the voltage value for each channel. Details of the process of acquiring the voltage value for each channel will be described later with reference to FIGS. 4 and 5. In S202, the capacitor 102 is charged until the time elapsed since the start of the process exceeds settling time 1. In S203, the CPU acquires the voltage value for each channel stored in EEPROM 108 and executes the following process. First, the CPU determines whether the voltage values ​​are larger or smaller based on the acquired voltage values ​​using the magnitude determination unit 109. Next, the CPU stores the determination result in EEPROM 108. Next, based on the determination result, the CPU determines the channel switching order using the switching order determination unit 110 so that the channel switching order is from smallest to largest voltage value, and stores the determined switching order in EEPROM 108.

[0024] In S204, the CPU resets the count value of the multiplexer switching counter 107. This process sets the count value to 0. In S205, the CPU executes a process of controlling SW101 to the ON state (conductive state). This process causes the state between the multiplexer 100 and the capacitor 102 to transition from a non-conductive state to a conductive state. In S206, the CPU increments the count value of the multiplexer switching counter 107 by 1. That is, the CPU increments the current count value of 0 by 1 to set the count value to 1. In S207, the CPU controls the multiplexer 100 based on the count value of the multiplexer switching counter 107 and the channel switching order. That is, the CPU controls the multiplexer 100 to switch to the channel corresponding to the count value based on the switching order stored in S203.

[0025] In S208, the CPU starts the timer 106. In S209, the CPU determines whether the timer time is longer than settling time 2. If the timer time exceeds settling time 2, the CPU advances the process of S209 to S210. On the other hand, if the timer time is equal to or less than settling time 2, the CPU continues the process of S209. Since the switching order is set from smallest to largest voltage value in S203, when the count value of the multiplexer switching counter 107 is 1, the voltage value becomes smallest in all channels. Therefore, AD conversion can be performed in a short settling time 2. Furthermore, since the switching order is set from smallest to largest voltage value, the potential difference between the channels before and after switching is small. Therefore, AD conversion can be performed in other channels in a short settling time. Note that the process of S203 is based on the premise that the capacitor 102 has been charged until settling time 1 has been exceeded in S202.

[0026] In S210, the CPU controls SW101 to be in the OFF state (non-conducting state). This control stops charging of the capacitor 102. As a result, AD conversion by the voltage comparator circuit 103 can be started. In S211, the CPU starts AD conversion. As described above, AD conversion is performed by the voltage comparator circuit 103, and is a process of converting analog voltages for each channel into digital values ​​as voltage values ​​for each of channels Ch1 to Ch4. In S212, the CPU determines whether AD conversion has been completed. If AD conversion has been completed, the CPU advances the process of S212 to S213. If AD conversion has not been completed, the CPU continues the process of S212. In S213, the CPU reads the count value of the multiplexer switching counter 107 and controls the selector 104 to select the channels in the order stored in the EEPROM 108. In other words, the CPU controls the selector 104 to switch the channels so that the channels correspond to the count value of the multiplexer switching counter 107. In S214, the CPU writes the AD conversion result to the AD conversion result register. In S215, the CPU controls SW101 to be in the on state (conducting state). This control starts charging the capacitor 102. In S216, the CPU determines whether or not to continue the measurement. If the measurement is to be continued, the CPU advances the process of S216 to S217. In S217, the CPU determines whether or not the count value of the multiplexer switching counter 107 is 4. If the count value of the multiplexer switching counter 107 is 4, the CPU advances the process of S217 to S218. If the count value of the multiplexer switching counter 107 is 4, AD conversion has been performed on all channels. If the count value of the multiplexer switching counter 107 is not 4, the CPU returns the process of S217 to the process of S206. In S206, 1 is added to the current count value of the multiplexer switching counter 107, making the count value 2, and the processes of S206 to S215 are repeated again to perform AD conversion.In S218, the CPU determines the magnitude relationship of the voltage values ​​using the magnitude determination unit 109 based on the voltage values ​​for each channel stored in the AD conversion result register, and determines the switching order using the switching order determination unit 110. On the other hand, if measurement is not to be continued, the CPU advances the process of S216 to S219. In S219, the CPU controls SW101 to the off state (non-conducting state) and ends the process. Note that the CPU may also perform the process of determining the switching order using the switching order determination unit 110. If the CPU determines the switching order, it is possible to reduce the number of accesses to the EEPROM 108. Furthermore, if the switching order is determined by the switching order determination unit 110, it is possible to reduce the load on the CPU.

[0027] (Details of S202 processing) In S401, the CPU controls SW101 to be in the on state (conducting state). This control starts charging the capacitor 102. In S402, the CPU controls the multiplexer 100 based on a switching order pre-recorded in the EEPROM 108. In S403, the CPU starts the timer 106. In S404, the CPU determines whether the time counted by the timer 106 exceeds settling time 1. If the time counted by the timer 106 exceeds settling time 1, the CPU advances the process of S404 to S405. If the time counted by the timer 106 is equal to or less than settling time 1, the CPU repeats the process of S404. That is, the process of S403 starts a charging time measurement process in S404 to determine whether the charging time for the capacitor 102 exceeds settling time 1. In S405, the CPU controls SW101 to be in the off state. In S406, the CPU starts AD conversion. As described above, AD conversion is performed by the voltage comparator circuit 103, and is a process of converting the analog voltage for each channel into a digital value as the voltage value of each of channels Ch1 to Ch4. In S407, the CPU determines whether the AD conversion has been completed. If the AD conversion has been completed, the CPU advances the process of S407 to S408. If the AD conversion has not been completed, the CPU continues the process of S407. In S408, the CPU controls the selector 104 based on the switching order pre-stored in the EEPROM 108. For example, if AD conversion is performed after switching to channel Ch1 of the multiplexer 100, the selector 104 switches to channel Ch1. This allows the AD-converted digital value to be stored in the AD conversion result register 1. In S409, the CPU writes to the AD conversion result register. In S410, the CPU controls SW101 to be in the on state (conducting state). In S411, the CPU determines whether the channel is the last in the switching order. If it is the last channel in the switching order, the CPU advances the process from S411 to S412. In S412, the CPU controls SW101 to the OFF state (non-conducting state) and ends the process.On the other hand, if the channel is not the last one in the switching order, the CPU returns the process of S411 to the process of S402. Note that the switching order is stored in advance in the EEPROM 108, as described in S402.

[0028] FIG. 6 illustrates measurement results in the first embodiment. FIG. 6(a) illustrates an example of the voltage values ​​or AD values ​​acquired in S202 for each of channels Ch1 to Ch4. Here, the AD values ​​are values ​​acquired by repeatedly executing the processes of S803 to S825 in FIG. 8, as will be described in the second embodiment. In FIG. 6(a), the magnitude relationship of the voltage values ​​is channel Ch4<channel Ch1<channel Ch2<channel Ch3. Therefore, to arrange the voltage values ​​in ascending order, the channel switching order must be changed to channel Ch4, Ch1, Ch2, Ch3. FIG. 6(b) illustrates an example of the transition of the voltage value of the capacitor 102 when the channel switching order is changed based on the voltage values ​​in FIG. 6(a) and voltage values ​​are measured by the processes of S204 to S217. As is clear from FIG. 6(b), if the magnitude order of the channels is changed, the measurement order will be changed from the next measurement when the count value of the multiplexer switching counter 107 reaches 4. 7 is a diagram showing the measurement results of S202 in FIG. 2. That is, FIG. 7 is a diagram showing an example of the transition of the voltage value of the capacitor 102 when the voltage value is measured by the processes of S401 to S406 in FIG. 4 and S407 to S412 in FIG. 5. In this way, by using the settling time 1 for all channels, accurate AD conversion is possible even if the voltage value of each channel is unknown. Note that FIG. 6(b) shows an example in which the discharge process by the discharge circuit 121 is performed only after the voltage measurement of channel Ch3. On the other hand, FIG. 7 shows an example in which the discharge process by the discharge circuit 121 is performed after the voltage measurement of channels Ch3 and Ch4, respectively.

[0029] (effect) As a result, the channel switching order is changed from smallest to largest based on the acquired voltage values. This process makes it possible to reduce the potential difference in voltage values ​​before and after channel switching. This reduces the time required to charge and discharge the capacitor, and shortens the time required for AD conversion of each channel.

[0030] (Second embodiment) In the first embodiment, only the switching order is considered, and AD conversion is performed by changing the settling time to 2, which is shorter than settling time 1. Therefore, when the voltage value of each channel fluctuates significantly, accurate AD conversion is difficult with settling time 2. Therefore, in the second embodiment, an example is described in which measurement is possible in a short time even when the voltage value of each channel fluctuates significantly. Also, in the second embodiment, an example is described in which AD conversion can be performed with higher accuracy than in the first embodiment by optimizing the settling time based on previously acquired voltage values. In the second embodiment, the channel switching order is changed so that the channel voltage values ​​are in ascending order, and the following processing is performed. That is, in the second embodiment, processing is performed to set the settling time based on the potential difference between the channels or the difference between the maximum and minimum AD values ​​of each channel previously acquired.

[0031] 8 to 10 show flowcharts of the second embodiment. FIG. 8 is a flowchart illustrating the processing of the AD conversion device according to the second embodiment. FIG. 9 is a flowchart illustrating the processing of the AD conversion device according to the second embodiment. FIG. 10 is a flowchart illustrating the processing of the AD conversion device according to the second embodiment. The processing shown in FIGS. 8 to 10 is implemented by the CPU in the control circuit 105 by reading a program stored in ROM into RAM and executing it. Specifically, the processing shown in FIGS. 8 to 10 is implemented by the CPU reading and executing program 21. More specifically, the processing shown in FIGS. 8 to 10 is executed as follows after the AD conversion device is powered on and initialization processing is performed. That is, the AD conversion device executes the processing when the electrical continuity between the analog voltage terminals and the multiplexer 100 is recognized via channels Ch1 to Ch4. Note that some or all of the functions of the steps in FIGS. 8 to 10 may be implemented by hardware such as an ASIC or electronic circuit. The symbol "S" in the description of each process indicates a step in the flowchart.

[0032] In S801, the CPU sets settling time 1 and settling time 2 and stores them in the EEPROM 108. In the second embodiment, even if the voltage value of each channel fluctuates greatly, processing that allows measurement in a short time is executed. Large fluctuations in the voltage value are expected to indicate a large load connected to the analog voltage terminal. When the load is large, the analog voltage output from the load also increases, and it is expected that a long time is required for the voltage supplied to the capacitor 102 to stabilize. Therefore, settling time 1 is set to be sufficiently long, as in the first embodiment. On the other hand, settling time 2 is set to be shorter than settling time 1 because it is expected that the potential difference between the channels is small and the time it takes for the voltage value to stabilize is shorter than settling time 1.

[0033] In S802, the CPU acquires the voltage value of each channel and stores it in the EEPROM 108. That is, in S802, the CPU acquires the voltage value for each channel. As described above with reference to Figures 4 and 5, the process of acquiring the voltage value for each channel is detailed in S802, where the capacitor 102 is charged until the time elapsed since the start of the process exceeds the settling time 1.

[0034] In S803, the CPU determines whether the voltage values ​​of each channel are large or small using the magnitude determination unit 109, and determines the channel switching order using the switching order determination unit 110. Here, the voltage value of each channel is the voltage value of each channel obtained by the process of S802. Alternatively, the voltage value of each channel may be an average value based on multiple measurements of the AD value of each channel obtained by the process of S827. In S804, the arithmetic circuit 111 calculates the potential difference between the voltage values ​​of the previous and next channels in the switching order determined in S803 (hereinafter referred to as the potential difference of S804), and stores it in the EEPROM 108. In S805, the CPU sets a threshold for the potential difference of S804 (hereinafter referred to as the inter-channel voltage threshold or the threshold of S805), and stores it in the EEPROM 108. In S806, the magnitude determination unit 109 compares the potential difference of S804 with the threshold of S805, and stores the result in the EEPROM 108. In S807, the magnitude judgment unit 109 extracts the maximum and minimum values ​​of the 10 previously acquired AD values ​​for each channel, calculates the difference between them using the arithmetic circuit 111, and stores the difference in the EEPROM 108. Here, the previously acquired AD values ​​are values ​​acquired by repeatedly executing the processes of S603 to S625, as described with reference to FIG. 6(a). For example, to acquire 10 sets of past data, the process of S603 to S625 is repeated 40 (=4×10) times, since the number of channels multiplied by the number of data to be acquired. In S808, the CPU sets a threshold (hereinafter referred to as the single-channel voltage threshold or the S808 threshold) for the difference calculated in S807 (hereinafter referred to as the S807 difference), and stores the threshold in the EEPROM 108. In S809, the magnitude judgment unit 109 compares the S807 difference with the S808 threshold to determine whether the difference is larger or smaller, and stores the result in the EEPROM 108. In S810, the CPU resets the multiplexer switching counter 107 to set the count value to 0. In S811, the CPU turns on SW101 (to the conductive state) to establish electrical continuity between the multiplexer 100 and the capacitor 102. In S812, the CPU adds 1 to the count value of the multiplexer switching counter 107 to set the count value to 1.In S813, the CPU controls the multiplexer 100 so that the first channel is selected based on the switching order stored in the EEPROM 108, as in the case of the count value described above. That is, the CPU controls the multiplexer 100 based on the count value of the multiplexer switching counter 107 and the channel switching order. In S814, the CPU starts the timer 106. In S815, the CPU determines the following (i) to (iii). In (i), based on the result of S806, it is determined whether the potential difference in voltage value between the channel measured immediately before, i.e., the previously measured channel, is equal to or greater than a threshold value (single-channel voltage threshold). In (ii), based on the result of S809, it is determined whether the difference between the minimum and maximum voltage values ​​in the channel is equal to or greater than a threshold value (inter-channel voltage threshold). In (iii), it is determined whether the channel measured immediately before, i.e., the previously measured channel, was (ii). If any of the above (i) to (iii) applies, the CPU advances the process of S815 to S816. In S816, the CPU determines whether the timer time exceeds settling time 1. If the timer time exceeds settling time 1, the CPU advances the process of S816 to S818. If the timer time is equal to or less than settling time 1, the CPU continues the process of S816. In other words, the CPU performs AD conversion for settling time 1, which is a sufficiently long settling time.

[0035] Here, we will explain why settling time 1 is applied to (i) above. This is because in use cases where the potential difference between channels before and after switching is large, it is expected that it will take time for the capacitor voltage value to stabilize. We will explain why settling time 1 is applied to (ii) above. This is because in use cases where the voltage value of a channel corresponding to (ii) is expected to fluctuate significantly each time it is measured, the potential difference in the voltage value from the channel measured immediately before may become large. We will explain why settling time 1 is applied to (iii) above. This is because in use cases where the channel previously measured was (ii), the measurement is made immediately after the channel corresponding to (ii) above, so the potential difference in the voltage value from the channel measured immediately before may become large.

[0036] On the other hand, if none of (i) to (iii) of S815 applies, the CPU advances the process of S815 to S817. In S817, the CPU determines whether the timer time exceeds settling time 2. If the timer time exceeds settling time 2, the CPU advances the process of S817 to S818. If the timer time is equal to or less than settling time 2, the CPU continues the process of S817. In other words, if none of (i) to (iii) of S815 applies, the CPU performs AD conversion for settling time 2, which is a settling time shorter than settling time 1.

[0037] In S818, the CPU controls SW101 to the OFF state (non-conducting state). That is, when the time of the timer 106 exceeds the settling time, the CPU controls SW101 to the OFF state (non-conducting state). In S819, the CPU starts AD conversion. In S820, the CPU determines whether the AD conversion has ended. If the AD conversion has ended, the CPU advances the process of S820 to S821. If the AD conversion has not ended, the CPU continues the process of S820. In S821, the CPU reads the count value of the multiplexer switching counter 107 and controls the selector 104 so that the channels are in the order stored in the EEPROM 108. That is, the CPU controls the selector 104 so that the channels correspond to the value of the multiplexer switching counter 107. In S822, after switching the selector 104, the CPU writes the AD conversion result to the AD conversion result register. In S823, the CPU controls SW101 to the ON state (conducting state). In S824, the CPU determines whether or not to continue the measurement. If the measurement is to be continued, the CPU advances the process of S824 to S825. In S825, the CPU determines whether or not the count value of the multiplexer switching counter 107 is 4. If the count value of the multiplexer switching counter 107 is 4, the CPU advances the process of S825 to S826. In S826, the CPU stores the values ​​for each channel stored in the AD conversion result register in EEPROM 108. In S827, the CPU calculates the average value of the 10 AD values ​​previously acquired for each channel, stores this average value in EEPROM 108, and returns the process of S827 to S803. In S825, if the count value of the multiplexer switching counter 107 is not 4, the CPU returns the process of S825 to S812. In S812, for example, if the value of the multiplexer switching counter 107 is 1, the CPU adds 1 to the value of 1 to make the value 2, and performs AD conversion again in S812 to S823. On the other hand, if measurement is not to be continued, the CPU advances the process of S824 to the process of S828. In S828, the CPU controls SW101 to the OFF state (non-conducting state) and ends the process.

[0038] FIG. 11 shows measurement results in the second embodiment. FIG. 11(a) shows an example of the maximum and minimum AD values ​​previously acquired for each channel. FIG. 11(b) shows an example of the transition of the voltage value of the capacitor 102 when the channel switching order is determined based on the average AD value of FIG. 11(a) and measurements are performed by the processes of S803 to S825. FIG. 11(b) shows an example in which settling time 1 is applied to channel Ch1 as a result of the determination in S815(ii). FIG. 11(b) also shows an example in which settling time 1 is applied to channel Ch2 as a result of the determination in S815(iii). Note that FIG. 11(b) shows an example in which the discharge process by the discharge circuit 121 is performed only after the voltage measurement of channel Ch3.

[0039] (effect) As described above, according to the second embodiment, the settling time may be optimized based on the potential difference between channels before and after switching or the range of fluctuation of the voltage value in each channel (for example, whether the difference between the minimum and maximum values ​​is equal to or greater than a threshold value). According to this processing, if it is assumed that the load connected to the analog voltage terminal is large, the settling time is set to settling time 1. This makes it possible to ensure an appropriate charging time. Therefore, it is possible to perform AD conversion with higher accuracy than in the first embodiment.

[0040] <Other embodiments> Although various examples and embodiments of the present disclosure have been shown and described above, the spirit and scope of the present disclosure are not limited to the specific descriptions in this specification. The present disclosure is not limited to the above-described embodiments, and various modifications may be made. Furthermore, the present disclosure may be realized by appropriately combining parts of the above-described embodiments.

[0041] (Variation 1) For example, although an example has been described in which four analog voltage terminals are connected to the input side of the multiplexer 100 via four channels Ch1, Ch2, Ch3, and Ch4, the present invention is not limited to this example and five or more analog voltage terminals may be connected to the input side of the multiplexer 100 via five or more channels.

[0042] (Variation 2) Furthermore, while the control example has been described in which all voltage values ​​obtained from multiple channels are rearranged in ascending order, this is not limiting. The voltage values ​​obtained from some of the multiple voltage values ​​obtained from multiple channels may be rearranged in ascending order. For example, among channels Ch1 to Ch4, only the voltage values ​​obtained from channels Ch1 and Ch2 may be rearranged in ascending order. For example, if the voltage value obtained from channel Ch1 is higher than the voltage value obtained from channel Ch2, the switching order is rearranged so that channel Ch1 comes after channel Ch2. With this operation, the discharge process of capacitor 102 is not required when switching from channel Ch2 to channel Ch1. Therefore, the time required to switch between at least two channels can be shortened. In other words, even if the channel switching order is rearranged in a partial ascending order obtained by partial rearrangement, the switching time can be shortened.

[0043] (Variation 3) Although the above description is of an example in which the settling time is optimized based on the potential difference between channels before and after switching or the range of voltage fluctuations in each channel, the present invention is not limited to this. For example, if the current AD value of channel Ch3 is significantly different from the previous nine AD values ​​acquired, an abnormality flag indicating that channel Ch3 should be excluded from the next voltage measurement may be stored in EEPROM 108. In this way, for example, if the output of a temperature monitoring device is supplied as an analog voltage to one of the multiple analog voltage terminals and the analog voltage indicates an abnormal value, the abnormality flag can be referenced to enable early maintenance.

[0044] The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., ASIC) that realizes one or more functions. The program may also be provided by recording it on a computer-readable storage medium.

[0045] The disclosure of the present embodiment includes configurations typified by the following analog-to-digital conversion device and analog-to-digital conversion method.

[0046] <Configuration 1> An analog-to-digital conversion device having a multiplexer that selectively switches an output channel from among a plurality of input channels, an acquisition means for acquiring a voltage value of each of the plurality of channels; a control means for controlling the switching of the output channels from among the plurality of channels so that the magnitudes of the respective voltage values ​​are in ascending order; An analog-to-digital conversion device comprising:

[0047] <Configuration 2> The analog-to-digital conversion device according to configuration 1 further comprises a voltage holding circuit provided between the output side of the multiplexer and the input side of the acquisition means, which is charged to the same potential as the analog voltages supplied from each of the plurality of channels, and which holds the charged analog voltages.

[0048] <Configuration 3> a voltage comparison circuit provided on the output side of the voltage holding circuit; The voltage comparison circuit a comparison means for converting the analog voltage held by the voltage holding circuit into a digital value based on a deviation between the analog voltage and a preset reference voltage; The acquisition means; Including, 3. The analog-to-digital conversion device according to configuration 2, wherein the acquisition means acquires the digital values ​​as the respective voltage values.

[0049] <Configuration 4> further comprising a determination means for determining the magnitude relationship between the respective voltage values, 3. The analog-to-digital conversion device according to configuration 2, wherein the control means determines the order based on the magnitude relationship.

[0050] <Configuration 5> a switch provided between the multiplexer and the voltage holding circuit, the switch bringing the output side of the multiplexer and the voltage holding circuit into either a conductive state or a non-conductive state; The analog-to-digital conversion device according to configuration 4, wherein the control means controls the switch from the conductive state to the non-conductive state when the time elapsed since charging of the voltage holding circuit started exceeds a settling time, which is the time required for the voltage of the voltage holding circuit to stabilize.

[0051] <Configuration 6> voltages corresponding to the respective voltage values ​​are supplied from a plurality of analog voltage terminals via the plurality of channels; The analog-to-digital conversion device according to configuration 5, wherein the control means sets a first settling time as the settling time when the magnitudes of the voltages supplied from the plurality of analog voltage terminals are unknown, and sets a second settling time, which is shorter than the first settling time, as the settling time when the magnitudes of the voltages supplied from the plurality of analog voltage terminals have been acquired as the respective voltage values.

[0052] <Configuration 7> The analog-to-digital conversion device according to configuration 6, wherein the control means sets the first settling time as the settling time when a potential difference in voltage values ​​between channels before and after switching from among the plurality of channels is equal to or greater than a predetermined inter-channel voltage threshold, and sets the second settling time as the settling time when a potential difference in voltage values ​​between channels before and after switching from among the plurality of channels is less than the inter-channel voltage threshold.

[0053] <Configuration 8> The analog-to-digital conversion device according to configuration 6, wherein the control means sets the settling time to the first settling time when, among the results of multiple measurements of the voltage values ​​of each of the channels, a difference between the minimum and maximum voltage values ​​of the measurement results is equal to or greater than a predetermined single-channel voltage threshold, and sets the settling time to the second settling time when, among the results of multiple measurements of the voltage values ​​of each of the channels, a difference between the minimum and maximum voltage values ​​of the measurement results is less than the single-channel voltage threshold.

[0054] <Configuration 9> 5. The analog-to-digital conversion device according to configuration 4, wherein the control means sets an average value of measurement results obtained by performing measurements multiple times for each of the plurality of channels as the magnitude of each of the voltage values.

[0055] <Configuration 10> A plurality of registers; a selector provided between an output side of the voltage comparator circuit and input sides of the plurality of registers, the selector being capable of selecting one of the plurality of registers as a destination for storing the digital value; The analog-to-digital conversion device according to configuration 3, further comprising:

[0056] <Configuration 11> a discharge circuit that discharges the analog voltage held by the voltage holding circuit; The analog-to-digital conversion device of claim 5, characterized in that when the control means controls the switch from the conductive state to the non-conductive state while selecting the last channel in the sequence as the channel to be output from among the plurality of channels, it causes the discharge circuit to start discharging.

[0057] <Configuration 12> An analog-to-digital conversion method for an analog-to-digital conversion device having a multiplexer that selectively switches an output channel from among a plurality of input channels, comprising: an acquisition step of acquiring a voltage value of each of the plurality of channels; a control step of performing control to change the order of switching channels to be output from among the plurality of channels so that the magnitudes of the respective voltage values ​​are in ascending order; 1. An analog-to-digital conversion method comprising: [Explanation of symbols]

[0058] 100 Multiplexer 101 SW 102 Capacitor 103 Voltage comparison circuit 104 Selectors 105 Control circuit 106 Timer 107 Multiplexer Switching Counter 108 EEPROM 109 Size judgment part 110 Switching order determination unit 111 Arithmetic circuit

Claims

1. An analog-to-digital conversion device having a multiplexer that selectively switches an output channel from among a plurality of input channels, an acquisition means for acquiring a voltage value of each of the plurality of channels; a control means for controlling the switching of the output channels from among the plurality of channels so that the magnitudes of the respective voltage values ​​are in ascending order; An analog-to-digital conversion device comprising:

2. 2. The analog-to-digital conversion device according to claim 1, further comprising a voltage holding circuit provided between the output side of the multiplexer and the input side of the acquisition means, which is charged to the same potential as the analog voltages supplied from each of the plurality of channels and holds the charged analog voltages.

3. a voltage comparison circuit provided on the output side of the voltage holding circuit; The voltage comparison circuit a comparison means for converting the analog voltage held by the voltage holding circuit into a digital value based on a deviation between the analog voltage and a preset reference voltage; The acquisition means; Including, 3. The analog-to-digital conversion device according to claim 2, wherein the acquisition means acquires the digital values ​​as the respective voltage values.

4. further comprising a determination means for determining the magnitude relationship between the respective voltage values, 3. The analog-to-digital conversion device according to claim 2, wherein said control means determines said order based on said magnitude relationship.

5. a switch provided between the multiplexer and the voltage holding circuit, the switch bringing the output side of the multiplexer and the voltage holding circuit into either a conductive state or a non-conductive state; 5. The analog-to-digital conversion device according to claim 4, wherein the control means controls the switch from the conductive state to the non-conductive state when the time elapsed since charging of the voltage holding circuit began exceeds a settling time, which is the time required for the voltage of the voltage holding circuit to stabilize.

6. voltages corresponding to the respective voltage values ​​are supplied from a plurality of analog voltage terminals via the plurality of channels; 6. The analog-to-digital conversion device according to claim 5, wherein the control means sets a first settling time as the settling time when the magnitudes of the voltages supplied from the plurality of analog voltage terminals are unknown, and sets a second settling time, which is shorter than the first settling time, as the settling time when the magnitudes of the voltages supplied from the plurality of analog voltage terminals have been acquired as the respective voltage values.

7. 7. The analog-to-digital conversion device according to claim 6, wherein the control means sets the first settling time as the settling time when a potential difference in voltage values ​​between channels before and after switching from among the plurality of channels is equal to or greater than a predetermined inter-channel voltage threshold, and sets the second settling time as the settling time when a potential difference in voltage values ​​between channels before and after switching from among the plurality of channels is less than the inter-channel voltage threshold.

8. 7. The analog-to-digital conversion device according to claim 6, wherein the control means sets the settling time to the first settling time when, among the results of multiple measurements of the voltage values ​​of each of the channels, a difference between the minimum and maximum voltage values ​​of the measurement results is equal to or greater than a predetermined single-channel voltage threshold, and sets the settling time to the second settling time when, among the results of multiple measurements of the voltage values ​​of each of the channels, a difference between the minimum and maximum voltage values ​​of the measurement results is less than the single-channel voltage threshold.

9. 5. The analog-to-digital conversion device according to claim 4, wherein the control means sets an average value of measurement results obtained by measuring a plurality of times for each of the plurality of channels as the magnitude of each of the voltage values.

10. A plurality of registers; a selector provided between an output side of the voltage comparator circuit and input sides of the plurality of registers, the selector being capable of selecting one of the plurality of registers as a destination for storing the digital value; 4. The analog-to-digital conversion device according to claim 3, further comprising:

11. a discharge circuit that discharges the analog voltage held by the voltage holding circuit; The analog-to-digital conversion device according to claim 5, characterized in that when the control means controls the switch from the conductive state to the non-conductive state while selecting the last channel in the sequence as the channel to be output from among the plurality of channels, the control means causes the discharge circuit to start discharging.

12. An analog-to-digital conversion method for an analog-to-digital conversion device having a multiplexer that selectively switches an output channel from among a plurality of input channels, comprising: an acquisition step of acquiring a voltage value of each of the plurality of channels; a control step of performing control to change the order of switching channels to be output from among the plurality of channels so that the magnitudes of the respective voltage values ​​are in ascending order; 1. An analog-to-digital conversion method comprising:

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