Wafer processing tape

Abstract

To provide a wafer processing tape capable of suppressing warpage of a wafer and facilitating peeling of the wafer from the tape after completion of a back grinding step and a dicing step, and to provide a wafer processing method using the wafer processing tape.SOLUTION: A wafer processing tape comprising: a base layer having a first face and a second face opposite to the first face; and a front face layer laminated on the first face and in contact with a wafer, wherein a storage modulus ES1 of the front face layer at 23 °C is 30MPa or more, and a storage modulus EM1 of the base layer at 23 °C is less than 30MPa.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The present invention relates to a tape for wafer processing. [Background technology]

[0002] When a semiconductor wafer (hereinafter also referred to as "wafer") or the like is diced, a dicing tape is attached to the wafer, the wafer is diced, and the dicing tape is expanded. After expansion, the chips obtained by dicing the wafer are picked up (peeled) from the dicing tape.

[0003] As such a backgrind tape, for example, Patent Document 1 discloses an adhesive film including a base layer, an irregularity-absorbing resin layer, and an adhesive resin layer in this order. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2019-065168 Summary of the Invention [Problem to be solved by the invention]

[0005] Patent document 1 explains that by providing an adhesive film with an irregularity-absorbing resin layer, the irregularities caused by the bumps can be absorbed even if the size of the bumps formed on the surface of the wafer becomes large, and that by making the irregularity-absorbing resin layer have a specific composition, the cutting ability of the adhesive film can be improved.

[0006] Before singulating a wafer, a back-grinding process is generally performed in which the back side of the wafer, on which no elements or the like are provided, is polished to thin the wafer, and a dicing process is generally performed in which the wafer is diced after the back-grinding process. In both the back-grinding process and the dicing process, the wafer needs to be fixed to a pedestal, and tape is used to fix the wafer to the pedestal in both processes. While the tape used in both processes was typically different, using the same tape in both processes and allowing the back-grinding process and the dicing process to be performed continuously can enable more efficient singulation of the wafer.

[0007] However, it was found that when the same tape is used in both processes, the wafer warps significantly during the dicing process. When a wafer with a large warp is diced, the wafer cannot be divided as designed, and not only does this deteriorate the division ability, but the warpage of the wafer can also make it difficult to transport.

[0008] Furthermore, it is preferable to make it easy to peel the wafer from the tape after the back grinding and dicing steps, from the viewpoint of facilitating subsequent steps.

[0009] The present invention has been made in consideration of the above-mentioned problems, and has an object to provide a wafer processing tape that can suppress warping of the wafer and make it easier to peel the wafer from the tape after the back-grinding process and dicing process are completed, and a wafer processing method that uses the wafer processing tape. [Means for solving the problem]

[0010] The present inventors have conducted extensive research to solve the above problems, and as a result, have discovered a method for manufacturing a semiconductor device comprising: a base layer having a first surface and a second surface opposite to the first surface; and a surface layer laminated on the first surface and in contact with a wafer, wherein the surface layer has a storage modulus E at 23°C of S1 is 30 MPa or more, and the storage modulus E of the base material layer at 23 ° C. M1However, they found that a wafer processing tape having a compressive strength of less than 30 MPa can solve the above problems, and thus completed the present invention.

[0011] That is, the present invention includes the following aspects. [1] a substrate layer having a first surface and a second surface opposite to the first surface; a surface layer laminated on the first surface and in contact with the wafer; The storage modulus E of the surface layer at 23 ° C. S1 is 30 MPa or more, The storage modulus E of the substrate layer at 23°C M1 is less than 30 MPa, Tape for wafer processing. [2] The storage modulus E S1 The storage modulus E M1 The ratio (E M1 / E S1 ) is 0.05 to 0.90, [1] The wafer processing tape according to [1]. [3] The storage modulus E of the surface layer at 120 ° C. S2 The storage modulus E of the base material layer at 120 ° C. M2 The ratio (E M2 / E S2 ) is 0.3 to 1.4, [1] or [2]. The wafer processing tape according to [1] or [2]. [4] The thickness of the surface layer is 5 to 40% of the total thickness of the wafer processing tape. The tape for wafer processing according to any one of [1] to [3]. [5] The thickness of the base layer is 50 to 250 μm. The tape for wafer processing according to any one of [1] to [4]. [6] The thickness of the surface layer is 3 to 30 μm. The tape for wafer processing according to any one of [1] to [5]. [7] The substrate layer contains an acrylic elastomer. The tape for wafer processing according to any one of [1] to [6]. [8] The surface layer contains an acrylic elastomer. The tape for wafer processing according to any one of [1] to [7]. [9] a back surface layer laminated on the second surface; The storage modulus E of the back layer at 23 ° C. B1 is 30 MPa or more, The tape for wafer processing according to any one of [1] to [8].

[10] The storage modulus E B1 The storage modulus E of the base layer at 23 ° C. M1 The ratio (E M1 / E B1 ) is 0.05 to 0.90, [9] The wafer processing tape according to [9].

[11] The storage modulus E of the back layer at 120 ° C. B2 The storage modulus E of the base material layer at 120 ° C. M2 The ratio (E M2 / E B2 ) is 0.3 to 1.4, [9] or

[10] . The wafer processing tape according to

[10] .

[12] The thickness of the back surface layer is 5 to 40% of the total thickness of the wafer processing tape. The tape for wafer processing according to any one of [9] to

[11] .

[13] The thickness of the back surface layer is 3 to 30 μm. The tape for wafer processing according to any one of [9] to

[12] .

[14] The back surface layer contains an acrylic elastomer. The tape for wafer processing according to any one of [9] to

[13] .

[15] a back-grinding step of grinding a non-element-formed surface of the wafer attached to the wafer processing tape; and a dicing step of dicing the wafer attached to the wafer processing tape after the back-grinding step, The tape for wafer processing according to any one of [1] to

[14] .

[16] a bonding step of bonding a surface layer of the tape for wafer processing according to any one of [1] to

[15] to an element-forming surface of a wafer; a back grinding step of grinding a non-element forming surface of the wafer bonded to the wafer processing tape; a dicing step of dicing the wafer bonded to the wafer processing tape after the back-grinding step; Wafer processing method.

[17] In the dicing step, a modified portion is generated inside the wafer by laser dicing.

[16] The wafer processing method according to

[16] .

[18] a peeling step of heating and peeling off the wafer processing tape after the dicing step; The wafer processing method according to

[16] or

[17] . [Brief explanation of the drawings]

[0012] [Figure 1A] 1 is a perspective view of a wafer processing tape according to an embodiment of the present invention; [Figure 1B] 1B shows an example of a cross-sectional view taken along line AA' in FIG. 1A. [Figure 2] An example of a wafer 200 to be attached to the wafer processing tape 100 is shown. [Figure 3A] FIG. 10 shows an example of a perspective view of a back grinding process. [Figure 3B] 3B shows an example of a cross-sectional view taken along line AA' in FIG. 3A. [Figure 4A] 1A and 1B show an example of a perspective view of a dicing process. [Figure 4B] 4B shows an example of a cross-sectional view taken along line AA' in FIG. 4A. DETAILED DESCRIPTION OF THE INVENTION

[0013] Hereinafter, an embodiment of the present invention (hereinafter referred to as "the present embodiment") will be described in detail with reference to the drawings as necessary, but the present invention is not limited to this, and various modifications are possible without departing from the spirit of the present invention. In the drawings, the same elements are given the same reference numerals, and redundant explanations will be omitted. Furthermore, positional relationships such as up, down, left, and right will be based on the positional relationships shown in the drawings unless otherwise specified. Furthermore, the dimensional ratios of the drawings are not limited to those shown in the drawings.

[0014] 1. Wafer processing tape The wafer processing tape of this embodiment includes a base layer having a first surface and a second surface opposite to the first surface, and a surface layer laminated on the first surface and in contact with the wafer, and the surface layer has a storage modulus E at 23°C of S1 is 30 MPa or more, and the storage modulus E of the base material layer at 23 ° C. M1 However, it is less than 30 MPa.

[0015] FIG. 1 shows an example of a perspective view of the wafer processing tape of this embodiment. The wafer processing tape 100 of this embodiment may be composed of a base layer 110 and a surface layer 120. Alternatively, as shown in FIG. 1A, it may be composed of a base layer 110, a surface layer 120, and a back layer 130, and other layers may be provided as necessary. Of the two surfaces of the base layer 110, the surface facing the surface layer 120 is referred to as a first surface 111, and the surface opposite the first surface 111 is referred to as a second surface 112. The back layer 130 is provided on the second surface 112 side.

[0016] 2 shows an example of a wafer 200 attached to the wafer processing tape 100. The wafer 200 has an element-forming surface 210 on which elements 230 such as circuits are formed, and a non-element-forming surface 220 on the opposite side of the element-forming surface 210 on which no elements 230 are formed.

[0017] The wafer 200 is not particularly limited, but may be a conventional general-purpose semiconductor wafer such as a silicon wafer, a gallium nitride wafer, a silicon carbide wafer, or a sapphire wafer.

[0018] As will be described later, in the wafer processing method of this embodiment, preferably, after the wafer processing tape 100 is bonded to the element forming surface 210 of the wafer 200, a backgrinding process is performed to grind the non-element forming surface 220 of the wafer 200, and then a dicing process is performed to irradiate the wafer 200 with a laser to form the modified region 240 without peeling the wafer 200 from the wafer processing tape 100. In a wafer processing tape used when such a backgrinding process and dicing process are performed consecutively, it is required that warpage of the wafer be suppressed during the dicing process in order to improve the divisibility and transportability of the wafer 200.

[0019] From this viewpoint, in the wafer processing tape 100 of this embodiment, the storage modulus E M1 It is specified that the pressure is less than 30 MPa.

[0020] The surface area of ​​the wafer 200 after the dicing process tends to be larger than the surface area of ​​the wafer 200 before the dicing process. For example, when the dicing process is performed by laser dicing, in which a laser is irradiated onto the wafer 200 to form a modified portion inside the wafer 200, the volume of the modified portion expands, and therefore the surface area of ​​the wafer 200 after the dicing process tends to be larger. In particular, when the wafer 200 is made of a single crystal such as silicon, the modified portion formed by laser irradiation tends to expand in volume as it becomes polycrystallized.

[0021] Thus, the dimensions of the wafer processing tape 100 remain unchanged while the wafer 200 expands during the dicing process. Therefore, the surface area of ​​the wafer 200 increases after the dicing process. As the wafer processing tape 100 expands in the in-plane direction of the first surface 111 and the second surface 112, a contracting stress acts on the wafer processing tape 100 in the in-plane direction. If this contracting force is large, the wafer 200 warps. Furthermore, since the wafer 200 after the dicing process has already undergone the back-grinding process, its thickness is thin. Therefore, it tends to warp more easily due to the contracting force. The in-plane direction here refers to the in-plane direction of the surface of the wafer processing tape 100, which is perpendicular to the stacking direction in which the wafer 200 is stacked on the wafer processing tape 100.

[0022] In this regard, the wafer processing tape 100 of this embodiment has a storage modulus E M1 Since the compressive strength is less than 30 MPa and the wafer 200 is flexible, the contraction force is sufficiently weak, and warpage of the wafer 200 after the dicing process can be reduced.

[0023] Furthermore, it is preferable that the wafer processing tape 100 can be easily peeled off from the wafer 200 after the wafer processing tape 100 is attached to the wafer 200 and the backgrinding process and dicing process are performed, from the viewpoint of making each process easier to perform and reducing contamination such as glue residue on the wafer 200.

[0024] In this regard, the wafer processing tape 100 of this embodiment has a storage modulus E S1 Since the tape 100 has a suitable hardness of 30 MPa or more, it can prevent the wafer processing tape 100 and the wafer 200 from being excessively adhered to each other, and can facilitate peeling of the wafer 200 from the wafer processing tape 100. In other words, it can improve the peelability of the wafer 200.

[0025] As described above, the wafer processing tape 100 of this embodiment has the base layer 110 and the surface layer 120, and therefore can reduce warpage of the wafer 200 and improve the peelability of the wafer 200 at the same time.

[0026] Storage modulus E of base layer 110 M1 is preferably 0.1 to 30.0 MPa, 0.1 to 25.0 MPa, or 0.1 to 20.0 MPa. M1 When the thickness is within the above range, the warpage of the wafer 200 tends to be further reduced.

[0027] Storage modulus E of surface layer 120 S1 is preferably 30.0 to 200.0 MPa, 40.0 to 175.0 MPa, or 50.0 to 150.0 MPa. S1 When the thickness is within the above range, the peelability of the wafer 200 tends to be further improved.

[0028] Storage modulus E of base layer 110 S1 Storage modulus E of the surface layer 120 M1 The ratio (E M1 / E S1 ) is preferably 0.001 to 0.900, 0.010 to 0.800, 0.050 to 0.700, 0.075 to 0.600, or 0.100 to 0.500. When the ratio is within the above range, warpage of the wafer 200 can be further reduced, and the peelability of the wafer 200 can be further improved.

[0029] In this embodiment, the storage modulus of the base layer 110 and the storage modulus of the surface layer 120 are measured at 23°C. Here, 23°C is a reference temperature for performing a wafer processing method, such as a backgrinding process, in this embodiment. In this regard, it is also conceivable that the wafer 200 bonded to the wafer processing tape 100 may be processed at a temperature higher or lower than 23°C in some cases. However, even if the actual temperature during processing of the wafer 200 bonded to the wafer processing tape 100 is not 23°C but is higher or lower than this, it can be said that warpage of the wafer 200 can be reduced and peelability of the wafer 200 can be improved by ensuring that the storage modulus of the base layer 110 and the storage modulus of the surface layer 120 measured with reference to 23°C fall within the predetermined range.

[0030] The storage modulus of the base layer 110 and the surface layer 120 can be adjusted by the type and composition of the base layer 110 and the surface layer 120. For example, when a block copolymer of monomers containing methyl (meth)acrylate (MMA) and n-butyl (meth)acrylate (BA) is used in the base layer 110 or the surface layer 120, the storage modulus of the copolymer tends to improve by increasing the proportion of MMA, and tends to decrease by increasing the proportion of BA.

[0031] Furthermore, from the viewpoint of sufficiently weakening the above-mentioned contraction force of the wafer processing tape 100 and reducing warpage of the wafer 200 after the dicing process, the wafer processing tape 100 is stretched 10% of its original length in at least one direction within the plane of the wafer processing tape 100 at 23°C and held there, and in the load change curve against time, the point at which the wafer processing tape 100 has stretched 10% is set to t=0s, and the contraction load at t=30s is preferably 0 to 10N, 0 to 8N, 0 to 6N, 0 to 4N, or 0 to 2N.

[0032] When the shrinkage load becomes sufficiently low after a sufficient amount of time has passed since the wafer processing tape 100 was stretched, warpage of the wafer 200 after the dicing process tends to be reduced.

[0033] In this embodiment, the wafer processing tape 100 is stretched 10% relative to its original length in at least one direction within the plane of the wafer processing tape 100 and held in place, and the load-change curve versus time is measured at 23°C. Here, 23°C is a reference temperature used in this embodiment to indicate the temperature at which the wafer processing tape 100 is peeled from the wafer 200 after the dicing process. In this regard, it is also possible that the wafer processing tape 100 may be peeled from the wafer 200 at temperatures higher or lower than 23°C. However, even if the actual temperature at which the wafer processing tape 100 is peeled from the wafer 200 is not 23°C but is higher or lower than this, it can be said that warpage of the wafer 200 can be reduced by the contraction load satisfying a predetermined range in the load-change curve measured based on 23°C.

[0034] In this embodiment, 10% is used as a reference value for the degree of elongation when the wafer processing tape 100 is stretched and held at 23°C relative to its original length in at least one direction within the plane of the wafer processing tape 100. In this regard, it is expected that the wafer processing tape 100 may elongate by more or less than 10% after the dicing process in some cases. However, even if the degree of elongation of the wafer processing tape 100 after the dicing process is not 10%, but is more or less than this, it can be said that warpage of the wafer 200 can be reduced by ensuring that the contraction load measured based on 10% satisfies a predetermined range.

[0035] In this embodiment, the wafer processing tape 100 is stretched and held at 23°C by 10% of its original length in at least one direction within the plane of the wafer processing tape 100. It can be said that warpage of the wafer 200 can be reduced by ensuring that the shrinkage load satisfies a predetermined range in at least one direction. The one direction is not particularly limited, but may be, for example, the following direction. That is, in measuring the shrinkage load, a test piece of the wafer processing tape 100 is fixed to a measuring device. The one direction may be the one within the plane of the wafer processing tape 100 whose length does not change due to such fixation. Alternatively, the one direction may be the MD direction of the base layer 110. Alternatively, the TD direction of the base layer 110 may be the one direction. The MD direction is the direction in which resin flows when fabricating the base layer 110, and the TD direction is a direction perpendicular to the MD direction.

[0036] In this embodiment, the shrinkage load at t=30 s is used as a reference value for the shrinkage load. Here, 30 seconds is a reference value for the time from the end of the dicing process until the start of the next process, such as transporting the wafer 200. In this regard, it is expected that the next process, such as transporting the wafer 200, will start after a time longer or shorter than 30 seconds has elapsed since the end of the dicing process. However, even if the time until the start of the next process, such as transporting, is longer or shorter than 30 seconds, it can be said that warpage of the wafer 200 can be reduced by the shrinkage load measured based on t=30 s satisfying a predetermined range.

[0037] The shrinkage load is not particularly limited, but is measured, for example, according to the method described in JIS Z0237, except that the temperature condition is 23°C and the wafer processing tape 100 is stretched and held at 10% of its original length. In this case, the test piece has a rectangular parallelepiped shape with a width of 10 mm and a length of 100 mm, and is stretched and held at 10% of its original length in the longitudinal direction.

[0038] The wafer processing tape 100 of this embodiment is preferably used in a wafer processing method including a back-grinding process for polishing the non-element forming surface 220 of the wafer 200 attached to the wafer processing tape 100, and a dicing process for dicing the wafer 200 attached to the wafer processing tape 100 after the back-grinding process.

[0039] Each component of the wafer processing tape 100 of this embodiment will be described in detail below.

[0040] 1.1. Base material layer The wafer processing tape 100 of this embodiment includes a base layer 110 .

[0041] The thickness of the base layer 110 at room temperature (23°C) is preferably 50 to 250 μm, 75 to 225 μm, or 100 to 200 μm. The thinner the base layer 110, the smaller the contraction force of the base layer 110, and the more likely it is that warpage of the wafer 200 can be reduced. On the other hand, if the base layer 110 is too thin, the wafer processing tape 100 will not be able to adhere sufficiently to the wafer 200, and the wafer 200 may not be sufficiently fixed in the back-grinding and dicing processes. From this perspective, if the thickness of the base layer 110 is within the above range, warpage of the wafer 200 can be reduced and the wafer 200 will tend to be sufficiently fixed.

[0042] Furthermore, the thickness of the base layer 110 at room temperature is preferably 50 to 90%, 55 to 85%, or 60 to 80% of the total thickness of the wafer processing tape 100. When the thickness of the base layer 110 is within the above range, warpage of the wafer 200 tends to be reduced, and the peelability of the wafer 200 tends to be improved.

[0043] Furthermore, when the wafer processing tape 100 of this embodiment is attached to the wafer 200, it is preferable to heat the wafer processing tape 100 to a high temperature before attaching it to the wafer 200 in order to improve the adhesion between the wafer processing tape 100 and the wafer 200. Here, if the storage modulus of the base layer 110 at high temperatures is low, the flexibility of the wafer processing tape 100 improves, and the wafer 200 tends to be able to be sufficiently fixed. From this perspective, the storage modulus E of the base layer 110 at 120°C is M2 is preferably 0.01 to 2.00 MPa, 0.05 to 1.75 MPa, 0.10 to 1.50 MPa, 0.30 to 1.25 MPa, or 0.50 to 1.00 MPa.

[0044] In addition, from the viewpoint of achieving both the fixation of the wafer 200 and the reduction of the warpage of the wafer 200, the storage elastic modulus E M1 Storage modulus E of the base layer 110 at 120 ° C. M2 The ratio (E M2 / E M1 ) is preferably 0.001 to 0.300, 0.010 to 0.200, 0.020 to 0.150, 0.030 to 0.100, or 0.030 to 0.050. Alternatively, the ratio (E M2 / E M1 ) is preferably 0.001 to 0.050.

[0045] The base layer 110 is not particularly limited, and may include, for example, a polymer. More specifically, the base layer 110 may include acrylic polymers such as copolymers of monomers containing ethylene, (meth)acrylic acid, and a (meth)acrylic acid ester, copolymers of monomers containing ethylene and ethyl (meth)acrylate, copolymers of monomers containing ethylene and (meth)acrylic acid, copolymers of monomers containing methyl (meth)acrylate and n-butyl (meth)acrylate, copolymers of monomers containing methyl (meth)acrylate, n-butyl (meth)acrylate, and 2-ethylhexyl (meth)acrylate, copolymers of monomers containing methyl (meth)acrylate, n-butyl (meth)acrylate, and 2-hydroxyethyl (meth)acrylate, homopolymers of (meth)acrylic acid esters, urethane copolymers, polyvinyl chloride, polyethylene terephthalate, ethylene-vinyl acetate copolymers, polyethylene, polypropylene, propylene copolymers, copolymers of monomers containing ethylene and (meth)acrylic acid, and copolymers of monomers containing ethylene, (meth)acrylic acid, and a (meth)acrylic acid ester, crosslinked with metal ions. Among these, acrylic polymers are preferred. The acrylic polymer is preferably an acrylic elastomer. The acrylic elastomer is preferably a copolymer of a monomer containing methyl (meth)acrylate and n-butyl (meth)acrylate, or a copolymer of a monomer containing methyl (meth)acrylate, n-butyl (meth)acrylate, and 2-ethylhexyl (meth)acrylate, and more preferably a block copolymer of a monomer containing methyl (meth)acrylate and n-butyl (meth)acrylate, or a block copolymer of a monomer containing methyl (meth)acrylate, n-butyl (meth)acrylate, and 2-ethylhexyl (meth)acrylate. The block copolymer of a monomer containing methyl (meth)acrylate, n-butyl (meth)acrylate, and 2-ethylhexyl (meth)acrylate is preferably a block copolymer of a monomer mixture containing methyl (meth)acrylate, n-butyl (meth)acrylate, and 2-ethylhexyl (meth)acrylate.

[0046] When a block copolymer of monomers containing methyl (meth)acrylate and n-butyl (meth)acrylate is used in the base layer 110, the molar ratio of the content of methyl (meth)acrylate to n-butyl (meth)acrylate is 0.5 to 1.0, 0.6 to 0.9, or 0.7 to 0.9. When the content is within the above range, warpage of the wafer 200 tends to be reduced, and the peelability of the wafer 200 tends to be improved.

[0047] The weight-average molecular weight of the polymer in the base layer 110 is preferably 30,000 to 100,000, 40,000 to 90,000, 45,000 to 80,000, or 50,000 to 75,000. When the weight-average molecular weight is within the above range, the peelability of the wafer 200 tends to be improved.

[0048] The molecular weight distribution of the polymer in the base layer 110 is preferably 0.5 to 2.0, and more preferably 0.7 to 1.8. The molecular weight distribution is the value obtained by dividing the weight average molecular weight by the number average molecular weight. When the molecular weight distribution is within the above range, the peelability of the wafer 200 tends to be improved.

[0049] The "weight average molecular weight" and "number average molecular weight" in this embodiment can be measured by gel permeation chromatography.

[0050] The content of the polymer such as the acrylic elastomer in the base layer 110 is preferably 80 to 100 mass %, 85 to 98 mass %, or 90 to 95 mass % with respect to the entire base layer 110.

[0051] The base layer 110 may contain additives other than resins as needed. Examples of additives include, but are not limited to, plasticizers, heat stabilizers, colorants, organic lubricants, inorganic lubricants, surfactants, processing aids, and antistatic agents. One type of additive may be used alone, or two or more types may be used in combination.

[0052] The content of the additive with respect to the entire base material layer 110 is preferably 0.1 to 10.0 mass %, 0.5 to 5.0 mass %, or 1.0 to 2.5 mass %.

[0053] The substrate layer 110 may be a single layer or multi-layer structure comprising the materials described above.

[0054] 1.2.Surface layer The wafer processing tape 100 of this embodiment includes a surface layer 120 .

[0055] The thickness of the surface layer 120 at room temperature (23° C.) is preferably 3 to 30 μm, 4 to 25 μm, or 5 to 20 μm. When the thickness of the surface layer 120 is within the above range, warpage of the wafer 200 tends to be further reduced, and the peelability of the wafer 200 tends to be further improved.

[0056] Furthermore, the thickness of the surface layer 120 at room temperature is preferably 1 to 70%, 2 to 60%, 3 to 50%, 5 to 40%, 5 to 35%, or 5 to 30% of the total thickness of the wafer processing tape 100. When the thickness of the surface layer 120 is within the above range, warpage of the wafer 200 tends to be further reduced, and the peelability of the wafer 200 tends to be further improved.

[0057] Furthermore, when the wafer processing tape 100 of this embodiment is attached to the wafer 200, it is preferable to heat the wafer processing tape 100 to a high temperature before attaching it to the wafer 200 in order to improve the adhesion between the wafer processing tape 100 and the wafer 200. Here, if the storage modulus of the surface layer 120 at high temperatures is too large, the flexibility is insufficient and the wafer 200 tends to be insufficient to secure the tape, while if it is too small, the wafer processing tape 100 tends to adhere too closely to the wafer 200, reducing the ease of peeling the wafer 200. That is, in order to secure the wafer 200 sufficiently and ensure the ease of peeling the wafer 200, it is preferable that the storage modulus of the surface layer 120 at high temperatures be within an appropriate range. Specifically, the storage modulus E of the surface layer 120 at 120°C is S2is preferably 0.5 to 5.0 MPa, 0.6 to 4.0 MPa, 0.7 to 3.5 MPa, 0.8 to 3.0 MPa, 0.9 to 2.5 MPa, or 1.0 to 2.0 MPa.

[0058] In addition, from the viewpoint of achieving both the fixation property of the wafer 200 and the peelability of the wafer 200, the storage modulus E S1 Storage modulus E of the surface layer 120 at 120 ° C. S2 The ratio (E S2 / E S1 ) is preferably 0.001 to 0.050, 0.005 to 0.040, or 0.010 to 0.030.

[0059] The surface layer 120 is not particularly limited, but may include, for example, a polymer. More specifically, examples of the surface layer 120 include copolymers of monomers containing ethylene, (meth)acrylic acid, and a (meth)acrylic acid ester; copolymers of monomers containing ethylene and ethyl (meth)acrylate; copolymers of monomers containing ethylene and (meth)acrylic acid; copolymers of monomers containing methyl (meth)acrylate and n-butyl (meth)acrylate; copolymers of monomers containing methyl (meth)acrylate, n-butyl (meth)acrylate, and 2-ethylhexyl (meth)acrylate; copolymers of monomers containing methyl (meth)acrylate, n-butyl (meth)acrylate, and 2-hydroxyethyl (meth)acrylate; and acrylic polymers such as homopolymers of (meth)acrylic acid esters; urethane copolymers, polyvinyl chloride, polyethylene terephthalate, ethylene-vinyl acetate copolymers, polyethylene, polypropylene, and propylene copolymers. Among these, acrylic polymers are preferred. As the acrylic polymer, acrylic elastomers are preferred. The acrylic elastomer is preferably a copolymer of monomers containing methyl (meth)acrylate and n-butyl (meth)acrylate, or a copolymer of monomers containing methyl (meth)acrylate, n-butyl (meth)acrylate, and 2-ethylhexyl (meth)acrylate, and more preferably a block copolymer of monomers containing methyl (meth)acrylate and n-butyl (meth)acrylate, or a block copolymer of monomers containing methyl (meth)acrylate, n-butyl (meth)acrylate, and 2-ethylhexyl (meth)acrylate. As the block copolymer of monomers containing methyl (meth)acrylate, n-butyl (meth)acrylate, and 2-ethylhexyl (meth)acrylate, a block copolymer of a monomer mixture of methyl (meth)acrylate, n-butyl (meth)acrylate, and 2-ethylhexyl (meth)acrylate is preferred.

[0060] When a block copolymer of monomers containing methyl (meth)acrylate and n-butyl (meth)acrylate is used in the surface layer 120, the molar ratio of the content of methyl (meth)acrylate to n-butyl (meth)acrylate is 1.0 to 2.0, 1.1 to 1.9, 1.2 to 1.8, or 1.3 to 1.7. When the content is within the above range, warpage of the wafer 200 tends to be reduced, and the peelability of the wafer 200 tends to be improved.

[0061] The weight average molecular weight of the polymer in the surface layer 120 is preferably 35,000 to 100,000, 45,000 to 90,000, 50,000 to 80,000, or 60,000 to 75,000.

[0062] The molecular weight distribution of the polymer in the surface layer 120 is preferably 1.0 to 2.5, and more preferably 1.2 to 2.0.

[0063] The content of the copolymer such as an acrylic elastomer in the surface layer 120 is preferably 80 to 100 mass %, 85 to 98 mass %, or 90 to 95 mass % relative to the entire surface layer 120.

[0064] The surface layer 120 may contain additives other than resins as needed. Examples of additives include, but are not limited to, plasticizers, heat stabilizers, colorants, organic lubricants, inorganic lubricants, surfactants, processing aids, and antistatic agents. The additives may be used alone or in combination.

[0065] The content of the additive with respect to the entire surface layer 120 is preferably 0.1 to 10.0 mass %, 0.5 to 5.0 mass %, or 1.0 to 2.5 mass %.

[0066] The surface layer 120 may be a single layer or a multi-layer structure including the materials described above.

[0067] 1.3.Backing layer The wafer processing tape 100 of this embodiment may include a back surface layer 130 laminated on the second surface 112 of the base material layer 110 .

[0068] The back surface layer 130 can prevent the wafer processing tape 100 from excessively adhering to the wafer 200, which tends to improve the peelability of the wafer 200. Furthermore, when the wafer processing tape 100 is transported during the manufacturing process, the wafer processing tape 100 can be prevented from adhering too closely to a transport belt or the like. In other words, the tackiness of the base layer 110 can be suppressed, which tends to improve the transportability of the wafer processing tape 100 and suppress blocking.

[0069] The thickness of the back surface layer 130 at room temperature (23°C) is preferably 3 to 30 μm, 4 to 25 μm, or 5 to 20 μm. When the thickness of the back surface layer 130 is within the above range, the peelability of the wafer 200 tends to be further improved, and the tackiness of the base layer 110 tends to be further suppressed.

[0070] Furthermore, the thickness of the back surface layer 130 at room temperature is preferably 1 to 70%, 2 to 60%, 3 to 50%, 5 to 40%, 5 to 35%, or 5 to 30% of the total thickness of the wafer processing tape 100. When the thickness of the base layer 110 is within the above range, the peelability of the wafer 200 is further improved, and the tackiness of the base layer 110 tends to be further suppressed.

[0071] In addition, from the viewpoint of preventing the wafer processing tape 100 from excessively conforming to the wafer 200 and from the viewpoint of suppressing the tackiness of the base layer 110, it is preferable that the storage modulus of the back surface layer 130 at room temperature is appropriately low. Specifically, the storage modulus E B1 is preferably 30 MPa or more, 30.0 to 200.0 MPa, 40.0 to 175.0 MPa, or 50.0 to 150.0 MPa. B1 When the thickness is within the above range, the peelability of the wafer 200 is improved and the tackiness of the base layer 110 tends to be further suppressed.

[0072] Furthermore, when the wafer processing tape 100 of this embodiment is applied to the wafer 200, it is preferable to heat the wafer processing tape 100 to a high temperature before applying it to the wafer 200 in order to improve adhesion between the wafer processing tape 100 and the wafer 200. However, if the adhesion between the wafer processing tape 100 and the wafer 200 is too high, the wafer 200 may be difficult to peel in subsequent processes. In this regard, if the wafer processing tape 100 includes a back surface layer 130 and the storage modulus of the back surface layer 130 at high temperatures is within an appropriate range, excessive adhesion of the wafer processing tape 100 to the wafer 200 is suppressed, and the peelability of the wafer 200 tends to be improved. Specifically, the storage modulus E of the back surface layer 130 at 120°C is B2 is preferably 0.5 to 3.0 MPa, 0.7 to 2.5 MPa, or 1.0 to 2.0 MPa. B2 When the thickness is within the above range, the peelability of the wafer 200 tends to be further improved.

[0073] In order to improve the peelability of the wafer 200 and suppress the tackiness of the base layer 110, the storage modulus E B1 Storage modulus E of the back layer 130 at 120 ° C. B2 The ratio (E B2 / E B1 ) is preferably 0.001 to 0.050, 0.005 to 0.040, or 0.010 to 0.030.

[0074] The storage modulus of the back surface layer 130 can be adjusted by the type and composition of the back surface layer 130. For example, when a block copolymer of monomers containing methyl (meth)acrylate (MMA) and n-butyl (meth)acrylate (BA) is used in the back surface layer 130, the storage modulus of the copolymer tends to improve by increasing the proportion of MMA, and tends to decrease by increasing the proportion of BA.

[0075] The material of the back surface layer 130 is not particularly limited, but includes, for example, a polymer. More specifically, the same material as that of the front surface layer 120 can be used. The material of the back surface layer 130 is preferably an acrylic polymer, and more preferably an acrylic elastomer. The acrylic elastomer is preferably a copolymer of a monomer containing methyl (meth)acrylate and n-butyl (meth)acrylate, or a copolymer of a monomer containing methyl (meth)acrylate, n-butyl (meth)acrylate, and 2-ethylhexyl (meth)acrylate, and more preferably a block copolymer of a monomer containing methyl (meth)acrylate and n-butyl (meth)acrylate, or a block copolymer of a monomer containing methyl (meth)acrylate, n-butyl (meth)acrylate, and 2-ethylhexyl (meth)acrylate.

[0076] When a block copolymer of monomers containing methyl (meth)acrylate and n-butyl (meth)acrylate is used in the base layer 110, the content of methyl (meth)acrylate relative to n-butyl (meth)acrylate, in terms of molar ratio, is 1.0 to 2.0, 1.1 to 1.9, 1.2 to 1.8, or 1.3 to 1.7. When the content is within the above range, warpage of the wafer 200 tends to be reduced, and the peelability of the wafer 200 tends to be improved.

[0077] The weight average molecular weight of the polymer in the back surface layer 130 is preferably 35,000 to 100,000, 45,000 to 90,000, 50,000 to 80,000, or 60,000 to 75,000.

[0078] The molecular weight distribution of the polymer in the back surface layer 130 is preferably 1.0 to 2.5, and more preferably 1.2 to 2.0.

[0079] The content of the copolymer such as an acrylic elastomer in the back surface layer 130 is preferably 80 to 100 mass %, 85 to 98 mass %, or 90 to 95 mass % based on the entire back surface layer 130.

[0080] The back surface layer 130 may contain additives other than resins as needed. Examples of additives include, but are not limited to, plasticizers, heat stabilizers, colorants, organic lubricants, inorganic lubricants, surfactants, processing aids, and antistatic agents. The additives may be used alone or in combination.

[0081] The content of the additive with respect to the entire back surface layer 130 is preferably 0.1 to 10.0 mass %, 0.5 to 5.0 mass %, or 1.0 to 2.5 mass %.

[0082] The backing layer 130 may be a single layer or multi-layer structure including the materials described above.

[0083] From the viewpoint of simultaneously reducing the warpage of the wafer 200, improving the peelability of the wafer 200, and reducing the tackiness of the base layer 110, the storage modulus E B1 Storage modulus E of the base layer 110 at room temperature M1 The ratio (E M1 / E B1 ) is preferably 0.05 to 0.90, 0.10 to 0.70, or 0.15 to 0.50.

[0084] From the viewpoint of achieving both the fixation property of the wafer 200 and the peelability of the wafer 200, the storage modulus E S2 Storage modulus E of the base layer 110 at 120 ° C. M2 The ratio (E M2 / E S2 ) is preferably 0.30 to 1.40, 0.35 to 1.00, or 0.40 to 0.75.

[0085] From the viewpoint of achieving both the fixation property of the wafer 200 and the peelability of the wafer 200, the storage modulus E B2 Storage modulus E of the base layer 110 at 120 ° C. M2 The ratio (E M2 / E B2) is preferably 0.30 to 1.40, 0.35 to 1.00, or 0.40 to 0.75.

[0086] 1.4. Adhesive layer The wafer processing tape 100 of this embodiment may have an adhesive layer. The adhesive layer contributes to adhesion between the wafer 200 and the wafer processing tape 100. The adhesive layer may have an opening with a diameter smaller than the diameter of the wafer 200. When the adhesive layer has such an opening, an area of ​​the element forming surface 210 of the wafer 200 where no elements are present is attached to the adhesive layer so that the area of ​​the element forming surface 210 where elements are present is positioned within the opening. In this case, the area of ​​the element forming surface 210 where elements are present does not come into contact with the adhesive layer, which tends to prevent adhesive residue in that area.

[0087] The thickness of the adhesive layer is preferably 1 to 100 μm, 5 to 75 μm, 10 to 70 μm, 15 to 60 μm, or 20 to 50 μm.

[0088] The adhesive layer may contain a (meth)acrylate polymer, and preferably contains a (meth)acrylate polymer and a crosslinking agent.

[0089] 1.4.1. (Meth)acrylate polymers The (meth)acrylate monomer contained in the (meth)acrylate polymer is not particularly limited, and examples thereof include butyl (meth)acrylate, 2-butyl (meth)acrylate, t-butyl (meth)acrylate, pentyl (meth)acrylate, octyl (meth)acrylate, 2-ethylhexyl (meth)acrylate, nonyl (meth)acrylate, decyl (meth)acrylate, lauryl (meth)acrylate, methyl (meth)acrylate, ethyl (meth)acrylate, isopropyl (meth)acrylate, tridecyl (meth)acrylate, myristyl (meth)acrylate, cetyl (meth)acrylate, stearyl (meth)acrylate, cyclohexane (meth)acrylate, and the like. Examples of (meth)acrylic monomers such as hexyl (meth)acrylate, benzyl (meth)acrylate, dimethylacrylamide, diethylacrylamide, acryloylmorpholine, and isobornyl acrylate, and functional group-containing monomers include 2-hydroxyethyl (meth)acrylate, 2-hydroxypropyl (meth)acrylate, and 2-hydroxybutyl (meth)acrylate, which have a hydroxyl group; (meth)acrylic acid, crotonic acid, maleic acid, itaconic acid, fumaric acid, acrylamido-N-glycolic acid, and cinnamic acid, which have a carboxyl group; and allyl glycidyl ether and (meth)acrylic acid glycidyl ether, which have an epoxy group.

[0090] The content of the (meth)acrylate polymer is preferably 80 to 100 mass %, 85 to 99.5 mass %, or 90 to 99.0 mass %, relative to the total amount of the adhesive layer.

[0091] The glass transition temperature (Tg) of the (meth)acrylate polymer is preferably from -30 to 5°C, and more preferably from -25 to -5°C.

[0092] 1.4.2. Crosslinking Agents Examples of crosslinking agents include polyfunctional isocyanate crosslinking agents, polyfunctional epoxy crosslinking agents, etc. When the crosslinking agent reacts with the functional group, a crosslinked structure is formed with the functional group as the base point, which increases the cohesive strength of the adhesive and tends to reduce the contamination of the wafer processing tape 100.

[0093] The content of the crosslinking agent is preferably 0.1 to 10.0 mass %, 0.5 to 8.0 mass %, or 1.0 to 6.0 mass %, relative to the total amount of the adhesive layer.

[0094] In the adhesive layer, the mass ratio of the crosslinking agent to the (meth)acrylate polymer (mass of crosslinking agent / mass of (meth)acrylate polymer) is preferably 0.1 to 10.0 mass%, 0.5 to 8.0 mass%, or 1.0 to 6.0 mass%.

[0095] 2. Manufacturing method of wafer processing tape The method for producing the wafer processing tape 100 of this embodiment is not particularly limited, but the following method may be mentioned, for example.

[0096] The means for forming the base layer 110, the surface layer 120, and the back layer 130 is not particularly limited, but the above-mentioned various materials are mixed using a conventional melt kneading method or various mixing devices (single-screw or twin-screw extruder, roll, Banbury mixer, various kneaders, etc.) so that the components are uniformly dispersed, and the mixture is formed into the base material by the T-die method, calendar method, or inflation method. Preferably, the T-die method using an extruder with good thickness accuracy is used.

[0097] The means for forming the adhesive layer is not particularly limited, but the adhesive layer may be formed by dissolving the various materials in a solvent such as an organic solvent to form a varnish, applying this to the surface layer 120 by knife coating, roll coating, spray coating, gravure coating, bar coating, curtain coating, or the like, and then removing the solvent.The adhesive layer may be formed on the surface layer 120 by applying the various materials in a varnish form to a molding film and removing the solvent to form an adhesive layer, and then laminating this on the surface layer 120.

[0098] Alternatively, the various materials may be mixed without using a solvent, and the mixture may be applied onto the surface layer 120 by screen printing or the like to form an adhesive layer.

[0099] 3.Wafer processing method The wafer processing method of this embodiment includes a bonding process s101 in which a wafer processing tape 100 is bonded to the element forming surface 210 of the wafer 200, a back-grinding process s102 in which the non-element forming surface 220 of the wafer 200 bonded to the wafer processing tape 100 is polished, and a dicing process s103 in which the wafer 200 bonded to the wafer processing tape 100 is diced after the back-grinding process s102.

[0100] The wafer processing method of this embodiment tends to achieve both improved efficiency in the wafer processing process by using the same tape in the backgrinding step s102 and the dicing step s103, and improved divisibility of the wafer 200, by using the wafer processing tape 100.

[0101] Each step of the wafer processing method of this embodiment will be described in detail below.

[0102] 3.1. Bonding process In the wafer processing method of this embodiment, first, the wafer processing tape 100 is attached to the element formation surface 210 of the wafer 200. For example, the surface layer 120 may be attached to the element formation surface 210 of the wafer 200. If the wafer processing tape 100 has an adhesive layer, the exposed surface of the wafer processing tape 100 on the surface layer 120 side may be attached to the element formation surface 210 of the wafer 200. The exposed surface may be the surface of the adhesive layer opposite the surface layer 120. Alternatively, if the adhesive layer has an opening with a diameter smaller than the diameter of the wafer 200, the exposed surface may include the adhesive layer and a region within the opening of the surface layer 120. Alternatively, the region of the element formation surface 210 of the wafer 200 where no elements are present may be attached to the adhesive layer so that the region of the element formation surface 210 where elements are present contacts the region within the opening of the surface layer 120.

[0103] In the bonding process, in order to improve the adhesion between the wafer processing tape 100 and the wafer 200, it is preferable to heat the wafer processing tape 100 to a high temperature and then bond it to the wafer 200. In this case, the wafer processing tape 100 is heated to, but not limited to, a temperature of 80 to 200°C, more specifically, 120°C or 150°C, for example.

[0104] 3.2.Back grinding process Fig. 3A shows an example of a perspective view of the back-grinding step s102, and Fig. 3B shows an example of a cross-sectional view taken along line A-A' in Fig. 3A. As shown in Fig. 3A and Fig. 3B, in the back-grinding step s102, the non-element forming surface 220 of the wafer 200 is polished by a polishing machine P to thin the wafer 200.

[0105] 3.3.Dicing process The wafer processing method of this embodiment includes a dicing step s103 in which a wafer 200 bonded to a wafer processing tape 100 is diced. FIG. 4A shows an example of a perspective view of the dicing step s103, and FIG. 4B shows an example of a cross-sectional view taken along line A-A' in FIG. 4A. Note that FIGS. 4A and 4B show an example of a dicing method in which laser dicing is used, in which a laser is irradiated onto the wafer 200. The dashed lines in FIG. 4 indicate the path of the laser irradiated portion, and in a subsequent step of forming die chips, the wafer 200 is divided along the dashed line portions. L in FIG. 4A is a laser source.

[0106] When laser dicing is employed in the dicing step s103, as shown in FIGS. 4A and 4B, a modified region 240 is generated inside the wafer 200 by irradiating the wafer 200 with a laser. More specifically, in the dicing step s103, it is preferable to focus a pulsed laser inside the wafer 200 to form the modified region 240 inside the wafer 200. At this time, it is preferable that the modified region 240 does not appear on the surface of the wafer 200. Laser dicing that forms the modified region 240 inside the wafer 200 is also called stealth dicing. Note that although the modified region 240 is formed in the wafer 200 obtained by stealth dicing, the wafer 200 is not divided into die chips.

[0107] The laser source is not particularly limited, but examples thereof include ultraviolet lasers, visible light lasers, near-infrared lasers, and far-infrared lasers. More specifically, for example, an Nd:YAG laser can be used.

[0108] In this embodiment, since the wafer processing tape 100 is attached to the element forming surface 210 during the dicing step s103, it is preferable that the surface of the wafer 200 irradiated with the laser is the non-element forming surface 220.

[0109] The dicing method in the dicing step s103 is not limited to laser dicing, but may be blade dicing using a blade, plasma dicing using plasma, etc. Regardless of which dicing method is selected, the surface area of ​​the wafer 200 after the dicing step s103 tends to be larger than the surface area of ​​the wafer 200 before the dicing step s103.

[0110] 3.4. Peeling process The wafer processing method of this embodiment may include a peeling step s104 after the dicing step s103, in which the wafer processing tape 100 is heated and peeled off. In the peeling step s104, the wafer processing tape 100 is peeled off from the wafer 200 while being heated. The peeling step s104 is performed after the dicing step s103.

[0111] In the peeling step s104, the wafer processing tape 100 may be heated when peeling it from the wafer 200 to improve peelability. When heating, the wafer processing tape 100 is preferably heated to a temperature of 25°C or higher, more preferably to a temperature of 25°C to 70°C, and even more preferably to a temperature of 30°C to 60°C. It is believed that heating the wafer processing tape 100 makes the wafer processing tape 100 flexible, making it easier to peel the wafer processing tape 100 from the wafer 200.

[0112] 3.5.Dividing process When the dicing step s103 is performed by stealth dicing, a dividing step may be included in which the wafer 200 is divided at the modified portion 240. The dividing step is a step in which an expanding tape is attached to the wafer 200 and the expanding tape is expanded in the in-plane direction, thereby dividing the wafer 200 at the formed modified portion 240.

[0113] Although the wafer processing method has been exemplified above, the wafer processing tape 100 of this embodiment may be used to process an adherend such as a semiconductor package instead of a wafer. [Example]

[0114] The present invention will be described in more detail below using examples and comparative examples. The present invention is not limited to the following examples. Unless otherwise specified, experiments for each example and comparative example were carried out in an environment of 23°C (room temperature) and 1 atmosphere.

[0115] [Example 1] An acrylic elastomer, a block copolymer of methyl methacrylate (MMA) and n-butyl acrylate (BA) (MMA:BA (molar ratio) = 46:54, weight average molecular weight = 72,000, molecular weight distribution = 1.3), was molded by a T-die extrusion film-forming method to a thickness of 140 μm to obtain a base layer. Next, an acrylic elastomer, a block copolymer of MMA and BA (MMA:BA (molar ratio) = 61:39, weight average molecular weight = 73,000, molecular weight distribution = 1.4), was molded onto the base layer by a T-die extrusion film-forming method to a thickness of 20 μm to obtain a surface layer on the base layer. In this way, the wafer processing tape of Example 1 was obtained.

[0116] [Example 2] A base layer and a surface layer were obtained in the same manner as in Example 1, except that the thickness of the surface layer was 10 μm. Then, an acrylic elastomer, which is a block copolymer of MMA and BA (MMA:BA (molar ratio) = 61:39, weight average molecular weight = 73,000, molecular weight distribution = 1.4), was molded to a thickness of 10 μm on the surface of the base layer opposite the surface layer by a T-die extrusion film forming method, to obtain a back layer on the base layer. In this way, a wafer processing tape of Example 2 was obtained.

[0117] [Comparative Example 1] An acrylic elastomer, which is a block copolymer of methyl methacrylate (MMA) and n-butyl acrylate (BA) (MMA:BA (molar ratio) = 46:54, weight average molecular weight = 72,000, molecular weight distribution = 1.3), was molded by a T-die extrusion film forming method to a thickness of 160 μm to obtain a wafer processing tape of Comparative Example 1.

[0118] Comparative Example 2 A polyolefin ionomer (Fanclear HMD (product name) manufactured by Gunze Ltd., containing 15% by mass of methacrylic acid units), which is a metal ion crosslinked ethylene-methacrylic acid copolymer, was molded to a thickness of 150 μm to obtain a wafer processing tape of Comparative Example 2. The MFR (melt mass flow rate) of the polyolefin ionomer measured in accordance with JIS K7210 was 5 g / 10 min under conditions of 125°C and a load of 10.0 kg.

[0119] [Storage modulus measurement] The storage moduli of the base layer, surface layer, and back layer were measured in accordance with the storage modulus in tension mode as specified in JIS K7244-1:1998. Specifically, sheets of the base layer, surface layer, and back layer were used as samples, and dynamic viscoelasticity measurements were performed under normal atmospheric conditions. The dynamic viscoelasticity measuring device used was a "Rheomeric Series RSA III" (manufactured by TA Instruments). The measurement results gave storage moduli at 23°C and 120°C. (Measurement conditions) Measuring device: Rheomeric Series III (manufactured by TA Instruments) Environment: Nitrogen atmosphere Sample: 50mm length x 5mm width x 80μm thickness Test length: 10 mm Test mode: Tensile strength in a direction parallel to the surface of the base layer, surface layer, and back layer Frequency: 10Hz Temperature range: 0℃~150℃ Heating rate: 3℃ / min Strain range: 0.07% Measurement interval: 1Point / ℃

[0120] [Measurement of load relaxation] The wafer processing tapes of Examples 1 and 2 and Comparative Examples 1 and 2 were cut into specimens with a width of 10 mm and a length of 100 mm to prepare test specimens. The resulting test specimens were set in a Tensilon RTC-1210A (product name) manufactured by Orientec Co., Ltd., with the chuck distance set to 40 mm. The specimens were then pulled in the longitudinal direction at a pulling rate of 300 mm / min, and held in a state where they were elongated by 10% relative to their length in the longitudinal direction before pulling, i.e., 110 mm. The time when this state was reached was designated t=0 s, and the longitudinal contraction load (N) of the test specimens was measured over time. The contraction load at t=30 s is shown in the "Load Relaxation" column of Table 1.

[0121] [Measurement of warpage] When the wafer processing tape of each example was used, the amount of warpage of the wafer was measured according to the following method. The wafer processing tape for each example was attached to an 8-inch silicon mirror wafer (Nagano Electronics Co., Ltd., product name: 8-inch dummy wafer), and the wafer thickness was thinned to 110 μm using a back grinder (Disco Corporation, product name: DFG850). Then, using a stealth dicing device (Tokyo Seimitsu Co., Ltd., product name: ML300PlusIIIFH), the entire wafer was subjected to stealth dicing so that the chip size was 250 μm square. After stealth dicing, the wafer was left undisturbed on a horizontal table for 24 hours. After leaving the wafer undisturbed, the maximum warpage of the wafer was measured using a scale, and this was taken as the amount of warpage of the wafer.

[0122] The measured amount of warpage of the wafer was evaluated based on the following criteria: Table 1 shows the evaluation results of the amount of warpage of the wafer. [Evaluation criteria] ◯: The amount of warping is less than 5 mm. △: The amount of warpage is 5 mm or more and less than 10 mm. ×: The amount of warpage is 10 mm or more.

[0123] [Peel force measurement] The peel force required to peel each example of the wafer processing tape from the wafer was measured in accordance with the peel adhesive strength test method described in JIS K6854-1:1999, Part 1: 90-degree peeling. Specifically, a wafer was attached to the base layer or surface layer of the wafer processing tape, and a 2.0 kg roll was placed on the tape attached to the wafer to bring the tape and wafer into close contact. The tape was then left to stand for 20 minutes. A 90-degree peel test was then performed to measure the peel force. The measurement temperatures were 23°C, 60°C, 90°C, and 120°C, and the peel speed was 300 mm / min. The same type of wafer as used in the warpage measurement was used.

[0124] The measurement results of the wafer processing tape of each example are shown in Table 1. Note that the wafer processing tape of Comparative Example 1 was so softened at 150°C that the peel force could not be measured.

[0125] [Table 1] [Explanation of symbols]

[0126] 100...wafer processing tape, 110...base material layer, 111...first surface, 112...second surface, 120...surface layer, 130...back surface, 200...wafer, 210...element-forming surface, 220...non-element-forming surface, 230...element, 240...modified portion, P...polishing machine, L...laser source

Claims

1. a substrate layer having a first surface and a second surface opposite the first surface; a surface layer laminated on the first surface and in contact with the wafer; The storage modulus E of the surface layer at 23°C S1 is 30 MPa or more, The storage modulus E of the substrate layer at 23°C M1 is less than 30 MPa; Tape for wafer processing.

2. The storage elastic modulus E S1 The storage modulus E M1 The ratio (E M1 / E S1 ) is 0.05 to 0.90; The wafer processing tape according to claim 1 .

3. The storage modulus E of the surface layer at 120°C S2 The storage modulus E of the substrate layer at 120 ° C. M2 The ratio (E M2 / E S2 ) is 0.3 to 1.4; The wafer processing tape according to claim 1 .

4. the thickness of the surface layer is 5 to 40% of the total thickness of the wafer processing tape; The wafer processing tape according to claim 1 .

5. The thickness of the substrate layer is 50 to 250 μm. The wafer processing tape according to claim 1 .

6. The thickness of the surface layer is 3 to 30 μm. The wafer processing tape according to claim 1 .

7. The substrate layer contains an acrylic elastomer. The wafer processing tape according to claim 1 .

8. The surface layer contains an acrylic elastomer. The wafer processing tape according to claim 1 .

9. a back surface layer laminated on the second surface; The storage modulus E of the back surface layer at 23°C B1 is 30 MPa or more; The wafer processing tape according to claim 1 .

10. The storage elastic modulus E B1 The storage modulus E of the substrate layer at 23 ° C. M1 The ratio (E M1 / E B1 ) is 0.05 to 0.90; The wafer processing tape according to claim 9.

11. The storage modulus E of the back surface layer at 120°C B2 The storage modulus E of the substrate layer at 120 ° C. M2 The ratio (E M2 / E B2 ) is 0.3 to 1.4; The wafer processing tape according to claim 9.

12. the thickness of the backside layer is 5 to 40% of the total thickness of the wafer processing tape; The wafer processing tape according to claim 9.

13. The thickness of the back surface layer is 3 to 30 μm. The wafer processing tape according to claim 9.

14. The back surface layer contains an acrylic elastomer. The wafer processing tape according to claim 9.

15. a back-grinding step of grinding a non-element-formed surface of the wafer attached to the wafer processing tape; and a dicing step of dicing the wafer attached to the wafer processing tape after the back-grinding step, The wafer processing tape according to claim 1 .

16. a bonding step of bonding the surface layer of the wafer processing tape according to any one of claims 1 to 15 to the element formation surface of the wafer; a back grinding step of grinding a non-element forming surface of the wafer bonded to the wafer processing tape; a dicing step of dicing the wafer bonded to the wafer processing tape after the back-grinding step; Wafer processing method.

17. In the dicing step, a modified portion is generated inside the wafer by laser dicing. The wafer processing method according to claim 16.

18. a peeling step of heating and peeling off the wafer processing tape after the dicing step; The wafer processing method according to claim 16.

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