Quantum computation support method, and information processing apparatus

Abstract

To relax a quantum error in a quantum circuit using a non-Clifford gate.SOLUTION: The information processor 10 generates second quantum-bit circuits 3a, 3c,. by replacing the first two quantum-bit gates 4a to 7a in the first quantum-bit circuit 3 with a first equivalent circuit 7 including a second two quantum-bit gate 4b that performs a gate operation of phase-rotation by a first rotation angle. The information processor 10 replaces the first 2-qubit gates 3a to 3c in the first circuit 3 with a second equivalent circuit 8 including a third 2-qubit gate 8a that performs a gate operation of phase rotation of a second rotation angle to generate third circuits 5a, 5b,. The information processor 10 makes the quantum computer 1 execute the second quantum circuits 4a, 4b,. and the third quantum circuits 5a, 5b,., and outputs the average of the executed results as the executed result of the first quantum circuit 3.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a quantum computing assistance program, a quantum computing assistance method, and an information processing device. [Background technology]

[0002] Currently available quantum computers are of a type called NISQ (Noisy Intermediate-Scale Quantum Computer), which uses superconducting or ion-trapped quantum bits. These quantum devices have an error rate of around 1% and a quantum bit count of around 10-100. Such small-scale quantum computers cannot completely correct errors. Therefore, it is important to perform quantum computing using quantum circuits with as few errors as possible.

[0003] Quantum computers also implement one-qubit and two-qubit gates as quantum gates that can be used to manipulate qubits. These quantum gates are called native gates. Which two-qubit gates are supported as native gates depends on the quantum device type used in the quantum computer.

[0004] The gate fidelity of gate operations in quantum computers is not 100%. Therefore, when implementing quantum circuits in devices, it is appropriate to implement them with as few gates as possible to increase calculation accuracy.

[0005] In NISQ devices, overrotation of the gate rotation angle occurs. This causes coherent errors due to the quantum gates implemented. These coherent errors may be amplified depending on the circuit combination and quantum state. Quantum error mitigation is used to suppress such error amplification.

[0006] One of the methods to mitigate quantum errors caused by coherent noise is called Randomized Compiling (RC), which is a technique that suppresses the maximization of coherent errors by running multiple equivalent circuits and calculating the average probability of those circuits.

[0007] For example, techniques for generating quantum circuits have been proposed for automatically optimizing large-scale quantum circuits with continuous parameters. Quantum circuit design programs have also been proposed to reduce errors in quantum computing. Additionally, systems for quantum computing using RC have also been proposed. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Special Publication No. 2021-503116 [Patent Document 2] International Publication No. 2023 / 127022 [Patent Document 3] US Patent Application Publication No. 2019 / 0018721 Summary of the Invention [Problem to be solved by the invention]

[0009] RC enables quantum error mitigation, which suppresses the maximum value of coherent errors. However, the two-qubit gates that can be used in quantum circuits that apply RC are limited to Clifford gates. Therefore, even if the number of two-qubit gates can be reduced by using non-Clifford gates, quantum error mitigation requires the use of quantum circuits that use Clifford gates, which increases the number of two-qubit gates. In other words, the inability to apply conventional RC to quantum circuits that use non-Clifford gates makes it difficult to reduce the number of two-qubit gates in quantum circuits that apply quantum error mitigation.

[0010] In one aspect, the present invention aims to enable quantum error mitigation in quantum circuits using non-Clifford gates. [Means for solving the problem]

[0011] In one proposal, a quantum computing assistance program is provided that causes a computer to perform the following processes. The computer generates a second quantum circuit by replacing a first two-qubit gate in a first quantum circuit, the first two-qubit gate including a first two-qubit gate that performs a rotation gate operation on the second quantum bit around the X axis depending on the state of the first quantum bit, with a first equivalent circuit including a second two-qubit gate that performs a phase rotation gate operation on the second quantum bit by a first rotation angle depending on the state of the first quantum bit. The computer generates a third quantum circuit by replacing the first two-qubit gate in the first quantum circuit with a second equivalent circuit including a third two-qubit gate that performs a phase rotation gate operation on the second quantum bit by a second rotation angle depending on the state of the first quantum bit. The computer causes a quantum computer capable of executing the second two-qubit gate and the third two-qubit gate to execute the second quantum circuit and the third quantum circuit. The computer then outputs the average of the execution results of the second quantum circuit and the third quantum circuit as the execution result of the first quantum circuit. [Effects of the Invention]

[0012] According to one aspect, quantum error mitigation in quantum circuits using non-Clifford gates is enabled. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram illustrating an example of a quantum computing assistance method according to a first embodiment. [Figure 2] FIG. 1 is a diagram illustrating an example of the configuration of a quantum computing system. [Figure 3] FIG. 1 is a diagram illustrating an example of hardware for a classical computer and a quantum computer. [Figure 4]FIG. 1 is a diagram illustrating an example of a quantum circuit generated by RC. [Figure 5] FIG. 1 is a diagram illustrating an example of an equivalent circuit of a Toffoli gate. [Figure 6] FIG. 10 is a diagram showing an example of an equivalent circuit of a CRX(90) gate. [Figure 7] FIG. 1 is a diagram showing an example of an equivalent circuit of a Toffoli gate configured with Clifford gates. [Figure 8] FIG. 10 is a diagram showing an example of a conversion process to an equivalent circuit of a Toffoli gate using a CX gate. [Figure 9] FIG. 10 is a diagram showing an example of a process of converting a Toffoli gate into an equivalent circuit using a CZ gate. [Figure 10] FIG. 10 is a diagram illustrating a first example of an equivalent circuit of a CRX gate. [Figure 11] FIG. 10 is a diagram showing a second example of an equivalent circuit of a CRX gate. [Figure 12] FIG. 10 is a diagram showing an example of a process of converting a Toffoli gate into an equivalent circuit using a non-Clifford gate. [Figure 13] FIG. 1 is a diagram illustrating a first example of a quantum error mitigation technique for a CRX gate. [Figure 14] FIG. 10 is a diagram illustrating a second example of a quantum error mitigation technique for a CRX gate. [Figure 15] FIG. 10 is a diagram showing an example of a plurality of equivalent circuits of a CX gate. [Figure 16] FIG. 1 is a diagram illustrating an example of functions possessed by a classical computing device. [Figure 17] FIG. 10 is a diagram illustrating an example of a conversion process to a plurality of quantum circuits. [Figure 18] 1 is a flowchart illustrating an example of a procedure for quantum computing assisted processing on a classical computer. [Figure 19] 10 is a flowchart illustrating an example of a procedure for generating a plurality of quantum circuits. [Figure 20] FIG. 10 is a diagram illustrating an example of a comparison result of the influence of noise for each noise mitigation method. [Figure 21] FIG. 1 is a diagram illustrating an example of a quantum circuit used for noise mitigation. [Figure 22] 10A and 10B are diagrams illustrating an example of a simulation result when different coherent noises are applied. DETAILED DESCRIPTION OF THE INVENTION

[0014] The present embodiment will be described below with reference to the drawings. Note that each embodiment can be implemented in combination with a plurality of other embodiments within a range that does not contradict each other. [First embodiment] The first embodiment is a quantum computing assistance method for enabling quantum error mitigation when a quantum circuit using a non-Clifford gate is executed on a quantum computer.

[0015] Fig. 1 is a diagram illustrating an example of a quantum-assisted computing method according to a first embodiment. Fig. 1 illustrates an information processing device 10 that implements the quantum-assisted computing method. The information processing device 10 can implement the quantum-assisted computing method according to the first embodiment by, for example, executing a predetermined quantum-assisted computing program.

[0016] The information processing device 10 includes a storage unit 11 and a processing unit 12. The storage unit 11 is, for example, a memory or a storage device included in the information processing device 10. The processing unit 12 is, for example, a processor or an arithmetic circuit included in the information processing device 10.

[0017] The storage unit 11 stores, for example, a fourth quantum circuit 2 that indicates a quantum computation to be executed by the quantum computer 1. The storage unit 11 also stores a quantum computation support program that converts the fourth quantum circuit 2 into a quantum circuit that can be executed by the native gates of the quantum computer 1 and causes the quantum computer 1 to execute the quantum circuit.

[0018] The processing unit 12 converts the fourth quantum circuit 2 into a quantum circuit that can be executed by the native gates of the quantum computer 1 in accordance with the quantum computing support program, and causes the quantum computer 1 to execute the quantum circuit. For example, the processing unit 12 generates the first quantum circuit 3 based on the fourth quantum circuit 2 that includes the Toffoli gate 2a.

[0019] Specifically, the processing unit 12 generates the first quantum circuit 3 by replacing the Toffoli gate 2a in the fourth quantum circuit 2 with a third equivalent circuit 6a, 6b, ..., including fourth two-qubit gates 3d, 3e and first two-qubit gates 3a-3c. The first two-qubit gates 3a-3c are CRX gates that perform a 90-degree or -90-degree rotation gate operation around the X axis on the second qubit (target qubit) depending on the state of the first qubit (control qubit). The fourth two-qubit gates 3d, 3e are CX gates that invert the state of the target qubit depending on the state of the control qubit.

[0020] The first two-qubit gates 3a to 3c are non-Clifford gates. On the other hand, the fourth two-qubit gates 3d and 3e are Clifford gates. Therefore, quantum error mitigation using RC is possible for the fourth two-qubit gates 3d and 3e, but it is difficult to apply RC to the first two-qubit gates 3a to 3c.

[0021] The processing unit 12 generates second quantum circuits 4a, 4b, ... based on the first quantum circuit 3. For example, the processing unit 12 replaces the first two-qubit gates 3a to 3c in the first quantum circuit 3 with a first equivalent circuit 7 including a second two-qubit gate 7a. The second two-qubit gate 7a is a controlled phase gate that performs a gate operation of phase rotation of a second qubit (target qubit) by a first rotation angle depending on the state of the first qubit (control qubit).

[0022] Furthermore, when generating the second quantum circuits 4a, 4b, ..., the processing unit 12 replaces the fourth two-qubit gates 3d, 3e that are included in the first quantum circuit 3 and perform Clifford operations with a plurality of third equivalent circuits 6a, 6b, .... The plurality of third equivalent circuits 6a, 6b, ... are equivalent to the fourth two-qubit gates 3d, 3e, but have different configurations of one-qubit gates.

[0023] In the plurality of second quantum circuits 4a, 4b,... generated in this manner, the first two-qubit gate in the first quantum circuit 3 is replaced with a first equivalent circuit 7 including a second two-qubit gate 7a. Furthermore, in each of the plurality of second quantum circuits 4a, 4b,..., the fourth two-qubit gates 3d, 3e are replaced with one of the plurality of third equivalent circuits 6a, 6b,...

[0024] Furthermore, processing unit 12 generates third quantum circuits 5a, 5b, ... based on the first quantum circuit 3. For example, processing unit 12 replaces the first two-qubit gates 3a to 3c in first quantum circuit 3 with a second equivalent circuit 8 including a third two-qubit gate 8a. The third two-qubit gate 8a is a controlled phase gate that performs a gate operation for phase rotation of a second qubit (target qubit) by a second rotation angle depending on the state of the first qubit (control qubit).

[0025] The second rotation angle is different from the first rotation angle. For example, if the first rotation angle is "90", the second rotation angle is "-90". Furthermore, when generating the third quantum circuits 5a, 5b, . . . , the processing unit 12 replaces the fourth two-qubit gates 3d and 3e with a plurality of third equivalent circuits 6a, 6b, .

[0026] In the plurality of third quantum circuits 5a, 5b,... generated in this manner, the first two-qubit gates 3a-3c in the first quantum circuit 3 are replaced with a second equivalent circuit 8 including a third two-qubit gate 8a. Furthermore, in each of the plurality of third quantum circuits 5a, 5b,..., the fourth two-qubit gates 3d, 3e are replaced with one of the plurality of third equivalent circuits 6a, 6b,...

[0027] The processing unit 12 causes the quantum computer 1 to execute the second quantum circuits 4a, 4b,... and the third quantum circuits 5a, 5b,... The quantum computer 1 is capable of executing the second two-qubit gate 7a and the third two-qubit gate 8a as native gates. The processing unit 12 then outputs the average of the execution results (e.g., probability amplitudes) of the second quantum circuits 4a, 4b,... and the execution results (e.g., probability amplitudes) of the third quantum circuits 5a, 5b,... as the execution result of the first quantum circuit 3 or the fourth quantum circuit 2.

[0028] In this way, the second quantum circuits 4a, 4b, ... and the third quantum circuits 5a, 5b, ... which are equivalent to the first quantum circuit 3 are executed on the quantum computer 1, and the execution results are averaged, thereby mitigating quantum errors.

[0029] For example, the first two-qubit gates 3a to 3c are converted into multiple quantum circuits using controlled phase gates with rotation angles of "90" and "-90", respectively. This allows quantum error mitigation to be achieved even for the first two-qubit gates 3a to 3c, which are non-Clifford gates.

[0030] The fourth two-qubit gates 3d and 3e, which are Clifford gates, are subject to quantum error mitigation by RC, achieving quantum error mitigation for a quantum circuit that combines Clifford and non-Clifford gates.

[0031] Furthermore, by replacing Toffoli gate 2a in fourth quantum circuit 2 including Toffoli gate 2a with a circuit including fourth two-qubit gates 3d and 3e and first two-qubit gates 3a to 3c, first quantum circuit 3 is generated. This makes it possible to implement quantum error mitigation for quantum computation for fourth quantum circuit 2 including the Toffoli gate.

[0032] Second Embodiment The second embodiment is a quantum computing system that is capable of appropriate quantum error mitigation even in quantum circuits that use non-Clifford gates.

[0033] FIG. 2 is a diagram showing an example of the configuration of a quantum computing system. The quantum computing system 300 is a computer system that performs calculations using, for example, the principles of quantum mechanics. The quantum computing system 300 includes a classical computer 100 and a quantum computer 200. The classical computer 100 is a von Neumann computer. The quantum computer 200 is a non-von Neumann computer that performs quantum calculations by applying quantum gates to quantum bits. For example, the quantum computer 200 performs quantum calculations using a superconducting quantum bit device.

[0034] A terminal device 30 is connected to the classical computer 100 via a network 20. The terminal device 30 is a computer used by a user who requests quantum computing by the quantum computing system 300. The classical computer 100 receives a quantum computing request, including a quantum circuit, from, for example, the terminal device 30. A quantum circuit indicates the order of gate operations on quantum bits by arranging elements such as gates. A quantum bit is a bit that can represent a superposition state between the "0" state and the "1" state.

[0035] The classical computer 100 instructs the quantum computer 200 to perform a gate operation on a quantum bit in accordance with the quantum circuit included in the quantum computation request received from the terminal device 30. The classical computer 100 also obtains the measurement results of each quantum bit from the quantum computer 200.

[0036] The quantum computer 200 performs gate operations on quantum bits in accordance with instructions from the classical computer 100. The quantum computer 200 also measures the state of the quantum gate and transmits the measurement results to the classical computer 100.

[0037] FIG. 3 is a diagram showing an example of hardware for a classical computer and a quantum computer. A classical computer 100 is entirely controlled by a processor 101. A memory 102 and multiple peripheral devices are connected to the processor 101 via a bus 100a. The processor 101 may be a multiprocessor. The processor 101 is, for example, a central processing unit (CPU), a micro processing unit (MPU), or a digital signal processor (DSP). At least some of the functions realized by the processor 101 executing a program may be realized by an electronic circuit such as an application specific integrated circuit (ASIC) or a programmable logic device (PLD).

[0038] The memory 102 is used as a main storage device of the classical computer 100. The memory 102 temporarily stores at least a portion of the OS (Operating System) program and application programs to be executed by the processor 101. The memory 102 also stores various data used in processing by the processor 101. As the memory 102, for example, a volatile semiconductor storage device such as a RAM (Random Access Memory) is used.

[0039] The peripheral devices connected to the bus 100a include a storage device 103, a GPU (Graphics Processing Unit) 104, an input interface 105, an optical drive device 106, a device connection interface 107, a network interface 108, and a communication interface 109.

[0040] The storage device 103 electrically or magnetically writes and reads data to and from a built-in recording medium. The storage device 103 is used as an auxiliary storage device for a computer. The storage device 103 stores an OS program, application programs, and various data. Note that the storage device 103 may be, for example, an HDD (Hard Disk Drive) or an SSD (Solid State Drive).

[0041] The GPU 104 is an arithmetic unit that performs image processing and is also called a graphics controller. The GPU 104 is connected to a monitor 21. The GPU 104 displays an image on the screen of the monitor 21 in accordance with an instruction from the processor 101. The monitor 21 may be a display device using organic EL (Electro Luminescence) or a liquid crystal display device.

[0042] The input interface 105 is connected to a keyboard 22 and a mouse 23. The input interface 105 transmits signals sent from the keyboard 22 and the mouse 23 to the processor 101. The mouse 23 is an example of a pointing device, and other pointing devices can also be used. Examples of other pointing devices include a touch panel, a tablet, a touch pad, and a trackball.

[0043] The optical drive device 106 uses a laser beam or the like to read data recorded on an optical disc 24 or write data to the optical disc 24. The optical disc 24 is a portable recording medium on which data is recorded so that it can be read by reflected light. The optical disc 24 includes a DVD (Digital Versatile Disc), a DVD-RAM, a CD-ROM (Compact Disc Read Only Memory), a CD-R (Recordable) / RW (Rewritable), and the like.

[0044] The device connection interface 107 is an interface for connecting peripheral devices to the classical computer 100. For example, a memory device 25 or a memory reader / writer 26 can be connected to the device connection interface 107. The memory device 25 is a recording medium equipped with a function for communicating with the device connection interface 107. The memory reader / writer 26 is a device for writing data to a memory card 27 or reading data from the memory card 27. The memory card 27 is a card-type recording medium.

[0045] The network interface 108 is connected to a network 20. The network interface 108 is connected via the network 20 to other computers (including the terminal device 30) not shown.

[0046] The communication interface 109 is connected to the quantum computer 200. The communication interface 109 communicates with the quantum computer 200. For example, the communication interface 109 instructs the quantum computer 200 to execute a quantum circuit.

[0047] The classical computer 100 can realize the processing functions of the second embodiment by using the hardware described above. Note that the information processing device 10 shown in the first embodiment can also be realized by using hardware similar to that of the classical computer 100 shown in FIG.

[0048] The classical computer 100 realizes the processing functions of the second embodiment by executing a program recorded on, for example, a computer-readable recording medium. The program describing the processing to be executed by the classical computer 100 can be recorded on various recording media. For example, the program to be executed by the classical computer 100 can be stored in a storage device 103. The processor 101 loads at least a portion of the program in the storage device 103 into the memory 102 and executes the program. The program to be executed by the classical computer 100 can also be recorded on a portable recording medium such as an optical disk 24, a memory device 25, or a memory card 27. The program stored on the portable recording medium becomes executable after being installed on the storage device 103, for example, under the control of the processor 101. The processor 101 can also read and execute the program directly from the portable recording medium.

[0049] The quantum computer 200 includes a control device 201 and a quantum bit device 202. The control device 201 performs gate operations on quantum bits in the quantum bit device 202 in accordance with instructions from the classical computer 100. For example, the control device 201 performs gate operations on the quantum bits by irradiating the quantum bits with microwaves of a predetermined frequency.

[0050] The quantum bit device 202 has a plurality of quantum bits. The quantum bit device has, for example, superconducting quantum bits. The quantum bit device 202 is also called a quantum processing unit (QPU).

[0051] A user of the quantum computing system 300 generates a quantum circuit for solving a target problem by quantum computing, for example, using the terminal device 30. When the user instructs the terminal device 30 to execute quantum computing, the terminal device 30 transmits a quantum computing request including the generated quantum circuit to the quantum computing system 300.

[0052] In the quantum computing system 300, the classical computer 100 causes the quantum computer 200 to execute quantum computing based on a quantum circuit in response to a quantum computing request. At this time, the classical computer 100 converts the quantum circuit to be executed into a quantum circuit using executable quantum gates in accordance with the hardware specifications of the quantum computer 200 (such as native gates corresponding to quantum bit devices).

[0053] Quantum computation based on a quantum circuit specified by a user is performed by such a quantum computing system 300. In this case, the quantum computing system 300 performs quantum computation on the quantum circuit to be computed, reducing errors due to large unpredictable noise.

[0054] RC is a quantum error mitigation technology that reduces errors. FIG. 4 is a diagram showing an example of a quantum circuit generated by RC. RC generates an overall equivalent quantum circuit (equivalent circuit 92) by inserting a one-qubit gate into quantum circuit 91, which is the target of quantum computation. The type of one-qubit gate to be inserted is determined randomly within a range that satisfies overall equivalence. In FIG. 4, one-qubit gates included in quantum circuit 91 are shown as black rectangles, and one-qubit gates inserted in equivalent circuit 92 are shown as white rectangles. Adjacent one-qubit gates can be coupled. Therefore, an equivalent circuit 93 is generated in which adjacent one-qubits in equivalent circuit 92 are replaced with a single one-qubit gate.

[0055] In RC, multiple equivalent circuits are generated using a procedure similar to that of equivalent circuit 93. The multiple equivalent circuits generated are equivalent to quantum circuit 91 overall, but differ in the type of 1-qubit gate included or the order of gate operations.

[0056] Quantum noise varies depending on the quantum state of each quantum bit. Furthermore, it is difficult to measure and correct all noise in advance. Therefore, in RC, quantum computations are performed based on multiple equivalent circuits equivalent to the quantum circuit 91, each based on a random one-qubit gate, and the outputs of these quantum computations are averaged. This averaging can prevent errors from occurring in quantum computations when the noise is at its worst. In other words, quantum errors are mitigated.

[0057] RC is applicable when the two-qubit gate included in the quantum circuit 91 is a Clifford gate. Therefore, when RC is applied, quantum gates other than one-qubit gates included in the quantum circuit for solving the target problem are converted into Clifford gates of two qubits or less. For example, one of the quantum gates often used in quantum circuits is the Toffoli gate. Below, we will explain the gate operation of the Toffoli gate and the equivalent circuit of the Toffoli gate when RC is applied to achieve quantum error mitigation.

[0058] A Toffoli gate is a three-qubit gate. A quantum gate that can be operated by the quantum computer 200 is a one-qubit gate or a two-qubit gate. Therefore, a Toffoli gate is converted into an equivalent circuit that combines a one-qubit gate and a two-qubit gate.

[0059] Figure 5 shows an example of an equivalent circuit of a Toffoli gate. The Toffoli gate 31 is a quantum gate that uses two control qubits and one target qubit. If the states of the control qubits are both "1", the Toffoli gate 31 performs a gate operation that inverts the state of the target qubit.

[0060] The Toffoli gate 31 can be converted into an equivalent circuit 32 that combines a plurality of two-qubit gates. The equivalent circuit 32 is made up of three CRX gates 32a to 32c and two CX gates 32d and 32e.

[0061] CRX gates 32a to 32c are quantum gates that perform a rotation gate operation on a target quantum bit around the X axis at a predetermined rotation angle when the state of the control quantum bit is "1." If the rotation angle is "θ," the gate operation of the CRX(θ) gate is expressed by equation (1).

[0062]

number

[0063] The rotation angle of the CRX gates 32a and 32c is "90 degrees", and the gate operation of CRX(90) is expressed by equation (2).

[0064]

number

[0065] The rotation angle of the CRX gate 32b is "-90 degrees", and the gate operation of the CRX(-90) gate is expressed by equation (3).

[0066]

number

[0067] Of the quantum gates included in the equivalent circuit 32, the CX gates 32d and 32e are Clifford gates, and the gate operation is expressed by equation (4).

[0068]

number

[0069] On the other hand, the CRX gates 32a to 32c are non-Clifford gates, and therefore, in order to apply RC, the CRX gates 32a to 32c are converted into equivalent circuits using Clifford gates.

[0070] Figure 6 shows an example of an equivalent circuit of a CRX(90) gate. The CRX(90) gate 33 can be implemented using a CX gate or a CZ gate. The gate operation of the CX gate is shown in equation (4). The gate operation of the CZ gate is expressed in equation (5).

[0071]

number

[0072] The CRX(90) gate 33 can be replaced with an equivalent circuit 34 using a CX gate. Here, the control quantum bit of the CRX(90) gate 33 is the quantum bit "q0", and the target quantum bit is the quantum bit "q1".

[0073] In the equivalent circuit 34, first, a T gate 34a is arranged for the quantum bit "q0", and an H gate 34b is arranged for the quantum bit "q1". Next, a T gate 34c is arranged for the quantum bit "q1". Next, a CX gate 34d is arranged with the quantum bit "q0" as the control quantum bit and the quantum bit "q1" as the target quantum bit. Next, a T gate 34b is arranged for the quantum bit "q1". † Gate 34e is placed next. Next, CX gate 34f is placed with quantum bit "q0" as the control quantum bit and quantum bit "q1" as the target quantum bit. Finally, H gate 34g is placed at quantum bit "q1".

[0074] The CX gate 36 can be replaced with a circuit in which H gates 36a and 36c are placed before and after the target quantum bit of the CZ gate 36b. By applying this replacement to the equivalent circuit 34, an equivalent circuit 35 of a CRX(90) gate using a CZ gate is obtained.

[0075] In the equivalent circuit 35, first, a T gate 35a is arranged for the quantum bit "q0", and an H gate 35b is arranged for the quantum bit "q1". Next, a T gate 35c and an H gate 35d are arranged for the quantum bit "q1". Next, a CZ gate 35e is arranged to operate on the quantum bits "q0" and "q1". Next, an H gate 35f and a T gate 35c are arranged for the quantum bit "q1". † A gate 35g and an H gate 35h are arranged. Finally, a CZ gate 35i is arranged to operate on the quantum bit "q0" and the quantum bit "q1".

[0076] Note that if the gate operation of the H gate is performed consecutively on one quantum bit, the state of that quantum bit returns to its original state. Therefore, two consecutive H gates in the quantum circuit can be deleted. The H gate 34g in the equivalent circuit 34 is continuous with the H gate next to the CZ gate 35i, which is generated when the CX gate 34f is replaced with the CZ gate 35i. Therefore, those H gates have been deleted.

[0077] In this way, the CRX(90) gate 33 can be implemented using equivalent circuits 34, 35 that use a CX gate or a CZ gate. In many superconducting quantum devices, the CX gate or the CZ gate is the native gate. In a quantum computer 200 in which the CX gate or the CZ gate is the native gate, the gate operation of the CRX(90) gate can be performed using either equivalent circuit 34, 35.

[0078] 6, each of equivalent circuits 34 and 35 includes two two-qubit gates. When the CRX(-90) gate is replaced with an equivalent circuit, the equivalent circuit also includes two two-qubit gates.

[0079] 7 is a diagram showing an example of an equivalent circuit of a Toffoli gate composed of Clifford gates. By replacing each of the CRX gates 32a to 32c included in the equivalent circuit 32 of the Toffoli gate 31 with a circuit using a Clifford gate, an equivalent circuit 37 is obtained. The equivalent circuit 37 includes eight CX gates 37a to 37h.

[0080] It is possible to replace a part of the equivalent circuit 37 with another circuit. By replacing the circuit, the number of two-qubit gates can be reduced. 8 shows an example of a process for converting a Toffoli gate into an equivalent circuit using CX gates. For example, a subcircuit 37x in the equivalent circuit 37 includes consecutive H gates 37i and 37j. These H gates 37i and 37j can be deleted. Furthermore, the two CX gates 37c and 37d in the subcircuit 37x can be converted into three CX gates, as shown in conversion example 38a.

[0081] When CX gates 37c and 37d are converted according to conversion example 38a, a CX gate performing the same gate operation is placed next to CX gate 37b in partial circuit 37x. As shown in conversion example 38b, if CX gates with the same gate operation are consecutive, those CX gates can be deleted. As a result, partial circuit 37x in equivalent circuit 37 is converted into two CX gates 39b and 39c, as shown in partial circuit 39x.

[0082] Furthermore, the partial circuit 37y in the equivalent circuit 37 includes consecutive H gates 37k and 37l. These H gates 37k and 37l can be deleted. When the H gates 37k and 37l are deleted, T † The gate 37m and the T gate 37n are connected to each other. † If gate 37m and T gate 37n are consecutive, these quantum gates can also be deleted.

[0083] Furthermore, as shown in conversion example 38c, the order of the CX gate and the T gate can be swapped. †The same applies to the gate. Then, the CX gate 37e and the T † The order of the T gate 37p and the CX gate 37g can be interchanged. Furthermore, the order of the T gate 37p and the CX gate 37g can be interchanged. After such interchange, the partial circuit 37y can be converted from the three CX gates 37e to 37g into two CX gates, as shown in conversion example 38d. As a result, the partial circuit 37y in the equivalent circuit 37 can be converted into a partial circuit 39y including two CX gates 39d and 39e.

[0084] As a result of the above conversion process, the equivalent circuit 37 of the Toffoli gate 31 is converted into an equivalent circuit 39. The equivalent circuit 39 includes six CX gates 39a to 39f. That is, when the Toffoli gate 31 is implemented using the CX gates 39a to 39f, the number of two-qubit gates becomes six.

[0085] There are cases where the CX gate is not the native gate of the quantum computer 200, but the CZ gate is the native gate. In this case, the Toffoli gate 31 is converted into an equivalent circuit using the CZ gate.

[0086] 9 is a diagram showing an example of a process for converting a Toffoli gate into an equivalent circuit using CZ gates. CX gates 39a to 39f can be replaced with two H gates and a CZ gate, as shown in conversion example 38e. By converting all CX gates 39a to 39f in equivalent circuit 39 according to conversion example 38e, a Toffoli gate equivalent circuit 40 using CZ gates 40a to 40f is obtained.

[0087] Six CZ gates 40a to 40f are included in the equivalent circuit 40. That is, when the Toffoli gate 31 is implemented using the CZ gates 40a to 40f, the number of two-qubit gates becomes six.

[0088] The conversion of the Toffoli gate 31 into equivalent circuits 39 and 40 shown in Figures 8 and 9 is based on the assumption that the two-qubit gate is limited to a Clifford gate. If it is permitted to use a non-Clifford gate as the two-qubit gate, it is also possible to convert the Toffoli gate 31 into an equivalent circuit using fewer two-qubit gates.

[0089] Native gates for superconducting devices include the CZ gate (controlled Z gate) and the C-Phase gate (controlled phase rotation gate). The CZ gate is a two-qubit gate that inverts the phase of the target qubit when the control qubit is in the |1> state. The C-Phase gate is a two-qubit gate that rotates the phase of the target qubit by a predetermined rotation angle when the control qubit is in the |1> state.

[0090] When converting the Toffoli gate 31 into an equivalent circuit using non-Clifford gates, for example, the CRX gates 32a to 32c are converted into an equivalent circuit using C-Phase gates. The gate operation by the C-Phase gate with a rotation angle of "θ" is expressed by the following equation.

[0091]

number

[0092] 10 is a diagram showing a first example of an equivalent circuit of a CRX gate. CRX gate 32a included in equivalent circuit 32 of Toffoli gate 31 can be converted into equivalent circuit 41. The control quantum bit of CRX gate 32a is set to quantum bit "q0", and the target quantum bit is set to quantum bit "q1".

[0093] First, an X gate 41a is arranged for quantum bit "q0" of equivalent circuit 41. First, an RZ gate 41b with a rotation angle of "-90", a root X gate 41c, and a Z gate 41d are arranged for quantum bit "q1" of equivalent circuit 41. Next, a C-Phase gate 41e with a rotation angle of "90", in which quantum bit "q0" is the control quantum bit and quantum bit "q1" is the target quantum bit, is arranged. The gate operation by C-Phase gate 41e with a rotation angle of "90" is expressed by the following equation.

[0094]

number

[0095] After the C-Phase gate 41e, an X gate 41f and a T gate 41g are arranged for the quantum bit "q0" of the equivalent circuit 41. Also, an RZ gate 41h with a rotation angle of "-90", a root X gate 41i, and an RZ gate 41j with a rotation angle of "-90" are arranged for the quantum bit "q1" of the equivalent circuit 41.

[0096] In this way, the CRX gate 32a can be converted into an equivalent circuit 41 using a C-Phase gate 41e. The CRX gate 32c can also be converted into an equivalent circuit 41.

[0097] 11 is a diagram showing a second example of an equivalent circuit of a CRX gate. CRX gate 32b included in equivalent circuit 32 of Toffoli gate 31 can be converted into equivalent circuit 42. The control quantum bit of CRX gate 32b is quantum bit "q0," and the target quantum bit is quantum bit "q1."

[0098] An X gate 42a is first arranged for quantum bit "q0" of equivalent circuit 42. An RZ gate 42b with a rotation angle of "90" and a root X gate 42c are first arranged for quantum bit "q1" of equivalent circuit 42. Next, a C-Phase gate 42d with a rotation angle of "90", in which quantum bit "q0" is the control quantum bit and quantum bit "q1" is the target quantum bit, is arranged.

[0099] After the C-Phase gate 42d, an X gate 42e and a T gate 42f are arranged for the quantum bit "q0" of the equivalent circuit 42. Also, an H gate 42g is arranged for the quantum bit "q1" of the equivalent circuit 42.

[0100] By using the equivalent circuits 41 and 42 shown in FIGS. 10 and 11, the Toffoli gate 31 can be converted into an equivalent circuit using a non-Clifford gate. 12 is a diagram showing an example of a process for converting a Toffoli gate into an equivalent circuit using a non-Clifford gate. An equivalent circuit 32 of a Toffoli gate 31 can be converted into an equivalent circuit 43 using a C-Phase gate.

[0101] The CRX gate 32a of the equivalent circuit 32 is converted into a partial circuit 43a of the equivalent circuit 43. The CRX gate 32b of the equivalent circuit 32 is converted into a partial circuit 43b of the equivalent circuit 43. The CRX gate 32c of the equivalent circuit 32 is converted into a partial circuit 43c of the equivalent circuit 43. The CX gate 32d of the equivalent circuit 32 is converted into a partial circuit 43d of the equivalent circuit 43. The CX gate 32e of the equivalent circuit 32 is converted into a partial circuit 43e of the equivalent circuit 43.

[0102] By converting the Toffoli gate 31 into the equivalent circuit 43 in this way, it can be implemented with a total of five native two-qubit gates: two CZ gates and three C-Phase gates. In other words, by using a non-Clifford gate, the number of two-qubit gates used to implement the Toffoli gate 31 can be reduced compared to when using a non-Clifford gate.

[0103] Reducing the number of 2-qubit gates reduces the occurrence of errors in quantum computation. On the other hand, if non-Clifford gates are used, RC cannot be applied to the whole system. Therefore, the classical computer 100 applies RC only to two-qubit gates, which are Clifford gates, when generating quantum circuits to be executed by the quantum computer 200. The classical computer 100 then applies quantum error mitigation to CRX gates, which are non-Clifford gates, using a method different from RC.

[0104] 13 is a diagram showing a first example of a quantum error mitigation technique for a CRX gate. For example, suppose the control quantum bit of a CRX gate 44 with a rotation angle of "90" is quantum bit "q0" and the target quantum bit is quantum bit "q1." In this case, CRX gate 44 can be converted into equivalent circuit 41 using C-Phase gate 41e with a rotation angle of "90", and can also be converted into equivalent circuit 45 using C-Phase gate 45d with a rotation angle of "-90".

[0105] First, an RZ gate 45a with a rotation angle of "-90", a root X gate 45b, and a Z gate 45c are arranged for the quantum bit "q1" of the equivalent circuit 45. Next, a C-Phase gate 45d with a rotation angle of "-90" that operates on the quantum bits "q0" and "p1" is arranged. The gate operation of the C-Phase gate 45d with a rotation angle of "-90" is expressed by the following equation.

[0106]

number

[0107] After the C-Phase gate 45d, a T gate 45e is arranged for the quantum bit "q0" of the equivalent circuit 45. Also, a root X gate 45f and an RZ gate 45g with a rotation angle of "-90" are arranged for the quantum bit "q1" of the equivalent circuit 45.

[0108] In this way, there are two equivalent circuits 41 and 45 for the CRX gate 44 with a rotation angle of "90". By having the quantum computer 200 execute each of the two equivalent circuits 41 and 45 and averaging the measurement results, it becomes possible to mitigate quantum errors in the gate operation of the CRX gate 44 with a rotation angle of "90".

[0109] 14 is a diagram showing a second example of a quantum error mitigation technique for a CRX gate. For example, suppose the control quantum bit of a CRX gate 46 with a rotation angle of "-90" is quantum bit "q0" and the target quantum bit is quantum bit "q1." In this case, the CRX gate 46 can be converted into equivalent circuit 42 using a C-Phase gate 42d with a rotation angle of "90," and can also be converted into equivalent circuit 47 using a C-Phase gate 47c with a rotation angle of "-90."

[0110] An RZ gate 47a with a rotation angle of 90° and a root X gate 47b are arranged for quantum bit "q1" of equivalent circuit 47. Next, a C-Phase gate 47c with a rotation angle of -90° is arranged, with quantum bit "q0" as the control quantum bit and quantum bit "q1" as the target quantum bit.

[0111] After the C-Phase gate 47c, a T gate 47d is arranged for the quantum bit "q0" of the equivalent circuit 47. Also, an RZ gate 47e with a rotation angle of "90" and a root X gate 47f are arranged for the quantum bit "q1" of the equivalent circuit 47.

[0112] In this way, the CRX gate 46 with a rotation angle of "-90" has two equivalent circuits 42 and 47. By having the quantum computer 200 execute each of the two equivalent circuits 42 and 47 and averaging the measurement results, it becomes possible to mitigate quantum errors in the gate operation of the CRX gate 46 with a rotation angle of "-90".

[0113] For the CX gates 32d and 32e included in the equivalent circuit 32 of the Toffoli gate 31, quantum error mitigation is possible by RC. 15 is a diagram showing an example of a plurality of equivalent circuits of a CX gate. In each of the equivalent circuits 51, 52, 53,... of the CX gate 50 shown in FIG. 15, one-qubit gates 51b-51h, 52b-52h, 53b-53g... are arranged on both sides of a CZ gate 51a, 52a, 53a... The one-qubit gates 51b-51h, 52b-52h, 53b-53g... are Clifford gates. The one-qubit gates 51b-51h, 52b-52h, 53b-53g... in the equivalent circuits 51, 52, 53... are randomly configured under the condition that they are equivalent to the CX gate 30 as a whole.

[0114] By implementing the CX gates 32d and 32e included in the equivalent circuit 32 of the Toffoli gate 31 using a plurality of equivalent circuits 51, 52, 53, etc. as shown in FIG. 15, quantum error mitigation by RC is realized for the gate operations of the CX gates 32d and 32e.

[0115] In this way, quantum error mitigation is possible for quantum circuits that contain a mixture of Clifford and non-Clifford gates. Non-Clifford gates are permitted to be included in quantum circuits that apply quantum error mitigation. As a result, the depth of the quantum circuit becomes shallower, and the number of errors that occur is reduced.

[0116] 16 is a diagram illustrating an example of functions of a classical computer device. The classical computer 100 includes a computation request receiving unit 110, a quantum circuit conversion unit 120, a quantum computation control unit 130, and an output probability averaging unit 140.

[0117] The computation request receiving unit 110 receives a quantum computation request from the terminal device 30. The computation request includes, for example, a quantum circuit including a gate with three or more qubits. The computation request receiving unit 110 requests the quantum circuit conversion unit 120 to convert the acquired quantum circuit. Furthermore, upon receiving a computation result from the output probability averaging unit 140, the computation request receiving unit 110 transmits the computation result to the terminal device 30 that sent the computation request.

[0118] The quantum circuit conversion unit 120 converts the quantum circuit acquired from the computation request receiving unit 110 into multiple quantum circuits using native gates in the quantum computer 200. At this time, the quantum circuit conversion unit 120 converts a CX gate into multiple equivalent circuits using CZ gates by RC. Furthermore, the quantum circuit conversion unit 120 converts a CRX gate into multiple equivalent circuits using C-Phase gates with different rotation angles. The quantum circuit conversion unit 120 combines the multiple equivalent circuits generated for each 2-qubit gate to generate multiple converted quantum circuits equivalent to the acquired quantum circuit. The quantum circuit conversion unit 120 then transmits the multiple generated quantum circuits to the quantum computation control unit 130.

[0119] The quantum computing control unit 130 instructs the quantum computer 200 to perform a gate operation on the quantum bit in accordance with each of the multiple quantum circuits acquired from the quantum circuit conversion unit 120. Each time a gate operation according to a quantum circuit is completed, the quantum computing control unit 130 receives a measurement result of the state of the quantum bit from the quantum computer 200. The measurement result is a probability distribution of the state of the quantum bit (bit string). The quantum computing control unit 130 transmits the measurement result obtained from each of the multiple quantum circuits to the output probability averaging unit 140.

[0120] The output probability averaging unit 140 determines the probability of each state by averaging the probability amplitudes for each quantum bit state obtained from each of the multiple quantum circuits. The output probability averaging unit 140 then calculates a solution to the problem to be calculated based on the probability distribution for each state, and transmits the solution to the calculation request receiving unit 110 as the result of the quantum computation.

[0121] The functions of each element shown in FIG. 16 can be realized, for example, by causing the classical computer 100 to execute a program module corresponding to that element. When a quantum computation request is input from a terminal device 30 to such a quantum computing system 300, the quantum circuit conversion unit 120 of the classical computer 100 converts the quantum circuit indicating the quantum computation procedure into a circuit using native gates of the quantum computer 200. For example, the quantum circuit conversion unit 120 decomposes the quantum gates in the quantum circuit to be executed into an equivalent circuit using CX gates and Toffoli gates. The quantum circuit conversion unit 120 further decomposes the Toffoli gate into an equivalent circuit 32 that combines a CX gate and a CRX gate (see FIG. 5).

[0122] The quantum circuit conversion unit 120 then converts the CX gate into a plurality of equivalent circuits with different circuit configurations, and converts the CRX gate into a plurality of equivalent circuits using a plurality of C-Phase gates with different rotation angles.

[0123] 17 is a diagram showing an example of conversion processing into a plurality of quantum circuits. For example, when the quantum computer 200 is caused to execute the gate operation of a C5X gate 60, the quantum circuit conversion unit 120 converts the C5X gate 60 into an equivalent circuit 61 that uses an ancillary quantum bit. The equivalent circuit 61 is composed of two H gates 61a and 61b, one CX gate 61c, and eight Toffoli gates 61d to 61k. The quantum circuit conversion unit 120 further converts each of the Toffoli gates 61d to 61k into an equivalent circuit 32.

[0124] The quantum circuit conversion unit 120 then converts the Toffoli gates 61d to 61k into equivalent circuits 32 to generate a plurality of quantum circuits 62a, 62b,... equivalent to the C5X gate 60. For each of the plurality of quantum circuits 62a, 62b,..., the quantum circuit conversion unit 120 converts the CX gates 61c, 32a, 32b, 32c into one of a plurality of equivalent circuits 51, 52,.... Furthermore, for each of the plurality of quantum circuits 62a, 62b,..., the quantum circuit conversion unit 120 converts the CRX gates 32a, 32c with a rotation angle of "90" into one of a plurality of equivalent circuits 41, 45. Furthermore, for each of the plurality of quantum circuits 62a, 62b,..., the quantum circuit conversion unit 120 converts the CRX gate 32b with a rotation angle of "-90" into one of a plurality of equivalent circuits 42, 47.

[0125] In each of the multiple quantum circuits 62a, 62b, etc., consecutive 1-qubit gates can be integrated into one 1-qubit gate. Any integrated 1-qubit gate can be rotated by using three Euler angles (θ, φ, λ) to perform a rotation gate operation “R Z (φ)·R X (90)·R Z (θ) R X (90)·R Z (λ)" can be implemented.

[0126] Below, the rotating gate operation "R Z (φ)·R X (90)·R Z (θ) R X (90)·R Z A series of quantum gates that perform "(λ)" is called a ZXZXZ gate. In current NISQ devices, it is possible to perform an arbitrary rotation angle R Z The rotation gate (rotation around the Z axis) is implemented, but X Rotation gates (rotation operations around the X axis) are limited to 90 degrees or 180 degrees. Therefore, the quantum circuit conversion unit 120 realizes gate operations of any one-qubit gate by converting a series of gate operations of consecutive one-qubit gates into the above-mentioned ZXZXZ gate.

[0127] This generates a plurality of quantum circuits 62a, 62b,... with different quantum gate configurations that are equivalent to the C5X gate 60 and can be executed by the quantum computer 200. Each of the plurality of quantum circuits 62a, 62b,... is executed by the quantum computer 200, and the average of the probability amplitudes for each state obtained as the measurement results is used as the calculation result, thereby obtaining a calculation result in which the influence of errors has been averaged.

[0128] Next, a specific description will be given of the procedure of the quantum computing assisted processing executed by the classical computer 100 for quantum computing with quantum error mitigation. 18 is a flowchart showing an example of the procedure of quantum computing assisted processing on a classical computer. The processing shown in FIG. 18 will be explained below in order of step number.

[0129] [Step S101] When the computation request receiving unit 110 receives a quantum computation request from the terminal device 30, it acquires a quantum circuit corresponding to the problem to be solved. For example, the quantum circuit is included in the received quantum computation request. In this case, the computation request receiving unit 110 acquires the quantum circuit from the quantum computation request. The computation request receiving unit 110 transmits the acquired quantum circuit to the quantum circuit conversion unit 120.

[0130] [Step S102] The quantum circuit conversion unit 120 decomposes the acquired quantum circuit into circuits that combine CX gates and Toffoli gates. [Step S103] The quantum circuit conversion unit 120 generates multiple quantum circuits with different quantum gate configurations that are equivalent to the acquired quantum circuit and can be executed on the quantum computer 200. In the generated quantum circuit, Toffoli gates are converted into equivalent circuits that use C-Phase gates. The quantum circuit conversion unit 120 transmits the generated multiple quantum circuits to the quantum computation control unit 130.

[0131] [Step S104] The quantum computation control unit 130 selects one unprocessed quantum circuit from the multiple generated quantum circuits. [Step S105] The quantum computation control unit 130 instructs the quantum computer 200 to perform quantum computation in accordance with the selected quantum circuit. For example, the quantum computation control unit 130 determines the timing of microwave irradiation to the quantum bit based on the quantum gate of the selected quantum circuit, and instructs the quantum computer 200 to irradiate the microwave at the determined timing.

[0132] [Step S106] When the quantum computation according to the quantum circuit is completed, the quantum computation control unit 130 obtains from the quantum computer 200 the measurement result of the state of the operated quantum bit. [Step S107] The quantum computing control unit 130 determines whether all of the generated quantum circuits have been selected. If all of the quantum circuits have been selected, the quantum computing control unit 130 proceeds to step S108. If there are any unselected quantum circuits, the quantum computing control unit 130 proceeds to step S104.

[0133] [Step S108] The quantum computing control unit 130 calculates the average value of the probability amplitudes of the quantum bit states based on the measurement results obtained by executing multiple quantum circuits. The quantum computing control unit 130 then calculates a solution to the problem to be solved based on the averaged probability amplitudes of the quantum bit states, and transmits the solution to the computation request receiving unit 110. The computation request receiving unit 110 transmits the obtained solution to the terminal device 30.

[0134] In this way, quantum computation with reduced quantum errors is realized. Next, the process of generating multiple quantum circuits will be described in detail. 19 is a flowchart showing an example of the procedure for generating a plurality of quantum circuits. The process shown in FIG. 19 will be explained below in order of step number.

[0135] [Step S201] The quantum circuit conversion unit 120 converts a Toffoli gate included in a quantum circuit to be executed into an equivalent circuit consisting of two CX gates and three CRX gates.

[0136] [Step S202] The quantum circuit conversion unit 120 generates 30 quantum circuits by converting the CX gates into equivalent circuits with 30 different configurations. For example, the quantum circuit conversion unit 120 generates 30 copies of the quantum circuit to be executed. Then, for each of the copied quantum circuits, the quantum circuit conversion unit 120 randomly selects an equivalent circuit to be applied from multiple equivalent circuits of CX gates, and converts all CX gates in the quantum circuit to the selected equivalent circuit.

[0137] [Step S203] The quantum circuit conversion unit 120 generates 30 quantum circuits in which all CRX gates in the 30 quantum circuits generated in step S202 are implemented as C-Phase gates with a rotation angle of 90 (C-Phase(90)). At this time, the quantum circuit conversion unit 120 converts consecutive 1-qubit gates in the generated quantum circuits into ZXZXZ gates.

[0138] [Step S204] The quantum circuit conversion unit 120 generates 30 quantum circuits in which all CRX gates in the 30 quantum circuits generated in step S202 are implemented as C-Phase gates with a rotation angle of "-90" (C-Phase(-90)). At this time, the quantum circuit conversion unit 120 converts consecutive 1-qubit gates in the generated quantum circuits into ZXZXZ gates.

[0139] In this way, the CRX gate, which is a non-Clifford gate, can be executed using multiple equivalent circuits with different configurations, just like the RC gate, and the execution results can be averaged. As a result, quantum computing that averages out the effects of noise can be realized.

[0140] As an evaluation index of the overall influence of noise, for example, TVD (Total Variation Distance) can be used. TVD is a value using the sum of the differences between the ideal probability without noise and the probability with noise, and is expressed by the following equation (9).

[0141]

number

[0142] p ideal (x) is the probability of occurrence of a sequence of quantum bit values ​​(bit sequence x) under ideal circumstances (noise-free circumstances). p(x) is the probability of occurrence of bit sequence x measured by actual measurement or simulation. In equation (9), for each bit sequence x belonging to the set X of possible bit sequences, the difference between the probability when there is noise and the probability when there is no noise is calculated. Then, half of the sum of these differences is the TVD. The smaller the TVD value, the less the influence of noise.

[0143] 20 is a diagram showing an example of the results of a comparison of the noise influence for each noise mitigation method. Graph 70 compares the TVD for each noise mitigation method applied when executing the equivalent circuit 32 of the Toffoli gate 31. The horizontal axis of graph 70 represents the output value of the Toffoli gate, and the vertical axis represents the TVD. Each of the four vertical bars for each output value of the Toffoli gate corresponds to a noise mitigation method.

[0144] The leftmost vertical bar shows the TVD when no noise mitigation techniques are applied (w / o RC). The second vertical bar from the left shows the TVD when the CX gate is converted to a random equivalent circuit and the CRX gate is converted to an equivalent circuit using a C-Phase gate with a rotation angle of 90° (w / RC1). The third vertical bar from the left shows the TVD when the CX gate is converted to a random equivalent circuit and the CRX gate is converted to an equivalent circuit using a C-Phase gate with a rotation angle of -90° (w / RC2). The rightmost vertical bar shows the TVD when the average of "w / RC1" and "w / RC2" is used as the measurement result (w / RC1+2).

[0145] As shown in Graph 70, for "w / RC1+2", any output value will be an intermediate value between "w / RC1" and "w / RC2". In other words, the effect of noise is averaged. As a result, it is possible to prevent noise from becoming extremely large at specific output values, and the amount of noise (TVD value) can be kept within a certain range. As a result, the amount of noise when the quantum circuit is executed can be kept within expectations, and the occurrence of errors can be suppressed.

[0146] 21 is a diagram showing an example of a quantum circuit used for noise mitigation. For example, quantum circuit 71 uses a C-Phase gate with a rotation angle of "90" to realize a gate operation equivalent to a Toffoli gate. Quantum circuit 72 uses a C-Phase gate with a rotation angle of "-90" to realize a gate operation equivalent to a Toffoli gate.

[0147] By converting the CZ gate of quantum circuit 71 into a plurality of random equivalent circuits using RC, a plurality of quantum circuits 71a, 71b, ... equivalent to Toffoli gates are obtained. In the "w / RC1" noise mitigation method, the calculation results when these quantum circuits 71a, 71b, ... are executed by quantum computer 200 are averaged.

[0148] By converting the CZ gate of quantum circuit 72 into a plurality of random equivalent circuits using RC, a plurality of quantum circuits 72a, 72b, ... equivalent to Toffoli gates are obtained. In the "w / RC2" noise mitigation method, the calculation results when these quantum circuits 72a, 72b, ... are executed by quantum computer 200 are averaged.

[0149] In the "w / RC1+2" noise mitigation method, the calculation results are averaged when the quantum computer 200 executes the quantum circuits 71a, 71b, ... used in "w / RC1" and 72a, 72b, ... used in "w / RC2".

[0150] Below, a description will be given of the simulation results when different coherent noises are applied during execution of the quantum circuit shown in FIG. Figure 22 shows an example of a simulation result when different coherent noises are applied. In the simulation, overrotation noise is applied as the coherent noise. Coherent noise is noise that occurs due to insufficient device calibration, and the noise increases depending on the quantum circuit and quantum state. If the amount and direction of coherent noise are unknown, the noise may become high, and when the noise amount is at its maximum, the calculation error becomes large. Therefore, even if the noise does not reach the minimum value in a quantum bit device, it is advantageous to use an average noise.

[0151] In graph 73, the horizontal axis represents the combination of the directions of overrotation noise for one-qubit gates and two-qubit gates, and the vertical axis represents the average TVD for the combination of the directions of overrotation noise. Line 73a represents the average TVD when no noise mitigation technique is applied (w / o RC). Line 73b represents the average TVD when the CX gate is converted to a random equivalent circuit and the CRX gate is converted to an equivalent circuit using a C-Phase gate with a rotation angle of "90" (w / RC1). Line 73c represents the average TVD when the CX gate is converted to a random equivalent circuit and the CRX gate is converted to an equivalent circuit using a C-Phase gate with a rotation angle of "-90" (w / RC2). Line 73d represents the average TVD when the average of "w / RC1" and "w / RC2" is used as the measurement result (w / RC1+2).

[0152] Graph 73 shows that in the case of "w / RC1+2", the TVD average value can be prevented from becoming the worst value. As described above, by adopting "w / RC1+2" as the quantum error mitigation method, the number of 2-qubit gates can be reduced compared to when implementing it using only Clifford gates, and quantum error mitigation can also be achieved. This prevents the coherent noise from reaching its worst value.

[0153] Although the embodiments have been described above, the configuration of each part shown in the embodiments can be replaced with other parts having similar functions. Any other components or processes may be added. Furthermore, any two or more configurations (features) of the above-described embodiments may be combined. [Explanation of symbols]

[0154] 1. Quantum computers 2 The fourth quantum circuit 2a Toffoli Gate 3 The first quantum circuit 3a-3c First two-qubit gate 3d, 3e Fourth two-qubit gate 4a, 4b,... Second quantum circuit 5a, 5b,... Third quantum circuit 6a, 6b,... Third equivalent circuit 7 First equivalent circuit 7a Second two-qubit gate 8 Second equivalent circuit 8a Third two-qubit gate 10. Information processing equipment 11 Storage section 12 Processing section

Claims

1. generating a second quantum circuit by replacing a first two-qubit gate in a first quantum circuit including a first two-qubit gate that performs a rotation gate operation on a second quantum bit about the X axis in accordance with the state of the first quantum bit with a first equivalent circuit that includes a second two-qubit gate that performs a phase rotation gate operation on the second quantum bit by a first rotation angle in accordance with the state of the first quantum bit; generating a third quantum circuit by replacing the first two-qubit gate in the first quantum circuit with a second equivalent circuit including a third two-qubit gate that performs a gate operation of phase rotation of the second quantum bit by a second rotation angle depending on the state of the first quantum bit; causing a quantum computer capable of executing the second two-qubit gate and the third two-qubit gate to execute the second quantum circuit and the third quantum circuit; outputting an average of the execution result of the second quantum circuit and the execution result of the third quantum circuit as the execution result of the first quantum circuit; A quantum computing support program that causes a computer to perform processing.

2. In the process of generating the second quantum circuit, the second quantum circuit is generated including the second two-qubit gate with a rotation angle of 90 degrees; In the process of generating the third quantum circuit, the third quantum circuit is generated, the third quantum circuit including the third two-qubit gate having a rotation angle of −90 degrees. The quantum computing support program according to claim 1.

3. generating the first quantum circuit by replacing the Toffoli gate in a fourth quantum circuit including the Toffoli gate with a circuit that combines the first two-qubit gate and a fourth two-qubit gate that inverts the state of the target qubit depending on the state of the control qubit; The quantum computing support program according to claim 1, further causing a computer to execute a process.

4. In the process of generating the second quantum circuit, a fourth two-qubit gate that is included in the first quantum circuit and performs a Clifford operation is converted into a plurality of third equivalent circuits that are equivalent to the fourth two-qubit gate and have different configurations of one-qubit gates, thereby generating a plurality of the second quantum circuits; In the process of generating the third quantum circuit, the fourth two-qubit gate is converted into each of the plurality of third equivalent circuits, thereby generating a plurality of the third quantum circuits. The quantum computing support program according to claim 1.

5. generating a second quantum circuit by replacing a first two-qubit gate in a first quantum circuit including a first two-qubit gate that performs a rotation gate operation on a second quantum bit about the X axis in accordance with the state of the first quantum bit with a first equivalent circuit that includes a second two-qubit gate that performs a phase rotation gate operation on the second quantum bit by a first rotation angle in accordance with the state of the first quantum bit; generating a third quantum circuit by replacing the first two-qubit gate in the first quantum circuit with a second equivalent circuit including a third two-qubit gate that performs a gate operation of phase rotation of the second quantum bit by a second rotation angle depending on the state of the first quantum bit; causing a quantum computer capable of executing the second two-qubit gate and the third two-qubit gate to execute the second quantum circuit and the third quantum circuit; outputting an average of the execution result of the second quantum circuit and the execution result of the third quantum circuit as the execution result of the first quantum circuit; A quantum computing-assisted method in which processing is performed by a computer.

6. a processing unit that generates a second quantum circuit by replacing a first two-qubit gate in a first quantum circuit including a first two-qubit gate that performs a rotation gating operation on a second quantum bit about the X axis in accordance with the state of the first quantum bit with a first equivalent circuit that includes a second two-qubit gate that performs a gating operation of a phase rotation of the second quantum bit by a first rotation angle in accordance with the state of the first quantum bit, and generates a third quantum circuit by replacing the first two-qubit gate in the first quantum circuit with a second equivalent circuit that includes a third two-qubit gate that performs a gating operation of a phase rotation of the second quantum bit by a second rotation angle in accordance with the state of the first quantum bit, and causes a quantum computer that can execute the second two-qubit gate and the third two-qubit gate to execute the second quantum circuit and the third quantum circuit, and outputs an average of an execution result of the second quantum circuit and an execution result of the third quantum circuit as an execution result of the first quantum circuit; An information processing device having the above.

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