Adaptive method for efficiently reading retention degraded NAND data

Abstract

To provide an adaptive method for efficiently reading NAND data deteriorated in retention.SOLUTION: A method of operation of a computing device with a solid state drive (SSD) includes obtaining an existing read retry table including a sequential list of voltage index sets for reading a flash memory of the SSD, determining an aging parameter of the SSD, identifying a retry voltage index set from the sequential list based on the aging parameter, and reading the flash memory using the retry voltage index set.SELECTED DRAWING: Figure 3A

Description

[Technical Field]

[0001] The present disclosure relates to a method for controlling a computing device equipped with a solid-state drive (SSD) that includes flash memory. [Background technology]

[0002] Flash memory in SSDs (e.g., NAND- or NOR-based memory devices) offers improved read and write speeds compared to hard disk drives in computing devices. However, like any other type of storage media, the information stored in flash memory can become corrupted through degradation. One mechanism for flash memory degradation is charge loss, which causes bit read errors when reading from flash memory. To ensure accurate memory reads and maintain the full usability of flash memory, an efficient method for compensating for charge loss is needed. Summary of the Invention [Means for solving the problem]

[0003] Generally, one or more embodiments of the present invention relate to a method of operating a computing device with a solid-state drive (SSD), the method including obtaining an existing read retry table including a sequential list of voltage index sets for reading flash memory of the SSD, determining an aging parameter for the SSD, identifying a retry voltage index set from the sequential list based on the aging parameter, and reading the flash memory using the retry voltage index set.

[0004] Generally, one or more embodiments of the present invention relate to a non-transitory computer-readable medium (CRM) storing computer-readable program code for operating a computing device with an SSD, the computer-readable program code causing the computing device to retrieve an existing read retry table including a sequential list of voltage index sets for reading flash memory of the SSD, determine aging parameters for the SSD, identify a retry voltage index set from the sequential list based on the aging parameters, and read the flash memory using the retry voltage index set.

[0005] Generally, one or more embodiments of the present invention relate to a computing device including a solid-state drive (SSD) including a flash memory and a processor configured to read the flash memory, wherein the processor is configured to retrieve an existing read retry table including a sequential list of voltage index sets for reading the flash memory, determine an aging parameter for the SSD, identify a retry voltage index set from the sequential list based on the aging parameter, and read the flash memory using the retry voltage index set.

[0006] Other aspects of the present invention will become apparent from the following description and appended claims. [Brief explanation of the drawings]

[0007] [Figure 1A] FIG. 1A is a perspective view of a computing device in accordance with one or more embodiments of the present invention. [Figure 1B] FIG. 1B is a schematic diagram of various subcomponents of the computing device of FIG. 1A in accordance with one or more embodiments of the present invention. [Figure 1C]FIG. 1C is a schematic diagram of subcomponents of the SSD of the computing device of FIG. 1A in accordance with one or more embodiments of the present invention. [Figure 2A] FIG. 2A is a schematic diagram of a flash memory cell in an SSD. [Figure 2B] FIG. 2B is a diagram of a typical read and a degraded read from a flash memory. [Figure 2C] Figure 2C shows an existing read retry table for reading flash memory. [Figure 3A] FIG. 3A is a flowchart of a method according to one or more embodiments of the present invention. [Figure 3B] FIG. 3B is a flowchart of a method according to one or more embodiments of the present invention. [Figure 4] FIG. 4 is an example of generating a retry pattern according to one or more embodiments. [Figure 5] FIG. 5 is a non-limiting example of a read retry process workflow according to one or more embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0008] Specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, in which like elements in the various drawings are designated with like reference numerals for consistency.

[0009] In the following detailed description of embodiments of the present invention, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating the description.

[0010] To combat read degradation and maintain SSD functionality, conventional solutions employ a read retry process with iterative voltage settings that re-read any portions of flash memory that contain bit read errors. As described in further detail below, embodiments of the present invention improve the read retry process by using one or more (i.e., a pattern of) adaptive read retry voltage index sets that increase the speed and efficiency of the read retry process.

[0011] FIG. 1A illustrates a perspective view of a computing device 10 in accordance with one or more embodiments of the present invention.

[0012] Computing device 10 (e.g., a laptop personal computer (PC), tablet PC, desktop PC, convertible PC) is provided with at least one SSD. Embodiments of the present invention can be implemented on virtually any type of computing device 10, regardless of the platform used. For example, computing device 10 may be one or more mobile devices (e.g., a laptop computer, a smartphone, a personal digital assistant, a tablet computer, or other mobile devices), a desktop computer, a server, a blade in a server chassis, or any other type of computing device or devices that has at least minimum processing power, memory, and input / output devices to perform one or more embodiments of the present invention.

[0013] FIG. 1B shows a schematic diagram of various subcomponents of computing device 10 of FIG. 1A in accordance with one or more embodiments of the present invention.

[0014] The computing device 10 includes a motherboard MB having multiple subcomponents. The subcomponents installed on the motherboard MB include a central processing unit (CPU) 12, memory 14, a graphics processing unit (GPU) 16 (e.g., a video subsystem), a chipset 18, a firmware memory 20, an embedded controller 22, a power control circuit 24, and a storage device 26 (e.g., a hard disk drive (HDD), a solid-state drive (SSD)). The computing device 10 may further include a fan and a power supply.

[0015] In one or more embodiments, the above-described subcomponents of computing device 10 may be omitted, included in multiple quantities, combined as a single subcomponent (e.g., a processor acting as a controller for one or more subcomponents), and / or located in other portions of computing device 10. For example, the SSDs described herein may be individual components, embedded components (e.g., part of storage device 26), any combination of the above, or any suitable implementation in the configuration of computing device 10.

[0016] Furthermore, it will be understood that computing device 10 may include other subcomponents (e.g., peripherals, removable components, external power supplies) internally or externally beyond those listed above without departing from the scope of this disclosure. For example, although the following embodiments are described with respect to an internal SSD, the present invention may be directed to any type of SSD (e.g., an external SSD) connected to computing device 10.

[0017] As described above, embodiments of the present invention can be implemented on virtually any type of computing device 10. For example, computing device 10 can include one or more computer processors, associated memory (e.g., random access memory (RAM), cache memory, flash memory), one or more storage devices, and numerous other elements and functions. A computer processor may be an integrated circuit for processing instructions. For example, a computer processor may be one or more cores, or micro-cores, of a processor. Computing device 10 may also include one or more input devices, such as a camera, a touchscreen, a keyboard, a mouse, a microphone, a touchpad, an electronic pen, or any other type of input device. Furthermore, computing device 10 may include one or more output devices, such as a projector, a display screen (e.g., an OLED display or other pixel-addressable display device), external storage, or any other output device. One or more of the output devices may be the same as or different from the input devices. Computing device 10 can be connected to a network (e.g., a local area network (LAN), a wide area network (WAN) such as the Internet, a mobile network, or any other type of network) via a network interface connection (not shown). The input and output devices may be connected locally or remotely (e.g., via a network) to the computer processor, memory, and storage devices. Many different types of computing device 10 exist, and the above-described subcomponents of computing device 10 may take other forms.

[0018] Software instructions in the form of computer-readable program code that implement embodiments of the present invention may be stored, in whole or in part, temporarily or permanently, on a non-transitory computer-readable medium such as a CD, DVD, storage device, diskette, tape, flash memory, physical memory, or any other computer-readable storage medium. In particular, the software instructions may correspond to computer-readable program code that, when executed by a processor, is configured to implement embodiments of the present invention.

[0019] FIG. 1C shows a schematic diagram of subcomponents of the SSD of computing device 10 of FIG. 1A in accordance with one or more embodiments of the present invention.

[0020] In one or more embodiments, storage device 26 is an SSD that includes a processor 261 (e.g., a controller) and one or more units of flash memory 262 (i.e., flash memory devices). Each flash memory 262 includes a plurality of flash memory cells 200 (e.g., NAND devices, NOR devices), which are described in further detail below with reference to FIG. 2A. For example, flash memory device 262 may be organized into pages and / or blocks of flash memory cells 200.

[0021] Processor 261 controls reading from and writing to flash memory 262. In one or more embodiments, another processor in computing device 10 (e.g., CPU processor 12, GPU processor 16, an integrated circuit, a remote processing device) may control reading from and writing to flash memory 262. The SSD may further include firmware used by processor 261 to read from and write to flash memory 262.

[0022] FIG. 2A is a schematic diagram of a flash memory cell 200 of an SSD.

[0023] An SSD includes multiple flash memory cells 200 that store information. Each flash memory cell 200 includes a substrate 202 having a source 204 and a drain 206. A control gate 208 is used to control charge carriers in an accumulation layer 212 (e.g., a charge trap, a floating gate). A gate oxide 210 and a tunnel oxide 211 separate the accumulation layer 212 from the control gate 208 and the substrate 202, respectively.

[0024] The data retention capability of flash memory cell 200 can degrade as flash memory cell 200 ages. One degradation mechanism is charge loss in storage layer 212 through tunnel oxide 211 over time. Charge loss can be affected by various parameters, such as the number of rewrite cycles of flash memory cell 200, the temperature of the SSD, and / or the amount of operation (e.g., time since power-on). Over time, as more electrons in the floating gate or charge traps leak through tunnel oxide 211, the amount of charge remaining in the floating gate or charge traps decreases. As a result, the voltage threshold used to properly read flash memory cell 200 must be shifted from its original value, as shown in FIG. 2B.

[0025] FIG. 2B shows a diagram of an ideal read and a degraded read from a flash memory cell 200.

[0026] 2B, an ideal read includes multiple program states P (e.g., bit sequences) that are fully distinguished by multiple voltage thresholds Vth (i.e., a set of voltage indexes). In other words, the voltage read value from flash memory 262 can be compared to a set of voltage indexes to determine the program state or stored value of flash memory 262.

[0027] In the bottom diagram of Figure 2B, charge loss in flash memory 262 degrades the read value, resulting in a bit read error. Due to the loss of charge in storage layer 212, the read value from flash memory 262 shifts / condenses to the left, causing the distribution of a given program state to straddle the original voltage threshold. The portion of the distribution for each program state that is now below the original voltage threshold level is incorrectly read as the adjacent program state. The SSD firmware may implement a read retry process to attempt to re-read the intended program state of flash memory 262 by compensating for the change in voltage read.

[0028] FIG. 2C shows an existing read retry table 250 for reading the flash memory 262.

[0029] A conventional read retry process uses a read retry table 250 containing a predefined sequential list of voltage index sets for reading the flash memory 262. To adapt to changes in voltage read values, each voltage index set establishes a new set of thresholds for distinguishing between expected program states. As shown in FIG. 2C, a conventional read retry table 250 can contain dozens of individual voltage index sets (i.e., rows in the read retry table). The SSD firmware sequentially uses each voltage index set in the read retry table 250 to reread the flash memory 262 until the bit read error is resolved. However, this conventional approach may take too long to complete before the original bit read error causes a problem for the computing device 10 (e.g., an application / operating system hang, a blue screen).

[0030] As described in further detail below, embodiments of the present invention improve upon conventional read retry processes by using one or more (i.e., a pattern of) adaptive read retry voltage index sets that increase the speed and efficiency of the read retry process. In one or more embodiments, an aging parameter of the SSD is determined to characterize the degree of degradation of the flash memory. Based on the aging parameter, an appropriate voltage index set can be selected from a conventional read retry table 250 to read the flash memory 262 without lengthy repetitive processing.

[0031] FIG. 3A shows a flowchart of a method 300 according to one or more embodiments of the present invention.

[0032] At 310, a processor (e.g., processor 261 of the SSD, processor 12 of computing device 10, or any processor connected to the SSD) retrieves an existing read retry table 250 that includes a sequential list of voltage index sets for reading flash memory 262. The existing read retry table 250 may be stored in firmware memory of the SSD.

[0033] The processor determines aging parameters for the SSD at 320. As described in more detail below with respect to Figure 3B, the aging parameters may be determined using a variety of different methods.

[0034] At 330, the processor identifies a retry voltage index set from a sequential list in the existing read retry table 250 based on the aging parameter.

[0035] Optionally, at 340, the processor generates one or more retry patterns, each including multiple voltage index sets identified from the sequential list based on one or more aging parameters, and the retry pattern defines a series of retry voltage index sets from the sequential list that can be used sequentially in re-read operations without having to determine a new retry voltage index set after each failure.

[0036] In some embodiments, each entry (i.e., voltage index set) in a retry pattern corresponds to a different element of the aging parameter (e.g., one entry corresponding to an aging parameter based on P / E cycles, another entry corresponding to an aging parameter based on temperature), or a different aging parameter. In some embodiments, the retry patterns may be listed sequentially based on the importance of the corresponding aging parameter. The retry patterns may include the retry voltage index set identified in 330 as the first sequential entry of the first retry pattern.

[0037] In one or more embodiments, the processor may generate a predetermined number of retry patterns. The set of retry patterns may be used sequentially in a reread operation without having to determine a new retry pattern after each failure. In some embodiments, the predetermined number of retry patterns may be enumerated sequentially based on the importance of an aging parameter used to generate each retry pattern.

[0038] At 350, the processor reads the flash memory using the retry voltage index set of the SSD. In embodiments using a retry pattern, the processor may sequentially use the retry pattern entries (e.g., starting with the retry voltage index set identified at 330). In embodiments using multiple retry patterns, the processor may sequentially use the list of retry patterns (e.g., starting with the first retry pattern generated at 340).

[0039] 3B shows a flowchart of a method 320 according to one or more embodiments of the present invention. As described above, the method 320 includes determining aging parameters of the SSD.

[0040] At 322, the processor identifies the type of aging parameter to determine. As described above, the aging of an SSD (or one or more flash memory devices 262 or one or more flash memory cells 200 therein) may be characterized by several parameters. For example, the number of program / erase (P / E) cycles of a flash memory device 262 or flash memory cell 200 may correlate to the degree of degradation. Similarly, ambient temperature and / or elapsed operating time may correlate to the degree of degradation.

[0041] Under different operating conditions of computing device 10, certain aging parameters may more accurately characterize the degree of degradation. For example, under consistent use, elapsed operating time may provide an accurate estimate of degradation. However, if use varies greatly in time or intensity, a direct measurement of P / E cycles may provide a more accurate estimate of degradation.

[0042] If the processor identifies P / E cycles as the aging parameter determined in 322, the process proceeds to 323.

[0043] If the processor specifies elapsed time as the aging parameter to be determined at 322 , the process proceeds to 324 .

[0044] If the processor identifies temperature as the aging parameter to be determined at 322, the process proceeds to 325.

[0045] At 323, the processor determines the number of P / E cycles of the flash memory 262. The number of P / E cycles may be determined based on the particular portion of the flash memory 262 being read (e.g., flash memory device 262, page or block of flash memory 262, flash memory cell 200). Alternatively, the number of P / E cycles may be a statistical approximation (e.g., average, mean, median, mode) of one or more or all portions of the SSD.

[0046] At 324, the processor determines the elapsed time since enablement of the SSD. The elapsed time may be a measure of the operational time of a particular portion of the SSD being read (e.g., flash memory device 262, a page or block of flash memory device 262, flash memory cell 200) or the entire SSD.

[0047] In one or more embodiments, the processor obtains a non-volatile memory express (NVME) timestamp from the basic input / output system (BIOS) of the computing device 10. Based on the NVMe timestamp (e.g., feature identifier 0Eh), the processor can calculate the elapsed operating time (e.g., the elapsed operating time of the SSD, the flash memory device 262, a page or block of the flash memory device 262, or the flash memory cell 200) by counting the elapsed time since the host enabled it.

[0048] At 325, the processor determines the temperature of the SSD from the sensor. The sensor may be a thermometer (e.g., a thermocouple) built into the SSD or located on or adjacent to the SSD. In some embodiments, the sensor may be located within computing device 10 within a distance of the SSD to estimate the temperature of the SSD.

[0049] At 326, the processor determines and outputs aging parameters based on one or more types of input information determined at 323 through 325. The aging parameters can take many forms.

[0050] In some embodiments, the aging parameter is an index value (e.g., row number / label) in an existing read retry table determined based on the information obtained in 323-325. The information obtained in 323-325 may be converted into an aging parameter by one or more algorithms, equations, associations, transformations, logic trees, etc. For example, an estimate of the degree of deterioration may be generated by multiplying the elapsed time determined in 324 by the probability of deterioration increasing per unit time. The degree of deterioration may be associated with one or more rows in the existing read retry table 250, one or more of which indexes are output as the aging parameter.

[0051] In some embodiments, the aging parameter is based on multiple types of input information obtained in 323-325 (e.g., method 320 can include multiple iterations of 323-325 performed sequentially or in parallel). For example, the temperature determined in 325 can be used in combination with the number of P / E cycles determined in 323 to determine the aging parameter. If degradation due to P / E cycles is temperature dependent, including both types of input information from 323 and 325 can more accurately estimate the extent of degradation and provide a more appropriate aging parameter.

[0052] In some embodiments, the aging parameter includes multiple entries (e.g., multiple index values ​​in an existing read retry table, each based on one or more measurements). As described above, the processor can utilize one or more types of information determined in 323-325 to determine a set of estimates of the degree of degradation. Thus, the aging parameter can include multiple entries (e.g., individual indexes in the existing read retry table 250) based on each type of information and / or a combination of different types of information. As discussed in further detail below with respect to FIG. 4, in some embodiments, the multiple entries can be used to generate a retry pattern that includes multiple voltage index sets (e.g., corresponding to multiple entries in the aging parameter).

[0053] In some embodiments, the aging parameters include direct measurements from the information obtained in 323-325 (e.g., number of P / E cycles, elapsed time, temperature) instead of corresponding index values ​​in the existing read retry table 250. The direct measurements may later be converted (e.g., in the process of reading the SSD in 350) into corresponding index values ​​in the existing read retry table 250.

[0054] One or more of the individual processes shown in the flowcharts of Figures 3A-3B may be omitted, repeated, combined, and / or performed in a different order (e.g., parallelized) than that shown in this disclosure. For example, the "end" of a method may be directly connected to the "start" to perform the method in a loop. Alternatively or additionally, one or more processes may be combined in one or more embodiments.

[0055] Each process may be implemented by hardware (e.g., circuits, physical components), software (e.g., machine code, programming on a non-transitory computer-readable medium), or any combination thereof. The processes may be executed actively or passively. For example, some steps may be executed at intervals based on polling and / or may be event / interrupt driven in accordance with one or more embodiments of the present invention. Additional processes may also be executed. Thus, the scope of the present invention should not be limited by the specific configurations shown in FIGS. 3A-3B.

[0056] FIG. 4 illustrates an example of generating a retry pattern according to one or more embodiments.

[0057] In the following non-limiting example, an existing read retry table 250 includes a predefined sequential list of voltage index sets for reading flash memory 262. A conventional read retry method iterates through the voltage index sets in the sequential list (i.e., attempts RR-1, followed by RR-2, RR-3, etc.).

[0058] In one or more embodiments, the computing device 10 performs a series of determinations of the number of P / E cycles, temperature, and elapsed time according to 323-325 above. Each determination is associated with a corresponding index in the existing read retry table 250. In this non-limiting example, the number of P / E cycles indicates a level of degradation that can be compensated for using a voltage index set labeled RR-5, the temperature indicates a level of degradation that can be compensated for using a voltage index set labeled RR-6, and the elapsed time indicates a level of degradation that can be compensated for using a voltage index set labeled RR-8. In other words, the aging parameters can be a list (RR-5, RR-6, RR-8). Alternatively, the aging parameters can be a list of corresponding measurements.

[0059] In some embodiments, computing device 10 can generate retry pattern 400 based on the aging parameter. In this non-limiting example, the retry pattern includes a first set of retry voltage indexes, a second set of retry voltage indexes, and a third set of retry voltage indexes that correspond to RR-5, RR-6, and RR-8, respectively, in existing read retry table 250. Thus, a read retry method according to one or more embodiments of the present invention iterates through the voltage index sets in retry pattern 400 (i.e., attempts RR-5, followed by RR-6, followed by RR-8, etc.).

[0060] The retry pattern 400 may be an ordered list based on the priority of the metrics used to determine one or more aging parameters. For example, the first sequential entry of the retry pattern may be selected based on the number of program / erase (P / E) cycles of the flash memory 262, since P / E cycles may be the most important consideration for estimating degradation. The second sequential entry of the retry pattern may be selected based on the temperature of the SSD or the elapsed operating time of the SSD, depending on which metric is more important for estimating degradation. Information regarding the relative levels of importance may be determined when the aging parameters are determined, may be predefined, or may be determined at any appropriate time (e.g., upon startup, reboot, application launch, start of processing procedure, or hardware and / or software configuration change).

[0061] FIG. 5 illustrates a non-limiting example of a read retry process workflow according to one or more embodiments.

[0062] First, the host of the computing device initiates a boot-up process and causes the BIOS of the computing device to enable timestamps (e.g., NVMe timestamps). If the enablement process fails, the BIOS retries enabling the timestamps until it is successful.

[0063] In one or more embodiments, one or more aging parameters of the SSD are determined when the SSD is powered on (e.g., during startup of the computing device, upon installation of an external SSD). Alternatively, the one or more aging parameters may be determined in response to execution of a predetermined process of the computing device (e.g., booting, rebooting, launching an application, initiating a procedure, changing a hardware and / or software configuration).

[0064] One or more retry patterns are generated based on one or more aging parameters. In some embodiments, this may involve identifying a single retry voltage index set from an existing read retry table (e.g., a retry pattern including a single entry). In some embodiments, one or more of the retry patterns include multiple entries based on different aging parameters of the SSD (e.g., different measurements or elements of the aging parameter), as described above with respect to FIG. 4. The one or more retry patterns may be stored in memory of the SSD (e.g., in firmware) or in memory of the computing device 10.

[0065] When the host requests data from the SSD, it determines whether a read retry process is necessary (e.g., a bit read error is detected). If a read retry process is not necessary, the SSD reads the data and sends it to the host. If a read retry process is necessary, a retry voltage index set is selected from one or more retry patterns to attempt to re-read the data. If the first re-read attempt fails (i.e., the first retry voltage index set cannot be used to generate the data without a bit read error), the next retry voltage index set is selected and used to attempt to re-read the data until the SSD read is successful.

[0066] Although this specification includes a limited number of examples of aging parameters, it will be understood that any suitable metric may be used as or to determine an aging parameter, and therefore, embodiments of the present invention should not be limited to the above non-limiting examples.

[0067] One or more of the embodiments of the present invention may have one or more of the following improvements to computing devices: faster flash memory data read speeds, reduced use of computational resources (processing attempts) during the read retry process, improved consumer functionality by preventing unexpected errors (e.g., application / operating system timeouts, blue screens) during the read retry process.

[0068] While this disclosure has been described with respect to a limited number of embodiments, it should be appreciated that those skilled in the art, having the benefit of this disclosure, may devise various other embodiments without departing from the scope of the invention, which scope should therefore be limited only by the appended claims. [Explanation of symbols]

[0069] 10. Computing Devices 12 Central Processing Unit, CPU Processor 14 Memory 16 Graphics Processing Unit, GPU Processor 18 Chipset 20 Firmware Memory 22 Embedded Controllers 24 Power control circuit 26 Storage Devices 200 flash memory cells 202 Substrate 204 Source 206 Drain 208 Control Gate 210 Gate oxide 211 Tunnel oxide 212 Accumulation layer 250 Read Retry Table 261 processor 262 Flash memory, flash memory devices 300 ways 320 method 400 retry pattern MB Motherboard

Claims

1. 1. A method of operation of a computing device with a solid state drive (SSD), said method comprising: Obtaining an existing read retry table containing a sequential list of voltage index sets for reading flash memory of the SSD; determining aging parameters for the SSD; identifying a retry voltage index set from the sequential list based on the aging parameter; reading the flash memory using the retry voltage index set; A method comprising:

2. Determining the number of program / erase (P / E) cycles of said flash memory. further comprising 2. The method of claim 1, wherein the aging parameter is based on the number of program / erase (P / E) cycles of the flash memory.

3. The number of P / E cycles is determined based on a page or block of the flash memory, or a flash memory cell of the flash memory. The method of claim 2.

4. Determining the elapsed time since enablement of the SSD. further comprising 2. The method of claim 1, wherein the aging parameter is based on the age of the SSD, the flash memory, a page or block of the flash memory, or a flash memory cell of the flash memory.

5. obtaining a non-volatile memory express timestamp from a basic input / output system of said computing device; calculating the elapsed time; The method of claim 4 further comprising:

6. Determining the temperature of the SSD from a sensor. further comprising The method of claim 1 , wherein the aging parameter is based on the temperature.

7. generating a first retry pattern including a plurality of voltage index sets from the sequential list; further comprising a first sequential entry of the first retry pattern is the retry voltage index set; reading the flash memory using sequential entries of the first retry pattern starting from the retry voltage index set; The method of claim 1.

8. each entry of the first retry pattern is based on a different aging parameter of the SSD; The method of claim 7.

9. the first sequential entry of the first retry pattern is selected based on the number of program / erase (P / E) cycles of the flash memory; The method of claim 8.

10. a second sequential entry of the first retry pattern is selected based on a temperature of the SSD; 10. The method of claim 9.

11. a second sequential entry of the first retry pattern is selected based on an elapsed time since enablement of the SSD; 10. The method of claim 9.

12. generating a predetermined number of retry patterns including the first retry pattern; further comprising each retry pattern includes a plurality of voltage index sets from the sequential list; reading the flash memory using the predetermined number of retry patterns, starting with the first retry pattern; The method of claim 7.

13. the first retry pattern is generated in response to execution of a predetermined process of the computing device; The method of claim 7.

14. the predetermined process is the startup of the computing device; The method of claim 13.

15. 1. A non-transitory computer readable medium (CRM) storing computer readable program code for operating a computing device having a solid state drive (SSD), the computer readable program code causing the computing device to: Obtaining an existing read retry table containing a sequential list of voltage index sets for reading flash memory of the SSD; determining aging parameters for the SSD; identifying a retry voltage index set from the sequential list based on the aging parameter; reading the flash memory using the retry voltage index set; A non-transitory computer-readable medium for causing

16. a solid-state drive (SSD) including flash memory; a processor configured to read the flash memory; 1. A computing device comprising: the processor: obtaining an existing read retry table containing a sequential list of voltage index sets for reading the flash memory; determining aging parameters for the SSD; identifying a retry voltage index set from the sequential list based on the aging parameter; Reading the flash memory using the retry voltage index set 1. A computing device configured to:

Images