Memory device, method of manufacturing memory device, and semiconductor device

Abstract

To provide a method of manufacturing a semiconductor device having a three dimensional stacked structure, and a storage device.SOLUTION: A storage device 1000 includes a substrate 200 including an insulating surface 210 and a plurality of storage cells 100 arranged on the insulating surface, and includes a storage cell array in which the plurality of storage cells are repeatedly arranged along first and second horizontal directions and a vertical direction, and one transistor included in each storage cell includes a gate insulating layer 1112, a gate structure 1113, and an active layer 1111 parallel to the insulating surface. The gate structure includes a gate body portion side 1113A, the gate body portion includes a first gate 11131, the first gate extends along a sidewall of the active layer, the gate insulating layer is located between the first gate and the active layer and includes a common source structure including a common source 110 and a bit line structure 120, the bit line structure includes a plurality of bit lines extending along a first direction, and the active layer includes source terminals 11111 connected to the common source structure and drain terminals 11113 connected to the bit lines.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present application belongs to the field of semiconductor technology, and in particular to a memory device, a method for manufacturing a memory device, and a semiconductor device. [Background technology]

[0002] As technology nodes shrink, the memory cell of DRAM (Dynamic Random Access Memory) has gradually shifted from a 1T1C (1 Transistor 1 Capacitor) structure to a 1T0C (1 Transistor 0 Capacitor) structure. The adoption of a capacitor-free structure has reduced the volume of the memory cell and improved memory density.

[0003] In conventional technology, DRAM memory cells are typically arranged spatially in a repeated manner to form a three-dimensional stacked structure with high memory density. However, as the number of layers in the three-dimensional stacked structure increases and the process node shrinks, the difficulty of the manufacturing process gradually increases. Summary of the Invention

[0004] The embodiments of the present application provide a memory device that aims to solve the technical problem of difficulty in the manufacturing process of a semiconductor device having at least a three-dimensional stacked structure.

[0005] The present embodiment is realized as follows, and the storage device includes: a substrate including an insulating surface; a memory cell array including a plurality of memory cells arranged on the insulating surface, the plurality of memory cells being repeatedly arranged along a first horizontal direction, a second horizontal direction, and a vertical direction, the first horizontal direction intersecting the second horizontal direction; each of the memory cells includes a transistor, the transistor including an active layer, a gate insulating layer, and a gate structure, the gate structure including the gate body portion, the gate body portion including a first gate, the active layer being parallel to the insulating surface, the first gate extending along a sidewall of the active layer, and the gate insulating layer being located between the first gate and the active layer; The memory device further includes a common source structure and a bit line structure, the bit line structure including a plurality of bit lines, each of the bit lines extending along the first horizontal direction, the active layer including a source terminal and a drain terminal, the source terminal connected to the common source structure, and the drain terminal connected to the bit line.

[0006] An embodiment of the present application further provides a method for manufacturing a storage device, the method comprising: providing a substrate; providing a plurality of film layer pairs stacked along a vertical direction on the substrate, each film layer pair including a semiconductor material layer and a first insulating dielectric layer arranged in sequence along the vertical direction; etching the plurality of film layer pairs to form a plurality of first slits repeatedly arranged along a first horizontal direction and a second horizontal direction, the first horizontal direction intersecting the second horizontal direction, the first slits penetrating the plurality of film layer pairs along a vertical direction, forming a second insulating dielectric layer to fill the first slits, the semiconductor material layer on one side of the first slits in the second horizontal direction being formed into a bit line structure, the bit line structure including a plurality of bit lines, each of the bit lines extending along the first horizontal direction, and a common source structure formed on a side of the first slit away from the bit line; Etching the second insulating dielectric layer within the first slits to form a plurality of first trenches repeatedly arranged along the first horizontal direction and the second horizontal direction, the first trenches penetrate the second insulating dielectric layer along a vertical direction, the first trenches correspond one by one to the first slits, two opposite sidewalls of the first trenches in the first horizontal direction both expose the semiconductor material layer, and when projected orthogonally onto the substrate, two opposite sidewalls of the first trenches in the second horizontal direction extend into the first slits; forming a gate material layer on the entire sidewall of the first trench, forming a gate insulating material layer located between the gate material layer and the surface of the semiconductor material layer exposed by the first trench, and filling a space surrounded by the gate material layer with a third insulating dielectric layer; etching the gate material layer to form a plurality of second trenches repeatedly arranged along the first horizontal direction and the second horizontal direction, the second trenches penetrating the gate material layer, thereby forming the gate material layer into first gate structures and second gate structures spaced apart in the first horizontal direction; and filling the second trench with a fourth insulating dielectric layer.

[0007] An embodiment of the present application further provides a semiconductor device, the semiconductor device comprising: A substrate; a transistor stack including a plurality of transistors vertically stacked on the substrate; the transistor includes an active layer and a gate electrode, the active layer extends along a horizontal direction, the gate electrode is located on a sidewall of the active layer, and all the gate electrodes in the transistor stack overlap each other in orthogonal projection onto the substrate; The gate electrode includes an integrated gate body portion and a conductor portion, the gate body portion is arranged along the length direction of the active layer, the conductor portion is located on the side of the gate body portion away from the active layer, and the conductor portion is located on both horizontal ends of the gate body portion.

[0008] In the memory device of the embodiment of the present application, multiple 1T0C structure DRAM memory cells are repeatedly arranged along the first horizontal direction, the second horizontal direction, and the vertical direction, and the memory cells have a simple structure, high memory density, and a simple manufacturing process.The memory capacity can be increased by further increasing the number of stacked layers as needed. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a three-dimensional schematic diagram of a storage device according to an embodiment of the present application; [Figure 2] 2 is a schematic cross-sectional view of the memory device shown in FIG. 1 taken along the C1 cross section. [Figure 3] 1A and 1B are schematic cross-sectional views of a transistor according to an embodiment of the present application in a first horizontal direction and a second horizontal direction. [Figure 4] 3A and 3B are cross-sectional schematic diagrams of a transistor in a first horizontal direction and a second horizontal direction according to another embodiment of the present application; [Figure 5] 2 is a schematic cross-sectional view of the memory device shown in FIG. 1 taken along the C2 cross section. [Figure 6] 2 is a schematic cross-sectional view of the memory device shown in FIG. 1 taken along the C3 cross section. [Figure 7] 2 is a schematic cross-sectional view of the memory device shown in FIG. 1 taken along the C4 cross section. [Figure 8] 1 is a structural schematic diagram of a storage device according to an embodiment of the present application; [Figure 9] 10A and 10B are cross-sectional schematic diagrams of a storage device according to another embodiment of the present application, taken along a first horizontal direction and a second horizontal direction. [Figure 10] 1 is a flow diagram of a method for manufacturing a memory device according to an embodiment of the present application. [Figure 11] FIG. 1 is a process flow diagram of a method for manufacturing a memory device according to an embodiment of the present application. [Figure 12] FIG. 1 is a process flow diagram of a method for manufacturing a memory device according to an embodiment of the present application. [Figure 13] FIG. 1 is a process flow diagram of a method for manufacturing a memory device according to an embodiment of the present application. [Figure 14]FIG. 1 is a process flow diagram of a method for manufacturing a memory device according to an embodiment of the present application. [Figure 15] FIG. 1 is a process flow diagram of a method for manufacturing a memory device according to an embodiment of the present application. [Figure 16] FIG. 1 is a process flow diagram of a method for manufacturing a memory device according to an embodiment of the present application. [Figure 17] FIG. 1 is a process flow diagram of a method for manufacturing a memory device according to an embodiment of the present application. [Figure 18] FIG. 1 is a process flow diagram of a method for manufacturing a memory device according to an embodiment of the present application. [Figure 19] FIG. 1 is a process flow diagram of a method for manufacturing a memory device according to an embodiment of the present application. [Figure 20] 2 is a schematic diagram of the circuit connections of a memory cell according to an embodiment of the present application; DETAILED DESCRIPTION OF THE INVENTION

[0010] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be described in more detail with reference to the accompanying drawings and examples. Examples of the embodiments are shown in the accompanying drawings, and the same or similar reference numerals throughout the drawings represent the same or similar elements, or elements having the same or similar functions. It should be understood that the embodiments described below with reference to the accompanying drawings are illustrative and are used only to interpret the present application, and do not limit the present application. It should also be understood that the specific examples described herein are used only to interpret the present application, and do not limit the present application.

[0011] In the description of this application, the orientations or positional relationships shown in the descriptions of directions and positional relationships are based on the orientations or positional relationships shown in the accompanying drawings, and this is for the convenience and simplification of the description of this application, and does not suggest or imply that the referred-to devices or elements have to have a particular orientation or be configured and operated in a particular orientation, and therefore should not be understood as limiting this application.

[0012] Additionally, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or the number of technical features depicted. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more unless otherwise clearly and specifically defined.

[0013] The following disclosure provides many different embodiments or examples for realizing different configurations of the present application. To simplify the disclosure of the present application, specific example components and configurations are described below. Of course, these are merely examples and are not intended to limit the present application. Furthermore, while reference numbers and / or characters may be duplicated in different examples throughout the present application, such duplication is for the sake of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed. Furthermore, while the present application provides examples of various specific processes and materials, those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0014] In the examples of this application, the technical concept of "layer" refers to a material portion that includes a region having a thickness. A layer may extend over the entire substructure or superstructure, or may have a smaller extent than the substructure or superstructure. Furthermore, a layer may be a uniform or non-uniform region of a continuous structure whose thickness is less than the thickness of the continuous structure.

[0015] For example, a layer may be between any pair of horizontal surfaces between the top and bottom surfaces of a continuous structure, or between any pair of horizontal surfaces located at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, may include one or more layers therein, and / or may have one or more layers above, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductor and contact layers (layers in which interconnect lines and / or via contacts are formed) and one or more dielectric layers.

[0016] In the examples of the present application, the technical concept "vertical / vertically" should be understood as being perpendicular to the lateral surfaces of the substrate, and the technical concept "parallel" should be understood as being parallel to the lateral surfaces of the substrate.

[0017] Specifically, "perpendicular" means nearly perpendicular, and refers to a state in which the angle between two lines is 80° or more and 100° or less, including an angle of 85° or more and 95° or less. "Parallel" means approximately parallel or nearly parallel, and refers to a state in which the angle between two lines is -10° or more and 10° or less, including an angle of -5° or more and 5° or less.

[0018] In the examples of this application, the technical concept of "A and B are disposed in the same layer" means that A and B are formed simultaneously by the same patterning process. The technical concept of "the orthogonal projection of B is within the range of the orthogonal projection of A" means that the boundary of the orthogonal projection of B is contained within the boundary of the orthogonal projection of A, or the boundary of the orthogonal projection of A overlaps with the boundary of the orthogonal projection of B.

[0019] The technical concept of "A and B are an integral structure" in the examples of this application can mean that there is no obvious boundary interface such as a fault or gap in the microstructure. Generally, a film layer that is patterned onto a film layer to form a connection is an integral structure. For example, A and B are formed into a single film layer using the same material, and the structures having a connection relationship are simultaneously formed through the same patterning process.

[0020] Referring to FIGS. 1 to 7, a storage device 1000 according to an embodiment of the present application includes: a substrate 200 including an insulating surface 210; a memory cell array including a plurality of memory cells 100 arranged on an insulating surface 210, the plurality of memory cells 100 being repeatedly arranged along a first horizontal direction, a second horizontal direction, and a vertical direction, the first horizontal direction intersecting the second horizontal direction; Each memory cell 100 includes one transistor, the transistor including an active layer 1111, a gate insulating layer 1112, and a gate structure 1113, the gate structure 1113 including a gate body portion 1113A, the gate body portion 1113A including a first gate 11131, the active layer 1111 being parallel to the insulating surface 210, the first gate 11131 extending along the sidewall of the active layer 1111, the gate insulating layer 1112 being disposed between the gate structure 1113 and the active layer 1111; The memory device 1000 further comprises a common source 110 and a bit line structure 120, the bit line structure 120 comprising a plurality of bit lines, each bit line extending along a first horizontal direction, the active layer 1111 including a source terminal 11111 and a drain terminal 11112, the source terminal 11111 being connected to the common source 110 and the drain terminal 11112 being connected to the bit line.

[0021] Specifically, the substrate 200 comprises a semiconductor substrate 200 and an insulating layer located on the side of the semiconductor substrate 200 closer to the memory cell array, and the surface of the insulating layer away from the semiconductor substrate 200 is formed as the insulating surface 210 of the substrate 200, and the memory cells 100 and the semiconductor substrate 200 are insulated by the insulating layer and arranged at a distance from each other.

[0022] The substrate 200 may include at least one of a semiconductor material, such as silicon (e.g., single crystal silicon (Si)), silicon germanium (SiGe), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), and silicon carbide (SiC). Illustratively, the semiconductor substrate 200 may be a single crystal silicon substrate 200, and optionally, the semiconductor substrate 200 includes logic circuitry.

[0023] In one embodiment, the insulating layer is silicon dioxide (SiO2), silicon nitride (SiN x The insulating material may include insulating materials commonly used in the art, such as ethylene glycol tetrafluoroethylene (EPDM), propylene glycol tetrafluoroethylene (PEPC ...

[0024] In one embodiment, substrate 200 may be a single layer structure, such as a single layer structure made of at least one of silicon, germanium, gallium arsenide, and the like.

[0025] In another embodiment, the substrate 200 may be a composite substrate 200 including a multi-layer structure, such as a stack of silicon and silicon germanium, a stack of silicon and silicon carbide, silicon-on-insulator, germanium-on-insulator, silicon germanium-on-insulator, etc.

[0026] In another embodiment, the substrate 200 is an insulating substrate, and its top surface is an insulating surface 210. The insulating substrate may be composed of a non-conductive material such as glass, plastic, or a sapphire wafer. Alternatively, the substrate 200 may be made of silicon dioxide (SiO2) or silicon nitride (SiN x ) or other insulating dielectric materials.

[0027] It is understood that the first horizontal direction and the second horizontal direction are parallel to the substrate, and the vertical direction is perpendicular to the substrate. In the embodiment shown in Figure 1, the first horizontal direction is the Y-axis direction, the second horizontal direction is the X-axis direction, and the vertical direction is the Z-axis direction. It is understood that it is sufficient if the first horizontal direction, the second horizontal direction, and the vertical direction intersect. Preferably, the first horizontal direction is perpendicular to the second horizontal direction. Preferably, in the embodiment shown in Figure 1, the X-axis direction is perpendicular to the Y-axis direction, and the X-axis and Y-axis directions are perpendicular to the Z-axis direction.

[0028] In the memory device 1000 of the embodiment of the present application, a plurality of memory cells 100 are repeatedly arranged along a first horizontal direction, a second horizontal direction, and a vertical direction to form a memory cell array, and the memory cells 100 have a simple structure, high memory density, and a simple manufacturing process. The number of stacked layers can be further increased as needed to increase the memory capacity.

[0029] In the embodiment of the present application, the memory device 1000 can be considered to have multiple memory element layers stacked in a vertical direction, and in each memory element layer, multiple memory cells 100 are repeatedly arranged along a first horizontal direction and a second horizontal direction to form an array arrangement as shown in Figure 2. It is understood that the array arrangement within a memory element layer is identical.

[0030] The term "repeatedly arranged" refers to the fact that the memory cell array has a three-dimensional stacked structure, and the memory cells 100 therein do not have completely identical structures. That is, the structures of the memory cells 100 may be the same or different.

[0031] For example, as shown in FIG. 1 , the functional structures of two adjacent memory cells 100 in the X direction are symmetrical about the common source 110, i.e., not completely repeated spatially. Exemplarily, the size, material, component structure, etc. of any two memory cells 100 may be the same or different. Exemplarily, the extension directions of the active layers 1111 of any two memory cells 100 may be the same or different. However, this is not limited thereto and may vary depending on specific circumstances.

[0032] 1 only shows a memory device 1000 formed by three-dimensionally stacking multiple memory cells 100. It will be understood that the memory device 1000 may include any number of memory element layers, and that a memory element layer may include any number of memory cells 100. The memory cells 100 may be arbitrarily distributed and expanded along a first horizontal direction, a second horizontal direction, and a vertical direction to meet different memory requirements.

[0033] In the embodiment of the present application, the memory device 1000 is a DRAM memory device, and its basic memory cell 100 is a DRAM memory cell with a 1T0C structure, that is, each memory cell 100 includes one transistor, i.e., a single transistor may be the smallest memory cell 100 in the memory device 1000, as shown in Figures 3 and 4.

[0034] In the memory cell 100, the active layer 1111 is parallel to the insulating surface 210. Exemplarily, but not limited to, the active layer 1111 extends along a second horizontal direction. For example, in other embodiments, the active layer 1111 can extend along a third horizontal direction that intersects both the first and second horizontal directions. Alternatively, in yet another embodiment, the active layer 1111 can be curved, depending on the specific circumstances.

[0035] In the memory cell 100, the gate structure 1113 includes a gate body 1113A, which includes a first gate 11131, and the first gate 11131 extends along a sidewall of the active layer 1111. The gate body 1113A is a portion of the gate structure 1113 that can control the active layer 1111; that is, the gate body 1113A can be understood as a portion of the gate structure 1113 that extends along the active layer 1111. The active layer 1111 includes an upper surface, a lower surface, and two sidewalls located between the upper and lower surfaces. The first gate 11131 extends along a sidewall of the active layer 1111 that is parallel to the substrate 200. The first gate 11131 is approximately perpendicular to the substrate 200, and is located on one side of the active layer 1111 in an orthogonal projection of the substrate 200.

[0036] In the embodiment of the present application, the source terminal 11111 of the memory cell 100 is connected to a common source structure, which can be connected to a fixed potential such as ground, so that a fixed potential can be applied to the source terminal 11111 of the DRAM memory cell 100 in the 1T0C structure.

[0037] In one embodiment, the material of the common source structure may be the same as or different from the material of the active layer 1111. Illustratively, the material of the common source structure may be a conductive material such as polysilicon, doped polysilicon, or a metal (e.g., tungsten or titanium nitride). As shown in FIGS. 1, 2, 5, and 6, the common source structure includes at least one common source 110.

[0038] The common source structure includes at least one common source 110 vertically disposed on the substrate 200, and the common source 110 further extends along a first horizontal direction. The common source 110 is connected to a plurality of source terminals 11111 adjacent to each other in the vertical direction, and the source terminals 11111 adjacent to each other in the first horizontal direction are connected to the same common source 110.

[0039] 5, the common source 110 can vertically penetrate all memory layers, for example, vertically penetrate each layer of a multi-layer memory layer from top to bottom. Vertically adjacent transistors in different memory layers can be connected to the same common source 110.

[0040] As shown in FIG. 2, in the same memory element layer, the memory cells 100 are arranged along a first horizontal direction to form a column, and the common source 110 extends along the first horizontal direction, so that each memory cell 100 of the transistors in the same column can be correspondingly connected to the same common source 110.

[0041] Furthermore, the functional structures of the two columns of memory cells 100 adjacent to the common source 110 in the second horizontal direction are arranged symmetrically with respect to the common source 110 and are both connected to the same common source 110. That is, the two columns of memory cells 100 adjacent to each other in the second horizontal direction can share the common source 110.

[0042] Therefore, the common source 110 can be formed as a plate-like structure extending in a plane formed in the vertical direction and the first horizontal direction. Therefore, the common source 110 can be formed by etching a larger trench and then filling the trench with a conductive material, which can reduce the difficulty of the manufacturing process and has low impedance.

[0043] As shown in FIG. 8, the common source structure may include multiple common sources 110, which are arranged along a second horizontal direction.

[0044] However, the present invention is not limited to this, and in other embodiments not shown, the common source structure includes a plurality of common sources 110 arranged vertically on the substrate 200, the common sources 110 are connected to a plurality of vertically adjacent source terminals 11111, and the source terminals 11111 adjacent in the first horizontal direction are connected to different common sources 110, i.e., the common sources 110 are formed as columnar vertical conductors that penetrate at least two adjacent memory element layers, and in this case, the common sources 110 are considered to be vertical contact elements, and a plurality of vertical contact elements are stacked vertically to form the common source structure.

[0045] Alternatively, the common source structure may include a plurality of common sources 110 extending along a first horizontal direction, each common source 110 corresponding to a storage element layer, with source terminals 11111 adjacent in the first horizontal direction connected to the same common source 110 and source terminals 11111 adjacent in the vertical direction connected to different common sources 110. That is, the common sources 110 are formed as linear horizontal conductors extending along the first horizontal direction, and multiple common sources 110 may be stacked vertically to reduce the horizontal area of ​​the common source structure.

[0046] The present application does not particularly limit the common source structure, and it may be specifically set according to specific needs.

[0047] 1, 2, and 8, the memory device 1000 has a bit line structure including a plurality of bit lines extending along a first horizontal direction, and the drain terminals 11112 of the memory cells 100 are connected to the bit lines. In an embodiment of the present application, a particular memory cell 100 in the memory cell array can be selected by cross-positioning the gate structures 1113 and the bit lines.

[0048] Each memory element layer may include a plurality of bit lines. The plurality of bit lines may be spaced apart along the second horizontal direction. In the same memory element layer, the memory cells 100 may be arranged along the first horizontal direction to form a column, and the bit lines may extend along the first horizontal direction, with the memory cells 100 in the same column being connected to the same bit line.

[0049] 2 and 8, in the memory element layer, two columns of memory cells 100 adjacent to a bit line in the second horizontal direction are arranged symmetrically around the bit line in terms of functional structure and are both connected to the same bit line. That is, the two columns of memory cells 100 adjacent to each other in the second horizontal direction can share the bit line.

[0050] In one embodiment, the material of the bit line may be the same or different from the material of the common source 110 and the active layer 1111 .

[0051] By way of example, the material of the bit line may be polysilicon, doped polysilicon, or a metal (e.g., tungsten, titanium nitride, etc.), as long as it is electrically conductive to provide electrical connection to the source of the transistor.

[0052] For example, the bit line and the active layer 1111 of the transistor may be made of the same material and connected together.

[0053] In one embodiment, the material of the bit line may be the same as the material of the active layer 1111, and the bit line and the active layer 1111 in the same memory element layer may be provided by the same semiconductor material layer 2, that is, they may be respectively part of the same semiconductor material layer 2 and formed integrally. Among these, the semiconductor material layer 2 may be made of N-type polysilicon or P-type polysilicon, for example, N-type polysilicon.

[0054] Optionally, the doping concentration of the bit lines may be higher than the doping concentration of the active layer 1111 .

[0055] In an embodiment of the present application, as shown in Figures 1, 5 to 7, the memory device 1000 may further include an insulating spacer layer 160 used to electrically isolate the active layers 1111 of transistors in adjacent vertically stacked layers from the bit lines.

[0056] In one embodiment, the material of the insulating spacer layer 160 may be the same as or different from the material of the gate insulating layer 1112. Illustratively, the material of the insulating spacer layer 160 may be SiO2, SiN x Alternatively, it may be an insulating material such as TEOS (Tetraethoxysilane) or a low dielectric constant material.

[0057] In an embodiment of the present application, the gate body portion 1113A further includes a second gate 11132, which extends along the sidewall of the active layer 1111, and in a normal projection of the substrate 200, the first gate 11131 and the second gate 11132 are located separately on both sides of the active layer 1111 and extend along the sidewall of the active layer 1111.

[0058] As shown in FIGS. 2 to 7, the transistor in the memory cell 100 is a dual-gate transistor, and the two gates are a first gate 11131 and a second gate 11132.

[0059] The first gate 11131 and the second gate 11132 of the gate structure 1113 in the transistor are arranged opposite each other on both sides of the active layer 1111 in the horizontal direction, which improves the gate controllability over the channel in the transistor. In particular, in the case of a memory cell with a 1T0C structure, it becomes easier to achieve full depletion of the channel region.

[0060] In the embodiment of the present application, the material of the gate structure 1113 may include a conductive material such as a metal (e.g., tungsten or titanium nitride), where the materials of the first gate 11131 and the second gate 11132 may be the same or different. Preferably, the materials of the first gate 11131 and the second gate 11132 are the same.

[0061] Furthermore, the first gate 11131 and the second gate 11132 may have the same or different shapes and widths, and may be arranged completely opposite or partially opposite to each other. Preferably, the first gate 11131, the second gate 11132, and the active layer 1111 all extend along the second horizontal direction.

[0062] As shown in Figures 1, 2, and 7, multiple vertically adjacent memory cells 100 form a memory cell stack, and in the multiple memory cells 100 in the memory cell stack, the orthogonal projections of the active layer 1111, the gate insulating layer 1112, and the gate structure 1113 onto the substrate 200 respectively overlap, and the overlapping portions of the orthogonal projections of the gate structure 1113 onto the substrate 200 are correspondingly connected.

[0063] As an example of the present application, two adjacent vertically stacked memory cells 100 have identical structures and are fabricated or patterned simultaneously, so that the orthogonal projections of the structures in the upper and lower memory cells 100 onto the substrate 200 overlap, respectively.

[0064] It is understood that since the vertically adjacent storage cells 100 are located at different depths, a certain process error occurs between them in the manufacturing process, and the overlapping includes both a perfect overlapping and an approximate overlapping.

[0065] In the gate structure 1113, overlapping portions in the orthogonal projection onto the substrate 200 are correspondingly connected, i.e., the gate structure 1113 includes a gate body portion 1113A and other portions, and when the gate body portions 1113A overlap in the orthogonal projection onto the substrate 200, the gate body portions 1113A are connected to each other, and when the other portions overlap in the orthogonal projection onto the substrate 200, the other portions are connected to each other. The gate body portion 1113A includes a first gate 11131 and a second gate 11132, and when the first gate 11131 and the second gate 11132 overlap in the orthogonal projection onto the substrate 200, the first gate 11131 and the second gate 11132 are connected to each other.

[0066] 2 and 7, a plurality of vertically adjacent storage cells 100 form a storage cell stack, and the orthogonal projections of the gate structures 1113 of the storage cells 100 in the storage cell stack onto the substrate 200 overlap with each other. The plurality of storage cell stacks include a first storage cell stack 111A and a second storage cell stack 112A, and the first storage cell stack 111A and the second storage cell stack 112A are adjacent to each other in a first horizontal direction to form a storage cell stack group 11A.

[0067] In one memory cell stack group 11A, the first gate 11131 of the first memory cell stack 111A is arranged opposite the first gate 11131 of the second memory cell stack 112A, and the gate structure 1113 further includes a conductor portion 1113B, which includes a first conductor portion 11133 formed integrally with the first gate 11131. When projected orthogonally onto the substrate 200, the first conductor portion 11133 is located on the side of the first gate 11131 away from the active layer 1111, and the first conductor portion 11133 is located at both horizontal ends of the first gate 11131.

[0068] In this embodiment, there is no particular limitation as to whether the orthogonal projections of the active layer 1111 and the gate insulating layer 1112 onto the substrate 200 overlap with each other.

[0069] As shown in Figures 2 and 7, the memory device 1000 has a plurality of memory cell stacks distributed horizontally on the substrate 200, among which there are at least two memory cell stacks adjacent in the first horizontal direction, which are a first memory cell stack 111A and a second memory cell stack 112A.

[0070] The first memory cell stack 111A and the second memory cell stack 112A are adjacent to each other in the first horizontal direction to form a memory cell stack group 11 A. That is, there are no other memory cell stacks between the first memory cell stack 111A and the second memory cell stack 112A.

[0071] The first gate 11131 of the first memory cell stack 111A is disposed opposite the first gate 11131 of the second memory cell stack 112A. That is, the first gates 11131 of the first memory cell stack 111A and the second memory cell stack 112A are located between the active layer 1111 of the first memory cell stack 111A and the active layer 1111 of the second memory cell stack 112A.

[0072] 2, in the memory cell 100, the gate structure 1113 further includes a conductor portion 1113B, and the conductor portion 1113B includes a first conductor portion 11133 formed integrally with the first gate 11131. In an orthogonal projection onto the substrate 200, the first conductor portion 11133 is arranged on a side of the first gate 11131 away from the active layer 1111 and is arranged at both ends of the first gate 11131 in the horizontal direction. However, this is not limitative. In some embodiments not shown, the first conductor portion 11133 is arranged at one end of the first gate 11131.

[0073] Specifically, the first gate 11131 in the embodiment of the present application is substantially C-shaped. As shown in Figure 2, the first gate 11131 extends along the active layer 1111, and the first conductor portion 11133 extends from both ends of the first gate 11131 away from the active layer 1111 along a first horizontal direction.

[0074] It should be noted that the present application does not limit the angle between the first gate 11131 and the first conductor portion 11133, and this angle may be an acute angle, an obtuse angle, a right angle, etc. The angles between different first gates 11131 and first conductor portions 11133 may be the same or different. In some embodiments, the first gates 11131 and the first conductor portions 11133 may be connected by transitioning in an arc shape. Furthermore, the embodiments of the present application do not particularly limit whether the gate structure 1113 includes a second gate 11132.

[0075] 1 and 2, the memory cell stack group 11A is repeatedly arranged in the first horizontal direction. In the embodiments of the present application, there is no particular limitation on whether the gate structure 1113 includes the second gate 11132.

[0076] 2 , in some embodiments, the gate body portion further includes a second gate 11132, which is the same as described above and will not be described again here. The conductor portion 1113B further includes a second conductor portion 11134 formed integrally with the second gate 11132, which, when projected orthogonally onto the substrate 200, is located on the side of the second gate 11132 away from the active layer 1111 and at both ends of the second gate 11132 in the horizontal direction. However, without being limited thereto, in some embodiments not shown, the second conductor portion 11134 is located at one end of the second gate 11132.

[0077] Specifically, the second gate 11132 in the embodiment of the present application is substantially "C" shaped. In the embodiment shown in Figure 2, the second gate 11132 extends along the active layer 1111, and the second conductor portion 11134 extends from both ends of the second gate 11132 away from the active layer 1111 along the first horizontal direction.

[0078] It should be noted that the present application does not limit the angle between the second gate 11132 and the second conductor portion 11134, and this angle may be an acute angle, an obtuse angle, a right angle, etc. The angles between different second gates 11132 and second conductor portions 11134 may be the same or different. In some embodiments, the second gates 11132 and the second conductor portions 11134 may be connected by transitioning in an arc shape.

[0079] When the memory cell stack groups 11A are repeatedly arranged in the first horizontal direction and the gate structure 1113 includes a second gate 11132 and a second conductor portion 11134 connected to the second gate 11132, a "C"-shaped gate electrode is formed between two adjacent memory cell stacks in the first horizontal direction. The gate electrode can be understood as the entirety formed by the first gate 11131 and the first conductor portion 11133, or the entirety formed by the second conductor portion 11134 and the second gate 11132. The second gate 11132 is arranged opposite to the second gate 11132, i.e., between two adjacent memory cell stack groups 11A in the first horizontal direction.

[0080] Continuing to refer to Figures 2 and 9, further, between the gate structures 1113 of at least one group of adjacent first memory cell stacks 111A and second memory cell stacks 112A, a first insulating layer 130, a second insulating layer 140 and a third insulating layer 150 are formed in sequence in the direction from the gate structure 1113 of the first memory cell stack 111A to the gate structure 1113 of the second memory cell stack 112A.

[0081] Among these, the first insulating layer 130 and the third insulating layer 150 are made of the same material, and the first insulating layer 130 and the third insulating layer 150 are in contact with the gate body portion 1113A of the first memory cell stack 111A and the gate body portion 1113A of the second memory cell stack 112A, respectively. The second insulating layer 140 is disposed between the conductor portion 1113B of the adjacent first memory cell stack 111A and second memory cell stack 112A, and is in contact with the conductor portion 1113B of the first memory cell stack 111A and the conductor portion 1113B of the second memory cell stack 112A.

[0082] A gap region is included between the active layer 1111 of the adjacent first memory cell stack 111A and the active layer 1111 of the adjacent second memory cell stack 112A. In both the first memory cell stack 111A and the second memory cell stack 112A, at least a portion of the gate structure 1113 is located within the gap region, and at least a portion of the gate structure 1113 includes at least a portion of the gate body portion 1113A and at least a portion of the conductor portion 1113B, and the portions of the gate structure 1113 located within the gap region are arranged opposite to each other.

[0083] 2, the memory cell 100 includes a first gate 11131, and a spacing region is included between the active layers 1111 of a group of adjacent first and second memory cell stacks 111A and 112A. In the first and second memory cell stacks 111A and 112A, the first gate 11131 is disposed in the spacing region, and the gate structure 1113 includes a first conductor portion 11131, in which: The first insulating layer 130 and the third insulating layer 150 may be formed in the same layer and may be made of the same material. The first insulating layer 130 and the third insulating layer 150 contact the gate body portion 1113A, i.e., the first insulating layer 130 and the third insulating layer 150 contact the first gate 11131 of the first memory cell stack 111A and the second memory cell stack 112A, respectively. The second insulating layer 140 is disposed between adjacent first conductor portions 11133 and contacts the first conductor portions 11133. In other words, the second insulating layer 140 separates the first conductor portions 11133 located in the spacing region.

[0084] However, the present application is not limited thereto, and in some embodiments, the storage cell 100 further includes a second gate 11132, and the second gate 11132 and the second conductor portion 11134 are disposed in a spacing region, and in the spacing region: The first insulating layer 130 and the third insulating layer 150 may be formed in the same layer and may be made of the same material. The first insulating layer 130 and the third insulating layer 150 contact the gate body portion 1113A. That is, the first insulating layer 130 and the third insulating layer 150 contact the second gate 11132 of the first memory cell stack 111A and the second memory cell stack 112A, respectively. The second insulating layer 140 is disposed between adjacent second conductor portions 11134 and contacts the second conductor portions 11134. That is, the second insulating layer 140 separates the second conductor portions 11134 located in the spacing region.

[0085] 2, in a pair of memory cell stacks adjacent in the first horizontal direction, i.e., the first memory cell stack 111A and the second memory cell stack 112A, the portions of the gate structures 1113 located in the gap region may be formed from the same material layer. For example, after forming a cylindrical conductive film layer extending vertically in the gap region, a vertical slit is formed to cut and separate the conductive film layer.

[0086] This cutting and separation may be performed by etching. Before etching, the hollow portion of the cylindrical conductive film layer is filled with an insulating material, and then an etching process is performed to form a vertical slit. The slit separates the conductive film layer into two spaced apart portions, which are respectively formed as the first gate 11131 and the first conductor portion 11133 or the second gate 11132 and the second conductor portion 11134 of the adjacent first and second memory cell stacks 111A and 112A of the group. The remaining insulating material contacts the gate body portion 1113A of the first and second memory cell stacks 111A and 112A, respectively, to form the first and third insulating layers 130 and 150. The conductor portions 1113B of the first memory cell stack 111A and the second memory cell stack 112A face each other across a vertical slit, which exposes the opposing conductor portions 1113B, and the first insulating layer 130 and the third insulating layer 150 can be completely or partially separated by this vertical slit (as shown in Figure 9), and the second insulating layer 140 fills this vertical slit and contacts the conductor portions 1113B.

[0087] The first insulating layer 130 and the third insulating layer 150 separate the gate body portions 1113A of two memory cells 100 adjacent in the first horizontal direction, and the second insulating layer 140 separates the conductor portions 1113B of two memory cells 100 adjacent in the first horizontal direction.

[0088] The first insulating layer 130 and the third insulating layer 150 can be formed in one process, so that SiO2, SiN x The same insulating material, such as TEOS, can be used. The materials of the first insulating layer 130 and the third insulating layer 150 can be the same as or different from the materials of the gate insulating layer 1112 and the insulating spacer layer 160, and are not particularly limited in the present application. The material of the second insulating layer 140 can be the same as or different from the materials of the first insulating layer 130 and the third insulating layer 150.

[0089] In some embodiments, the first insulating layer 130 and the third insulating layer 150 may be a single layer or a multi-layer structure, and the second insulating layer 140 may be a single layer or a multi-layer structure, which are not particularly limited in the present application.

[0090] Furthermore, the first insulating layer 130 and the third insulating layer 150 can be completely or partially separated by this vertical slit. Specifically, in an orthogonal projection onto the substrate 200, the first insulating layer 130 and the third insulating layer 150 are arranged separately on both sides of the second insulating layer 140 (FIG. 2), or the first insulating layer 130 and the third insulating layer 150 are partially connected (FIG. 9).

[0091] 9, the above-mentioned slit can also be formed only between two opposing conductor portions 1113B (two first conductor portions 11133 or two second conductor portions 11134) in two memory cells 100 adjacent to each other in the second horizontal direction. That is, the slit cuts the originally connected gate structures 1113 in the two memory cells 100 adjacent to each other in the first horizontal direction and extends partially into the insulating material. That is, the first insulating layer 130 and the third insulating layer 150 are partially connected.

[0092] Even when the first insulating layer 130 is partially connected to the third insulating layer 150, it is understood that the first insulating layer 130, the second insulating layer 140, and the third insulating layer 150 are arranged in sequence between the gate structures 1113 of adjacent first and second memory cell stacks 111A and 112A of this group, from the gate structure 1113 of the first memory cell stack 111A to the gate structure 1113 of the second memory cell stack 112A.

[0093] Furthermore, between the gate structures 1113 of adjacent first memory cell stacks 111A and second memory cell stacks 112A of the group (i.e., at least one group), in orthogonal projection onto the substrate 200, a first insulating layer 130 is formed in the area surrounded by the gate body portion 1113A, conductor portion 1113B, and second insulating layer 140 of the first memory cell stack 111A, and the edge of the first insulating layer 130 extending along the conductor portion 1113B of the first memory cell stack 111A is also adjacent to the second insulating layer 140, and a third insulating layer 150 is formed in the area surrounded by the gate body portion 1113A, conductor portion 1113B, and second insulating layer 140 of the second memory cell stack 112A, and the edge of the third insulating layer 150 extending along the conductor portion 1113B of the second memory cell stack 112A is also adjacent to the second insulating layer 140.

[0094] Referring to FIG. 16, vertical slits for cutting and separating the conductive film are formed by etching, and the etching can include a first step of anisotropic etching and a second step of wet etching.

[0095] The first anisotropic etching step forms pre-trenches 10A that penetrate the conductive film and the insulating material filling the hollow portions of the cylindrical conductive film layer. The pre-trenches 10A essentially cut and separate the conductive film, and also pattern the insulating material filling the hollow portions of the cylindrical conductive film layer into the first insulating layer 130 and the third insulating layer 150.

[0096] The first insulating layer 130 is formed in a space surrounded by the pre-trench 10A and the conductive film on the first memory cell stack 111A side, and the portion of the conductive film extending along the active layer 1111 of the first memory cell stack 111A is formed as the gate body portion 1113A of the first memory cell stack 111A, and the end face of the first insulating layer 130 away from the gate body portion 1113A of the first memory cell stack 111A and the end face of the conductive film on the first memory cell stack 111A side away from its gate body portion 1113A form a continuous surface, and this continuous surface is exposed to the pre-trench 10A.

[0097] Similarly, the third insulating layer 150 is formed in a space surrounded by the pre-trench 10A and the conductive film on the second memory cell stack 112A side, and the portion of the conductive film extending along the active layer 1111 of the second memory cell stack 112A is formed as the gate body portion 1113A of the second memory cell stack 112A, and the end face of the third insulating layer 150 away from the gate body portion 1113A of the second memory cell stack 112A and the end face of the conductive film on the second memory cell stack 112A away from its gate body portion 1113A form a continuous surface, and this continuous surface is exposed to the pre-trench 10A.

[0098] In order to completely cut and separate the conductive film and avoid short circuits between the conductor portions 1113B of adjacent first memory cell stacks 111A and second memory cell stacks 112A of this group, a second step of wet etching is performed to selectively etch the conductive film exposed by the pre-trenches 10A to form the gate structures 1113 of the first memory cell stacks 111A and second memory cell stacks 112A.

[0099] Compared to the previous continuous surface, the end surface of the conductive film exposed by the pre-trench 10A is "set back" by wet etching, exposing the surfaces of the first insulating layer 130 and the third insulating layer 150 that were originally in contact with the conductive film, and the pre-trench 10A is expanded to form a slit for embedding the second insulating layer 140, so that the exposed surface is formed in contact with the second insulating layer 140 (as shown in Figure 16).

[0100] Therefore, when projected orthogonally onto the substrate 200, the side of the first insulating layer 130 extending along the conductor portion 1113B of the first memory cell stack 111A is also adjacent to the second insulating layer 140, and the side of the third insulating layer 150 extending along the conductor portion 1113B of the second memory cell stack 112A is also adjacent to the second insulating layer 140.

[0101] The second insulating layer 140 may be an insulating material layer or an air gap having an insulating function, and the present application does not particularly limit the composition of the second insulating layer 140. In a preferred embodiment, as shown in Fig. 2, the second insulating layer 140 separates the first insulating layer 130 and the third insulating layer 150 as a whole, so that the size of the slit where the second insulating layer 140 is located is increased, which reduces the difficulty of the process.

[0102] Furthermore, the second insulating layer 140 comprises a low dielectric constant (Low K) material, i.e., the second insulating layer 140 can be formed of a material with a dielectric constant of less than 3.9, which helps reduce parasitic capacitance between transistors, including reducing coupling between the gate structures 1113 of two adjacent memory cells 100 in the first horizontal direction.

[0103] In particular, in this embodiment, the gate structures 1113 of two adjacent memory cells 100 in the first horizontal direction include conductor portions 1113B, and the distance between the nearest conductor portions 1113B of the two adjacent memory cells 100 in the first horizontal direction is smaller than the distance between the nearest gate body portions 1113A. Therefore, the material selected to design the second insulating layer 140 includes a low-dielectric-constant material, which can more significantly reduce the coupling between the gate structures 1113 of the two adjacent memory cells 100 in the first horizontal direction.

[0104] Furthermore, based on the above technical solutions, the transistor in the embodiments of the present application can be a junctionless field effect transistor, so there is no need to pattern dope the source and drain of the transistor, which simplifies the process flow and reduces the manufacturing cost.

[0105] In the embodiment of the present application, the active layer 1111 is parallel to the insulating surface 210, i.e., the active layer 1111 is perpendicular to the vertical direction, and the material thereof includes polysilicon, preferably the material thereof includes N-type doped polysilicon, but is not limited thereto, and the specific material of the active layer 1111 can be set according to actual needs.

[0106] Furthermore, in the embodiment of the present application, the transistor is a junctionless transistor, i.e., the active layer 1111 also includes a channel region 11113 located between a source terminal 11111 and a drain terminal 11112, and the source terminal 11111, the drain terminal 11112, and the channel region 11113 have the same conductivity type. In the memory cell 100, the channel region 11113 is arranged corresponding to a first gate 11131 and a second gate 11132. That is, the channel region 11113 is located between the first gate 11131 and the second gate 11132, and the width of the channel region 11113 in the direction from the first gate 11131 to the second gate 11132 is less than 40 nm.

[0107] If the active layer 1111 is made of polysilicon or N-type doped polysilicon, the width of the channel region 11113 is less than 40 nm. If the active layer 1111 is made of non-polysilicon, the width of the channel region 11113 can have a different range.

[0108] Of these, the width of the channel region 11113 in the direction from the first gate 11131 to the second gate 11132 refers to the distance in the first horizontal direction between two side surfaces of the channel region 11113. By making the width of the channel region 11113 in the direction from the first gate 11131 to the second gate 11132 less than 40 nm, the transistor can be made into a memory cell 100 with a 1T0C structure, making it possible to read and write from and to the memory cell 100.

[0109] For example, a method for read and write operations is proposed for the polysilicon memory cell 100 proposed in the embodiments of the present application, which includes one junctionless transistor and the material of the active layer 1111 includes N-type doping. Referring to Figure 20, the method includes the following steps:

[0110] Applying a negative voltage to the gate structure 1113 and a positive voltage to the drain terminal via the bit line BL accumulates holes in the channel region, lowering the transistor's threshold voltage and completing a "write 1" operation. Applying a positive voltage to the gate structure 1113 and a negative voltage to the drain terminal via the bit line BL causes carrier recombination in the channel region, restoring the transistor's threshold voltage and completing a "write 0" operation. Applying a read voltage to the gate structure 1113 generates drain currents of different magnitudes due to the difference in threshold voltages caused by the write operation, allowing the "0" and "1" states to be distinguished during a read operation.

[0111] For example, the width of the channel region 11113 may be 30 nm, 20 nm, 10 nm, etc. Furthermore, the cross-sectional shape of the channel region 11113 perpendicular to the second horizontal direction may be a geometric shape such as a circle, a square, a rectangle, a hexagon, an octagon, etc., but is not particularly limited in the present application.

[0112] The gate insulating layer 1112 is disposed between the transistor gate structure 1113 and the active layer 1111 (channel region 11113). The material thereof may include, but is not limited to, SiO2 or a high-k material. Exemplarily, the material of the active layer 1111 includes silicon, such as polysilicon, N-type or P-type doped polysilicon. The gate insulating layer 1112 can be formed by oxidizing a surface containing the silicon-containing material. The unoxidized silicon-containing material layer forms the active layer 1111, so that the gate insulating layer 1112 is formed only on the sidewalls of the active layer 1111. The width of the channel region 11113 can be smaller than at least one of the source terminal 11111 and the drain terminal 11112, but is not limited to this.

[0113] As shown in FIG. 7, in some embodiments, an insulating material layer can be deposited on the surface of the active layer 1111 to form a gate insulating layer 1112, so that the gate insulating layers 1112 of multiple memory cells 100 are formed as a single structure.

[0114] Furthermore, in one embodiment of the present application, in gate structure 1113: The first gate 11131 and the second gate 11132 are electrically connected to realize synchronous control of the first gate 11131 and the second gate 11132 in the gate structure 1113; and / or The first gate 11131 and the second gate 11132 are independently controlled, i.e., the first gate 11131 and the second gate 11132 are electrically connected to an external circuit, respectively, to realize different control of the gate structure 1113, thereby improving the charge retention capability of the DRAM storage cell 100 with the 1T0C structure; and / or The first gate 11131 and the second gate 11132 are controlled independently, and the first gate 11131 and the second gate 11132 do not completely overlap on their opposing surfaces. That is, in the memory cell 100, the projection surfaces of the first gate 11131 and the second gate 11132 on the active layer 1111 do not completely overlap. This improves the charge retention capability of the 1T0C structure DRAM memory cell 100.

[0115] The first gate 11131 and the second gate 11132 are electrically connected, and the electrical connection between them can be achieved by providing a conductive connection structure on the top and / or bottom of the first gate 11131 and the second gate 11132, but this is not limited to this and can be determined according to the situation as long as the two are electrically connected.

[0116] The first gate 11131 and the second gate 11132 do not completely overlap on the opposing surfaces; for example, the length of the first gate 11131 is greater than the length of the second gate 11132, or the projections of the first gate 11131 and the second gate 11132 onto the active layer 1111 are offset in the horizontal direction, but this application is not particularly limited thereto.

[0117] In the memory device 1000 of the embodiment of the present application, a plurality of DRAM memory cells 100 having a 1T0C structure are repeatedly arranged along a first horizontal direction, a second horizontal direction, and a vertical direction, and the memory cells 100 have a simple structure and high memory density. The memory capacity can be increased by further increasing the number of stacked layers as needed. Therefore, the transistor can be a junctionless field-effect transistor, and there is no need to perform patterned ion implantation into the active layer 1111, thereby reducing process difficulty and saving manufacturing costs. In the transistor of the memory cell 100, the first gate 11131 and the second gate 11132 of the gate structure 1113 are arranged on both sides of the active layer 1111 in the horizontal direction, which can improve gate controllability over the transistor channel.

[0118] The embodiment of the present application further proposes a manufacturing method of the storage device 1000, which is used to manufacture the storage device 1000 in the above-mentioned embodiment. Referring to Figure 10, the manufacturing method of the storage device 1000 includes the following steps.

[0119] Specifically, referring to FIG. 11, in step S100, a substrate 1A is prepared.

[0120] In some embodiments, substrate 1A may be substrate 200. The contents of substrate 1A may refer to the description of substrate 200 in the embodiment of storage device 1000 above, and will not be repeated here. However, without being limited thereto, in other embodiments, the substrate may be a temporary substrate.

[0121] Continuing to refer to FIG. 11, in step S200, a plurality of film layer pairs 1 stacked along the vertical direction are provided on a substrate 1A, and each film layer pair 1 includes a semiconductor material layer 2 and a first insulating dielectric layer 3 arranged in sequence along the vertical direction.

[0122] A plurality of film layer pairs 1 are stacked along the vertical direction to form a stack structure, i.e., the stack structure includes first insulating dielectric layers 3 and semiconductor material layers 2 alternately stacked along the vertical direction.

[0123] The semiconductor material layer 2 and the first insulating dielectric layer 3 can be formed by thin film deposition methods such as chemical vapor deposition (CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD).

[0124] It will be appreciated that any suitable materials and deposition processes may be used to form the first insulating dielectric layer 3 and the semiconductor material layer 2 described above.

[0125] Among these, the material of the semiconductor material layer 2 can be a material containing silicon, such as a semiconductor material such as N-type polysilicon, but is not limited to this, and oxide semiconductor materials can also be used for the semiconductor material layer 2, and is determined according to specific circumstances.

[0126] Taking an oxide semiconductor as an example, the semiconductor material layer 2 can be an indium gallium zinc oxide (IGZO) layer. Note that examples of metal oxide materials include ITO, IWO, ZnO, x , InO x , In2O3, InWO, SnO2, TiOx, InSnO x , Zn x O y N z , Mg x Zn y O z , In x Zn y O z , In x Ga y Zn z O a , Zr x In y Zn z O a , Hf x In y Zn z O a , Sn x Iny Zn z O a , Al x Sn y In z Zn a O d , Si x In y Zn z O a , Zn x Sn y O z , Al x Zn y Sn z O a , Ga x Zn y Sn z O a , Zr x Zn y Sn z O a , InGaSiO, etc., and can be selected appropriately depending on the actual situation.

[0127] In one example, the material of the first insulating dielectric layer 3 may be an insulating material such as SiO2, SiN x may be.

[0128] In one embodiment, the stacked structure may be a stacked structure of SiO2 layer (first insulating dielectric layer 3) / N-type polysilicon layer (semiconductor material layer 2).

[0129] 12 and 13, in step S300, the plurality of film layer pairs 1 are etched to form a plurality of first slits 4 repeatedly arranged along a first horizontal direction and a second horizontal direction, the first horizontal direction intersecting the second horizontal direction, the first slits 4 penetrating the plurality of film layer pairs 1 along a vertical direction, and a second insulating dielectric layer 5 is formed to fill the first slits 4. In the second horizontal direction, the semiconductor material layer 2 on one side of the first slits 4 is formed into a bit line structure 120, the bit line structure 120 including a plurality of bit lines, each extending along the first horizontal direction, and a common source structure is formed on the side of the first slits 4 away from the bit line structure 120.

[0130] Here, the first horizontal direction and the second horizontal direction are the same as those described above, and therefore will not be repeated here.

[0131] In the embodiment of the present application, the laminate structure formed by the multiple film layer pairs 1 is patterned to form first slits 4 penetrating the laminate structure along the vertical direction. That is, the first slits 4 vertically penetrate each semiconductor material layer 2 and the first insulating dielectric layer 3. The first slits 4 can be formed by etching downward from the top semiconductor material layer 2 in a direction perpendicular to the substrate 1A using, for example, an anisotropic etching process (e.g., a dry etching process such as an ion etching process or a reactive ion etching process, a wet etching process, or an etching process combining dry etching and wet etching). A plurality of first slits 4 are present, and the multiple first slits 4 are repeatedly arranged along the first horizontal direction and the second horizontal direction. That is, the multiple first slits 4 are distributed in an array in the laminate structure. As shown in FIG. 12 , the multiple first slits 4 are arranged in a row along the first horizontal direction, and the first slits 4 in two adjacent rows in the second horizontal direction are symmetrically distributed.

[0132] As shown in FIG. 12, the semiconductor material layer 2 between adjacent first slits 4 in the first horizontal direction is used to fabricate an active layer 1111, and in the second horizontal direction, the semiconductor material layer 2 on one side of the first slit 4 is formed into a bit line structure.

[0133] It is understood that of the portion of the semiconductor material layer 2 used to fabricate the active layer 1111, one end connected to the bit line structure is used to form a drain terminal, and one end of the portion of the semiconductor material layer 2 used to fabricate the active layer 1111, away from the bit line connected thereto, is used to form a source terminal, which is used to connect a common source structure.

[0134] The method for manufacturing the memory device 1000 further includes the step of fabricating a common source structure. Optionally, the common source is formed on a side of the first slit 4 away from the bit line structure. It is understood that the common source structure is electrically connected to the source terminal.

[0135] 13, the first slits 4 are then filled with a second insulating dielectric layer 5, and the material of the second insulating dielectric layer 5 may be the same as or different from the material of the first insulating dielectric layer 3. Exemplarily, the material of the second insulating dielectric layer 5 may be SiO2.

[0136] 14, in step S400, the second insulating dielectric layer 5 in the first slits 4 is etched to form a plurality of first trenches 6 repeatedly arranged in a first horizontal direction and a second horizontal direction, the first trenches 6 penetrate the second insulating dielectric layer 5 along the vertical direction, the first trenches 6 correspond to the first slits 4 one by one, the two opposite sidewalls of the first trenches 6 in the first horizontal direction both expose the semiconductor material layer 2, and when projected orthogonally onto the substrate 1A, the two opposite sidewalls of the first trenches 6 in the second horizontal direction extend into the first slits 4.

[0137] Specifically, the first trenches 6 penetrate the second insulating dielectric layer 5 along the vertical direction and are located within each first slit 4, and the first trenches 6 expose the semiconductor material layer 2 and the first insulating dielectric layer 3 between two first trenches 6 adjacent in the first horizontal direction. When orthogonally projected onto the substrate 1A, two opposite sidewalls of the first trenches 6 in the first horizontal direction may overlap the sidewalls of the first slits 4. It will be understood that the semiconductor material layer 2 between two first trenches 6 adjacent in the first horizontal direction is used to form a channel region 11113.

[0138] In an orthogonal projection onto the substrate 1A, the sidewall of the first trench 6 on the opposite side in the second horizontal direction is contained within the first slit 4. It is understood that a second insulating dielectric layer 5 exists between the first trench 6 and the bit line structure, and that a second insulating dielectric layer 5 is also formed between the first trench 6 and the common source structure to be formed. The second insulating dielectric layer 5 exposes the channel region of the active layer 1111 and can cover the source terminal and the drain terminal.

[0139] In subsequent steps, the first trench 6 is used to form the gate structure 1113, so by controlling the size of the first trench 6, the length of the gate structure 1113 that will later be formed in the first trench 6, i.e., the length the gate body portion extends horizontally along the active layer 1111, can be controlled.

[0140] In the embodiments of the present application, the etching process can be a dry etching, a wet etching, or a combination of a dry etching and a wet etching process.

[0141] Specifically, referring to Figures 15 and 16, in step S500, a gate material layer 7 is formed on the entire sidewall of the first trench 6, a gate insulating material layer 8 is formed between the gate material layer 7 and the surface of the semiconductor material layer 2 exposed by the first trench 6, and a third insulating dielectric layer 9 is filled in the first trench 6.

[0142] Filling the first trench 6 with the third insulating dielectric layer 9 is understood to mean filling the space surrounded by the gate material layer 7 with the third insulating dielectric layer 9 .

[0143] Among them, the gate material layer 7 is used to form the gate structure 1113 , and the gate insulating material layer 8 is used to form the gate insulating layer 1112 .

[0144] 15, the gate insulating material layer 8 is formed on at least the surface of the semiconductor material layer 2 exposed by the first trench 6. In one embodiment, the semiconductor material layer 2 includes silicon, such as N-type doped polysilicon, and the gate insulating material layer 8 is obtained by oxidizing the semiconductor material layer 2, with the remaining semiconductor material layer 2 being formed as the channel region 11113. Therefore, as shown in FIGS. 4 and 15, the gate insulating material layer 8 is formed only on the surface of the active layer exposed by the first trench 6. Furthermore, since the semiconductor material layer 2 consumes a certain thickness, the width of the channel region 11113 to be formed later can be smaller than the width of the source terminal 11111 and the drain terminal 11112 (not shown). In another embodiment, the gate insulating material layer 8 is deposited on the entire sidewall of the first trench 6, and the formed memory cell 100 is as shown in FIG. 3.

[0145] Optionally, the gate material layer 7 is disposed on the entire sidewall of the first trench 6, for example, but not limited to, in the shape of a vertical cylinder. In some embodiments, the gate material layer 7 may have the shape of multiple rings that are vertically stacked and spaced apart from each other, depending on the specific situation. The manufacturing process thereof may be a deposition process commonly used in the art.

[0146] Furthermore, the method for manufacturing the gate material layer 7 may include the step of depositing a conductive layer on the entire inner wall of the first trench 6, and removing the portion of the conductive layer located at the bottom of the first trench 6. Removal of the portion of the conductive layer located at the bottom of the first trench 6 may be achieved by anisotropic etching.

[0147] The third insulating dielectric layer 9 may be formed by deposition, i.e., after forming the gate material layer 7 on the entire sidewall of the first trench 6, an insulating material is deposited in the remaining first trench 6 surrounded by the gate material layer 7 to form the third insulating dielectric layer 9.

[0148] The material of the third insulating dielectric layer 9 may be the same as or different from the material of the first insulating dielectric layer 3 and the material of the second insulating dielectric layer 5. Preferably, the material of the third insulating dielectric layer 9 is the same as the material of the first insulating dielectric layer 3 and the material of the second insulating dielectric layer 5, i.e., the material of the third insulating dielectric layer 9 is SiO2 or SiN x may be.

[0149] Furthermore, the material of the conductor layer may be the same as or different from the material of the semiconductor material layer 2. In one embodiment of the present application, the material of the conductor layer is different from the material of the semiconductor material layer 2, and the conductor layer may be tungsten (W), titanium nitride (TiN), etc.

[0150] Specifically, referring to FIG. 16, in step S600, the gate material layer 7 is etched to form a plurality of second trenches 10 repeatedly arranged along a first horizontal direction and a second horizontal direction, and the second trenches 10 penetrate the gate material layer 7, thereby forming the gate material layer 7 into first gate structures 11 and second gate structures 12 spaced apart in the first horizontal direction.

[0151] The etching method includes at least anisotropic etching, and in order to reduce the difficulty of the etching process, preferably, in the process of etching the gate material layer 7 to form the second trench 10, a portion of the third insulating dielectric layer 9 is also etched. That is, the second trench 10 also penetrates the third insulating dielectric layer 9. That is, the second trench cuts the third insulating dielectric layer 9 into the second insulating layer and the third insulating layer, which are partially connected.

[0152] Preferably, a second trench 10 cuts through the third insulating dielectric layer 9 to form spaced apart second and third insulating layers.

[0153] Preferably, in the process of etching the gate material layer 7 to form the second trench 10, a portion of the second insulating dielectric layer 5 is also etched. That is, the second trench 10 also penetrates the second insulating dielectric layer 5. This can further reduce the difficulty of the etching process.

[0154] In the embodiment of the present application, the second trench 10 extending along the second horizontal direction and penetrating the gate material layer 7 in the vertical direction is understood to mean that the second trench 10 cuts the gate material layer 7 into two opposing parts in the first horizontal direction, so that the gate material layer 7 is formed into a first gate structure 11 and a second gate structure 12 spaced apart in the first horizontal direction.

[0155] It is understood that the first gate structure 11 and the second gate structure 12 belong to two storage cells adjacent in the first horizontal direction, respectively.

[0156] Of these, after etching is completed, the remaining third insulating dielectric layer 9 is located in the space surrounded by the second trench 10 and the first gate structure 11 and the space surrounded by the second trench 10 and the second gate structure 12, respectively, to form the second insulating layer and the third insulating layer. That is, during the process of etching the second trench 10, the third insulating dielectric layer 9 covers and protects the portions of the first gate structure 11 and the second gate structure 12 that extend along the surface of the semiconductor material layer 2 exposed by the first trench 6.

[0157] In the etching for forming a hole or trench penetrating the stacked structure, anisotropic etching such as dry etching is usually employed, and it is understood that the greater the number of stacked layers in the stacked structure, the greater the aspect ratio of the formed hole or trench, making the etching process more difficult. As shown in the examples of the present application, when the aspect ratio of the second trench 10 is high, there is a risk that anisotropic dry etching will not be able to completely cut through the gate material layer 7, which may result in a short circuit between the first gate structure 11 and the second gate structure 12, resulting in a reduced yield.

[0158] In this regard, the etching of the gate material layer 7 in step S600 can be realized by step S610.

[0159] In step S610, portions of the gate material layer 7 located on two opposite sidewalls of the first trench 6 in the second horizontal direction are anisotropically etched to form pre-trenches 10A. The pre-trenches 10A penetrate the gate material layer 7 without exposing portions of the gate material layer 7 located on two opposite sidewalls of the first trench 6 in the first horizontal direction. The gate material layer 7 exposed by the pre-trenches 10A is wet-etched to form a first gate structure 11 and a second gate structure 12.

[0160] The pre-trench 10A basically cuts the gate material layer 7 to form two parts facing each other in a first horizontal direction, and then performs a wet etching step to form the gate material layer 7 into the first gate structure 11 and the second gate structure 12 spaced apart in the first horizontal direction, thereby reducing the risk of short circuits and the difficulty of the etching process. However, the process for etching the gate material layer 7 exposed by the pre-trench 10A to form the first gate structure 11 and the second gate structure 12 may be any other isotropic etching process commonly used in the art and may be determined according to specific circumstances.

[0161] A portion of the gate material layer 7 located on two opposite sidewalls of the first trench 6 in the second horizontal direction is anisotropically etched to form a pre-trench 10A, and the pre-trench 10A does not expose a portion of the gate material layer 7 located on two opposite sidewalls of the first trench in the first horizontal direction. That is, the pre-trench 10A overlaps with two opposite sides of the gate material layer 7 in the second horizontal direction when orthogonally projected onto the substrate 1A, and is spaced apart from the two opposite sides of the gate material layer 7 in the first horizontal direction. Therefore, when wet etching is performed, the etchant can only contact the ends of the gate material layer 7 exposed by the pre-trench 10A.

[0162] Preferably, the pre-trench 10A also penetrates the third insulating dielectric layer 9, and the wet etch selectively etches the gate material layer 7 without etching the third insulating dielectric layer 9.

[0163] Specifically, a pre-trench 10A is formed by anisotropic etching, and the pre-trench 10A penetrates the gate material layer 7 and the third insulating dielectric layer 9. The pre-trench 10A basically cuts and separates the gate material layer 7, and at the same time, the third insulating dielectric layer 9 filled in the hollow portion of the cylindrical gate material layer 7 is patterned into the second insulating layer and the third insulating layer.

[0164] The second insulating layer and the third insulating layer are each formed in a space surrounded by the pre-trench 10A and the gate material layer 7, which is basically cut into two parts and separated. Portions of the gate material layer 7 extending along two opposite sides of the first slit 4 in the first horizontal direction are formed as gate body portions. The end faces of the second insulating layer and the third insulating layer, which are in contact with the gate material layer 7 and are away from the gate body portion, form a continuous surface with the end face of the gate material layer 7 that is away from the gate body portion. As shown in FIG. 16, this continuous surface is exposed to the pre-trench 10A.

[0165] In order to completely cut and separate the gate material layer 7 and avoid a short circuit between the first gate structure 11 and the second gate structure 12, a second step of wet etching is carried out to selectively etch the gate material layer 7 exposed by the pre-trenches 10A to form the first gate structure 11 and the second gate structure 12.

[0166] Compared to the previous continuous surface, the end surface of the gate material layer 7 exposed by the pre-trench 10A is "set back" by wet etching, exposing the surfaces of the second and third insulating layers that were originally in contact with the gate material layer 7, and the pre-trench 10A is expanded to form the second trench 10, as shown in Figure 16.

[0167] Preferably, the wet etching does not etch the portions of the first gate structure 11 and the second gate structure 12 that extend along the surface of the semiconductor material layer 2 exposed by the first trench 6. Specifically, the degree of wet etching of the gate material layer 7 can be achieved by controlling the wet etching time, thereby reducing the risk of short circuits without affecting the gate length.

[0168] Referring to Figures 2, 14, and 19, the first gate structure 11 and the second gate structure 12 each include a portion extending along the surface of the semiconductor material layer 2 exposed by the first trench 6, i.e., a gate body portion 1113A, and a portion located on the side of the gate body portion 1113A away from the active layer 1111, i.e., a conductor portion 1113B, and the conductor portion 1113B is located at both horizontal ends of the gate body portion 1113A.

[0169] As a result, the semiconductor material layer 2 located between two first slits 4 adjacent in the first horizontal direction is formed as an active layer 1111, and the portion of the gate insulating material layer 8 located between the gate structure 1113 and the active layer 1111 is formed as a gate insulating layer 1112. The active layer 1111, the gate insulating layer 1112, and the gate structure 1113 form a memory cell 100 of the memory device 1000. One end of the active layer 1111 is connected to a bit line, and the other end is connected to a common source structure. It is understood that the gate structure 1113 is either the first gate structure 11 or the second gate structure 12 described above, and that the first gate structure 11 and the second gate structure 12 belong to two memory cells 100.

[0170] Specifically, referring to FIG. 17, in step S700, the second trench 10 is filled with a fourth insulating dielectric layer 13.

[0171] The fourth insulating dielectric layer 13 is formed as the first insulating layer.

[0172] 2 in the embodiment of the memory device 1000. The fourth insulating dielectric layer 13 insulates and separates the gate structures 1113 of transistors adjacent in the first horizontal direction.

[0173] In addition, the fourth insulating dielectric layer 13 used to form the first insulating layer can be an insulating material layer or an air gap, and the present application does not particularly limit the compositions of the fourth insulating dielectric layer 13 and the first insulating layer.

[0174] Furthermore, the material of the fourth insulating dielectric layer 13 includes a low dielectric constant material.

[0175] Illustratively, the fourth insulating dielectric layer 13 may be formed of a material with a dielectric constant of less than 3.9 to help reduce parasitic capacitance between transistors.

[0176] The material of the fourth insulating dielectric layer 13 may be the same as or different from the material of the first insulating dielectric layer 3 to the third insulating dielectric layer 9. Furthermore, the material of the fourth insulating dielectric layer 13 may be different from the material of the first insulating dielectric layer 3 to the third insulating dielectric layer 9.

[0177] In the embodiment of the present application, the material of the third insulating dielectric layer 9 is SiO2 or SiN x The material of the fourth insulating dielectric layer 13 may be a low dielectric constant material.

[0178] In this way, the second insulating layer, the first insulating layer, and the third insulating layer are provided between two gate bodies adjacent in the first horizontal direction.

[0179] It should be noted that the second insulating layer here is the first insulating layer 130 in the above-described embodiment of the storage device 1000, and the third insulating layer is the third insulating layer 150 in the above-described embodiment of the storage device 1000. It is understood that the second insulating layer and the third insulating layer are formed after the third insulating dielectric layer 9 is patterned.

[0180] Furthermore, in one embodiment of the present application, two first trenches 6 adjacent to each other in the first horizontal direction have two surfaces facing each other in the first horizontal direction that do not completely overlap each other.

[0181] Two first trenches 6 adjacent in the first horizontal direction can be used to form a gate structure 1113 in the same transistor, and the gate structure 1113 includes a first gate 11131 and a second gate 11132, so that the two opposing surfaces of the two first trenches 6 adjacent in the first horizontal direction do not completely overlap, and the first gate 11131 and the second gate 11132 that do not completely overlap on the opposing surfaces can be formed. The memory cell 100 includes a transistor, and the transistor includes a first gate 11131 and a second gate 11132 that are opposed and do not completely overlap, as in the previous embodiment, and will not be repeated here.

[0182] In some embodiments, a method for forming a common source structure includes the following steps. In step S310, a common source 110 is formed, where the common source 110 includes a plurality of vertical contact elements.

[0183] The embodiment in which the common source 110 includes a vertical contact element is the same as the embodiment of the storage device 1000 described above, and will not be repeated here.

[0184] In a preferred embodiment of the present application, the common source 110 is a plate-like structure extending along a first horizontal direction, i.e., parallel to the bit line structure 120, and the common source 110 passes vertically through the stacked structure and is connected to each semiconductor material layer 2.

[0185] Based on the above, a method for forming a common source structure includes etching a plurality of film layer pairs 1 to form a plurality of third slits repeatedly arranged in a second horizontal direction; the third slits extend along a first horizontal direction and vertically penetrate the plurality of film layer pairs 1; filling the third slits with a conductive material to form a common source 110; and the common source 110 is connected to vertically adjacent semiconductor material layers 2, or the common source 110 is connected to each semiconductor material layer 2.

[0186] 18 and 20 , the semiconductor material layer 2 and the fourth insulating dielectric layer 13 are etched to form a third trench 14. The third trench 14 extends along a first horizontal direction and penetrates the semiconductor material layer 2 and the fourth insulating dielectric layer 13. The third trench 14 is filled with a conductive layer 15 to form a common source 110.

[0187] Here, the embodiment in which the common source 110 includes a plate-like structure is the same as the embodiment of the storage device 1000 described above, and therefore will not be repeated here.

[0188] It should be noted that although the contents of the manufacturing method of the memory device in this embodiment are described according to the order of the method steps, in a specific implementation, the order of some method steps can be changed, for example, the step of fabricating the common source structure can be performed after step S200 and before any step, and can be implemented according to specific needs.

[0189] In one embodiment, the method for forming the common source structure includes forming the semiconductor material layer 2 on either side of the first slit 4 in the second horizontal direction a bit line structure 120 and a common source 110, respectively.

[0190] The embodiment in which the common source 110 includes horizontal wiring extending along the first direction is similar to that described above and will not be repeated here.

[0191] In addition to the beneficial effects of the memory device 1000 embodiment described above, the memory device manufacturing method according to the present application can reduce the risk of short circuits and significantly improve the yield of the memory device 1000 without affecting the gate length.

[0192] In the above-described embodiment, the present application proposes a 3D 1T0C DRAM memory device, which has a C-shaped gate electrode to reduce the risk of short circuits. However, in a semiconductor device including a 3D stack in which repeating cells have horizontal channels and vertical gates, fabricating a C-shaped gate can reduce short circuits. Therefore, the present application also proposes the following semiconductor device embodiment.

[0193] A semiconductor device according to an embodiment of the present application includes a substrate and a transistor stack including a plurality of transistors vertically stacked on the substrate, the transistors including an active layer and a gate electrode, the active layer extending along a horizontal direction, the gate electrode being located on a sidewall of the active layer, all of the gate electrodes in the transistor stack overlapping each other when orthogonally projected onto the substrate, the gate electrode including an integrated gate body portion and a conductor portion, the gate body portion being disposed along the length direction of the active layer, the conductor portion being located on a side of the gate body away from the active layer, and the conductor portion being located at both ends of the gate body portion in the horizontal direction.

[0194] Here, the structures of the gate body, conductor, gate electrode, and transistor stack are similar to the gate body, conductor, gate structure, and memory cell stack including only one transistor in the memory device embodiment described above, and therefore will not be repeated here. In some embodiments not shown, the conductor portion may be located at one horizontal end of the gate body portion.

[0195] In the semiconductor device of the embodiment of the present application, the transistor included in the repeat cell is not particularly limited and can be a JFET or a MOSFET. However, it should be noted that if the transistor is a MOSFET, the transistor also includes a gate insulating layer, and the gate insulating layer is located between the gate body and the active layer. It is understood that the repeat cell can include structures other than the transistors described in the above embodiment.

[0196] In the embodiment of the present application, there are a plurality of transistor stacks, and the plurality of transistor stacks are distributed in a horizontal direction on a substrate, and the gate electrodes of two adjacent transistor stacks are arranged opposite to each other in the horizontal direction perpendicular to the extending direction of the gate body portions. It can be understood that the gate electrodes of two adjacent transistor stacks are arranged opposite each other, i.e., the gate electrodes of the two transistor stacks are located between the active layers of the two transistor stacks and are arranged toward each other, with the gate body portions and conductor portions facing each other.

[0197] For example, the extension direction of the active layer and the gate body is the second horizontal direction, and the horizontal direction perpendicular to the extension direction of the gate body is the first horizontal direction, i.e., the gate electrodes of two transistor stacks adjacent to each other in the first horizontal direction are arranged opposite each other.

[0198] In the embodiment of the present application, the gate electrodes of adjacent transistor stacks arranged opposite each other are "C" shaped. Forming the gate electrodes of the transistor stacks into a "C" shape can be specifically achieved by a method including step S610 of the above-described memory device manufacturing method, namely, forming a pre-trench by etching so that the gate material layers integrally fabricated to form the gate electrodes of the adjacent transistor stacks are essentially cut, and then performing wet etching to form the gate electrodes of the adjacent transistor stacks that are cut from each other. This is similar to the above and will not be repeated here. Therefore, the cut is ensured, the risk of short circuits is reduced, and the gate length is not affected.

[0199] Furthermore, in an embodiment of the present application, the semiconductor device includes a first insulating layer, a second insulating layer, and a third insulating layer, which are sequentially arranged between the gate electrodes of two adjacent transistor stacks in a horizontal direction perpendicular to the extending direction of the gate body portion. The first insulating layer and the third insulating layer are made of the same material and contact the gate body portions of the two adjacent transistor stacks, respectively. The second insulating layer is arranged between the conductive portions of the two adjacent transistor stacks and contacts the conductor portions of the two adjacent transistor stacks.

[0200] Specifically, the first insulating layer and the third insulating layer separate the gate bodies of two transistor stacks adjacent in a first horizontal direction (i.e., a horizontal direction perpendicular to the extension direction of the gate bodies), and the second insulating layer separates the conductors of two transistor stacks adjacent in the first horizontal direction. The first insulating layer and the third insulating layer can be formed in a single process, so that the first insulating layer and the third insulating layer can be formed using SiO2, SiN x Alternatively, the same insulating material, such as TEOS, can be used for both.

[0201] Furthermore, since the gate electrodes can be fabricated by step S610 in the memory device manufacturing method, a first insulating layer and a third insulating layer are formed between the gate electrodes of two adjacent transistor stacks, respectively, in the areas surrounded by the gate electrodes and the second insulating layer of two adjacent memory cell stacks when projected orthogonally onto the substrate, and the side extending along the conductor portion of the first insulating layer that contacts it is also adjacent to the second insulating layer, and the side extending along the conductor portion of the third insulating layer that contacts it is also adjacent to the second insulating layer.

[0202] The material of the second insulating layer may be the same as or different from the materials of the first insulating layer and the third insulating layer, but since the second insulating layer is formed by a process different from that of the first insulating layer and the third insulating layer, the material of the second insulating layer is preferably different from that of the first insulating layer and the third insulating layer.

[0203] The structures, materials, and functions of the first insulating layer, the second insulating layer, and the third insulating layer mentioned in the embodiments of the semiconductor device are basically the same as the structures, materials, and functions of the first insulating layer, the second insulating layer, and the third insulating layer mentioned in the embodiments of the memory device. For other details of the first insulating layer, the second insulating layer, and the third insulating layer not mentioned in the embodiments of the semiconductor device, reference can be made to the corresponding details of the first insulating layer, the second insulating layer, and the third insulating layer in the embodiments of the memory device, and further description thereof will be omitted here.

[0204] Furthermore, in the embodiments of the present application, the first insulating layer and the third insulating layer are separately disposed on either side of the second insulating layer, or the first insulating layer and the third insulating layer are partially connected.

[0205] A certain gap region is provided between adjacent transistor stacks, and the gate electrodes of the transistors are included in this gap region. The portions of the gate electrodes located in the gap region can be made from the same material layer. For example, a cylindrical conductive film layer extending perpendicularly to the gap region is formed, and then a vertical strip is formed to cut and separate the conductive film layer.

[0206] Here, the cutting and separation can be performed by etching. Before etching, the hollow portion of the cylindrical conductive film layer is filled with an insulating material, and then an etching process is performed to form a vertical slip, which separates the conductive film layer into two spaced-apart parts that are respectively formed as the gate body portion and the conductor portion of the adjacent transistor stack, and the remaining insulating material forms the first insulating layer and the second insulating layer, respectively. The conductor portions of the two transistor stacks face each other, and the vertical slip exposes the facing conductor portions. The first insulating layer and the third insulating layer can be completely or partially separated by the vertical slip, and the second insulating layer fills the vertical slip and contacts the conductor portions.

[0207] For example, the slip may be formed only between two opposing conductors in two second horizontally adjacent transistor stacks, i.e., the slip cuts the originally connected gate electrodes in the two second horizontally adjacent transistor stacks and extends partially into the insulating material, i.e., the first insulating layer is partially connected to the third insulating layer.

[0208] In a preferred embodiment, the second insulating layer entirely separates the first insulating layer from the third insulating layer, so that the slip size is increased and the process difficulty can be reduced.

[0209] Furthermore, in an embodiment of the present application, the second insulating layer comprises a low dielectric constant (Low K) material.

[0210] That is, the second insulating layer can be formed of a material with a dielectric constant of less than 3.9, which contributes to reducing parasitic capacitance between transistors, including reducing coupling between the gate electrodes of two horizontally adjacent transistors.

[0211] In particular, in the embodiment of the present application, the gate electrodes of two horizontally adjacent transistors include a conductor portion, and the distance between the closest conductor portions of the two horizontally adjacent transistors is smaller than the distance between the closest gate body portions of the two horizontally adjacent transistors. Therefore, by designing the material selected for the second insulating layer to include a low-k material, it is possible to more significantly reduce the coupling between the gate electrodes of the two horizontally adjacent transistors and avoid crosstalk caused by the conductor portions of the two adjacent transistors being too close to each other.

[0212] Furthermore, in the embodiment of the present application, overlapping portions of the gate electrodes in orthogonal projection onto the substrate are connected correspondingly.

[0213] That is, the gate electrodes within the transistor stack are fabricated as a single unit, i.e., the gate electrodes of each transistor within the transistor stack are connected as a single unit, and the gate electrodes are fabricated in a single process, so that all vertically stacked transistors can be controlled by a single vertically arranged gate electrode, simplifying the manufacturing flow of the semiconductor device and reducing manufacturing costs.

[0214] In a semiconductor device according to an embodiment of the present application, a plurality of transistors are vertically stacked to form a transistor stack, each having a horizontal channel and a vertical gate, and the gates of adjacent transistor stacks can be fabricated synchronously, thereby reducing manufacturing costs. The vertical gate includes a gate body portion extending horizontally along the active layer and conductor portions disposed on both horizontal ends of the gate body portion, and the conductor portions are horizontally disposed on the side of the gate body portion away from the active layer, thereby reducing the risk of short circuits between the vertical gates without affecting the gate length.

[0215] In the description herein, terms such as "Example 1" and "Example 2" mean that the specific features, structures, materials, or characteristics described in combination with the embodiment or example are included in at least one embodiment or example of the present application. In the description herein, general expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described can be combined in any suitable manner in one or more embodiments or examples.

[0216] The above description is only a preferred embodiment of the present application, and does not limit the present application. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present application shall fall within the protection scope of the present application. [Explanation of symbols]

[0217] Memory device 1000; substrate 200; insulating surface 210; memory cell 100; active layer 1111; source terminal 11111; drain terminal 11112; channel region 11113; gate insulating layer 1112; gate structure 1113; gate body portion 1113A; first gate 11131; second gate 11132; conductor portion 1113B; first conductor portion 11133; second conductor portion 11134; memory cell stack group 11A; first memory cell stack 111A; second memory cell stack 112A; common source 110; bit line structure 120; first insulating layer 130; second insulating layer 140; third insulating layer 150; insulating spacer layer 160; Substrate-1A; film layer pair-1; semiconductor material layer-2; first insulating dielectric layer-3; first slit-4; second insulating dielectric layer-5; first trench-6; gate material layer-7; gate insulating material layer-8; third insulating dielectric layer-9; second insulating layer-9a; third insulating layer-9b; second trench-10; pre-trench-10A; first gate structure-11; second gate structure-12; fourth insulating dielectric layer / first insulating layer-13; third trench-14; conductive layer-15.

Claims

1. 1. A storage device comprising: a substrate including an insulating surface; a memory cell array including a plurality of memory cells arranged on the insulating surface, the plurality of memory cells being repeatedly arranged along a first horizontal direction, a second horizontal direction, and a vertical direction, the first horizontal direction intersecting the second horizontal direction; each of the memory cells includes a transistor, the transistor including an active layer, a gate insulating layer, and a gate structure, the gate structure including the gate body portion, the gate body portion including a first gate, the active layer being parallel to the insulating surface, the first gate extending along a sidewall of the active layer, and the gate insulating layer being located between the first gate and the active layer; The memory device further comprises a common source structure and a bit line structure, the bit line structure including a plurality of bit lines, each of the bit lines extending along the first horizontal direction, the active layer including a source terminal and a drain terminal, the source terminal connected to the common source structure, and the drain terminal connected to the bit line.

1. A storage device comprising:

2. The gate body further includes a second gate, the second gate extending along a sidewall of the active layer, and the first gate and the second gate being disposed on opposite sides of the active layer when orthogonally projected onto the substrate.

2. The storage device according to claim 1.

3. A plurality of the vertically adjacent memory cells form a memory cell stack, and in the plurality of memory cells in the memory cell stack, orthogonal projections of the active layer, the gate insulating layer, and the gate structure onto the substrate overlap, and overlapping portions of the orthogonal projections of the gate structure onto the substrate are connected correspondingly.

2. The storage device according to claim 1.

4. the vertically adjacent plurality of storage cells form a storage cell stack, and in the storage cell stack, orthogonal projections of the gate structures onto the substrate overlap; the plurality of memory cell stacks include a first memory cell stack and a second memory cell stack, the first memory cell stack and the second memory cell stack are adjacent to each other in a first horizontal direction to form a memory cell stack group, and in the memory cell stack group, the first gate of the first memory cell stack is arranged opposite to the first gate of the second memory cell stack; The gate structure further includes a conductor portion, the conductor portion including a first conductor portion formed integrally with the first gate, the first conductor portion being located on a side of the first gate away from the active layer when projected onto the substrate, and the first conductor portion being located at both ends of the first gate in a horizontal direction.

2. The storage device according to claim 1.

5. The memory cell stack groups are repeatedly arranged in the first horizontal direction.

5. The storage device according to claim 4.

6. the gate body includes a second gate, the second gate extends along a sidewall of the active layer, and the first gate and the second gate are disposed on opposite sides of the active layer when orthogonally projected onto the substrate; the conductor portion further includes a second conductor portion formed integrally with the second gate, the second conductor portion being located on a side of the second gate away from the active layer when orthogonally projected onto the substrate, and the second conductor portion being located on both ends of the second gate in a horizontal direction; The second gates are disposed between two of the memory cell stack groups adjacent in the first horizontal direction so as to face each other.

6. The storage device according to claim 5.

7. Between the gate structures of at least one group of adjacent first and second memory cell stacks, a first insulating layer, a second insulating layer, and a third insulating layer are formed in this order in a direction from the gate structure of the first memory cell stack to the gate structure of the second memory cell stack, and the first insulating layer and the third insulating layer are made of the same material; The first insulating layer and the third insulating layer contact the gate body portion of the first memory cell stack and the gate body portion of the second memory cell stack, respectively, and the second insulating layer is disposed between the opposing conductor portions of the first memory cell stack and the second memory cell stack, and contacts the conductor portion of the first memory cell stack and the conductor portion of the second memory cell stack.

7. The storage device according to claim 4, wherein the first and second storage units are connected to the first and second storage units.

8. between the gate structures of at least one group of adjacent first and second memory cell stacks, in orthogonal projection onto the substrate, the first insulating layer is formed in a region surrounded by the gate body portion, the conductor portion, and the second insulating layer of the first memory cell stack, and a side of the first insulating layer extending along the conductor portion of the first memory cell stack is also adjacent to the second insulating layer; The third insulating layer is formed in a region surrounded by the gate body portion, the conductor portion, and the second insulating layer of the second memory cell stack, and a side of the third insulating layer extending along the conductor portion of the second memory cell stack is adjacent to the second insulating layer.

8. The storage device according to claim 7.

9. In the orthogonal projection onto the substrate, The first insulating layer and the third insulating layer are disposed separately on both sides of the second insulating layer, or the first insulating layer and the third insulating layer are partially connected to each other.

8. The storage device according to claim 7.

10. The second insulating layer comprises a low dielectric constant material.

8. The storage device according to claim 7.

11. The transistor is a junctionless transistor, the material of the active layer includes N-type doped polysilicon, the active layer further includes a channel region located between the source terminal and the drain terminal, and in the memory cell, the channel region is located between the first gate and the second gate, and the width of the channel region in a direction from the first gate to the second gate is less than 40 nm.

10. The storage device according to claim 2 or 6.

12. In the gate structure, the first gate and the second gate are electrically connected; and / or the first gate and the second gate are independently controlled; and / or the first gate and the second gate are controlled independently, and the first gate and the second gate do not completely overlap on their opposing surfaces.

10. The storage device according to claim 2 or 6.

13. The common source structure includes at least one common source vertically disposed on the substrate, the common source further extending along the first horizontal direction, the common source connected to the source terminals of a plurality of the active layers adjacent in the vertical direction, and the source terminals of the active layers adjacent in the first horizontal direction connected to the same common source.

2. The storage device according to claim 1.

14. The transistor is a junctionless transistor.

14. The storage device according to claim 1, wherein the first and second storage units are connected to the first and second storage units.

15. providing a substrate; providing a plurality of film layer pairs stacked along a vertical direction on the substrate, each film layer pair including a semiconductor material layer and a first insulating dielectric layer arranged in sequence along the vertical direction; etching the plurality of film layer pairs to form a plurality of first slits repeatedly arranged along a first horizontal direction and a second horizontal direction, the first horizontal direction intersecting the second horizontal direction, the first slits penetrating the plurality of film layer pairs along a vertical direction, forming a second insulating dielectric layer to fill the first slits, the semiconductor material layer on one side of the first slits in the second horizontal direction being formed into a bit line structure, the bit line structure including a plurality of bit lines, each of the bit lines extending along the first horizontal direction, and a common source structure formed on a side of the first slit away from the bit line; Etching the second insulating dielectric layer within the first slits to form a plurality of first trenches repeatedly arranged along the first horizontal direction and the second horizontal direction, the first trenches penetrate the second insulating dielectric layer along a vertical direction, the first trenches correspond one by one to the first slits, two opposite sidewalls of the first trenches in the first horizontal direction both expose the semiconductor material layer, and when projected orthogonally onto the substrate, two opposite sidewalls of the first trenches in the second horizontal direction extend into the first slits; forming a gate material layer on the entire sidewall of the first trench, forming a gate insulating material layer located between the gate material layer and the surface of the semiconductor material layer exposed by the first trench, and filling a space surrounded by the gate material layer with a third insulating dielectric layer; etching the gate material layer to form a plurality of second trenches repeatedly arranged along the first horizontal direction and the second horizontal direction, the second trenches penetrating the gate material layer, thereby forming the gate material layer into first gate structures and second gate structures spaced apart in the first horizontal direction; filling the second trench with a fourth insulating dielectric layer.

10. A method for manufacturing a storage device comprising the steps of:

16. The step of etching the gate material layer to form a plurality of second trenches repeatedly arranged along the first horizontal direction and the second horizontal direction, the second trenches penetrating the gate material layer, so that the gate material layer is formed into first gate structures and second gate structures spaced apart in the first horizontal direction, includes: anisotropically etching portions of the gate material layer located on two opposite sidewalls of the first trench in the second horizontal direction to form pre-trenches, the pre-trenches penetrating the gate material layer and not exposing portions of the gate material layer located on two opposite sidewalls of the first trench in the first horizontal direction; wet etching the gate material layer exposed by the pre-trench to form the second trench.

16. The method for manufacturing a storage device according to claim 15.

17. anisotropically etching portions of the gate material layer located on two opposite sidewalls of the first trench in the second horizontal direction to form a pre-trench, The method further includes etching the third insulating dielectric layer, wherein the pre-trenching causes the third insulating dielectric layer to be formed into second and third insulating layers at least partially spaced apart in the first horizontal direction.

17. The method for manufacturing a storage device according to claim 16.

18. forming a gate material layer over the sidewalls of the first trench; depositing a conductive layer over the entire inner wall of the first trench and removing a portion of the conductive layer located at the bottom of the first trench.

16. The method for manufacturing a storage device according to claim 15.

19. a method of forming the gate insulating material layer comprising depositing; or The material of the semiconductor material layer includes polysilicon, and the method of forming the gate insulating material layer includes thermally oxidizing the semiconductor material layer.

16. The method for manufacturing a storage device according to claim 15.

20. the material of the fourth insulating dielectric layer comprises a low-k material; and / or The material of the third insulating dielectric layer is different from the material of the fourth insulating dielectric layer.

16. The method for manufacturing a storage device according to claim 15.

21. Two of the first trenches adjacent to each other in the first horizontal direction have two surfaces facing each other in the first horizontal direction that do not completely overlap each other.

16. The method for manufacturing a storage device according to claim 15.

22. forming the common source structure includes: etching the layer of semiconductor material to form a third trench extending along a first horizontal direction, the third trench passing entirely through the layer of semiconductor material, and filling the third trench with a conductive layer to form the common source structure; In the second horizontal direction, the common source structure and the bit line structure are located on both sides of the first slit, respectively.

16. The method for manufacturing a storage device according to claim 15.

23. A substrate; a transistor stack including a plurality of transistors vertically stacked on the substrate; the transistor includes an active layer and a gate electrode, the active layer extends along a horizontal direction, the gate electrode is located on a sidewall of the active layer, and all the gate electrodes in the transistor stack overlap each other in orthogonal projection onto the substrate; The gate electrode includes an integrated gate body and a conductor, the gate body being disposed along the length of the active layer, the conductor being located on a side of the gate body away from the active layer, and the conductor being located on both ends of the gate body in the horizontal direction. A semiconductor device characterized by:

24. There are a plurality of the transistor stacks, and the plurality of transistor stacks are distributed in a horizontal direction on the substrate; In a horizontal direction perpendicular to the extending direction of the gate body portion, the gate electrodes of two adjacent transistor stacks are arranged opposite to each other.

24. The semiconductor device according to claim 23.

25. the semiconductor device comprises a first insulating layer, a second insulating layer, and a third insulating layer; In a horizontal direction perpendicular to the extending direction of the gate body portion, the first insulating layer, the second insulating layer, and the third insulating layer are sequentially arranged between the gate electrodes of the two adjacent transistor stacks, the first insulating layer and the third insulating layer are made of the same material, and are in contact with the gate body portions of the two adjacent transistor stacks, respectively, and the second insulating layer is arranged between the conductive portions of the two adjacent transistor stacks and is in contact with the conductor portions of the two adjacent transistor stacks.

25. The semiconductor device according to claim 24.

26. Between the gate structures of the two adjacent transistor stacks, in orthogonal projection onto the substrate, The first insulating layer and the third insulating layer are respectively formed in regions surrounded by the gate electrodes and the second insulating layers of the two adjacent memory cell stacks, and the sides of the first insulating layer extending along the conductor portions in contact with the first insulating layer are also adjacent to the second insulating layer, and the sides of the third insulating layer extending along the conductor portions in contact with the third insulating layer are also adjacent to the second insulating layer.

26. The semiconductor device according to claim 25.

27. In the orthogonal projection onto the substrate, The first insulating layer and the third insulating layer are separately disposed on both sides of the second insulating layer, or the first insulating layer and the third insulating layer are partially connected to each other.

26. The semiconductor device according to claim 25.

28. The second insulating layer includes a low dielectric constant material.

26. The semiconductor device according to claim 25.

29. the transistor further comprises a gate insulating layer, the gate insulating layer being located between the gate body and the active layer; and / or The overlapping portions of the gate electrodes in the orthogonal projection onto the substrate are connected to each other.

24. The semiconductor device according to claim 23.

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