Display device and method for driving display device

Abstract

The present disclosure provides a display device and a driving method of the display device.SOLUTION: The source driver of the display device is configured to transmit the data signal to the plurality of sub-pixels, the data signal includes the second data signal (configured to control the brightness of the sub-pixels of the display panel) after the first moment, the voltage generator of the display device includes the common voltage pin for outputting the common voltage signal, and the switch controller connected between the common voltage pin and the common electrode is configured to turn on the circuit between the common voltage pin and the common electrode after the first moment, so that the instantaneous flicker phenomenon at startup is improved.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to the field of display technology, and more particularly to a display device and a driving method thereof. [Background technology]

[0002] During the startup process of an LCD (Liquid Crystal Display), the source driver chip transmits valid data voltages to the data lines of the display area after receiving a data latch signal. However, before this, the voltage on the data lines changes due to the capacitor coupling between the data lines transmitting invalid voltages and the signal lines transmitting other signals. This causes an abnormal voltage difference between the two ends of the liquid crystal molecules, resulting in a momentary flicker on the display screen.

[0003] Therefore, conventional LCDs have a momentary flicker phenomenon during the startup process, which needs to be improved urgently. Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present disclosure is to provide a display device and a driving method for the display device to improve the flicker phenomenon that exists when the display device is turned on. [Means for solving the problem]

[0005] An embodiment of the present disclosure provides a display device including a display panel, a source driver, a voltage generator, and a switch controller, wherein the display panel includes a first substrate, a second substrate facing the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate, the first substrate including a plurality of subpixels arranged in an array, and the second substrate including a common electrode, the source driver is electrically connected to the first substrate and is used to transmit data signals to the plurality of subpixels, the data signals including a first data signal before a first time and a second data signal after the first time, the second data signal being used to control luminance of the subpixels of the display panel, the voltage generator includes a common voltage pin for outputting a common voltage signal, and the switch controller is connected between the common voltage pin and the common electrode and is used to conduct a circuit between the common voltage pin and the common electrode after the first time.

[0006] In some embodiments, the display device further includes a timing controller, the timing controller being electrically connected to the source driver, the timing controller being used to control the source driver to output the second data signal after the first time, and the switch controller being used to control the source driver to conduct a circuit between the common voltage pin and the common electrode after the first time, the timing controller being used to output a switch control signal, the switch control signal including a first switch control signal after the first time, and the switch controller being used to control the conduction of the circuit between the common voltage pin and the common electrode based on the first switch control signal.

[0007] In some embodiments, the timing controller is used to output a data output enable signal, the data output enable signal including a first data output enable signal from the first time onwards, the source driver is used to output the second data signal based on the first data output enable signal, and the timing controller is used to generate the switch control signal based on the data output enable signal.

[0008] In some embodiments, the voltage generator is used to transmit a source operating voltage to the source driver, and the timing controller is electrically connected to the source driver, and the timing controller is used to generate the switch control signal based on the source operating voltage.

[0009] In some embodiments, the switch controller includes a switch input terminal electrically connected to the common voltage pin, a switch output terminal electrically connected to the common electrode, and a switch control terminal electrically connected to the timing controller and used to conduct a circuit between the switch input terminal and the switch output terminal after the first time.

[0010] In some embodiments, the switch control terminal is used to load the switch control signal, and the switch control signal is used to control whether a circuit between the switch input terminal and the switch output terminal is made conductive or cut off.

[0011] In some embodiments, the switch controller includes a first switch transistor and a second switch transistor, a gate of the first switch transistor configured as the switch control terminal, a source of the first switch transistor grounded, a gate of the second switch transistor electrically connected to the drain of the first switch transistor, a source of the second switch transistor configured as the switch input terminal, and a drain of the second switch transistor configured as the switch output terminal.

[0012] An embodiment of the present disclosure further provides a method for driving a display device, the display device including a display panel, a source driver, a voltage generator, and a switch controller, the display panel including a first substrate, a second substrate facing the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate, the first substrate including a plurality of subpixels arranged in an array, the second substrate including a common electrode, and the voltage generator including a common voltage pin, the method for driving the display device including controlling the source driver to transmit data signals to the plurality of subpixels, the data signals including a first data signal before a first time and a second data signal after the first time, and controlling the switch controller to conduct a circuit between the common voltage pin and the common electrode after the first time, thereby causing the common voltage pin to transmit a common voltage signal to the common electrode.

[0013] In some embodiments, the display device further includes a timing controller electrically connected to the source driver, wherein controlling the switch controller to conduct a circuit between the common voltage pin and the common electrode after the first time includes controlling the timing controller to output a data output enable signal and a switch control signal, wherein the data output enable signal includes a first data output enable signal after the first time and the switch control signal includes a first switch control signal after the first time, and controlling the switch controller to conduct a circuit between the common voltage pin and the common electrode based on the first switch control signal, and controlling the source driver to transmit a data signal to the plurality of sub-pixels includes controlling the source driver to output the second data signal based on the first data output enable signal.

[0014] An embodiment of the present disclosure further provides a display device, the display device including a display panel, a source driver, and a voltage generator, the display panel including a first substrate, a second substrate disposed opposite to the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate; the first substrate includes a plurality of sub-pixels arranged in an array, the second substrate includes a common electrode, the source driver is electrically connected to the first substrate and is used to transmit data signals to the plurality of sub-pixels, the data signals including a first data signal before a first time and a second data signal after the first time, the second data signal being used to control the brightness of the sub-pixels of the display panel, and the voltage generator is electrically connected to the display panel and is used to transmit a common voltage signal to the common electrode after the first time. [Effects of the Invention]

[0015] The present disclosure provides a display device and a driving method for the display device, wherein the display panel of the display device includes a first substrate, a second substrate disposed opposite the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate, and a switch controller connected between the common voltage pin (used to output a common voltage signal) and the common electrode (included in the second substrate) is disposed, so that the switch controller is used to conduct a circuit between the common voltage pin and the common electrode after the first time, thereby avoiding a rise in the potential of the in-plane data line due to parasitic capacitor coupling caused by the common electrode being loaded to the common electrode before the first time, and avoiding a drop in the potential of the in-plane data line due to the driving transistor of the sub-pixel (included in the first substrate) transmitting charge, thereby avoiding a large voltage difference between the common electrode and the sub-pixel, which causes a momentary flicker phenomenon at start-up. [Brief explanation of the drawings]

[0016] [Figure 1] 1 is a schematic diagram of a display device according to a first embodiment of the present disclosure; [Figure 2] FIG. 2 is a three-dimensional view of a display panel provided in an embodiment of the present disclosure. [Figure 3] FIG. 2 is an equivalent circuit diagram of a subpixel provided in an embodiment of the present disclosure. [Figure 4] FIG. 10 is a schematic diagram of a display device according to a second embodiment of the present disclosure. [Figure 5] FIG. 2 is a waveform diagram of some signals of the display device provided in the embodiment of the present disclosure. [Figure 6] 1 is a flowchart of a driving method for a display device provided in an embodiment of the present disclosure. [Figure 7] 1 is a flowchart of a driving method for a display device provided in an embodiment of the present disclosure. [Figure 8] FIG. 10 is a schematic diagram of a display device according to a third embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0017] Below, the technical solutions of the embodiments of the present disclosure will be described in conjunction with the drawings of the embodiments of the present disclosure. In describing this disclosure, the terms "first," "second," etc. are used for descriptive purposes only and do not denote the relative importance or quantity of the implied technical features, and thus a feature defined as "first" or "second" may explicitly or implicitly include one or more of said features. Reference to an "embodiment" in this disclosure means that a particular feature, structure, or characteristic described in the embodiment is included in at least one embodiment of the present disclosure. The embodiments described in this disclosure can be combined with other embodiments. The present disclosure provides a display device, which may include, but is not limited to, the following examples and combinations of the following examples.

[0018] In some embodiments, as shown in FIGS. 1 to 5 , a display device 100 includes a display panel 10, a source driver 20, a voltage generator (which may be, but is not limited to, a power manager 30), and a switch controller 40. The display panel 10 includes a first substrate 103, a second substrate 104 disposed opposite the first substrate 103, and a liquid crystal layer 102 disposed between the first substrate 103 and the second substrate 104. The first substrate 103 includes a plurality of sub-pixels P arranged in an array. The second substrate 104 includes a common electrode 101. The source driver 20 is electrically connected to the first substrate 103 and is configured to transmit a data signal (data) to the plurality of sub-pixels P. 5, the data signal data includes a first data signal data1 before a first time t1 and a second data signal data2 after the first time t1, the second data signal data2 is used by the display panel 10 to control the brightness of the sub-pixel P (the light source may be provided by a backlight panel), the voltage generator includes a common voltage pin 301 for outputting a common voltage signal VCOM_1A, and the switch controller 40 is connected between the common voltage pin 301 and the common electrode 101 and is used to conduct a circuit between the common voltage pin 301 and the common electrode 101 after the first time t1.

[0019] As shown in FIG. 1, the display device 100 may further include a gate driver 50. The gate driver 50 may be a gate driving circuit located on a substrate of the display panel 10, or may be a chip provided independently of the display panel 10 (FIG. 1 illustrates only the latter as an example). For ease of explanation, FIG. 1 illustrates only an array arrangement of a plurality of subpixels P, which may be arranged, for example, in n rows and m columns (n ​​and m are both positive integers). The display panel 10 further includes a plurality of gate lines (GL1 to GLn) electrically connected to the gate driver 50 and a plurality of data lines (DL1 to DLM) electrically connected to a source driver 20. The gate driver 50 generates a plurality of gate signals "gate" corresponding to the sub-pixels P of the plurality of rows. Each gate line (any of GL1 to GLn) is electrically connected to the sub-pixels P of a corresponding row to transmit a corresponding gate signal "gate" to the sub-pixels P of the corresponding row. Each gate signal "gate" includes a gate enable pulse for controlling the sub-pixels P of the corresponding row to be turned on. The gate enable pulses are arranged sequentially on the time axis to sequentially turn on the sub-pixels P of the corresponding plurality of rows. Each data line (any of DL1 to DLM) is electrically connected to the sub-pixels P of a corresponding column to transmit a corresponding data signal "data" generated by the source driver 20. Each data signal "data" includes a plurality of data voltages (all included in the same second data signal "data2") corresponding to the sub-pixels P of the column. The plurality of data signals "data" corresponding to the sub-pixels P of the plurality of columns are matched so that the plurality of data voltages corresponding to the sub-pixels P of the row can be transmitted to the corresponding sub-pixels P via the plurality of data lines (DL1 to DLM) when the sub-pixels P of each row are turned on.

[0020] Here, the display device 100 may be a liquid crystal display device. As shown in Fig. 2, the common electrode 101 may be the entire film layer disposed opposite the plurality of subpixels P, and a liquid crystal layer 102 is filled between the plurality of subpixels P and the common electrode 101. The liquid crystal molecules in the liquid crystal layer 102 in a region corresponding to each subpixel P are deflected in accordance with a voltage difference V1 between the subpixel P and the common electrode 101 (Fig. 2 shows that the potential of the subpixel P is higher than the potential of the common electrode 101, but in practice this is not limited to this), and a corresponding degree of transmittance to the backlight is realized so that the region in the display panel 10 exhibits a corresponding brightness.

[0021] As shown in FIG. 3, FIG. 3 is an equivalent circuit diagram formed by one of the sub-pixels P, a corresponding gate line (any of GL1 to GLn), a corresponding data line (any of DL1 to DLM), and a common electrode 101. As shown in FIG. 5, the source operating voltage AVDD may be a signal generated by the power supply manager 30 and acting on the source driver 20, the common voltage signal VCOM_1A may be a signal at the common voltage pin 301 in the present invention, the target common voltage signal VCOM_1B may be a signal at the common electrode 101 in the present invention, the contrast source signal Sout0 may be a signal at a pin electrically connected to a corresponding data line of the source driver 20 in a proportional example (when the common electrode 101 directly acts on the common voltage signal VCOM_1A), the source signal Sout may be a signal at a pin electrically connected to a corresponding data line of the source driver 20 when the common electrode 101 acts on the target common voltage signal VCOM_1B, the contrast source signal Sout0 / source signal Sout may be approximately the same as the corresponding contrast data signal data0 / data signal data, and the data output enable signal TP may be a signal generated by the timing controller 60 of the display device 100 and acting on the source driver 20.

[0022] Here, the power manager 30, the switch controller 40, and the timing controller 60 may be electrically connected to the display panel 10 through a PCB (Printed Circuit Board).

[0023] In addition, in the drawings of the present invention, the voltage generator is exemplified as the power supply manager 30, but in reality, the voltage generator may also be a gamma voltage generator (not shown), which may further provide a plurality of gamma voltages to the source driver 20. Of course, the above-mentioned power supply manager 30 may also provide a timing operating voltage VDD to the timing controller 60 and a source operating voltage AVDD to the source driver 20, and the timing operating voltage VDD is used to generate at least the data output enable signal TP, and the function of the source operating voltage AVDD can be referred to in the following description.

[0024] After the display device 100 is turned on, the source operating voltage AVDD gradually rises, and at time t0, when the boost reaches the lower limit value AVDD_uvlo of the source operating voltage, the common voltage signal VCOM_1A begins to gradually rise to reach its stable value. At time t1, when the boost of the source operating voltage AVDD reaches its stable value, the data output enable signal TP is at the data latch pulse p. Prior to this (i.e., before time t1), the source driver 20 has not yet output the effective potential of the source signal Sout / contrast source signal Sout0 (which at this point is the potential of the above-mentioned first data signal data1). In other words, the in-plane data lines are still in a suspended state (which can be considered to be at a potential close to ground). Only after the data output enable signal TP becomes the data latch pulse p (i.e., after time t1), the source signal Sout / contrast source signal Sout0 is at the effective potential (i.e., the potential of the above-mentioned second data signal data2, which can be set larger and / or smaller than the stable value of the common voltage signal VCOM_1A / target common voltage signal VCOM_1B). Whether the potential of the second data signal DATA2 is greater than or less than the stable value of the common voltage signal VCOM_1A / target common voltage signal VCOM_1B can be represented as a positive data voltage or a negative data voltage, respectively, which can control the deflection of the liquid crystal molecules in opposite directions. The positive data voltage and the negative data voltage (collectively referred to as effective potential) are both used to control the display panel 10 to display the screen normally.

[0025] In the comparative example, the common voltage pin 301 is electrically connected to the common electrode 101 at a constant voltage, so the potential of the common electrode 101 (which is the same as the amplitude of the common voltage signal VCOM_1A) gradually increases from time t0. As shown in FIGS. 3 and 5, the presence of a first stray capacitance Cdv between the common electrode 101 and a data line (any of DL1 to DLM) couples the common electrode 101 to the data line, causing the potentials of the corresponding data signal data and the contrast source signal Sout0, which are then referred to as the contrast source signal Sout0, to increase. Furthermore, the presence of a second stray capacitance Cgd between the data line (any of DL1 to DLM) and the corresponding gate line (any of GL1 to GLn) also increases the potential of the gate line. As a result, the drive transistor 105 in the display panel 10 is not fully turned off (is slightly turned on), so the charge on the data line leaks to the subpixel P (pixel electrode), and the potential of the contrast source signal Sout0 decreases. However, between t0 and t1, the source driver 20 has not yet output the effective potential of the contrast source signal Sout0, and therefore the potential increased when the data line is coupled to the common electrode 101 cannot be maintained. As a result, a voltage difference exists between the data line and the common electrode 101, causing the liquid crystal molecules at the corresponding positions to be deflected. After startup, the source driver 20 outputs the effective potential of the contrast source signal Sout0, causing a momentary flicker phenomenon before the screen is displayed normally.

[0026] In this embodiment, a switch controller 40 is installed, which is connected between the common voltage pin 301 and the common electrode 101, and is used to make the circuit between the common voltage pin 301 and the common electrode 101 conductive after the first time t1. Therefore, between t0 and t1 before that, the common voltage signal VCOM_1A gradually rises, but the common electrode 101 in the plane is in a suspended state, and the target common voltage signal VCOM_1B is considered to be at a potential close to ground. Therefore, the potential of the source signal Sout of the data line and the pin of the source driver electrically connected to the data line is coupled to the common voltage signal VCOM_1B and does not rise (it may be considered to be at a potential close to ground), and there is no voltage difference across the liquid crystal molecules, thereby improving the momentary flicker phenomenon at startup. Then, after the first time t1, the switch controller 40 becomes conductive, the potential of the target common voltage signal VCOM_1B (i.e., the potential of the common electrode 101) rises to the potential of the common voltage signal VCOM_1A at this time (its stable value), and the source driver 20 also outputs the effective potential of the source signal Sout1, thereby displaying the screen normally.

[0027] 1 to 5, the display device 100 further includes a timing controller 60. The timing controller 60 is electrically connected to the source driver 20, and is used to control the source driver 20 to output a second data signal (data2) after the first time t1, and is used to control the switch controller 40 to make a circuit between a common voltage pin 301 and a common electrode 101 (included in the display panel 10) conductive after the first time t1. The timing controller 60 is used to output a switch control signal (Control), and the switch control signal (Control) includes a first switch control signal (Control1) that is positioned after the first time t1, and the switch controller 40 is used to control the circuit between the common voltage pin 301 and the common electrode 101 to be conductive based on the first switch control signal (Control1).

[0028] The timing controller 60 is electrically connected to the source driver 20, so that it can control the output of the second data signal data2 after the first time t1, and can directly or indirectly control the switch controller 40 to make the circuit between the common voltage pin 301 and the common electrode 101 (included in the display panel 10) conductive, so that the common electrode 101 loads the common voltage signal VCOM_1A, which is approaching its stable value at this time, and the potential of the common electrode 101 can also quickly reach the stable value of the common voltage signal VCOM_1A, and the brightness of each sub-pixel P in the display panel 10 can be determined based on the corresponding second data signal data2.

[0029] 1 to 5, the timing controller 60 is used to output the data output enable signal TP, which includes a first data output enable signal TP1 located after a first time t1, and the source driver 20 is used to output a second data signal data2 based on the first data output enable signal TP1, and the timing controller 60 is used to generate the switch control signal Control based on the data output enable signal TP.

[0030] Here, the source driver 20 is used to output a data signal data based on a data output enable signal TP. As shown in FIG. 5, the data output enable signal TP1, which occurs after a first time t1 in the data output enable signal TP, may include a plurality of data latch pulses p, and the data signal data2, which occurs after the first time t1 in the data signal data, may include a plurality of data voltages (the first and second partial data voltages may be greater than or less than the stable values ​​of the common voltage signal VCOM_1A / target common voltage signal VCOM_1B, and the first and second partial data voltages may be set alternately). As described above, the first and second partial data voltages may be referred to as positive and negative data voltages, respectively, and both may control the deflection of liquid crystal molecules in opposite directions. The positive and negative data voltages (collectively referred to as effective potentials) are both used to control the display panel 10 to display a screen normally.

[0031] Each data latch pulse p is used to control multiple buffer pins of the source driver 20 to transmit multiple corresponding data voltages (corresponding to multiple sub-pixels P in the same row) to multiple data lines, so that multiple rows of sub-pixels P are sequentially loaded with corresponding data voltages under the action of multiple data latch pulses p. For example, in FIG. 5, based on the consecutively arranged multiple data latch pulses p, each buffer pin can sequentially output multiple data voltages, each of which corresponds to multiple rows of sub-pixels P as first partial data voltages. Furthermore, based on the consecutively arranged multiple data latch pulses p, each buffer pin can sequentially output multiple data voltages, each of which corresponds to multiple rows of sub-pixels P as second partial data voltages. The first partial data voltages and the second partial data voltages can correspond to a data amount of one frame, less than one frame, or more than one frame, all of which can realize the polarity inversion function of the display device 100.

[0032] Since the starting points of the first data output enable signal TP1 and the first switch control signal Control are both the first time t1, the starting time of the second data signal data2 output by the source driver 20 based on the first data output enable signal TP1 and the starting time of the circuit between the common voltage pin 301 and the common electrode 101 controlled based on the first switch control signal Control are both the same, thereby avoiding the screen flicker phenomenon at startup caused by the potential of VCOM_1A (its stable value) being loaded before the common electrode 101 generates the second data signal data2.

[0033] In some embodiments, as shown in FIGS. 1 to 5, the voltage generator (e.g., power supply manager 30) is used to transmit a source operating voltage AVDD to the source driver 20, the timing controller 60 is electrically connected to the source driver 20 (see dashed line) to load the source operating voltage AVDD, and the timing controller 60 is used to generate the switch control signal Control based on the source operating voltage AVDD.

[0034] Specifically, the source operating voltage AVDD is transmitted to the source driver 20 for use as the operating voltage of the buffer therein. In operation, the buffer can output a corresponding data signal (data) to a corresponding data line (one of DL1 to DLM) based on a signal (related to the data signal) at its input end. At the same time, the magnitude of the source operating voltage AVDD can affect the magnitude of the current at the output end of the buffer. As shown in FIG. 5, when the display device 100 starts up, the source operating voltage AVDD provided by the voltage generator (e.g., the power manager 30) needs to gradually increase to its stable value. If this is the case, the current at the output end of the buffer can be increased sufficiently to ensure that the data signal (data, then referred to as the source signal Sout) can be properly input to the display panel 10. Combining the above description, it can be seen that the source operating voltage AVDD reaches its stable value at a first time t1.

[0035] In some embodiments, as shown in FIGS. 1 to 4, the switch controller 40 includes a switch input terminal 401 electrically connected to the common voltage pin 301, a switch output terminal 402 electrically connected to the common electrode 101, and a switch control terminal 403 electrically connected to the timing controller 60 and used to establish conduction between the switch input terminal 401 and the switch output terminal 402 after the first time t1.

[0036] Combining the descriptions in the above specification, the data output enable signal TP generated by the timing controller 60 is used to determine the data signal DATA generated by the source driver 20. Since the start time of the first data output enable signal TP1 and the start time of the second data signal DATA2 are both the first time, in this embodiment, the switch control terminal 403 is electrically connected to at least one of the timing controller 60 and the source driver 20 to receive at least one of the data output enable signal TP and the data signal DATA, thereby making the circuit between the switch input terminal 401 and the switch output terminal 402 conductive and the circuit between the common voltage pin 301 and the common electrode 101 conductive at the first time according to the potential status.

[0037] 1 and 4, the switch control signal Control may be generated based on the data output enable signal TP generated by the timing controller 60. As shown in Fig. 5, the timing controller 60 can determine in real time whether the first data output enable signal TP1 appears in the data output enable signal TP, and can synchronously output the first switch control signal Control1 to make the circuit between the switch input terminal 401 and the switch output terminal 402 conductive at the time when the first data output enable signal TP1 appears (i.e., the time when the first data latch pulse p appears). Until now, when the first switch control signal Control1 does not appear, the switch control signal Control breaks the circuit between the switch input terminal 401 and the switch output terminal 402.

[0038] 1 and 4, the switch control signal Control may be generated based on the source operating voltage AVDD transmitted to the source driver 20. As shown in Fig. 5, in order to realize the above function, the switch control signal Control may be generated based on the source operating voltage AVDD acquired by the source driver 20, and the timing controller 60 may synchronously output the first switch control signal Control1 at the time when the source operating voltage AVDD reaches its stable value (i.e., the time when the first data latch pulse p appears).

[0039] In some embodiments, as shown in FIG. 4 , the switch controller 40 includes a first switch transistor Q1 and a second switch transistor Q2, wherein a gate of the first switch transistor Q1 is configured as the switch control terminal 403, a source of the first switch transistor Q1 is grounded, a gate of the second switch transistor Q2 is electrically connected to the drain of the first switch transistor Q1, a source of the second switch transistor Q2 is configured as the switch input terminal 401, and a drain of the second switch transistor Q2 is configured as the switch output terminal 402.

[0040] For ease of explanation, based on the above circuit connection scheme, the following description will be given taking the first switch transistor Q1 as an NMOS tube and the second switch transistor Q2 as a PMOS tube as an example. A first resistor R1 may be connected between the gate and source of the second switch transistor Q2, and a second resistor R2 may be connected between the gate of the second switch transistor Q2 and the drain of the first switch transistor Q1. The resistance values ​​of the first resistor R1 and the second resistor R2 can be determined and set according to the function of the switch controller 40. Combining the waveform diagrams shown in FIG. 5, the operation process of the display device 100 can be as follows:

[0041] After startup, at time t1 when the source operating voltage AVDD reaches its stable value, the timing controller 60 outputs a first data output enable signal TP1 to the source driver 20, and the source signal Sout output by the source driver 20 is at an effective potential. That is, the in-plane sub-pixel P receives the first data signal data1, and the level of the switch control signal Control rises to form the first switch control signal Control1, making the first switch transistor Q1 of the NMOS tube conductive. The ground potential drops to the potential of the gate of the second switch transistor Q2 of the PMOS tube through the first switch transistor Q1, making the second switch transistor Q2 conductive, thereby realizing the conduction of the circuit between the common voltage pin 301 and the common electrode 101. The in-plane common electrode 101 is then loaded with the effective potential of the common voltage signal VCOM_1A (i.e., the potential of the target common voltage signal VCOM_1B).

[0042] Here, when the first switch transistor Q1 is off, the first resistor R1 raises the gate potential of the second switch transistor Q2, and when the first switch transistor Q1 is on, the second resistor R2 lowers the gate potential of the second switch transistor Q2. If the first resistor R1 is not installed and no line is connected between the gate and source of the second switch transistor Q2, the gate potential of the second switch transistor Q2 may drop due to external capacitive coupling or other influences when the first switch transistor Q1 is not yet on, resulting in the second switch transistor Q2 accidentally turning on. If only a wire is connected between the gate and source of the second switch transistor Q2 instead of the first resistor R1, the gate of the second switch transistor Q2 may not be pulled low when the first switch transistor Q1 is on, and may instead maintain the same potential as the common voltage signal VCOM_1A. The second resistor R2 serves as a current limiter.

[0043] Of course, the power supply manager 30 can also transmit the gamma voltage to the source driver 20, and the source driver 20 can generate a data voltage corresponding to each sub-pixel P based on the gray level and the gamma voltage of the sub-pixel P. Under the action of the external input signal VIN, the voltage generator (taking the power supply manager 30 as an example) can transmit a corresponding voltage signal to the timing controller 60 to control the operation, and transmit the source operating voltage AVDD and the gamma voltage to the source driver 20.

[0044] To better describe the above display device, the present disclosure further provides a driving method for the display device, which may include but is not limited to the following examples and combinations of the following examples.

[0045] In some embodiments, as in FIG. 6, the driving method of the display device includes, but is not limited to, the following and combinations of the following:

[0046] S1: Controlling the source driver to transmit data signals to a plurality of the sub-pixels, the data signals including a first data signal before a first time and a second data signal after the first time.

[0047] Here, the executing entity of S1 may include the source driver 20. For specific details of S1, please refer to the above specification.

[0048] S2: The switch controller controls the conduction of the circuit between the common voltage pin and the common electrode after the first time, so that the common voltage pin transmits a common voltage signal to the common electrode.

[0049] As described in the comparative example, when the common voltage pin 301 is electrically connected to the common electrode 101 at a constant level, the potential of the common electrode 101 (which is the same as the amplitude of the common voltage signal VCOM_1A) gradually rises from time t0, and the potential of the data line may rise due to coupling with the common electrode 101, and then drop due to the transmission of charge through the driving transistor 105. As a result, a voltage difference exists between the data line and the common electrode 101, causing a momentary flicker phenomenon at startup.

[0050] Here, the executing entity of S2 may include the switch controller 40. For specific details of S2, please refer to the relevant description in the above specification.

[0051] As described above, in the present invention, by installing a switch controller 40 connected between the common voltage pin 301 and the common electrode 101, it is used to make the circuit between the common voltage pin 301 and the common electrode 101 conductive after the first time t1, so that the common electrode 101 is in a suspended state, the potential of the data line does not rise, and there is no voltage difference between both ends of the liquid crystal molecules, thereby improving the momentary flicker phenomenon at startup.

[0052] In some embodiments, as in FIG. 7, S2 includes, but is not limited to:

[0053] S201: The timing controller controls the output of a data output enable signal and a switch control signal, the data output enable signal including a first data output enable signal from the first time onwards, and the switch control signal including a first switch control signal from the first time onwards.

[0054] Here, the execution entity of S201 may include the timing controller 60. For specific details of S201, please refer to the above specification. Of course, as described in the above specification, the switch control signal Control may be generated by the source driver 20.

[0055] S202: The switch controller controls the conduction of a circuit between the common voltage pin and the common electrode according to the first switch control signal.

[0056] Here, the executing entity of S202 may include the switch controller 40. For specific details of S202, please refer to the above specification.

[0057] Based on S201 and S202, S1 includes, but is not limited to:

[0058] S101: Controlling the source driver to output the second data signal according to the first data output enable signal.

[0059] Similarly, the execution body of S101 may include the source driver 20. For specific details of S101, please refer to the above specification.

[0060] As described above, the starting points of both the first data output enable signal TP1 and the first switch control signal Control are the first time t1, and therefore the starting time of the second data signal data2 output based on the first data output enable signal TP1 is also the same as the starting time at which the circuit between the common voltage pin 301 and the common electrode 101, which is controlled based on the first switch control signal Control, becomes conductive. This makes it possible to avoid screen flicker at startup, which is caused by the common electrode 101 being loaded with the potential of VCOM_1A (its stable value) before the second data signal data2 is generated.

[0061] The present disclosure further provides a display device. As shown in Figures 8, 2 and 3, the display device 100 includes a display panel 10, a source driver 20, and a power manager 30. The display panel 10 includes a first substrate 103, a second substrate 104 facing the first substrate 103, and a liquid crystal layer 102 between the first substrate 103 and the second substrate 104. The first substrate 103 includes a plurality of sub-pixels P arranged in an array. The second substrate 104 includes a common electrode 101. The source driver 20 is electrically connected to the first substrate 103. The display panel 10 includes a power supply manager 30, which is electrically connected to the display panel 10 and is used to transmit a common voltage signal VCOM_1A to the common electrode after the first time t1. The power supply manager 30 is electrically connected to the display panel 10 and is used to transmit a common voltage signal VCOM_1A to the common electrode after the first time t1. The power supply manager 30 is used to transmit a common voltage signal VCOM_1A to the common electrode after the first time t1. The power supply manager 30 is electrically connected to the display panel 10 and is used to transmit a common voltage signal VCOM_1A to the common electrode after the first time t1.

[0062] Specifically, the difference between the display device 100 of this embodiment and the previous embodiment is that in this embodiment, the switch controller 40 is integrated into the power manager 30. Of course, the power manager 30 may further include a power management module 302, which can generate the signals generated by the power manager 30 of the previous embodiment, i.e., the power management module 302 can generate at least the common voltage signal VCOM_1A. In this case, the switch output end 402 of the switch controller 40 integrated in the power manager 30 is the common voltage pin 301 for transmitting the common voltage signal VCOM_1A to the common electrode.

[0063] It can be understood that in this embodiment, since the switch controller 40 is integrated into the power supply manager 30, the power supply manager 30 can directly transmit the common voltage signal VCOM_1A to the common electrode after the first time t1, that is, in FIG. 8, the power supply manager 30 transmits the target common voltage signal VCOM_1B to the common electrode.

[0064] For technical features of the display panel 10, the subpixel P, the common electrode 101, the source driver 20, the data signal DATA, the first data signal DATA1, the second data signal DATA2, and the common voltage signal VCOM_1A of this embodiment, you may refer to the relevant descriptions of the previous embodiments.

[0065] The present disclosure provides a display device and a driving method for the display device, wherein the display panel of the display device includes a first substrate, a second substrate disposed opposite the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate, and a switch controller connected between the common voltage pin (used to output a common voltage signal) and the common electrode (included in the second substrate) is disposed, so that the switch controller is used to conduct a circuit between the common voltage pin and the common electrode after the first time, thereby avoiding a rise in the potential of the in-plane data line due to parasitic capacitor coupling caused by the common electrode being loaded to the common electrode before the first time, and avoiding a drop in the potential of the in-plane data line due to the driving transistor of the sub-pixel (included in the first substrate) transmitting charge, thereby avoiding a large voltage difference between the common electrode and the sub-pixel, which causes a momentary flicker phenomenon at start-up.

[0066] The display device and the driving method thereof provided by the embodiments of the present disclosure have been described in detail above. Specific examples have been used to illustrate the principles and implementations of the present disclosure. The description of the above embodiments is only intended to help understand the technical solutions and core ideas of the present disclosure. Those skilled in the art should understand that they may still modify the technical solutions described in the above embodiments or replace some technical features therein with equivalents. However, such modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A display device, a display panel, a source driver, a voltage generator, and a switch controller; the display panel includes a first substrate, a second substrate disposed opposite to the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate, the first substrate including a plurality of sub-pixels arranged in an array, and the second substrate including a common electrode; the source driver is electrically connected to the first substrate and is used to transmit data signals to the plurality of sub-pixels, the data signals including a first data signal before a first time and a second data signal after the first time, the second data signal being used to control luminance of the sub-pixels of the display panel; the voltage generator includes a common voltage pin for outputting a common voltage signal; the switch controller is connected between the common voltage pin and the common electrode, and is used to conduct a circuit between the common voltage pin and the common electrode after the first time; A display device characterized by:

2. further comprising a timing controller; the timing controller is electrically connected to the source driver, the timing controller is used to control the source driver to output the second data signal after the first time, and the switch controller is used to control the switch controller to conduct a circuit between the common voltage pin and the common electrode after the first time; the timing controller is used to output a switch control signal, the switch control signal including a first switch control signal after the first time, and the switch controller is used to control conduction of a circuit between the common voltage pin and the common electrode based on the first switch control signal; 2. The display device according to claim 1.

3. the timing controller is used to output a data output enable signal, the data output enable signal including a first data output enable signal at or after the first time; the source driver is used to output the second data signal based on the first data output enable signal; the timing controller is used to generate the switch control signal based on the data output enable signal; 3. The display device according to claim 2.

4. The voltage generator is used to transmit a source operating voltage to the source driver, and the timing controller is electrically connected to the source driver; the timing controller is used to generate the switch control signal based on the source operating voltage; 3. The display device according to claim 2.

5. The switch controller a switch input electrically connected to the common voltage pin; a switch output terminal electrically connected to the common electrode; a switch control terminal electrically connected to the timing controller and used to conduct a circuit between the switch input terminal and the switch output terminal after the first time point; 5. The display device according to claim 2, wherein the display device is a display device having a plurality of display areas.

6. The switch control terminal is used to load the switch control signal; The switch control signal is used to control whether a circuit between the switch input terminal and the switch output terminal is turned on or off.

6. The display device according to claim 5.

7. the switch controller includes a first switch transistor and a second switch transistor; a gate of the first switch transistor configured as the switch control terminal, and a source of the first switch transistor grounded; a gate of the second switch transistor electrically connected to a drain of the first switch transistor, a source of the second switch transistor configured as the switch input terminal, and a drain of the second switch transistor configured as the switch output terminal; 6. The display device according to claim 5.

8. A method for driving a display device, comprising: the display device includes a display panel, a source driver, a switch controller, and a voltage generator; the display panel includes a first substrate, a second substrate disposed opposite to the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate, the first substrate including a plurality of sub-pixels arranged in an array, the second substrate including a common electrode, and the voltage generator including a common voltage pin; The method for driving the display device includes: The source driver controls the plurality of sub-pixels to transmit data signals, the data signals including a first data signal before a first time and a second data signal after the first time; and controlling the switch controller to conduct a circuit between the common voltage pin and the common electrode after the first time, thereby causing the common voltage pin to transmit a common voltage signal to the common electrode. A method for driving a display device comprising:

9. The display device further includes a timing controller electrically connected to the source driver, and the switch controller controls the circuit between the common voltage pin and the common electrode to be conductive after the first time, The timing controller controls to output a data output enable signal and a switch control signal, the data output enable signal including a first data output enable signal after the first time, and the switch control signal including a first switch control signal after the first time; The switch controller controls the circuit between the common voltage pin and the common electrode to be conductive based on the first switch control signal; The source driver controls the transmission of data signals to the plurality of sub-pixels, controlling the source driver to output the second data signal based on the first data output enable signal; 9. The method for driving a display device according to claim 8.

10. A display device, a display panel, a source driver, and a voltage generator; the display panel includes a first substrate, a second substrate disposed opposite to the first substrate, and a liquid crystal layer disposed between the first substrate and the second substrate, the first substrate including a plurality of sub-pixels arranged in an array, and the second substrate including a common electrode; the source driver is electrically connected to the first substrate and is used to transmit data signals to the plurality of sub-pixels, the data signals including a first data signal before a first time and a second data signal after the first time, the second data signal being used to control luminance of the sub-pixels of the display panel; the voltage generator is electrically connected to the display panel and is used to transmit a common voltage signal to the common electrode after the first time; A display device characterized by:

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