Display device and electronic device

Abstract

To provide a display device capable of improving display quality by reducing coupling noise generated between wirings.SOLUTION: The display device includes a base layer including a display area in which a plurality of pixels are disposed and a non-display area disposed around the display area, a gate driver disposed in the non-display area and outputting a write scan signal, a scan line applying the write scan signal to the plurality of pixels and including a vertical line extending from the gate driver in a first direction and a horizontal line electrically connected to the vertical line and extending in a second direction crossing the first direction, and a shielding pattern overlapping the vertical line on a plane.SELECTED DRAWING: Figure 9A

Description

[Technical Field]

[0001] The present invention relates to a display device, and more particularly to a display device with improved display quality in a display area. [Background technology]

[0002] Generally, electronic devices that provide images to users, such as smartphones, digital cameras, laptops, navigation systems, and smart televisions, include a display device for displaying the images. The display device generates an image and provides the generated image to the user through a display screen.

[0003] The display device includes a plurality of pixels for generating an image, a scan driving circuit for applying scan signals to the pixels, a data driving unit for applying data voltages to the pixels, and an emission driving unit for applying emission signals to the pixels. The pixels receive the data voltages in response to the scan signals, and emit light of a brightness corresponding to the data voltages in response to the emission signals, thereby displaying an image.

[0004] A pixel can display moving and still images. When a pixel displays moving images, it can receive continuously updated images. When a pixel displays still images, it can maintain the image it was initially provided with and not receive any images thereafter. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Korean Patent Publication No. 2022-0063870 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a display device capable of improving display quality by reducing coupling noise occurring between wirings. [Means for solving the problem]

[0007] A display device according to an embodiment of the present invention includes a base layer including a display area in which a plurality of pixels are arranged and a non-display area arranged around the display area; a gate driver arranged in the non-display area and outputting a write scan signal; scan lines including vertical lines extending from the gate driver in a first direction and horizontal lines electrically connected to the vertical lines and extending in a second direction intersecting the first direction, and a shielding pattern overlapping the vertical lines in a plane; and a gate driver arranged in the non-display area and outputting a write scan signal.

[0008] According to an embodiment of the present invention, a display device includes a base layer including a display area and a non-display area disposed around the display area, a driving element layer disposed on the base layer, a plurality of light emitting elements disposed on the driving element layer, each light emitting element including a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer, and a gate driver disposed in the non-display area and outputting a write scan signal. The driving element layer includes a scan line electrically connected to the gate driver, a first transistor connected to the second electrode, a second transistor connected to the second electrode, a shielding pattern overlapping at least a portion of the scan line and a drain pattern of the second transistor in a plane.

[0009] According to an embodiment of the present invention, an electronic device includes a display device, an electronic module overlapping the display device, and a housing accommodating the display device. The display device includes a base layer including a display area in which a plurality of pixels are arranged and a non-display area arranged around the display area, a gate driver arranged in the non-display area and outputting a write scan signal, scan lines including vertical lines extending from the gate driver in a first direction and horizontal lines electrically connected to the vertical lines and extending in a second direction intersecting the first direction, and a shielding pattern overlapping the vertical lines in a plane. [Effects of the Invention]

[0010] Coupling noise caused by fluctuations in an electric field may occur between the second drain electrode pattern and the scan line, which are disposed on the same layer but are not electrically connected to each other. The display device of the present invention may include a shielding pattern that overlaps the second drain electrode pattern and the scan line in a plane and to which a constant voltage is applied. By shielding the second drain electrode pattern and the scan line using the shielding pattern to which the constant voltage is applied, coupling noise formed between the second drain electrode pattern and the scan line may be reduced or eliminated. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a perspective view of an electronic device according to one embodiment of the present invention; [Figure 2A] 2 is a cross-sectional view of a display device included in the electronic device of FIG. 1. [Figure 2B] FIG. 2B is a cross-sectional view of the display panel shown in FIG. 2A. [Figure 3] 1 is a block diagram of a display device according to an embodiment of the present invention; [Figure 4A] FIG. 2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. [Figure 4B] FIG. 2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. [Figure 4C] FIG. 2 is an equivalent circuit diagram of a pixel according to an embodiment of the present invention. [Figure 5] 1 is a simplified plan view of a display panel according to an embodiment of the present invention; [Figure 6] 3A and 3B are plan views showing one light emitting unit and one pixel driving unit connected thereto according to an embodiment of the present invention; [Figure 7A] 2 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present invention; FIG. [Figure 7B] 2 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present invention; FIG. [Figure 7C] 2 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present invention; FIG. [Figure 7D] 2 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present invention; FIG. [Figure 8] 2 is an enlarged plan view of a partial area of ​​a display panel according to an embodiment of the present invention; FIG. [Figure 9A] 7B is a cross-sectional view of a display panel according to an embodiment of the present invention, showing a portion corresponding to line II' in FIG. 7A. [Figure 9B] FIG. 9B is an enlarged cross-sectional view of a region BB′ in FIG. 9A. [Figure 10A] 7B is a cross-sectional view of a display panel according to another embodiment of the present invention, showing a portion corresponding to line II' in FIG. 7A. [Figure 10B] 7B is a cross-sectional view of a display panel according to another embodiment of the present invention, showing a portion corresponding to line II' in FIG. 7A. [Figure 11A] 1 is a simplified plan view of a display panel according to an embodiment of the present invention; [Figure 11B] FIG. 11B is an enlarged cross-sectional view of a CC′ region in FIG. 11A. [Figure 11C] FIG. 11B is an enlarged cross-sectional view of a region DD′ in FIG. 11A. [Figure 11D] 2 is a block diagram of a gate driver according to an embodiment of the present invention; [Figure 12] 1 is a simplified plan view of a display panel according to an embodiment of the present invention; [Figure 13A] 1 is a process diagram illustrating the arrangement order of circuit layers according to an embodiment of the present invention. [Figure 13B] 1 is a process diagram illustrating the arrangement order of circuit layers according to an embodiment of the present invention. [Figure 13C] 1 is a process diagram illustrating the arrangement order of circuit layers according to an embodiment of the present invention. [Figure 13D] 1 is a process diagram illustrating the arrangement order of circuit layers according to an embodiment of the present invention. [Figure 13E] 1 is a process diagram illustrating the arrangement order of circuit layers according to an embodiment of the present invention. [Figure 13F]1 is a process diagram illustrating the arrangement order of circuit layers according to an embodiment of the present invention. [Figure 13G] 1 is a process diagram illustrating the arrangement order of circuit layers according to an embodiment of the present invention. [Figure 14] 1 is a perspective view of an electronic device according to an embodiment of the present invention. [Figure 15] 15 is a view showing a folded state of the electronic device shown in FIG. 14. [Figure 16] FIG. 15 is an exploded perspective view of the electronic device shown in FIG. 14. [Figure 17] FIG. 15 is a block diagram of the electronic device shown in FIG. 14. [Figure 18] 1 is a diagram illustrating an electronic device according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0012] Because the present invention can be modified in various ways and can have various forms, specific embodiments are shown by way of example in the drawings and described in detail herein, but it should be understood that this is not to limit the invention to the particular form disclosed, but rather to include all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention.

[0013] In this specification, when a certain component (or region, layer, portion, etc.) is described as being "on," "coupled," or "bonded" to another component, it means that it can be directly disposed / coupled / bonded to the other component, or that a third component can be disposed therebetween.

[0014] The same reference numerals refer to the same elements, and in the drawings, thickness, proportions, and dimensions of elements are exaggerated for the purpose of efficiently explaining the technical contents.

[0015] "And / or" includes all combinations of one or more that the associated constructs may define.

[0016] Terms such as "first," "second," etc. may be used to describe various components, but the components should not be limited by these terms. These terms are used only to distinguish one component from another. For example, a first component may be referred to as a "second component," and similarly, a second component may be referred to as a "first component" without departing from the scope of the present invention. A singular expression includes a plural expression unless the context clearly dictates otherwise.

[0017] Furthermore, terms such as "under," "below," "on," and "above" are used to describe the relationship between components shown in the drawings. These terms are relative concepts and are described based on the directions shown in the drawings.

[0018] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this invention belongs. Furthermore, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the context of the relevant art, and unless interpreted as ideal or overly formal, they are expressly defined herein.

[0019] The use of terms such as "comprise" or "have" is intended to specify the presence of a stated feature, number, step, operation, component, part, or combination thereof, and should be understood as not precluding the possible presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0020] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[0021] Fig. 1 is a perspective view of an electronic device according to an embodiment of the present invention, Fig. 2A is a cross-sectional view of a display device included in the electronic device of Fig. 1, and Fig. 2B is a cross-sectional view of the display panel shown in Fig. 2A.

[0022] 1, the electronic device ED according to an embodiment of the present invention may have a rectangular shape having a short side extending in a first direction DR1 and a long side extending in a second direction DR2 intersecting the first direction DR1, but is not limited thereto, and the electronic device ED may have various shapes such as a circle and a polygon.

[0023] Hereinafter, a direction substantially perpendicular to a plane defined by the first direction DR1 and the second direction DR2 is defined as a third direction DR3. Also, in this specification, "in a plan view" can be defined as a state viewed from the third direction DR3.

[0024] The top surface of the electronic device ED may be defined as a display surface DS, and the display surface DS may have a plane defined by a first direction DR1 and a second direction DR2. An image IM generated by the electronic device ED may be provided to a user through the display surface DS.

[0025] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may display an image, while the non-display area NDA may not display an image. The non-display area NDA may surround the display area DA and define a border of the electronic device ED that may be printed in a specific color.

[0026] Although not shown, the electronic device ED may include a display device DD (see FIG. 2A), which will be described in more detail below.

[0027] 2A , the display device DD may include a display module DM, an anti-reflection layer RPL disposed on the display module DM, and a panel protection layer PPL disposed below the display module DM. The display module DM may include a display panel DP and a sensing layer ISL disposed on the display panel DP. The display panel DP may be a flexible panel. For example, the display panel DP may include a flexible substrate and a plurality of elements disposed on the flexible substrate.

[0028] The display panel DP according to an embodiment of the present invention is an emissive display panel and is not particularly limited. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The light-emitting layer of an organic light-emitting display panel may include an organic light-emitting material. The light-emitting layer of an inorganic light-emitting display panel may include quantum dots, quantum rods, etc. Hereinafter, the display panel DP will be described as an organic light-emitting display panel.

[0029] The sensing layer ISL may include a plurality of sensor units (not shown) for sensing an external input in a capacitive manner. The sensing layer ISL may be formed directly on the display panel DP without a separate adhesive layer during the manufacture of the display device DD.

[0030] The anti-reflection layer RPL may be disposed on the sensing layer ISL. The anti-reflection layer RPL may be directly formed on the sensing layer ISL during manufacturing of the display device DD. The anti-reflection layer RPL may be defined as an external light anti-reflection film. The anti-reflection layer RPL may reduce the reflectance of external light incident from above the electronic device ED toward the display panel DP.

[0031] For example, the sensing layer ISL may be formed directly on the display panel DP, and the anti-reflection layer RPL may be formed directly on the sensing layer ISL, but the embodiment of the present invention is not limited thereto. For example, the sensing layer ISL may be manufactured separately and attached to the display panel DP by an adhesive layer, and the anti-reflection layer RPL may be manufactured separately and attached to the sensing layer ISL by an adhesive layer.

[0032] The panel protection layer PPL may be disposed below the display panel DP. The panel protection layer PPL may protect the lower portion of the display panel DP. The panel protection layer PPL may include a flexible plastic material. For example, the panel protection layer PPL may include polyethylene terephthalate (PET).

[0033] Referring to FIG. 2B, the display panel DP may include a base layer BL, a driving element layer DDL arranged on the base layer BL, a light-emitting element layer LDL arranged on the driving element layer DDL, and an encapsulation layer ECL arranged on the light-emitting element layer LDL.

[0034] The base layer BL may include a display area DA and a non-display area NDA surrounding the display area DA. The base layer BL may include a flexible plastic material such as glass or polyimide (PI). The light emitting element layer LDL may be disposed on the display area DA.

[0035] A plurality of pixels may be disposed on the driving element layer DDL and the light emitting element layer LDL, and each pixel may include a transistor disposed on the driving element layer DDL and a light emitting element disposed on the light emitting element layer LDL and connected to the transistor.

[0036] The encapsulation layer ECL may be disposed on the driving element layer DDL to cover the light emitting element layer LDL, and may protect the pixels from moisture, oxygen, and external foreign substances.

[0037] FIG. 3 is a block diagram of a display device according to an embodiment of the present invention.

[0038] Referring to FIG. 3, the display device DD may include a display panel DP, panel drivers GDC and DDC, a power supply PWS, and a timing controller TC. In this embodiment, the display panel DP is described as an emissive display panel. The emissive display panel may include an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. In the following embodiments, an organic light-emitting display panel will be described in detail. The panel drivers GDC and DDC may include a gate driver GDC and a data driver DDC. Although FIG. 3 illustrates the gate driver GDC and the data driver DDC being disposed on the other side of the display panel DP, the gate driver GDC and the data driver DDC may also be disposed on one side of the display panel DP.

[0039] The display panel DP may include scan lines GWL1-GWLn, GCL1-GCLn, GIL1-GILn, GBL1-GBLn, GRL1-GRLn, light emitting lines ESL1-ESLn, and data lines DL1-DLm. The display panel DP may include a plurality of pixels connected to the scan lines GWL1-GWLn, GCL1-GCLn, GIL1-GILn, GBL1-GBLn, GRL1-GRLn, light emitting lines ESL1-ESLn, and data lines DL1-DLm (where m and n are integers greater than 1).

[0040] For example, a pixel PXij (where i and j are integers greater than 1) located on the ith horizontal line (or the ith pixel row) and the jth vertical line (or the jth pixel column) may be connected to the ith first scan line GWLi (or the write scan line), the ith second scan line GCLi (or the compensation scan line), the ith third scan line GILi (or the first initialization scan line), the ith fourth scan line GBLi (or the second initialization scan line), the ith fifth scan line GRLi (or the reset scan line), the jth data line DLj, and the ith emission line ESLi.

[0041] The pixel PXij may include a plurality of light emitting elements, a plurality of transistors, and a plurality of capacitors, and may receive a first power supply voltage VDD, a second power supply voltage VSS, a third power supply voltage VREF (or a reference voltage), a fourth power supply voltage VINT1 (or a first initialization voltage), a fifth power supply voltage VINT2 (or a second initialization voltage), and a sixth power supply voltage VCOMP (or a compensation voltage) through a power supply unit PWS.

[0042] The first and second power supply voltages VDD and VSS are set to have voltage values ​​such that a current flows through the light emitting device to emit light. For example, the first power supply voltage VDD may be set to a voltage higher than the second power supply voltage VSS.

[0043] The third power supply voltage VREF may be a voltage for initializing the gate of the driving transistor included in the pixel PXij. The third power supply voltage VREF may be used to implement a predetermined gray level by using a voltage difference with the data signal. To this end, the third power supply voltage VREF may be set to a predetermined voltage within the voltage range of the data signal.

[0044] The fourth power supply voltage VINT1 may be a voltage for initializing a capacitor included in the pixel PXij. The fourth power supply voltage VINT1 may be set to a voltage lower than the third power supply voltage VREF. For example, the fourth power supply voltage VINT1 may be set to a voltage lower than the difference between the third power supply voltage VREF and the threshold voltage of the driving transistor, i.e., a voltage lower than the third power supply voltage VREF by the threshold voltage of the driving transistor. However, the present invention is not limited thereto.

[0045] The fifth power supply voltage VINT2 may be a voltage for initializing the cathode of the light emitting element included in the pixel PXij. The fifth power supply voltage VINT2 may be set to a voltage lower than the first power supply voltage VDD or the fourth power supply voltage VINT1, or may be set to a voltage similar to or the same as the third power supply voltage VREF, but is not limited thereto. The fifth power supply voltage VINT2 may be set to a voltage similar to or the same as the first power supply voltage VDD.

[0046] The sixth power supply voltage VCOMP can supply a predetermined current to the driving transistor when the threshold voltage of the driving transistor is compensated.

[0047] 1 illustrates that the first to sixth power supply voltages VDD, VSS, VREF, VINT1, VINT2, and VCOMP are all supplied by the power supply unit PWS, but the present invention is not limited to this. For example, the first power supply voltage VDD and the second power supply voltage VSS may all be supplied regardless of the structure of the pixel PXij, and at least one of the third power supply voltage VREF, the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP may not be supplied depending on the structure of the pixel PXij.

[0048] In the embodiment of the present invention, the signal lines connected to the pixels PXij can be variously set in accordance with the circuit structure of the pixels PXij.

[0049] The gate driver GDC receives a first control signal SCS from the timing controller TC, and can supply scan signals to each of the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, and the fifth scan lines GRL1 to GRLn based on the first control signal SCS.

[0050] The scan signal may be set to a voltage that can turn on a transistor to which the scan signal is supplied. For example, a scan signal supplied to a P-type transistor may be set to a logic low level, and a scan signal supplied to an N-type transistor may be set to a logic high level. Hereinafter, the meaning of "a scan signal is supplied" may be understood to mean that the scan signal is supplied to a logic level that turns on a transistor controlled thereby.

[0051] In addition, the gate driver GDC receives a second control signal ECS from the timing controller TC and supplies light emitting signals to the light emitting lines ESL1 to ESLn based on the second control signal ECS. For example, the light emitting signals may be sequentially supplied to the light emitting lines ESL1 to ESLn.

[0052] The transistors connected to the light emitting lines ESL1 to ESLn of the present invention may be N-type transistors. In this case, the light emitting signals supplied to the light emitting lines ESL1 to ESLn may be set as gate-off voltages. The transistors receiving the light emitting signals may be turned off when the light emitting signals are supplied, and may be turned on otherwise.

[0053] The second control signal ECS includes a light emission start signal and a clock signal, and the gate driver GDC can be implemented as a shift register that sequentially shifts the light emission start signal in pulse form using the clock signal to sequentially generate and output light emission signals in pulse form.

[0054] According to an embodiment of the present invention, a single gate driver GDC may be provided. As a result, the non-display area NDA (see FIG. 1) where the gate driver GDC is disposed can be reduced. That is, a display area DA (see FIG. 1) with a sufficient area can be provided. However, the present invention is not limited thereto. According to an embodiment, a plurality of scan drivers may be provided to supply scan signals to the first scan lines GWL1 to GWLn, the second scan lines GCL1 to GCLn, the third scan lines GIL1 to GILn, the fourth scan lines GBL1 to GBLn, and the fifth scan lines GRL1 to GRLn, respectively, and a light emitting driver may be provided to supply light emitting signals to the light emitting lines ESL1 to ESLn.

[0055] The data driver DDC can receive the third control signal DCS and image data RGB from the timing controller TC. The data driver DDC can convert the digital image data RGB into analog data signals (i.e., data signals). The data driver DDC can supply data signals to the data lines DL1 to DLm in response to the third control signal DCS.

[0056] The third control signal DCS may include a data enable signal instructing output of a valid data signal, a horizontal start signal, a data clock signal, etc. For example, the data driver DDC may include a shift register that shifts the horizontal start signal in synchronization with the data clock signal to generate a sampling signal, a latch that latches image data RGB in response to the sampling signal, a digital-to-analog converter (or decoder) that converts the latched image data (e.g., digital data) into an analog data signal, and a buffer (or amplifier) ​​that outputs the data signal to the data lines DL1 to DLm.

[0057] The power supply unit PWS can supply the first power supply voltage VDD, the second power supply voltage VSS, and the third power supply voltage VREF to the display panel DP for driving the pixels PXij, and can also supply at least one voltage from the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP to the display panel DP.

[0058] As an example, the power supply unit PWS may supply the first power supply voltage VDD, the second power supply voltage VSS, the third power supply voltage VREF, the fourth power supply voltage VINT1, the fifth power supply voltage VINT2, and the sixth power supply voltage VCOMP to the display panel DP via a first power supply line VDL (see FIG. 4A), a second power supply line VSL (see FIG. 4A), a third power supply line (or a reference voltage line VRL, see FIG. 4A), a fourth power supply line (or a first initialization voltage line VIL1, see FIG. 4A), a fifth power supply line (or a second initialization voltage line VIL2, see FIG. 4A), and a sixth power supply line (or a compensation voltage line VCL, see FIG. 4A), which are not shown.

[0059] The power supply unit PWS can be implemented as a power management integrated circuit, but is not limited to this.

[0060] The timing controller TC can generate a first control signal SCS, a second control signal ECS, a third control signal DCS, and a fourth control signal PCS based on the input image data IRGB, a synchronization signal Sync (e.g., a vertical synchronization signal, a horizontal synchronization signal, etc.), a data enable signal DE, a clock signal, etc. The first control signal SCS and the second control signal ECS can be supplied to the gate driver GDC, the third control signal DCS can be supplied to the data driver DDC, and the fourth control signal PCS can be supplied to the power supply PWS. The timing controller TC can rearrange the input image data IRGB in accordance with the arrangement of the pixels PXij in the display panel DP to generate image data RGB (or frame data).

[0061] The gate driver GDC, data driver DDC, power supply PWS, and / or timing controller TC may be directly formed on the display panel DP or may be provided in the form of separate driver chips and connected to the display panel DP. Furthermore, at least two of the gate driver GDC, data driver DDC, power supply PWS, and timing controller TC may be provided on a single driver chip. For example, the data driver DDC and timing controller TC may be provided on a single driver chip.

[0062] Although the display device DD according to an embodiment has been described above with reference to FIGS. 1 to 3, the display device of the present invention is not limited thereto. Signal lines may be added or omitted depending on the pixel configuration. Furthermore, the connection relationship between a pixel and a signal line may be changed. When one of the signal lines is omitted, another signal line may replace the omitted signal line.

[0063] 4A, 4B, and 4C are equivalent circuit diagrams of pixels PXij, PXij-1, and PXij-2 connected to an i-th first scan line GWLi (hereinafter, referred to as the first scan line) and a j-th data line DLj (hereinafter, referred to as the data line), respectively, according to an embodiment of the present invention.

[0064] 4A, the pixel PXij includes a light emitting element LD and a pixel driving circuit PDC. The light emitting element LD is connected to a first power line VDL and the pixel driving circuit PDC.

[0065] The pixel driver PDC may be connected to a plurality of scan lines GWLi, GCLi, GILi, GBLi, GRLi, data lines DLj, light emitting lines ESLi, and a plurality of power supply voltage lines VDL, VSL, VIL1, VIL2, VRL, and VCL. The pixel driver PDC may include first to eighth transistors T1, T2, T3, T4, T5, T6, T7, and T8, a first capacitor C1, and a second capacitor C2. Hereinafter, a case will be described in which the first to eighth transistors T1, T2, T3, T4, T5, T6, T7, and T8 are all N-type transistors. However, the present invention is not limited thereto. Some of the first to eighth transistors T1 to T8 may be N-type transistors and the rest may be P-type transistors, or each of the first to eighth transistors T1 to T8 may be P-type transistors. The present invention is not limited to any one embodiment.

[0066] The gate of the first transistor T1 may be connected to a first node N1. The first electrode of the first transistor T1 may be connected to a second node N2, and the second electrode of the first transistor T1 may be connected to a third node N3. The first transistor T1 may be a driving transistor. The first transistor T1 may control a driving current ILD flowing from the first power supply line VDL to the second power supply line VSL via the light emitting element LD in response to the voltage of the first node N1. At this time, the first power supply voltage VDD may be set to a voltage having a higher potential than the second power supply voltage VSS.

[0067] In this specification, "electrically connecting a transistor to a signal line or between transistors" means "the source, drain, and gate of a transistor are integral with the signal line or are connected through a connecting electrode."

[0068] The second transistor T2 may include a gate connected to the write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1. The second transistor T2 may supply a data signal DATA to the first node N1 in response to a write scan signal GW transmitted through the write scan line GWLi. When the write scan signal GW is supplied to the write scan line GWLi, the second transistor T2 may be turned on to electrically connect the data line DLj to the first node N1.

[0069] The third transistor T3 may be connected between the first node N1 and a reference voltage line VRL. A first electrode of the third transistor T3 may receive the reference voltage VREF through the reference voltage line VRL, and a second electrode of the third transistor T3 may be connected to the first node N1. In this embodiment, a gate of the third transistor T3 may receive a reset scan signal GR through an i-th fifth scan line GRLi (hereinafter, a reset scan line). When the reset scan signal GR is supplied to the reset scan line GRLi, the third transistor T3 is turned on to provide the reference voltage VREF to the first node N1.

[0070] The fourth transistor T4 may be connected between the third node N3 and the first initialization voltage line VIL1. A first electrode of the fourth transistor T4 may be connected to the third node N3, and a second electrode of the fourth transistor T4 may be connected to the first initialization voltage line VIL1 that provides the first initialization voltage VINT1. The fourth transistor T4 may be referred to as a first initialization transistor. A gate of the fourth transistor T4 may receive a first initialization scan signal GI through an i-th third scan line GILi (hereinafter, referred to as the first initialization scan line). When the first initialization scan signal GI is provided to the first initialization scan line GILi, the fourth transistor T4 may be turned on to provide the first initialization voltage VINT1 to the third node N3.

[0071] The fifth transistor T5 may be connected between the compensation voltage line VCL and the second node N2. A first electrode of the fifth transistor T5 receives the compensation voltage VCOMP through the compensation voltage line VCL, and a second electrode of the fifth transistor T5 is connected to the second node N2 and electrically connected to the first electrode of the first transistor T1. A gate of the fifth transistor T5 may receive a compensation scan signal GC through an i-th second scan line GCLi (hereinafter, a compensation scan line). When the compensation scan signal GC is supplied to the compensation scan line GCLi, the fifth transistor T5 is turned on to provide the compensation voltage VCOMP to the second node N2, thereby compensating the threshold voltage of the first transistor T1 during the compensation period.

[0072] The sixth transistor T6 may be connected between the first transistor T1 and the light emitting element LD. Specifically, the gate of the sixth transistor T6 may receive an emission signal EM through an i-th emission line ESLi (hereinafter, referred to as an emission line). A first electrode of the sixth transistor T6 may be connected to the cathode of the light emitting element LD through a fourth node N4, and a second electrode of the sixth transistor T6 may be connected to the first electrode of the first transistor T1 through a second node N2. The sixth transistor T6 may be referred to as a first emission control transistor. When an emission signal EM is supplied to the emission line ESLi, the sixth transistor T6 may be turned on to electrically connect the light emitting element LD and the first transistor T1.

[0073] The seventh transistor T7 may be connected between the second power line VSL and the third node N3. A first electrode of the seventh transistor T7 may be connected to the second electrode of the first transistor T1 through the third node N3, and a second electrode of the seventh transistor T7 may receive the second power voltage VSS through the second power line VSL. A gate of the seventh transistor T7 may be electrically connected to the light-emitting line ESLi. The seventh transistor T7 may be referred to as a second light-emitting control transistor. When an light-emitting signal EM is supplied to the light-emitting line ESLi, the seventh transistor T7 is turned on to electrically connect the second electrode of the first transistor T1 to the second power line VSL.

[0074] In the present embodiment, the sixth transistor T6 and the seventh transistor T7 are illustrated as being connected to the same emission line ESLi and turned on by the same emission signal EM, but this is shown by way of example only, and the sixth transistor T6 and the seventh transistor T7 may be turned on independently by different signals that are distinct from each other. Also, in the pixel driver PDC according to an embodiment of the present invention, either the sixth transistor T6 or the seventh transistor T7 may be omitted.

[0075] The eighth transistor T8 may be connected between the second initialization voltage line VIL2 and the fourth node N4. That is, the eighth transistor T8 may include a gate connected to the i-th fourth scan line GBLi (hereinafter, the second initialization scan line), a first electrode connected to the second initialization voltage line VIL2, and a second electrode connected to the fourth node N4. The eighth transistor T8 may be referred to as a second initialization transistor. The eighth transistor T8 may supply the second initialization voltage VINT2 to the fourth node N4 corresponding to the cathode of the light emitting element LD in response to the second initialization scan signal GB transmitted through the second initialization scan line GBLi. The cathode of the light emitting element LD may be initialized by the second initialization voltage VINT2.

[0076] In this embodiment, some of the second to eighth transistors T2, T3, T4, T5, T6, T7, and T8 may be turned on simultaneously by the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 may be turned on simultaneously by the same scan signal. For example, the eighth transistor T8 and the fifth transistor T5 may be operated by the same compensation scan signal GC. The eighth transistor T8 and the fifth transistor T5 may be turned on / off simultaneously by the same compensation scan signal GC. In this case, the compensation scan line GCLi and the second initialization scan line GBLi may be provided as a substantially single scan line. Therefore, the cathode initialization of the light emitting element LD and the threshold voltage compensation of the first transistor T1 may be performed at the same timing. However, this is merely an example and is not limited to any one embodiment.

[0077] Furthermore, according to the present invention, the cathode initialization of the light emitting device LD and the threshold voltage compensation of the first transistor T1 can be performed by applying the same power supply voltage. For example, the compensation voltage line VCL and the second initialization voltage line VIL2 can be provided as a substantially single power supply voltage line. In this case, the cathode initialization operation and the compensation operation of the driving transistor are performed with a single power supply voltage, which can simplify the design of the driving unit. However, this is merely an example, and the present invention is not limited to any one embodiment.

[0078] The first capacitor C1 may be disposed between the first node N1 and the third node N3. The first capacitor C1 may store a differential voltage between the first node N1 and the third node N3. The first capacitor C1 may be referred to as a storage capacitor.

[0079] The second capacitor C2 may be disposed between the third node N3 and the second power line VSL. That is, one electrode of the second capacitor C2 may be connected to the second power line VSL, which receives the second power voltage VSS, and the other electrode of the second capacitor C2 may be connected to the third node N3. The second capacitor C2 may store a charge corresponding to the voltage difference between the second power voltage VSS and the third node N3. The second capacitor C2 may be referred to as a hold capacitor. The second capacitor C2 may have a higher storage capacitance than the first capacitor C1. Therefore, the second capacitor C2 may minimize a voltage change at the third node N3 in response to a voltage change at the first node N1.

[0080] In this embodiment, the light emitting element LD may be connected to the pixel driver PDC through a fourth node N4. The light emitting element LD may include an anode connected to the first power line VDL and a cathode facing the anode. In this embodiment, the light emitting element LD may be connected to the pixel driver PDC through the cathode. That is, in the pixel PXij according to the present invention, the connection node between the light emitting element LD and the pixel driver PDC is the fourth node N4, and the fourth node N4 may correspond to the connection node between the first electrode of the sixth transistor T6 and the cathode of the light emitting element LD. Therefore, the potential of the fourth node N4 may substantially correspond to the cathode potential of the light emitting element LD.

[0081] Specifically, the anode of the light emitting element LD is connected to the first power line VDL and receives the first power voltage VDD, which is a constant voltage, and the cathode is connected to the first transistor T1 through the sixth transistor T6. That is, in this embodiment, the first to eighth transistors T1 to T8 are N-type transistors, and the potential of the third node N3 corresponding to the source of the first transistor T1, which is the driving transistor, is not directly affected by the characteristics of the light emitting element LD. Therefore, even if degradation of the light emitting element LD occurs, the influence on the transistors constituting the pixel driver PDC, particularly the gate-source voltage Vgs of the driving transistor, can be reduced. That is, since the amount of change in driving current due to degradation of the light emitting element LD is reduced, image retention defects of the display panel that occur over time can be reduced and the lifespan can be improved.

[0082] Alternatively, as shown in FIG. 4B, pixel PXij-1 may include a pixel driver PDC-1 including two transistors T1 and T2 and a first capacitor C1. The pixel driver PDC-1 may be connected to the light emitting element LD, the write scan line GWLi, the data line DLj, and the second power line VSL. The pixel driver PDC-1 shown in FIG. 4B may correspond to the pixel driver PDC shown in FIG. 4A, with the third to eighth transistors T3 to T8 and the second capacitor C2 omitted.

[0083] Each of the first and second transistors T1 and T2 may be an N-type or P-type transistor. In this embodiment, a case where each of the first and second transistors T1 and T2 is an N-type transistor will be described as an example.

[0084] The first transistor T1 may include a gate connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The second node N2 may be a node connected to a first power line VDL, and the third node N3 may be a node connected to a second power line VSL. The first transistor T1 is connected to the light emitting element LD through the second node N2 and to the second power line VSL through the third node N3. The first transistor T1 may be a driving transistor.

[0085] The second transistor T2 may include a gate receiving a write scan signal GW through a write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1, and may provide a data signal DATA to the first node N1 in response to the write scan signal GW transmitted through the write scan line GWLi.

[0086] The first capacitor C1 may include an electrode connected to the first node N1 and an electrode connected to the third node N3, and may store a data signal DATA transmitted to the first node N1.

[0087] The light emitting device LD may include an anode and a cathode. In this embodiment, the anode of the light emitting device LD is connected to the first power line VDL, and the cathode is connected to the pixel driving unit PDC-1 through a second node N2. In this embodiment, the cathode of the light emitting device LD may be connected to the first transistor T1. The light emitting device LD may emit light in response to the amount of current flowing through the first transistor T1 of the pixel driving unit PDC-1.

[0088] In this embodiment, where the first and second transistors T1 and T2 are N-type transistors, the second node N2, to which the cathode of the light emitting device LD and the pixel driver PDC-1 are connected, may correspond to the drain of the first transistor T1. That is, it is possible to prevent a change in the gate-source voltage Vgs of the first transistor T1 due to the light emitting device LD. Therefore, since the amount of change in driving current due to deterioration of the light emitting device LD is reduced, image retention defects of the display panel that occur over time are reduced and the lifespan of the display panel is improved.

[0089] Alternatively, as shown in FIG. 4C, pixel PXij-2 may include a pixel driver PDC-2 including six transistors T1, T2, T3, T4a, T5a, and T6a and two capacitors C1 and C2.

[0090] The pixel driving unit PDC-2 may be connected to the light emitting element LD, the write scan line GWLi, the reset scan line GRLi, the compensation scan line GCLi, the i-th first light emitting line ESL1i (hereinafter referred to as the first light emitting line), the i-th second light emitting line ESL2i (hereinafter referred to as the second light emitting line), the data line DLj, the first power supply line VDL, the second power supply line VSL, the third power supply line VRL, and the initialization voltage line VIL.

[0091] The pixel driver PDC-2 shown in Figure 4C may have a structure similar to that of the pixel driver PDC shown in Figure 4A, with the fourth transistor T4 and the fifth transistor T5 omitted. The area of ​​the pixel driver PDC-2 shown in Figure 4C is smaller than the area of ​​the pixel driver PDC-1 shown in Figure 4A, making it easier to implement high resolution.

[0092] Each of the first to sixth transistors T1, T2, T3, T4a, T5a, and T6a may be an N-type or a P-type transistor. In this embodiment, a case where each of the first to sixth transistors T1, T2, T3, T4a, T5a, and T6a is an N-type transistor will be described as an example.

[0093] The first transistor T1 may include a gate connected to a first node N1, a first electrode connected to a second node N2, and a second electrode connected to a third node N3. The second node N2 may be a node connected to a first power line VDL, and the third node N3 may be a node connected to a second power line VSL. The first transistor T1 is connected to the light emitting element LD through the second node N2 and to the second power line VSL through the third node N3. The first transistor T1 may be a driving transistor.

[0094] The second transistor T2 may include a gate receiving a write scan signal GW through a write scan line GWLi, a first electrode connected to the data line DLj, and a second electrode connected to the first node N1, and may provide a data signal DATA to the first node N1 in response to the write scan signal GW transmitted through the write scan line GWLi.

[0095] The third transistor T3 may be connected between the first node N1 and a reference voltage line VRL. A first electrode of the third transistor T3 may receive the reference voltage VREF through the reference voltage line VRL, and a second electrode of the third transistor T3 may be connected to the first node N1. In this embodiment, a gate of the third transistor T3 may receive a reset scan signal GR through a reset scan line GRLi. When the reset scan signal GR is supplied to the reset scan line GRLi, the third transistor T3 is turned on to provide the reference voltage VREF to the first node N1.

[0096] The fourth transistor T4a may be connected between the first transistor T1 and the light emitting element LD. Specifically, the gate of the fourth transistor T4a may receive a first light emitting signal EM1 through a first light emitting line ESL1i. A first electrode of the fourth transistor T4a may be connected to the cathode of the light emitting element LD through a fourth node N4, and a second electrode of the fourth transistor T4a may be connected to the first electrode of the first transistor T1 through a second node N2. The fourth transistor T4a may be referred to as a first light emitting control transistor. When the first light emitting signal EM1 is provided to the first light emitting line ESL1i, the fourth transistor T4a may be turned on to electrically connect the light emitting element LD and the first transistor T1.

[0097] The fifth transistor T5a may be connected between the second power line VSL and the third node N3. A first electrode of the fifth transistor T5a may be connected to the second electrode of the first transistor T1 through the third node N3, and a second electrode of the fifth transistor T5a may receive the second power voltage VSS through the second power line VSL. A gate of the fifth transistor T5a may be electrically connected to the second light-emitting line ESL2i. The fifth transistor T5a may be referred to as a second light-emitting control transistor. When a second light-emitting signal EM2 is provided to the second light-emitting line ESL2i, the fifth transistor T5a is turned on to electrically connect the second electrode of the first transistor T1 to the second power line VSL.

[0098] In this embodiment, the fourth transistor T4a and the fifth transistor T5a are connected to first and second light-emitting lines ESL1i and ESL2i, respectively, and may be turned on by first and second light-emitting signals EM1 and EM2, respectively. That is, the fourth transistor T4a and the fifth transistor T5a may be turned on independently. However, this is merely an example and is not limiting. For example, in an embodiment of the present invention, the fourth transistor T4a and the fifth transistor T5a may be connected to the same light-emitting line and controlled by the same light-emitting signal. In addition, in the pixel driver PDC-2 according to an embodiment of the present invention, either the fourth transistor T4a or the fifth transistor T5a may be omitted.

[0099] The sixth transistor T6a may be connected between the initialization voltage line VIL and the fourth node N4. That is, the sixth transistor T6a may include a gate connected to the compensation scan line GCLi, a first electrode connected to the initialization voltage line VIL, and a second electrode connected to the fourth node N4. The sixth transistor T6a may be referred to as an initialization transistor. The sixth transistor T6a may supply the initialization voltage VINT to the fourth node N4 corresponding to the cathode of the light emitting element LD in response to the compensation scan signal GC transmitted through the compensation scan line GCLi. The cathode of the light emitting element LD may be initialized by the initialization voltage VINT.

[0100] The first capacitor C1 may be disposed between the first node N1 and the third node N3. The first capacitor C1 may store a differential voltage between the first node N1 and the third node N3. The first capacitor C1 may be referred to as a storage capacitor.

[0101] The second capacitor C2 may be disposed between the third node N3 and the second power line VSL. That is, one electrode of the second capacitor C2 may be connected to the second power line VSL, which receives the second power voltage VSS, and the other electrode of the second capacitor C2 may be connected to the third node N3. The second capacitor C2 may store a charge corresponding to the voltage difference between the second power voltage VSS and the third node N3. The second capacitor C2 may be referred to as a hold capacitor.

[0102] The light emitting device LD may include an anode and a cathode. In this embodiment, the anode of the light emitting device LD is connected to the first power line VDL, and the cathode is connected to the pixel driving unit PDC-2 through a fourth node N4. In this embodiment, the cathode of the light emitting device LD may be connected to the first transistor T1 through a fourth transistor T4a. The light emitting device LD may emit light in response to the amount of current flowing through the first transistor T1 of the pixel driving unit PDC-1.

[0103] In this embodiment, the first to sixth transistors T1, T2, T3, T4a, T5a, and T6a are N-type transistors, and therefore the potential of the third node N3 corresponding to the source of the first driving transistor T1 is not directly affected by the characteristics of the light emitting device LD. Therefore, even if degradation of the light emitting device LD occurs, the influence on the transistors constituting the pixel driver PDC-2, particularly the gate-source voltage Vgs of the driving transistor, can be reduced. In other words, since the amount of change in driving current due to degradation of the light emitting device LD is reduced, image retention defects of the display panel that occur over time can be reduced and the lifespan can be improved.

[0104] 4A, 4B, and 4C show circuits for pixel drivers PDC, PDC-1, and PDC-2 according to an embodiment of the present invention. As long as the display panel according to an embodiment of the present invention is a circuit connected to the cathode of the light emitting element LD, the number and arrangement of transistors and the number and arrangement of capacitors can be designed in various ways, and is not limited to any one embodiment.

[0105] 5 is a simplified plan view of a display panel according to an embodiment of the present invention, in which some components are omitted.

[0106] Referring to FIG. 5, the display panel DP may be divided into a display area DA and a non-display area (or non-display area NDA). The display area DA may include a plurality of light-emitting portions EP. The light-emitting portions EP may be areas that are each illuminated by a pixel PXij (see FIG. 3). Specifically, each of the light-emitting portions EP may correspond to a light-emitting aperture OP-PDL (see FIG. 9A), which will be described later.

[0107] The non-display area NDA may be disposed adjacent to the display area DA. In the present embodiment, the non-display area NDA is illustrated as surrounding the edge of the display area DA. However, this is merely an example, and the non-display area NDA may be disposed on one side of the display area DA or may be omitted, and is not limited to any one embodiment.

[0108] Although not shown, in one embodiment, the data driver DDC (see FIG. 3) may be provided in the form of a separate driver chip independent of the display panel DP and connected to the display panel DP. However, this is merely an example, and the data driver DDC may be formed in the same process as the gate driver GDC to form the display panel DP, and is not limited to any one embodiment. The data driver DDC may be disposed in the same region as the gate driver GDC, i.e., adjacent to the bottom of the display panel DP.

[0109] The display panel DP may have a length in the first direction DR1 that is longer than the length in the second direction DR2. A plurality of pixels PX11 to PXnm are illustratively arranged in n rows and m columns in the display area DA. In this embodiment, the display panel DP may include a gate driver GDC disposed adjacent to a lower end of the display panel DP. The gate driver GDC may be formed to extend in the first direction DR1.

[0110] For example, FIG. 5 illustrates write scan lines GWL1-GWLn among scan lines GWL1-GWLn, GCL1-GCLn, GIL1-GILn, GBL1-GBLn, and GRL1-GRLn (see FIG. 3). The gate driver GDC may be connected to the write scan lines GWL1-GWLn. However, the present invention is not limited thereto, and two gate drivers GDC may be provided. One of the two gate drivers GDC may be connected to some of the write scan lines GWL1-GWLn, and the other of the two gate drivers GDC may be connected to other parts of the write scan lines GWL1-GWLn. For example, one of the two gate drivers GDC may be connected to odd-numbered scan lines among the write scan lines GWL1-GWLn, and the other of the two gate drivers GDC may be connected to even-numbered scan lines among the write scan lines GWL1-GWLn.

[0111] In this embodiment, the gate driver GDC may be disposed in the non-display area NDA. However, the present invention is not limited thereto, and the gate driver GDC may overlap at least some of the light emitting units EP disposed in the display area DA in a plan view. By disposing the gate driver GDC in the display area DA, the area of ​​the non-display area NDA can be reduced compared to a conventional display panel in which the gate driver GDC is disposed in the non-display area, and a display device DD (see FIG. 1) with a thin bezel can be easily implemented.

[0112] FIG. 6 is a plan view showing one light emitting unit and one pixel driving unit connected thereto according to an embodiment of the present invention.

[0113] 6, the first and second light-emitting units EP1 and EP2 within the light-emitting unit EPU are aligned in the second direction DR2, and the third light-emitting unit EP3 is positioned in the first direction DR1 relative to the first and second light-emitting units EP1 and EP2. In this embodiment, the third light-emitting unit EP3 is illustrated as being sized to overlap the first and second light-emitting units EP1 and EP2 when viewed in the first direction DR1. The shapes and arrangements of the first to third light-emitting units EP1, EP2, and EP3, or the number of light-emitting units constituting the light-emitting unit EPU, may be variously selected and are not limited to any one embodiment. For example, the third light-emitting unit EP3 may include two sub-light-emitting units spaced apart in the second direction DR2.

[0114] The pixel driving unit PDU may include first to third pixel driving parts PDC1, PDC2, and PDC3 that drive the first to third light emitting parts EP1, EP2, and EP3, respectively. The first to third pixel driving parts PDC1, PDC2, and PDC3 may be arranged along a first direction DR1. The first to third pixel driving parts PDC1, PDC2, and PDC3 include first to third connection transistors TR1, TR2, and TR3 that are connected to the first to third light emitting parts EP1, EP2, and EP3, respectively. Each of the first to third connection transistors TR1, TR2, and TR3 may be a driving transistor (or first transistor), but is not limited thereto.

[0115] The width WH of one light-emitting unit EPU in the first direction DR1 may be larger than the width WH_C of a corresponding pixel driving unit PDU in the first direction DR1. For ease of explanation, the length WV of the light-emitting unit EPU in the second direction DR2 and the length WV of the pixel driving unit PDU in the second direction DR2 are illustrated as being the same, but this is not limiting. According to the present invention, by designing the width WH_C of the pixel driving unit PDU to be smaller than the width WH of the light-emitting unit EPU, it is possible to provide a display area DA (FIG. 2B) that is larger than the area occupied by the driving element layer DDL (see FIG. 2B). Therefore, a display panel DP with a narrow bezel can be provided.

[0116] 7A to 7D are enlarged plan views of a display panel according to an embodiment of the present invention, specifically, FIG. 7A is an enlarged view of the area AA′ shown in FIG.

[0117] 7A exemplarily illustrates two rows and two columns of light emitting units UT11, UT12, UT21, and UT22. Referring to FIG. 7A, the first row light emitting unit Rk includes light emitting units constituting the first row, first column light emitting unit UT11 and the first row, second column light emitting unit UT12, and the second row light emitting unit Rk+1 includes light emitting units constituting the second row, first column light emitting unit UT21 and the second row, second column light emitting unit UT22. One of the light emitting units UT11, UT12, UT21, and UT22 may correspond to the light emitting unit EPU described in FIG. 6.

[0118] The light-emitting portions EP1, EP2, and EP3 may correspond to the light-emitting portions EP1, EP2, and EP3 described in FIG. 6. That is, each of the light-emitting portions EP1, EP2, and EP3 may be an area where light is emitted by the light-emitting element described above. The light-emitting portions EP1, EP2, and EP3 may correspond to a unit that forms an image displayed on the display panel DP (see FIG. 2A). More specifically, each of the light-emitting portions EP1, EP2, and EP3 may correspond to an area defined by a light-emitting opening OP-PDL (see FIG. 9A) described below, particularly an area defined by the bottom surface of the light-emitting opening OP-PDL.

[0119] The light-emitting units EP1, EP2, and EP3 may include a first light-emitting unit EP1, a second light-emitting unit EP2, and a third light-emitting unit EP3. The first light-emitting unit EP1, the second light-emitting unit EP2, and the third light-emitting unit EP3 may emit light of different colors. For example, the first light-emitting unit EP1 may emit red light, the second light-emitting unit EP2 may emit green light, and the third light-emitting unit EP3 may emit blue light, but the color combinations are not limited thereto. Also, at least two of the first to third light-emitting units EP1, EP2, and EP3 may emit light of the same color. For example, the first to third light-emitting units EP1, EP2, and EP3 may all emit blue light or all emit white light.

[0120] The third light emitting unit EP3, which displays light emitted by a third light emitting element among the first to third light emitting units EP1, EP2, and EP3, may include two sub-light emitting units EP31 and EP32 spaced apart from each other in the second direction DR2. However, this is merely an example, and the third light emitting unit EP3 may be provided in a single pattern having an integral shape like the first and second light emitting units EP1 and EP2, or at least one of the first and second light emitting units EP1 and EP2 may include a spaced-apart sub-light emitting unit, and is not limited to any one embodiment.

[0121] The first row light-emitting unit Rk includes first to third light-emitting units EP1, EP2, and EP3 that constitute the first row, first column light-emitting unit UT11 and first to third light-emitting units EP1, EP2, and EP3 that constitute the first row, second column light-emitting unit UT12, and the second row light-emitting unit Rk+1 includes first to third light-emitting units EP1, EP2, and EP3a that constitute the second row, first column light-emitting unit UT21 and first to third light-emitting units EP1, EP2, and EP3 that constitute the second row, second column light-emitting unit UT22.

[0122] In one embodiment of the present invention, the shapes of the light emitting units constituting the first row, first column light emitting unit UT11 and the second row, second column light emitting unit UT22 may be substantially identical. Also, the shapes of the light emitting units constituting the first row, second column light emitting unit UT12 and the second row, first column light emitting unit UT21 may be substantially identical. The shapes of the light emitting units constituting the first row, first column light emitting unit UT11 may be different from the shapes of the light emitting units constituting the first row, second column light emitting unit UT12. For example, a portion of the first row light emitting unit Rk and a portion of the second row light emitting unit Rk+1 may have symmetrical shapes.

[0123] In one embodiment of the present invention, the third light-emitting part EP3a of the second row, first column light-emitting unit UT21 and the third light-emitting part EP3 of the first row, first column light-emitting unit UT11 may have a shape and arrangement that is line-symmetrical with respect to an axis aligned with the first direction DR1, and the third light-emitting part EP3 of the second row, second column light-emitting unit UT22 and the third light-emitting part EP3a of the first row, second column light-emitting unit UT12 may have a shape and arrangement that is line-symmetrical with respect to the axis aligned with the first direction DR1, but this is merely an example and is not limiting.

[0124] 7B illustrates light emitting portions arranged in a row. For ease of explanation, FIG. 7B also illustrates a plurality of second electrodes EL2_1, EL2_2, EL2_3, a plurality of pixel P driving circuits PDC1, PDC2, PDC3, first to third connecting electrodes CNE1, CNE2, CNE3, and a separator SPR. 7C illustrates a separator SPR within the display panel, a plurality of light emitting portions EP1, EP2, EP3 arranged within an area defined by the separator SPR, and a plurality of connecting electrodes CNE1, CNE2, CNE3.

[0125] 7B and 7C, the second electrodes EL2_1, EL2_2, and EL2_3 may be separated from one another by separators SPR and electrically disconnected. In this embodiment, one light-emitting unit UT11 may include three light-emitting portions EP1, EP2, and EP3. Therefore, the light-emitting unit UT11 may include three second electrodes EL2_1, EL2_2, and EL2_3 (hereinafter, first to third cathodes), three pixel driving portions PDC1, PDC2, and PDC3, and three connecting electrodes CNE1, CNE2, and CNE3. However, this is merely an example, and the number and arrangement of the light-emitting portions included in the light-emitting unit UT11 may be variously designed and is not limited to any one embodiment.

[0126] The first to third pixel driving units PDC1, PDC2, and PDC3 are electrically connected to the first to third light emitting elements LD1, LD2, and LD3, respectively, including the first to third light emitting units EP1, EP2, and EP3. In this specification, "connected" refers to being connected in direct physical contact with the first to third pixel driving units PDC1, PDC2, and PDC3, and includes being electrically connected to the first to third pixel driving units PDC1, PDC2, and PDC3.

[0127] Also, as shown in FIG. 7B, each area in which the first to third pixel driving units PDC1, PDC2, and PDC3 are defined on a plane may correspond to a unit in which transistors and capacitor elements constituting the pixel driving unit PDC (see FIG. 4A) for driving the light emitting element of the pixel are repeatedly arranged.

[0128] The first to third pixel driving units PDC1, PDC2, and PDC3 may be sequentially arranged along the first direction DR1, and may be designed independently of the positions and shapes of the first to third light emitting units EP1, EP2, and EP3.

[0129] For example, the first to third pixel driving units PDC1, PDC2, and PDC3 may be arranged in regions defined by the separators SPR, i.e., at positions different from those of the first to third cathodes EL2_1, EL2_2, and EL2_3, or may be designed to have shapes and areas different from those of the first to third cathodes EL2_1, EL2_2, and EL2_3. Alternatively, the first to third pixel driving units PDC1, PDC2, and PDC3 may be arranged to overlap positions where the first to third light emitting units EP1, EP2, and EP3 are present, respectively, and may be designed to have shapes having areas similar to those of the regions defined by the separators SPR, e.g., the first to third cathodes EL2_1, EL2_2, and EL2_3.

[0130] In this embodiment, the first to third pixel driving units PDC1, PDC2, and PDC3 are each illustrated as a rectangle, the first to third light emitting units EP1, EP2, and EP3 are each arranged in a different shape with a smaller area than the rectangle, and the first to third cathodes EL2_1, EL2_2, and EL2_3 are arranged at positions overlapping the first to third light emitting units EP1, EP2, and EP3, and are illustrated as irregular shapes.

[0131] 7B, the first pixel driver PDC1 may be disposed at a position where it partially overlaps with the first light emitter EP1, the second light emitter EP2, and other adjacent light emitting units. The second pixel driver PDC2 may be disposed at a position where it overlaps with the first light emitter EP1, the second light emitter EP2, and the third cathode EL2_3. The third pixel driver PDC3 may be disposed at a position where it overlaps with the third light emitter EP3. This is merely an example, and the positions and arrangements of the first to third pixel drivers PDC1, PDC2, and PDC3 may be designed in various shapes and arrangements independently of the first to third light emitters EP1, EP2, and EP3, and are not limited to any one embodiment.

[0132] The light emitting unit UT11 may include first, second, and third connecting electrodes CNE1, CNE2, and CNE3. The first connecting electrode CNE1 electrically connects the first light emitting element LD1 forming the first light emitting portion EP1 (or the first light emitting portion EP1 is defined) to the first pixel driving part PDC1, the second connecting electrode CNE2 electrically connects the second light emitting element LD2 forming the second light emitting portion EP2 to the second pixel driving part PDC2, and the third connecting electrode CNE3 electrically connects the third light emitting element LD3 forming the third light emitting portion EP3 to the third pixel driving part PDC3. Each of the first, second, and third light emitting elements LD1, LD2, and LD3 may include a first electrode EL1, an intermediate layer IML disposed on the first electrode EL1, and a second electrode EL2 disposed on the intermediate layer.

[0133] Specifically, the first to third connecting electrodes CNE1, CNE2, and CNE3 may be electrically connected to the first to third cathodes EL2_1, EL2_2, and EL2_3 and the first to third pixel driving parts PDC1, PDC2, and PDC3 in a one-to-one correspondence, respectively. For example, the first connecting electrode CNE1 may be electrically connected to the first pixel driving part PDC1 and the first cathode EL2_1, the second connecting electrode CNE2 may be electrically connected to the second pixel driving part PDC2 and the second cathode EL2_2, and the third connecting electrode CNE3 may be electrically connected to the third pixel driving part PDC3 and the third cathode EL2_3.

[0134] Each of the first to third connecting electrodes CNE1, CNE2, and CNE3 may be disposed on a pixel defining layer PDL (see FIG. 9A ), which will be described later. The first to third connecting electrodes CNE1, CNE2, and CNE3 may have a ring shape surrounding the corresponding first to third light emitting portions EP1, EP2, and EP3. In an embodiment of the present invention, each of the first to third connecting electrodes CNE1, CNE2, and CNE3 has a closed ring shape, but this is not limited thereto. For example, at least some of the first to third connecting electrodes CNE1, CNE2, and CNE3 may have an open ring shape with a portion broken.

[0135] Since the first to third connecting electrodes CNE1, CNE2, and CNE3 have an annular shape, the degree of freedom in the positions at which the first to third connecting electrodes CNE1, CNE2, and CNE3 are connected to the first to third pixel driving circuits PDC1, PDC2, and PDC3 can be improved. That is, by arranging the first to third connecting units CE1, CE2, and CE3 corresponding to arbitrary positions of the annular first to third connecting electrodes CNE1, CNE2, and CNE3, respectively, the first to third connecting electrodes CNE1, CNE2, and CNE3 can be connected to the first to third pixel driving circuits PDC1, PDC2, and PDC3 via the first to third connecting units CE1, CE2, and CE3. For example, the first connecting electrode CNE1 may be connected to the first pixel driver PDC1 through the first connection part CE1, the second connecting electrode CNE2 may be connected to the second pixel driver PDC2 through the second connection part CE2, and the third connecting electrode CNE3 may be connected to the third pixel driver PDC3 through a connecting wire CN3 (including the third connection part CE3 and the driving connection part CD3). That is, additional connecting wires connected to the first and second connecting electrodes CNE1 and CNE2 may be omitted.

[0136] One connection line CN3 may electrically connect the third pixel driver PDC3 and the third light emitting element LD3 constituting the third light emitting unit EP3. Specifically, the connection line CN3 may correspond to a node (see the fourth node N4 in FIG. 4A, the second node N2 in FIG. 4B, or the fourth node N4 in FIG. 4C) at which the light emitting element LD (see FIG. 4A) is connected to the pixel driver (PDC in FIG. 4A, PDC-1 in FIG. 4B, or PDC-2 in FIG. 4C).

[0137] The connecting wire CN3 may include a third connecting part CE3 and a driving connecting part CD3. The third connecting part CE3 may be provided on one side of the connecting wire CN3, and the driving connecting part CD3 may be provided on the other side of the connecting wire CN3.

[0138] The driving connection part CD3 may be a portion of the connecting wire CN3 connected to the third pixel driver PDC3. In this embodiment, the driving connection part CD3 may be connected to one electrode of a transistor constituting the third pixel driver PDC3. Specifically, the driving connection part CD3 may be connected to the drain of the sixth transistor T6 shown in FIG. 4A, the drain of the first transistor T1 shown in FIG. 4B, or the drain of the fourth transistor T4a shown in FIG. 4C. Therefore, the position of the driving connection part CD3 may correspond to the position of a transistor physically connected to the connecting wire CN3 in the pixel driver. The third connection part CE3 may be a portion of the connecting wire CN3 connected to the third light emitting element LD3. In this embodiment, the third connection part CE3 may be connected to the third connecting electrode CNE3.

[0139] The first connecting electrode CNE1 may include a first edge EG11 surrounding at least a portion of the first light emitting portion EP1 and a second edge EG12 surrounding the first edge EG11. The second connecting electrode CNE2 may include a first edge EG21 surrounding at least a portion of the second light emitting portion EP2 and a second edge EG22 surrounding the first edge EG21. The third connecting electrode CNE3 may include a first edge EG31 surrounding at least a portion of the third light emitting portion EP3 and a second edge EG32 surrounding the first edge EG31.

[0140] The first to third connecting electrodes CNE1, CNE2, and CNE3 may be arranged spaced apart from one another. For example, gaps GP1, GP2, and GP3 between adjacent connecting electrodes among the first to third connecting electrodes CNE1, CNE2, and CNE3 may overlap with separators SPR. For example, first edges EG11, EG21, and EG31 of the first to third connecting electrodes CNE1, CNE2, and CNE3 may not be covered with separators SPR, and second edges EG12, EG22, and EG32 of the first to third connecting electrodes CNE1, CNE2, and CNE3 may overlap with separators SPR. Alternatively, the second edges EG12, EG22, and EG32 of the first to third connecting electrodes CNE1, CNE2, and CNE3 may be covered with separators SPR.

[0141] In an embodiment of the present invention, the first to third connection parts CE1, CE2, and CE3 may be disposed at positions that do not overlap (do not overlap) the first to third light emitting parts EP1, EP2, and EP3 in a plan view. For example, a light emitting opening OP-PDL (see FIG. 9A) and a through hole OP-P (see FIG. 9A) spaced apart from the light emitting opening OP-PDL may be defined in the pixel defining layer PDL.

[0142] The through holes OP-P may include a first through hole OP-P1, a second through hole OP-P2, and a third through hole OP-P3. The first to third connection portions CE1, CE2, and CE3 may be arranged corresponding to the first to third through holes OP-P1, OP-P2, and OP-P3, respectively. The light emitting opening OP-PDL may include a first light emitting opening OP-PDL1, a second light emitting opening OP-PDL2, and a third light emitting opening OP-PLD3. The first to third light emitting portions EP1, EP2, and EP3 may be defined corresponding to the first to third light emitting openings OP-PDL1, OP-PDL2, and OP-PDL3, respectively. Therefore, the first to third connection portions CE1, CE2, and CE3 may be arranged at positions spaced apart from the first to third light emitting portions EP1, EP2, and EP3.

[0143] The first to third connecting electrodes CNE1, CNE2, and CNE3 may be disposed on the pixel defining layer PDL (see FIG. 9A ). In a plan view, the first connecting electrode CNE1 may surround the first light-emitting opening OP-PDL1, the second connecting electrode CNE2 may surround the second light-emitting opening OP-PDL2, and the third connecting electrode CNE3 may surround the third light-emitting opening OP-PDL3.

[0144] According to an embodiment of the present invention, the driving connection part CD3, which is a position where the connecting wire CN3 is connected to the transistor TR1 (see FIG. 9A) of the third pixel driving part PDC3, may be defined at a position not overlapping with the third connection part CE3 in a plan view and may be disposed at a position overlapping with the third light emitting part EP3. By connecting the third cathode EL2_3 and the pixel driving part PDC3 through the connecting wire CN3, restrictions depending on the position and shape of the third light emitting part EP3 are reduced in designing the pixel driving part PDC3, thereby improving design freedom.

[0145] The first to third cathodes EL2_1, EL2_2, and EL2_3 may be connected to the first to third connecting electrodes CNE1, CNE2, and CNE3. For example, the bottom surfaces of the first to third cathodes EL2_1, EL2_2, and EL2_3 may be connected to (or in contact with) the top surfaces of the first to third connecting electrodes CNE1, CNE2, and CNE3, respectively. This may further improve the contact reliability (or connection stability) between the first to third cathodes EL2_1, EL2_2, and EL2_3 and the first to third connecting electrodes CNE1, CNE2, and CNE3.

[0146] In addition, connection regions where the first, second, and third cathodes EL2_1, EL2_2, and EL2_3 and the first, second, and third connecting electrodes CNE1, CNE2, and CNE3 are connected may surround at least a portion of each of the first, second, and third light-emitting openings OP-PDL1, OP-PDL2, and OP-PDL3. The first, second, and third cathodes EL2_1, EL2_2, and EL2_R and the first, second, and third connecting electrodes CNE1, CNE2, and CNE3 may be connected in regions adjacent to the separators SPR, and each of the connection regions may be defined adjacent to the separators SPR. That is, the first, second, and third cathodes EL2_1, EL2_2, and EL2_R and the first, second, and third connecting electrodes CNE1, CNE2, and CNE3 may not be connected at specific points but may be connected over a relatively wide region, for example, a region similar in shape to each of the first, second, and third connecting electrodes CNE1, CNE2, and CNE3. That is, the area of ​​the connection region is increased, and the connection can proceed stably.

[0147] FIG. 7D illustrates the separator SPR, the light-emitting portions EP1, EP2, EP3, and the first electrode EL1.

[0148] 7D, the first electrode EL1 (hereinafter, anode) of the light emitting device LD (see FIG. 9A) according to an embodiment of the present invention may be provided in common to the first to third light emitting portions EP1, EP2, and EP3. That is, the anode EL1 may be formed as a single layer integral with the entire display area DA, and accordingly, the anode EL1 layer may be disposed overlapping the separator SPR. Alternatively, the anodes EL1 of the light emitting device LD may be formed as independent conductive patterns spaced apart from each other and electrically connected to each other through other conductive layers, and accordingly, the anode EL1 patterns may be disposed overlapping the separator SPR.

[0149] As described above, the first power supply voltage VDD (see FIG. 4A) is applied to the anode EL1, and a common voltage can be provided to all the light emitting portions. The anode EL1 can be connected to the first power supply line VDL (see FIG. 4A) that provides the first power supply voltage VDD in the non-display area NDA, or can be connected to the first power supply line VDL (see FIG. 4A) in the display area DA, and is not limited to any one embodiment.

[0150] According to this embodiment, the anode EL1 may have a plurality of openings defined therein, and the openings may penetrate the anode EL1 layer. The openings in the anode EL1 layer may be positioned so as not to overlap the light-emitting portion EP (see FIG. 5) and may be positioned so as to overlap the separator SPR. The openings may facilitate the discharge of gas generated from organic layers disposed below the anode EL1, such as the sixth insulating layer 60 (see FIG. 9A) described below. Therefore, gas generated from the organic layers disposed below the light-emitting device during the display panel manufacturing process may be sufficiently discharged, and the rate at which the light-emitting device deteriorates may be reduced by reducing the amount of gas discharged from the organic layers after manufacturing.

[0151] Figure 8 is an enlarged plan view of a portion of a display panel according to an embodiment of the present invention. Figure 8 illustrates pixel driving units PDU11, PDU12, PDU21, and PDU22 corresponding to light emitting units UT11, UT12, UT21, and UT22 shown in Figure 7A. One pixel driver among pixel driving units PDU11, PDU12, PDU21, and PDU22 may correspond to the pixel driving unit PDU shown in Figure 6. Pixel driving units PDU11, PDU12, PDU21, and PDU22 may include first, second, and third connection transistors TR1, TR2, and TR3, respectively. A description of these elements will be omitted as they overlap with the previous description.

[0152] 8, scan lines GWL1, GWL2, GWL3, GCL1, GRL1 and light emitting lines ESL1-1, ESL2-1 are shown. The scan lines GWL1, GWL2, GWL3, GCL1, GRL1 may be part of the scan lines GWL1 to GWLn, GCL1 to GCLn, GRL1 to GRLn and GRL1 to GRLn shown in FIG. 3, and the light emitting lines ESL1-1, ESL2-1 may be part of the light emitting lines ESL1 to ESLn.

[0153] According to an embodiment of the present invention, the first scan write line GWL1 may include a first vertical line (or vertical line VL1) extending in the second direction DR2 and a first horizontal line (or horizontal line HL1) extending in the first direction DR1. The first vertical line VL1 and the first horizontal line HL1 may be disposed on different layers. The first vertical line VL1 and the first horizontal line HL1 may be connected to each other through a contact hole CNTa. The first horizontal line HL1 may receive a write scan signal GW (see FIG. 4A) from the first vertical line VL1 and supply it to the first row pixel driving units PDU11 and PDU12. Although not shown, the first horizontal line HL1 may supply the write scan signal GW to all pixel driving units arranged in the first row. That is, all pixel driving units arranged in the first row may receive the same write scan signal GW.

[0154] Similarly, the second scan write line GWL2 may include a fourth vertical line VL4 extending in the second direction DR2 and a sixth horizontal line HL6 extending in the first direction DR1. The fourth vertical line VL4 and the sixth horizontal line HL6 may be connected to each other through contact holes CNTf. The sixth horizontal line HL6 may receive a write scan signal GW from the fourth vertical line VL4 and supply it to the second-row pixel driving units PDU21 and PDU22. The third scan write line GWL3 may include a seventh vertical line VL7 extending in the second direction DR2 and an eleventh horizontal line HL11 extending in the first direction DR1. The seventh vertical line VL7 and the eleventh horizontal line HL11 may be connected to each other through contact holes CNTk. The eleventh horizontal line HL11 may receive a write scan signal GW from the seventh vertical line VL7 and supply it to the third-row pixel driving units.

[0155] The write scan signal GW supplied by the first horizontal line HL1 to the first-row pixel driving units PDU11 and PDU12 may be defined as the first write scan signal, the write scan signal GW supplied by the sixth horizontal line HL6 to the second-row pixel driving units PDU21 and PDU22 may be defined as the second write scan signal, and the write scan signal GW supplied by the eleventh horizontal line HL11 to the second-row pixel driving units may be defined as the third write scan signal. The first to third write scan signals may be different from each other, or may have pulses with the same period.

[0156] According to an embodiment of the present invention, the first compensation scan line GCL1 may include a second vertical line VL2 extending in the second direction DR2, a second horizontal line HL2 extending in the first direction DR1, and a seventh horizontal line HL7. The second vertical line VL2, the second horizontal line HL2, and the seventh horizontal line HL7 may be disposed on different layers. The second vertical line VL2 and the second horizontal line HL2 may be connected to each other through a contact hole CNTb, and the second vertical line VL2 and the seventh horizontal line HL7 may be connected to each other through a contact hole CNTg. The second horizontal line HL2 may receive a compensation scan signal GC (see FIG. 4A) from the second vertical line VL2 and supply it to the first-row pixel driving units PDU11 and PDU12, and the seventh horizontal line HL7 may receive a compensation scan signal GC from the second vertical line VL2 and supply it to the second-row pixel driving units PDU21 and PDU22. Although not shown, the second horizontal line HL2 may supply the compensation scan signal GC to all pixel driving units arranged in the first row, and the seventh horizontal line HL7 may supply the compensation scan signal GC to all pixel driving units arranged in the second row. That is, all pixel driving units arranged in the first row and all pixel driving units arranged in the second row may receive the same compensation scan signal GC.

[0157] According to an embodiment of the present invention, the first reset scan line GRL1 may include a third vertical line VL3 extending in the second direction DR2, a third horizontal line HL3 extending in the first direction DR1, and an eighth horizontal line HL8. The third vertical line VL3, the third horizontal line HL3, and the eighth horizontal line HL8 may be disposed on different layers. The third vertical line VL3 and the third horizontal line HL3 may be connected to each other through a contact hole CNTc, and the third vertical line VL3 and the eighth horizontal line HL8 may be connected to each other through a contact hole CNTh. The third horizontal line HL3 may receive a reset scan signal GR (see FIG. 4A) from the third vertical line VL3 and supply it to the first-row pixel driving units PDU11 and PDU12, and the eighth horizontal line HL8 may receive the reset scan signal GR from the third vertical line VL3 and supply it to the second-row pixel driving units PDU21 and PDU22. Although not shown, the third horizontal line HL3 may supply a reset scan signal GR to all pixel driving units arranged in the first row, and the eighth horizontal line HL8 may supply a reset scan signal GR to all pixel driving units arranged in the second row. That is, all pixel driving units arranged in the first row and all pixel driving units arranged in the second row may receive the same reset scan signal GR.

[0158] According to an embodiment of the present invention, the 1-1 light-emitting line ESL1-1 may include a fifth vertical line VL5 extending in the second direction DR2, and a fourth horizontal line HL4 and a ninth horizontal line HL9 extending in the first direction DR1. The fifth vertical line VL5, the fourth horizontal line HL4, and the ninth horizontal line HL9 may be disposed on different layers. The fifth vertical line VL5 and the fourth horizontal line HL4 may be connected to each other through a contact hole CNTd, and the fifth vertical line VL5 and the ninth horizontal line HL9 may be connected to each other through a contact hole CNTi. The fourth horizontal line HL4 may receive a first light-emitting signal EM1 (see FIG. 4A ) from the fifth vertical line VL5 and provide the first light-emitting signal EM1 to the first-row pixel driving units PDU11 and PDU12, and the ninth horizontal line HL9 may receive the first light-emitting signal EM1 from the fifth vertical line VL5 and provide the first light-emitting signal EM1 to the second-row pixel driving units PDU21 and PDU22. Although not shown, the fourth horizontal line HL4 may supply the first light-emitting signal EM1 to all pixel driving units arranged in the first row, and the ninth horizontal line HL9 may supply the first light-emitting signal EM1 to all pixel driving units arranged in the second row. That is, all pixel driving units arranged in the first row and all pixel driving units arranged in the second row may receive the same first light-emitting signal EM1.

[0159] According to an embodiment of the present invention, the 2-1 light-emitting line ESL2-1 may include a sixth vertical line VL6 extending in the second direction DR2, a fifth horizontal line HL5 extending in the first direction DR1, and a tenth horizontal line HL10. The sixth vertical line VL6, the fifth horizontal line HL5, and the tenth horizontal line HL10 may be disposed on different layers. The sixth vertical line VL6 and the fifth horizontal line HL5 may be connected to each other through a contact hole CNTe, and the sixth vertical line VL6 and the tenth horizontal line HL10 may be connected to each other through a contact hole CNTj. The fifth horizontal line HL5 may receive a second light-emitting signal EM2 (see FIG. 4A ) from the sixth vertical line VL6 and provide the second light-emitting signal EM2 to the first-row pixel driving units PDU11 and PDU12, and the tenth horizontal line HL10 may receive the second light-emitting signal EM2 from the sixth vertical line VL6 and provide it to the second-row pixel driving units PDU21 and PDU22. Although not shown, the fifth horizontal line HL5 may supply the second light-emitting signal EM2 to all pixel driving units arranged in the first row, and the tenth horizontal line HL10 may supply the second light-emitting signal EM2 to all pixel driving units arranged in the second row, that is, all pixel driving units arranged in the first row and all pixel driving units arranged in the second row may receive the same second light-emitting signal EM2.

[0160] Figure 9A is a cross-sectional view of a display panel according to an embodiment of the present invention, showing a portion corresponding to line II' in Figure 7A, and Figure 9B is an enlarged cross-sectional view of region BB' in Figure 9A.

[0161] 9A, a display panel DP according to an embodiment of the present invention may include a base layer BS, a driving element layer DDL, a light emitting element layer LDL, an encapsulation layer ECL, and a sensing layer ISL. However, this is merely an example, and in an embodiment of the present invention, the display panel DP may not include the sensing layer ISL.

[0162] The driving element layer DDL may include a plurality of insulating layers 10, 20, 30, 40, 50, and 60 disposed on the base layer BS, and a plurality of conductive patterns and semiconductor patterns disposed between the insulating layers 10, 20, 30, 40, 50, and 60. The conductive patterns and semiconductor patterns may be disposed between the insulating layers 10, 20, 30, 40, 50, and 60 to form pixel driving units PDC1 and PDC2. For ease of explanation, FIG. 9A exemplarily illustrates a cross section of one region among regions where one light emitting unit is disposed.

[0163] The base layer BS may be a member that provides a base surface on which the pixel driving units PDC1 and PDC2 are disposed. The base layer BS may be a rigid substrate or a flexible substrate that allows bending, folding, rolling, etc. The base layer BS may be a glass substrate, a metal substrate, a polymer substrate, etc. However, embodiments of the present invention are not limited thereto, and the base layer BS may be an inorganic layer, an organic layer, or a composite material layer.

[0164] The base layer BS may have a multi-layer structure. The base layer BS may include a first polymer resin layer, a silicon oxide (SiOx) layer disposed on the first polymer resin layer, an amorphous silicon (a-Si) layer disposed on the silicon oxide layer, and a second polymer resin layer disposed on the amorphous silicon layer. The silicon oxide layer and the amorphous silicon layer may be referred to as a base barrier layer.

[0165] The polymer resin layer may include a polyimide-based resin. The polymer resin layer may also include at least one of an acrylate-based resin, a methacrylate-based resin, a polyisoprene-based resin, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. In this specification, a "-based" resin means that it contains a functional group of "-based."

[0166] Each of the insulating layer, conductive layer, and semiconductor layer disposed on the base layer BS may be formed by coating, deposition, etc. Then, the insulating layer, semiconductor layer, and conductive layer may be selectively patterned through multiple photolithography processes to form holes in the insulating layer, or semiconductor patterns, conductive patterns, signal lines, etc.

[0167] The driving element layer DDL may include first to sixth insulating layers 10, 20, 30, 40, 50, and 60 and pixel driving units PDC1 and PDC2, which are sequentially stacked on a base layer BS. Figure 5 exemplarily illustrates a first pixel driving unit PDC1 and a second pixel driving unit PDC2, which are the pixel driving units PDC to PDC-2 shown in Figures 4A to 4C. The first pixel driving unit PDC1 illustrates one transistor TR1 and two capacitors C1 and C2 in a pixel driving unit, and the second pixel driving unit PDC2 illustrates one transistor TR2 in a pixel driving unit. The transistor TR2 may be one of multiple transistors included in the second pixel driving unit PDC2.

[0168] The transistor TR1 of the first pixel driver PDC1 corresponds to a transistor connected to the light emitting device LD through the intermediate connecting electrode CN and the connecting electrode CNE, i.e., a connecting transistor connected to a node corresponding to the cathode of the light emitting device LD (the fourth node N4 in FIG. 4A, the second node N2 in FIG. 4B, or the fourth node N4 in FIG. 4C), and specifically may correspond to the sixth transistor T6 in FIG. 4A, the first transistor T1 in FIG. 4B, or the fourth transistor T4a in FIG. 4C. Hereinafter, the transistor TR1 of the first pixel driver PDC1 may be referred to as a connecting transistor. The light emitting device LD electrically connected to the first pixel driver PDC1 may be a first light emitting device LD1 (see FIG. 7C).

[0169] The second pixel driver PDC2 may be electrically connected to a second light emitting element LD2 (see FIG. 7C) adjacent to the first light emitting element LD1. For example, the second pixel driver PDC2 may be electrically connected to the second light emitting element LD2 through the middle connecting electrode and the second connecting electrode CNE2 (see FIG. 7C).

[0170] Although not shown, other transistors constituting the pixel driver PDC1 or PDC2 may have the same structure as the transistor TR1 or TR2 shown in Fig. 9A. However, this is merely an example, and other transistors constituting the pixel driver PDC1 or PDC2 may have a different structure from the transistor TR1 or TR2 shown in Fig. 9A, and are not limited to any one embodiment.

[0171] A first insulating layer 10 may be disposed on the base layer BS. The first insulating layer 10 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The first insulating layer 10 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the first insulating layer 10 is illustrated as a single-layer silicon oxide layer. The insulating layers described below may be inorganic layers and / or organic layers and may have a single-layer or multi-layer structure. The inorganic layer may include at least one of the above-mentioned materials, but is not limited thereto.

[0172] The first insulating layer 10 may cover the lower conductive layers BCL1 and BCL2. That is, the display panel DP may further include lower conductive layers BCL1 and BCL2 disposed overlapping the transistor TR1 or TR2. The lower conductive layers BCL1 and BCL2 may block the electric potential caused by polarization of the base layer BS from affecting the transistor TR1 or TR2. The lower conductive layers BCL1 and BCL2 may also block light incident on the transistor TR1 or TR2 from below. At least one of an inorganic barrier layer and a buffer layer may be further disposed between the lower conductive layers BCL1 and BCL2 and the base layer BS.

[0173] The lower conductive layers BCL1 and BCL2 may include a reflective metal, such as titanium (Ti), molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), or copper (Cu).

[0174] The lower conductive layers BCL1 and BCL2 may include a first lower conductive layer BCL1 and a second lower conductive layer BCL2. In this embodiment, the first lower conductive layer BCL1 may be connected to the source of the connection transistor TR1 through a first source electrode pattern S1 (or a 1-1 pattern). In this case, the first lower conductive layer BCL1 may be synchronized with the source of the connection transistor TR1. The second lower conductive layer BCL2 may be connected to the source of the transistor TR2 through a second source electrode pattern S2 (or a 1-2 pattern). In this case, the second lower conductive layer BCL2 may be synchronized with the source of the transistor TR2.

[0175] However, this is merely an example, and the lower conductive layer BCL1 or BCL2 may be connected to the gate of transistor TR1 or TR2 and synchronized with the gate. Alternatively, the lower conductive layer BCL1 or BCL2 may be connected to another electrode and independently receive a constant voltage or pulse signal. Alternatively, the lower conductive layer BCL1 or BCL2 may be provided in an isolated form from other conductive patterns. The lower conductive layer BCL1 or BCL2 according to an embodiment of the present invention may be provided in various forms and is not limited to any one embodiment.

[0176] The transistor TR1 of the first pixel driver PDC1 and the transistor TR2 of the second pixel driver PDC2 may be disposed on the first insulating layer 10. The transistor TR1 of the first pixel driver PDC1 may include a first semiconductor pattern SP1 and a first gate electrode GE1. The transistor TR2 of the second pixel driver PDC2 may include a second semiconductor pattern SP2 and a second gate electrode GE2. The first and second semiconductor patterns SP1 and SP2 may be disposed on the first insulating layer 10. The first and second semiconductor patterns SP1 and SP2 may include an oxide semiconductor. For example, the oxide semiconductor may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3). However, without being limited thereto, the first and second semiconductor patterns SP1 and SP2 may include amorphous silicon, low-temperature polycrystalline silicon, or polycrystalline silicon.

[0177] Each of the first and second semiconductor patterns SP1 and SP2 may include a source region, a drain region, and a channel region, which are differentiated according to their conductivity levels. For example, the first semiconductor pattern SP1 may include a first source region SR1, a first drain region DR_1, and a first channel region CR1. The first source region SR1 and the first drain region DR_1 may be separated by a first channel region CR1. The first channel region CR1 may overlap with the first gate electrode GE1 in a plan view. The second semiconductor pattern SP2 may include a second source region SR2, a second drain region (not shown), and a second channel region CR2. The second source region SR2 and the second drain region may be separated by a second channel region CR2. The second channel region CR2 may overlap with the second gate electrode GE2 in a plan view. Because the cut line I-I' does not pass through the second drain region of the second semiconductor pattern SP2, the second drain region is not shown in FIG. 5.

[0178] When the semiconductor pattern SP1 or SP2 is an oxide semiconductor, each of the source region SR1 or SR2 and the drain region DR_1 may be a reduced region, and therefore, each of the source region SR1 or SR2 and the drain region DR_1 may have a relatively higher reduced metal content than the channel region CR1 or CR2. Alternatively, when the semiconductor pattern SP1 or SP2 is polycrystalline silicon, each of the source region SR1 or SR2 and the drain region DR_1 may be a highly doped region.

[0179] The source region SR1 or SR2 and the drain region DR_1 may have a relatively high conductivity compared to the channel region CR1 or CR2. The source region SR1 or SR2 may correspond to the source electrode of the transistor TR1 or TR2, and the drain region DR_1 may correspond to the drain electrode of the transistor TR1 or TR2. As shown in FIG. 9A, a separate source electrode pattern S1 or S2 and a drain electrode pattern D1 or D2 may be further provided, connected to the source region SR1 or SR2 and the drain region DR_1, respectively. Specifically, the separate source electrode pattern S1 or S2 and the drain electrode pattern D1 or D2 may be integrally formed with one of the lines constituting the pixel driver (see PDC in FIG. 4A, PDC-1 in FIG. 4B, or PDC-2 in FIG. 4C), and are not limited to any one embodiment.

[0180] The second insulating layer 20 overlaps multiple pixels and can cover the semiconductor pattern SP1 or SP2. The second insulating layer 20 can be an inorganic and / or organic layer and can have a single-layer or multi-layer structure. The second insulating layer 20 can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In this embodiment, the second insulating layer 20 can be a single silicon oxide layer.

[0181] The gate electrodes GE1 and GE2 may be disposed on the second insulating layer 20. The first gate electrode GE1 may correspond to the gate of the transistor TR1 of the first pixel driver PDC1, and the second gate electrode GE2 may correspond to the gate of the transistor TR2 of the second pixel driver PDC2. The gate electrodes GE1 and GE2 may be disposed above the semiconductor patterns SP1 and SP2, respectively. However, this is merely an example, and the gate electrodes GE1 and GE2 may also be disposed below the semiconductor patterns SP1 and SP2, and are not limited to any one embodiment.

[0182] The gate electrodes GE1 and GE2 may include, but are not limited to, titanium (Ti), silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), or alloys thereof.

[0183] The scan write line GWL may be disposed on the second insulating layer 20. The scan write line GWL may include horizontal lines HL and vertical lines VL. The horizontal lines HL may be disposed directly on the second insulating layer 20. The horizontal lines HL may be formed in the same process as the gate electrodes GE1 and GE2. The horizontal lines HL may include, but are not limited to, titanium (Ti), silver (Ag), molybdenum (Mo), aluminum (Al), aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), or alloys thereof.

[0184] A third insulating layer 30 may be disposed on the gate electrodes GE1 and GE2. The third insulating layer 30 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0185] Among the plurality of conductive patterns S1, S2, D1, D2, CPE, CPE1, CPE2, and CPE3, the first capacitor electrode CPE1 and the second capacitor electrode CPE2 constitute a first capacitor C1. The first capacitor electrode CPE1 and the second capacitor electrode CPE2 may be spaced apart by a first insulating layer 10 and a second insulating layer 20.

[0186] In one embodiment of the present invention, the first capacitor electrode CPE1 and the first lower conductive layer BCL1 may have an integral shape. The second capacitor electrode CPE2 and the first gate electrode GE1 may also have an integral shape and be connected to each other, and the capacitor electrode CPE and the second gate electrode GE2 may also have an integral shape and be connected to each other. However, this is merely an example and is not particularly limited thereto. For example, the first capacitor electrode CPE1 and the first lower conductive layer BCL1 may be disposed in the same layer and spaced apart from each other. The second capacitor electrode CPE2 and the first gate electrode GE1 may be disposed in the same layer and spaced apart from each other. The capacitor electrode CPE and the second gate electrode GE2 may be disposed in the same layer and spaced apart from each other.

[0187] A third capacitor electrode CPE3 may be disposed on the third insulating layer 30. The third capacitor electrode CPE3 may be spaced apart from the second capacitor electrode CPE2 via the third insulating layer 30 and may overlap on a plane. The third capacitor electrode CPE3 may form a second capacitor C2 together with the second capacitor electrode CPE2.

[0188] A fourth insulating layer 40 may be disposed on the third insulating layer 30 and / or the third capacitor electrode CPE3. The fourth insulating layer 40 may be an inorganic layer and / or an organic layer and may have a single-layer or multi-layer structure. The fourth insulating layer 40 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0189] A first source electrode pattern S1 and a first drain electrode pattern D1 connected to the first semiconductor pattern SP1, and a second source electrode pattern S2 and a second drain electrode pattern D2 connected to the second semiconductor pattern SP2 may be disposed on the fourth insulating layer 40.

[0190] The first source electrode pattern S1 may be connected to the first source region SR1 of the connection transistor TR1 through the first contact hole CNT1, and the first source electrode pattern S1 and the first source region SR1 of the first semiconductor pattern SP may function as the source of the connection transistor TR1. The first drain electrode pattern D1 may be connected to the first drain region DR_1 of the connection transistor TR1 through the second contact hole CNT2, and the first drain electrode pattern D1 and the first drain region DR_1 of the first semiconductor pattern SP1 may function as the drain of the connection transistor TR1.

[0191] The second source electrode pattern S2 may be connected to the second source region SR2 and the second lower conductive layer BCL2 of the transistor TR2 of the second pixel driver PDC2 through a contact hole. The second source electrode pattern S2 and the second source region SR2 of the second semiconductor pattern SP2 may function as the source of the transistor TR2. The second drain electrode pattern D2 may be connected to the second gate electrode GE2 through a contact hole, and the second gate electrode GE2 may be connected to the second drain region (not shown) of the second semiconductor pattern SP2. That is, the second drain electrode pattern D2 may be connected to the second drain region of the transistor TR2, and the second drain electrode pattern D2 and the second drain region may function as the drain of the transistor TR2.

[0192] Vertical lines VL connected to the horizontal lines HL may be disposed on the fourth insulating layer 40. The vertical lines VL may be electrically connected to the horizontal lines HL through contact holes CNTa. The vertical lines VL may be formed in the same process as the first source electrode pattern S1, the first drain electrode pattern D1, the second source electrode pattern S2, and the second drain electrode pattern D2.

[0193] The fifth insulating layer 50 may be disposed on the first source electrode pattern S1, the first drain electrode pattern D1, the second source electrode pattern S2, and the second drain electrode pattern D2.

[0194] An intermediate connecting electrode CN may be disposed on the fifth insulating layer 50. The intermediate connecting electrode CN may electrically connect the first pixel driver PDC1 and the connecting electrode CNE. That is, the intermediate connecting electrode CN may electrically connect the first pixel driver PDC1 (more specifically, the connection transistor TR1 of the first pixel driver PDC1) and the light emitting device LD. The intermediate connecting electrode CN may be a connection node connecting the first pixel driver PDC1 and the light emitting device LD. That is, the intermediate connecting electrode CN may correspond to the fourth node N4 shown in FIG. 4A, the second node N2 shown in FIG. 4B, or the fourth node N4 shown in FIG. 4C.

[0195] A sixth insulating layer 60 may be disposed on the intermediate connecting electrode CN. The sixth insulating layer 60 may be disposed on the fifth insulating layer 50 to cover at least a portion of the intermediate connecting electrode CN. Each of the fifth insulating layer 50 and the sixth insulating layer 60 may be an organic layer. For example, each of the fifth insulating layer 50 and the sixth insulating layer 60 may include a general-purpose polymer such as BCB (Benzocyclobutene), polyimide, HMDSO (Hexamethyldisiloxane), PMMA (Polymethylmethacrylate), or PS (Polystyrene), a polymer derivative having a phenol-based group, an acrylic-based polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a blend thereof.

[0196] The sixth insulating layer 60 may have a through-hole OP-60 exposing at least a portion of the intermediate connecting electrode CN. The intermediate connecting electrode CN may be connected to the connecting electrode CNE through a portion exposed from the sixth insulating layer 60, and thus may be electrically connected to the light emitting element LD. That is, the intermediate connecting electrode CN, together with the connecting electrode CNE, may electrically connect the connecting transistor TR1 and the light emitting element LD. In the display panel DP according to an embodiment of the present invention, the sixth insulating layer 60 may be omitted or a plurality of sixth insulating layers 60 may be provided, and is not limited to any one embodiment. If the sixth insulating layer 60 is omitted, the intermediate connecting electrode CN may also be omitted.

[0197] The intermediate connecting electrode CN may include a first layer L1, a second layer L2, and a third layer L3 sequentially stacked along a third direction DR3. The second layer L2 may include a different material from the first layer L1. Also, the second layer L2 may include a different material from the third layer L3. The second layer L2 may have a relatively thicker thickness than the first layer L1. Also, the second layer L2 may have a relatively thicker thickness than the third layer L3. The second layer L2 may include a highly conductive material. In one embodiment, the second layer L2 may include aluminum (Al).

[0198] According to the present invention, the second drain electrode pattern D2 and the vertical line VL are disposed on the same layer, and although the second drain electrode pattern D2 and the vertical line VL are not electrically connected, they may overlap each other in a cross-sectional view. "Overlapping each other in a cross-sectional view" means that they overlap each other in a cross-sectional view in a predetermined direction. That is, the second drain electrode pattern D2 and the vertical line VL may overlap each other in a cross-sectional view because they are formed on the same layer, but they are not electrically connected to each other. When the second drain electrode pattern D2 and the vertical line VL, which are not electrically connected, overlap each other in a cross-sectional view, an electric field may fluctuate, and coupling noise caused by the fluctuation in the electric field may be generated or increased.

[0199] A shielding pattern SHP may be further disposed on the fifth insulating layer 50. According to an embodiment of the present invention, the shielding pattern SHP may overlap the vertical line VL and at least a portion of the second drain electrode pattern D2 in a plan view. The shielding pattern SHP may be formed using the same process as the intermediate connecting electrode CN. That is, the shielding pattern SHP may include a first layer L1, a second layer L2, and a third layer L3 sequentially stacked along the third direction DR3, just like the intermediate connecting electrode CN. The shielding pattern SHP may be connected to the second power line VSL (see FIG. 4A) and may receive a second power voltage VSS (see FIG. 4A). The shielding pattern SHP may be connected to the second power line VSL within the display area DA (see FIG. 5). However, the present invention is not limited thereto. The shielding pattern SHP may be connected to the first power line VDL (see FIG. 4A) and may receive a first power voltage VDD (see FIG. 4A).

[0200] According to the present invention, the shielding pattern SHP may overlap the vertical line VL and the second drain electrode pattern D2 on a plane. A second power supply voltage VSS (see FIG. 4A) may be applied to the shielding pattern SHP. That is, by shielding the vertical line VL and the second drain electrode pattern D2 using the shielding pattern SHP to which a constant voltage is supplied, coupling noise formed between the vertical line VL and the second drain electrode pattern D2 may be reduced or eliminated.

[0201] According to the present invention, the second source electrode pattern S2 and the vertical line VL are disposed on the same layer and are not electrically connected to each other, but may overlap each other in cross section. When the second source electrode pattern S2 and the vertical line VL, which are not electrically connected to each other, overlap in cross section, the electric field may fluctuate, and coupling noise caused by the electric field fluctuation may be generated or increased.

[0202] A metal pattern MTP may be further disposed on the fifth insulating layer 50. According to an embodiment of the present invention, the metal pattern MTP may overlap at least a portion of the second source electrode pattern S2 in a plan view. Although not shown in FIG. 9A, the metal pattern MTP may overlap at least a portion of the vertical line VL in a plan view. The metal pattern MTP may be formed using the same process as the intermediate connecting electrodes CN. That is, the metal pattern MTP may include a first layer L1, a second layer L2, and a third layer L3 sequentially stacked along the third direction DR3, just like the intermediate connecting electrodes CN. The metal pattern MTP may be connected to the second power line VSL (see FIG. 4A) and may receive a second power voltage VSS (see FIG. 4A). The metal pattern MTP may be connected to the second power line VSL in the display area DA (see FIG. 5). However, the present invention is not limited thereto. The metal pattern MTP may be connected to the first power line VDL (see FIG. 4A) and may receive a first power voltage VDD (see FIG. 4A).

[0203] According to the present invention, the metal pattern MTP may overlap the vertical line VL and the second source electrode pattern S2 in a plane. A second power supply voltage VSS (see FIG. 4A) may be applied to the metal pattern MTP. That is, by shielding the vertical line VL and the second source electrode pattern S2 using the metal pattern MTP to which a constant voltage is supplied, coupling noise formed between the vertical line VL and the second source electrode pattern S2 may be reduced or eliminated.

[0204] The light emitting element layer LDL may be disposed on the driving element layer DDL, and may include a pixel defining layer PDL, a light emitting element LD, and a separator SPR.

[0205] The pixel-defined layer PDL may be an organic layer, and may include, for example, general-purpose polymers such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), and polystyrene (PS), polymer derivatives having a phenolic group, acrylic polymers, imide polymers, aryl ether polymers, amide polymers, fluorine-based polymers, p-xylene-based polymers, vinyl alcohol-based polymers, and blends thereof.

[0206] In one embodiment, the pixel definition layer PDL may have a light absorbing property, for example, a black color. That is, the pixel definition layer PDL may include a black component (black coloring agent). The black component may include a black dye or a black pigment. The black component may include carbon black, a metal such as chromium, or an oxide thereof. The pixel definition layer PDL may correspond to a light-blocking pattern having a light-blocking property.

[0207] An opening OP-PDL (hereinafter referred to as a light-emitting opening) exposing at least a portion of a first electrode EL1 (described later) may be defined in the pixel defining layer PDL. A plurality of light-emitting openings OP-PDL may be provided and arranged corresponding to each light-emitting element. All components of the light-emitting element LD may be arranged overlapping each other in the light-emitting opening OP-PDL, and the light emitted by the light-emitting element LD may be substantially displayed in the light-emitting opening OP-PDL. Therefore, the shape of the first light-emitting portion EP1 (see FIG. 7C) may substantially correspond to the shape of the light-emitting opening OP-PDL on a plane.

[0208] A connecting electrode CNE may be disposed on the pixel defining layer PDL. The connecting electrode CNE may electrically connect the first pixel driver PDC1 and the light emitting device LD. That is, the first pixel driver PDC1 may be electrically connected to the light emitting device LD via the intermediate connecting electrode CN and the connecting electrode CNE. The connecting electrode CNE may correspond to the first connecting electrode CNE1 shown in FIG. 7A. The second connecting electrode CNE2 (see FIG. 7A) and the third connecting electrode CNE3 (see FIG. 7A) may also have a structure similar to the connecting electrode CNE of FIG. 9A.

[0209] The connecting electrode CNE may include a first edge EG1c adjacent to the light-emitting opening OP-PDL and a second edge EG2c (e.g., EG12, EG22, and EG32 in FIG. 7C) surrounding the first edge EG1c (e.g., EG11, EG21, and EG31 in FIG. 7C). The second electrode EL2 of the light-emitting element LD may be in contact with the connecting electrode CNE in a region adjacent to the second edge EG2c. Note that, in FIG. 9B, one of the opposing second edges EG2c may be, for example, EG12 (FIG. 7C), and the other may be, for example, EG22 (FIG. 7C).

[0210] The connecting electrode CNE may include a transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), or indium oxide (In2O3), but the material constituting the connecting electrode CNE is not limited to these examples.

[0211] A through hole OP-P spaced apart from the light emitting opening OP-PDL may be defined in the pixel defining layer PDL. A plurality of through holes OP-P may be provided and disposed corresponding to each light emitting element. The size of the through hole OP-P defined in the pixel defining layer PDL may be larger than the size of the through hole OP-60 defined in the sixth insulating layer 60. The connecting electrode CNE may be disposed in the through hole OP-P and the through hole OP-60 and connected to the intermediate connecting electrode CN.

[0212] The light emitting element LD may include a first electrode EL1, an intermediate layer IML, and a second electrode EL2.

[0213] The first electrode EL1 may be a semi-transparent, transmissive, or reflective electrode. According to one embodiment of the present invention, the first electrode EL1 may include a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a combination thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In2O3), and aluminum-doped zinc oxide (AZO). For example, the first electrode EL1 may include an ITO / Ag / ITO stacked structure.

[0214] In this embodiment, the first electrode EL1 may be an anode of the light emitting element LD. That is, the first electrode EL1 may be connected to the first power supply line VDL (see FIG. 4A) and may receive the first power supply voltage VDD (see FIG. 4A). The first electrode EL1 may be connected to the first power supply line VDL in the display area DA (see FIG. 5) or may be connected to the first power supply line VDL in the non-display area NDA. In the latter case, the first power supply line VDL may be disposed in the non-display area NDA (see FIG. 5), and the first electrode EL1 may extend to the non-display area NDA.

[0215] 9A shows the first electrode EL1 overlapping the light emitting opening OP-PDL and not overlapping the separator SPR, but as described above in FIG. 7D, the first electrode EL1 of the light emitting device may have a one-piece shape and a mesh or lattice shape with openings defined in some areas. That is, as long as the same first power supply voltage VDD can be applied to the first electrode EL1 of each of the plurality of light emitting devices, the shape of the first electrode EL1 may be various and is not limited to any one embodiment.

[0216] The intermediate layer IML may be disposed between the first electrode EL1 and the second electrode EL2. The intermediate layer IML may include an emitting layer EML and a functional layer FNL. The light-emitting element LD may include the intermediate layer IML with various structures and is not limited to any one embodiment. For example, the functional layer FNL may be provided as a plurality of layers, or may be provided as two or more layers separated by the emitting layer EML.

[0217] The emission layer EML may include an organic light-emitting material. The emission layer EML may also include an inorganic light-emitting material, or may be a mixed layer of an organic light-emitting material and an inorganic light-emitting material. In this embodiment, the emission layers EML included in adjacent emission units EP (see EP1 to EP3 in FIG. 7A) may include light-emitting materials that display different colors. For example, the emission layer EML included in each emission unit EP may emit one of blue, red, and green light. However, the present invention is not limited thereto, and the emission layers EML disposed in all emission units EP may include light-emitting materials that display the same color. In this case, the emission layers EML may emit blue light or white light.

[0218] The functional layer FNL may be disposed between the first electrode EL1 and the second electrode EL2. Specifically, the functional layer FNL may include a first intermediate functional layer FNLa (see FIG. 9B) disposed between the first electrode EL1 and the emitting layer EML, and a second intermediate functional layer FNLb (see FIG. 9B) disposed between the second electrode EL2 and the emitting layer EML. In one embodiment of the present invention, one of the first intermediate functional layer FNLa and the second intermediate functional layer FNLb may be omitted. In this embodiment, the emitting layer EML is illustrated as being inserted within the functional layer FNL. That is, it can be understood that the emitting layer EML is disposed between the first intermediate functional layer FNLa and the second intermediate functional layer FNLb.

[0219] The functional layer FNL can control charge transfer between the first electrode EL1 and the second electrode EL2. For example, the first intermediate functional layer FNLa can include a hole injection / transport material and / or an electron injection / transport material. The second intermediate functional layer FNLb can include at least one of an electron blocking layer, a hole transport layer, a hole injection layer, a hole blocking layer, an electron transport layer, an electron injection layer, and a charge generation layer.

[0220] The second electrode EL2 may be disposed on the intermediate layer IML. As described above, the second electrode EL2 may be connected to the connecting electrode CNE and electrically connected to the first pixel driver PDC1. That is, the second electrode EL2 may be electrically connected to the connecting transistor TR1 through the connecting electrode CNE.

[0221] The separator SPR may be disposed on the pixel defining layer PDL. In one embodiment, the second electrode EL2 and the functional layer FNL may be formed by common deposition on a plurality of pixels through an open mask. At this time, the second electrode EL2 and the functional layer FNL may be divided by the separator SPR. As described above, the separator SPR may have a closed line shape for each light emitting portion, and accordingly, the second electrode EL2 and the functional layer FNL may have a divided shape for each light emitting portion. In other words, the second electrode EL2 and the intermediate layer IML may be electrically independent for each adjacent pixel. The separator SPR will be described in detail below with reference to FIG. 9B.

[0222] 9A and 9B, the separator SPR may be disposed on the connecting electrode CNE disposed on the pixel defining layer PDL and on the gap GP between the connecting electrode CNE and the adjacent connecting electrode CNEn adjacent to the connecting electrode CNE.

[0223] The separator SPR may have a tapered shape. That is, the separator SPR may have a shape in which its width increases as it gets farther from the top surface of the pixel defining layer PDL (as it moves upward in FIG. 9B, etc.). The side surface TP of the separator SPR may have a shape in which the taper angle inclined from the top surface of the pixel defining layer PDL is an obtuse angle. However, this is merely an example, and as long as the separator SPR can electrically disconnect the second electrode EL2 for each pixel, the taper angle of the separator SPR may be set in various ways, for example, a dual structure with different taper angles may be used. The separator SPR may also have a tip-like structure, and is not limited to any one embodiment.

[0224] The separator SPR may include an insulating material, particularly an organic insulating material. The separator SPR may include an inorganic insulating material, may be formed of a multilayer of organic and inorganic insulating materials, or may include a conductive material depending on the embodiment. That is, the separator SPR is not particularly limited in terms of the type of material as long as it can electrically disconnect the second electrode EL2 for each pixel.

[0225] A dummy layer UP may be disposed on the separator SPR. The dummy layer UP may include a first dummy layer UP1 disposed on the separator SPR and a second dummy layer UP2 disposed on the first dummy layer UP1. The first dummy layer UP1 may be formed in the same process as the functional layer FNL and may include the same material. The first dummy layer UP1 may include a first dummy layer UP1a and a first dummy layer UP1b. The first dummy layer UP1a may be formed in the same process as the first intermediate functional layer FNLa and may include the same material. The first dummy layer UP1b may be formed in the same process as the second intermediate functional layer FNLb and may include the same material. The second dummy layer UP2 may be formed in the same process as the second electrode EL2 and may include the same material. That is, the first dummy layer UP1 and the second dummy layer UP2 may be formed simultaneously during the formation of the functional layer FNL and the second electrode EL2. 9A and 9B, the dummy layer UP may be formed not only on the top surface of the separator SPR but also on a portion of the side surface TP. In another embodiment, the display panel DP may not include the dummy layer UP. The dummy layer UP may be out of contact with the connecting electrode CNE and the second electrode EL2. The second dummy layer UP2 included in the dummy layer UP may be out of contact with the connecting electrode CNE and the second electrode EL2.

[0226] A portion where the second electrode EL2 contacts the connecting electrode CNE may be defined as a contact region. The contact region is provided adjacent to the separator SPR. In the contact region, an upper surface CNE-us of the connecting electrode CNE contacts a lower surface EL2-bs of the second electrode EL2. Because the separator SPR has a tapered shape and the contact region is provided adjacent to the separator SPR, at least a portion of the contact region where the second electrode EL2 contacts the connecting electrode CNE may be disposed under a side surface TP of the separator SPR.

[0227] In one embodiment, at least a portion of the connecting electrode CNE may be disposed under the separator SPR. The separator SPR may be disposed on the connecting electrode CNE and a gap GP between the connecting electrode CNE and an adjacent connecting electrode adjacent to the connecting electrode CNE, and the second edge EG2c of the second electrode EL2 may be covered by the separator SPR.

[0228] According to an embodiment of the present invention, the connecting electrode CNE has a shape that surrounds at least a portion of the light-emitting area EA in which the light-emitting element LD is disposed. Therefore, the degree of freedom in the position at which the connecting electrode CNE and the light-emitting element LD are connected and the degree of freedom in the position at which the connecting electrode CNE and the pixel driving circuit PDC are connected can be improved. Furthermore, the upper surface CNE-us of the connecting electrode CNE can be in contact with the lower surface EL2-bs of the second electrode EL2 of the light-emitting element LD through the contact region defined adjacent to the separator SPR. Therefore, the contact reliability between the connecting electrode CNE and the second electrode EL2 can be improved. Furthermore, the lower surface of the connecting electrode CNE is in contact with the upper surface of the intermediate connecting electrode CN, thereby improving the contact reliability. The display panel DP according to the embodiment can reduce or minimize the size of the through-holes OP-P and OP-60 for connecting the connecting electrode CNE and the intermediate connecting electrode CN through the above-described structure, thereby easily increasing the area or resolution of the light-emitting portion of the display panel DP.

[0229] 9A again, an encapsulation layer ECL may be disposed on the light emitting element layer LDL. The encapsulation layer ECL may cover the light emitting element LD and the separator SPR. The encapsulation layer ECL may include a first inorganic layer IL1, an organic layer OL, and a second inorganic layer IL2, which are sequentially stacked. However, without being limited thereto, the encapsulation layer ECL may further include a plurality of inorganic layers and organic layers. The encapsulation layer ECL may also be a glass substrate.

[0230] The first and second inorganic layers IL1 and IL2 protect the light emitting device LD from moisture and oxygen outside the display panel DP, and the organic layer OL protects the light emitting device LD from foreign substances such as particles remaining during the formation of the first inorganic layer IL1. The first and second inorganic layers IL1 and IL2 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, etc. The organic layer OL may include an acrylic organic layer, and the type of material is not limited to any one of them.

[0231] The sensing layer ISL can sense an external input. In this embodiment, the sensing layer ISL can be formed on the encapsulation layer ECL through a continuous process. At this time, the sensing layer ISL can be expressed as being directly disposed on the encapsulation layer ECL. "Directly disposed" can mean that no other components are disposed between the sensing layer ISL and the encapsulation layer ECL. That is, a separate adhesive member does not need to be disposed between the sensing layer ISL and the encapsulation layer ECL. However, this is merely an example, and in the display panel DP according to an embodiment of the present invention, the sensing layer ISL can be formed separately and then coupled to the display panel DP through an adhesive member, and the present invention is not limited to any one embodiment.

[0232] The sensing layer ISL may include a plurality of conductive layers and a plurality of insulating layers. The plurality of conductive layers may include a first sensing conductive layer MTL1 and a second sensing conductive layer MTL2, and the plurality of insulating layers may include first to third sensing insulating layers 71, 72, and 73. However, this is merely an example, and the number of conductive layers and insulating layers is not limited to any one embodiment.

[0233] Each of the first to third sensing insulating layers 71, 72, and 73 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3. The first to third sensing insulating layers 71, 72, and 73 may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. The first to third sensing insulating layers 71, 72, and 73 may include an organic film. The organic film may include at least one of acrylic resin, methacrylic resin, polyisoprene, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0234] The first sensing conductive layer MTL1 may be disposed between the first sensing insulating layer 71 and the second sensing insulating layer 72, and the second sensing conductive layer MTL2 may be disposed between the second sensing insulating layer 72 and the third sensing insulating layer 73. A portion of the second sensing conductive layer MTL2 may be connected to the first sensing conductive layer MTL1 through a contact hole CNT formed in the second sensing insulating layer 72. Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may have a single-layer structure or a multi-layer structure stacked along the third direction DR3.

[0235] The single-layer sensing conductive layer can include a metal layer or a transparent conductive layer. The metal layer can include molybdenum, silver, titanium, copper, aluminum, or an alloy thereof. The transparent conductive layer can include a transparent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium zinc tin oxide (IZTO). Alternatively, the transparent conductive layer can include a conductive polymer such as PEDOT, a metal nanowire, graphene, or the like.

[0236] The multi-layered sensing conductive layer can include a metal layer, such as a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti), or can include at least one metal layer and at least one transparent conductive layer.

[0237] The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may constitute a sensor that senses an external input in the sensing layer ISL. The sensor may be driven in a capacitive manner, and may be driven by either a mutual capacitance (mutual-capacitance) or a self-capacitance (self-capacitance) manner. However, this is merely an example, and the sensor may be driven by a resistive, ultrasonic, or infrared method in addition to the capacitive method, and is not limited to any one embodiment.

[0238] Each of the first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may include a transparent conductive oxide or may have a metal mesh shape formed of an opaque conductive material. The first sensing conductive layer MTL1 and the second sensing conductive layer MTL2 may have various materials and shapes as long as the visibility of the image displayed by the display panel DP is not reduced, and are not limited to any one embodiment.

[0239] 10A and 10B are cross-sectional views of a display panel according to another embodiment of the present invention, showing a portion corresponding to line II' in FIG. 7A. Hereinafter, descriptions that overlap with those previously described will be omitted.

[0240] 10A, the display panel DPa of the present invention may include a shielding pattern SHPa disposed on the fifth insulating layer 50. According to an embodiment of the present invention, the shielding pattern SHPa may overlap the vertical line VL and at least a portion of the second drain electrode pattern D2 in a plan view. The shielding pattern SHPa may be formed in the same process as the intermediate connecting electrode CN. The shielding pattern SHPa may be connected to the third power line VRL (see FIG. 4A) and may receive the third power voltage VREF. The shielding pattern SHPa may be connected to the third power line VRL within the display area DA (see FIG. 5).

[0241] By shielding the vertical line VL and the second drain electrode pattern D2 using the shielding pattern SHPa to which a constant voltage is applied, coupling noise formed between the vertical line VL and the second drain electrode pattern D2 can be reduced or eliminated.

[0242] Referring to FIG. 10B, the driving element layer DDL of the display panel DPb of the present invention may include insulating layers 10a and 10b. According to an embodiment of the present invention, the driving element layer DDL may include a sub-shielding pattern SSHP disposed on the base layer BS. The sub-shielding pattern SSHP may be covered by the first insulating layer 10a among the insulating layers 10a and 10b. According to an embodiment of the present invention, the sub-shielding pattern SSHP may overlap the vertical line VL and at least a portion of the second drain electrode pattern D2 in a plan view. The sub-shielding pattern SSHP may be connected to the second power supply line VSL (see FIG. 4A) and may receive the second power supply voltage VSS (see FIG. 4A). The sub-shielding pattern SSHP may be connected to the second power supply line VSL within the display area DA (see FIG. 5). However, the present invention is not limited thereto. The sub-shielding pattern SSHP may be connected to the first power supply line VDL (see FIG. 4A) and may receive the first power supply voltage VDD (see FIG. 4A).

[0243] 10B, the sub-shielding pattern SSHP may be disposed in the same layer as the lower conductive layers BCL1 and BCL2. That is, the sub-shielding pattern SSHP may be formed in the same process as the lower conductive layers BCL1 and BCL2. In this case, the sub-shielding pattern SSHP may be referred to as a third lower conductive layer.

[0244] By shielding the vertical line VL and the second drain electrode pattern D2 using the sub-shielding pattern SSHP to which a constant voltage is applied, coupling noise formed between the vertical line VL and the second drain electrode pattern D2 can be reduced or eliminated.

[0245] Figure 11A is a simplified plan view of a display panel according to an embodiment of the present invention. Figure 11B is an enlarged cross-sectional view of a CC' region in Figure 11A. Figure 11C is an enlarged cross-sectional view of a DD' region in Figure 11A. Figure 11D is a block diagram of a gate driver according to an embodiment of the present invention. Hereinafter, descriptions that overlap with those previously described will be omitted.

[0246] 11A, the display panel DPc may include a write scan line GWLa. A plurality of write scan lines GWLa may be provided. The write scan line GWLa will be described in detail with reference to FIGS. 11B and 11C.

[0247] 11B and 11C show write scan lines GWL1a, GWL2a, GWL3a, GWLn-2, ​​GWLn-1, and GWLn. The write scan lines GWL1a, GWL2a, GWL3a, GWLn-2, ​​GWLn-1, and GWLn may be part of the write scan line GWLa shown in FIG. 11A.

[0248] 11A to 11C, the first scan write line GWL1a may include first vertical lines VL1a and VL2a extending in the second direction DR2 and a first horizontal line HL1 extending in the first direction DR1. The first vertical lines VL1a and VL2a and the first horizontal line HL1 may be disposed on different layers. The first vertical lines VL1a and VL2a may include a first sub-vertical line VL1a and a second sub-vertical line VL2a spaced apart from each other in the first direction DR1 and extending side by side in the second direction DR2. The first sub-vertical line VL1a and the first horizontal line HL1 may be connected to each other through a contact hole CNTa. Hereinafter, the description of the write scan lines GWL2a, GWL3a, GWLn-2, ​​GWLn-1, and GWLn may be the same as the description of the first scan write line GWL1a.

[0249] The second scan write line GWL2a may include second vertical lines VL1b and VL2b and a sixth horizontal line HL6. The second vertical lines VL1b and VL2b may include a first sub-vertical line VL1b and a second sub-vertical line VL2b spaced apart from each other in the first direction DR1 and extending side by side in the second direction DR2. The first sub-vertical line VL1b and the sixth horizontal line HL6 may be connected to each other through contact holes CNTf.

[0250] The third scan write line GWL3a may include third vertical lines VL1c and VL2c and an eleventh horizontal line HL11. The third vertical lines VL1c and VL2c may include a first sub-vertical line VL1c and a second sub-vertical line VL2c spaced apart from each other in the first direction DR1 and extending side by side in the second direction DR2. The first sub-vertical line VL1c and the eleventh horizontal line HL11 may be connected to each other through a contact hole CNTk.

[0251] The nth scan write line GWLn may include nth vertical lines VL1n and VL2n, or may further include a first horizontal line HL1. The nth vertical lines VL1n and VL2n may include a first sub-vertical line VL1n and a second sub-vertical line VL2n spaced apart from each other in the first direction DR1 and extending side by side in the second direction DR2. The second sub-vertical line VL2n and the first horizontal line HL1 may be connected to each other through a contact hole CNT1.

[0252] The (n-1)th scan write line GWLn-1 may include the (n-1)th vertical lines VL1n-1 and VL2n-1. Alternatively, the (n-1)th scan write line GWLn-1 may further include a sixth horizontal line HL6. The (n-1)th vertical lines VL1n-1 and VL2n-1 may include a first sub-vertical line VL1n-1 and a second sub-vertical line VL2n-1 spaced apart from each other in the first direction DR1 and extending side by side in the second direction DR2. The second sub-vertical line VL2n-1 and the sixth horizontal line HL6 may be connected to each other through a contact hole CNTm.

[0253] The (n-2)th scan write line GWLn-2 may include the (n-2)th vertical lines VL1n-2 and VL2n-2. Alternatively, the (n-2)th scan write line GWLn-2 may further include the eleventh horizontal line HL11. The (n-2)th vertical lines VL1n-2 and VL2n-2 may include a first sub-vertical line VL1n-2 and a second sub-vertical line VL2n-2 spaced apart from each other in the first direction DR1 and extending side by side in the second direction DR2. The second sub-vertical line VL2n-2 and the eleventh horizontal line HL11 may be connected to each other through a contact hole CNTn.

[0254] The first horizontal line HL1 may be connected to the first sub-vertical line VL1a and the second sub-vertical line VL2n, the sixth horizontal line HL6 may be connected to the first sub-vertical line VL1b and the second sub-vertical line VL2n-1, and the eleventh horizontal line HL11 may be connected to the first sub-vertical line VL1c and the second sub-vertical line VL2n-2.

[0255] FIG. 11D is a block diagram showing stages ST-W1, ST-W2, ST-C, ST-R, ST-E1, and ST-E2 to explain the gate driver GDCa of FIG. 11A.

[0256] 11D, the gate driver GDCa may include a first write stage ST-W1, a second write stage ST-W2, a compensation stage ST-C, a reset stage ST-R, a first light-emitting stage ST-E1, and a second light-emitting stage ST-E2. The first write stage ST-W1 includes a plurality of stages ST1 to ST n The second write stage ST-W2 includes a plurality of stages ST1a to ST n a, and the compensation stage ST-C includes a plurality of stages ST1b to ST n / 2 b, and the reset stage ST-R is a series of stages ST1c to ST n / 2 The first light-emitting stage ST-E1 includes a plurality of stages ST1d to ST n / 2The second light-emitting stage ST-E2 includes a plurality of stages ST1e to ST n / 2 According to one embodiment of the present invention, a plurality of stages ST1 to ST n and multiple stages ST1a to ST n In other words, according to an embodiment of the present invention, as shown in FIG. n The direction in which the stages ST1a to ST n The directions in which the a's are arranged in order are opposite to each other. n respectively output first to n-th write scan signals GW1 to GWn, and a plurality of stages ST1a to ST n a output the first to n-th write scan signals GW1 to GWn, respectively.

[0257] As shown in FIG. 11D, multiple stages ST1 to ST n outputs first to n-th write scan signals GW1 to GWn, and n a outputs first to n-th write scan signals GW1 to GWn, and a plurality of stages ST1b to ST n / 2 b outputs first to n-th compensation scan signals GC1 to GCn, and a plurality of stages ST1c to ST n / 2 c outputs first to n-th reset scan signals GW1 to GWn, and a plurality of stages ST1d to ST n / 2 d outputs 1-1 to 1-n light emission signals EM1-1 to EM1-n, and n / 2 The 2-1 to 2-n light emission signals EM2-1 to EM2-n can be output.

[0258] 11A to 11D, pixels arranged in the first row among the plurality of pixels PX11 to PXnm may be connected to a first horizontal line HL1. For example, the first horizontal line HL1 may receive a first write scan signal GW1 from the first vertical line VL1a and a first write scan signal GW1 from the second sub-vertical line VL2n and supply the signal to the first row pixel driving units PDU11, PDU12, PDU1n-1, and PDU1n. That is, the first horizontal line HL1 may supply the first write scan signal GW1 to all pixel driving units arranged in the first row. All pixel driving units arranged in the first row may receive the same first write scan signal GW1. By receiving the same first write scan signal GW1 on both sides of all pixel driving units arranged in the first row, delays in signals applied according to the positions of the first row pixel driving units may be reduced.

[0259] 8 and 11D, among the pixels PX11 to PXnm, the pixels arranged in the first row may be connected to the second horizontal line HL2, and the pixels arranged in the second row may be connected to the seventh horizontal line HL7. For example, the second horizontal line HL2 may receive the first compensation scan signal GC1 from the second vertical line VL2 and supply it to the pixel driving units PDU11, PDU12, PDU1n-1, and PDU1n of the first row, and the seventh horizontal line HL7 may receive the second compensation scan signal GC2 from the second vertical line VL2 and supply it to the pixel driving units PDU21, PDU22, PDU2n-1, and PDU2n of the second row. That is, the second horizontal line HL2 may supply the first compensation scan signal GC1 to all pixel driving units arranged in the first row, and the seventh horizontal line HL7 may supply the second compensation scan signal GC2 to all pixel driving units arranged in the second row. According to one embodiment, the first compensation scan signal GC1 and the second compensation scan signal GC2 may be the same. That is, all pixel driving units arranged in the first and second rows may receive the same compensation scan signal. Similarly, the first to n-th reset scan signals GW1 to GWn, the 1-1st to 1-nth light emitting signals EM1-1 to EM1-n, and the 2-1st to 2-nth light emitting signals EM2-1 to EM2-n may be applied to the pixels PX11 to PXnm.

[0260] FIG. 12 is a plan view showing a simplified display panel according to an embodiment of the present invention.

[0261] 12, the display panel DPd of the present invention may include a gate driver GDCb, a first driver GWD1, and a second driver GWD2. The first driver GWD1 may be connected to one side of a write signal line GWLb, and the second driver GWD2 may be connected to the other side of the write signal line GWLb. The first driver GWD1 may be disposed in a first region (e.g., a left region) of the non-display area NDA, the second driver GWD2 may be disposed in a second region (e.g., a right region) of the non-display area NDA, and the gate driver GDCb may be disposed in a third region (e.g., a lower region) of the non-display area NDA.

[0262] 11D and 12, the first driver GWD1 includes a first write stage ST-W1, the second driver GWD2 includes a second write stage ST-W2, and the gate driver GDCb includes a compensation stage ST-C, a reset stage ST-R, a first light-emitting stage ST-E1, and a second light-emitting stage ST-E2. That is, the first driver GWD1 outputs first to n-th write scan signals GW1 to GWn, the second driver GWD2 outputs first to n-th write scan signals GW1 to GWn, and the gate driver GDCb outputs first to n-th compensation scan signals GC1 to GCn, first to n-th reset scan signals GW1 to GWn, 1-1 to 1-n light-emitting signals EM1-1 to EM1-n, and 2-1 to 2-n light-emitting signals EM2-1 to EM2-n.

[0263] 13A through 13G are process diagrams illustrating the placement sequence of circuit layers according to one embodiment of the present invention.

[0264] 13A to 13G, the conductive patterns and the semiconductor patterns may have a structure in which they are repeatedly arranged in a predetermined pattern on a plane. Figures 13A to 13G illustrate a portion of one of the first to third pixel drivers PDC1, PDC2, and PDC3 shown in Figure 6.

[0265] Referring to FIG. 13A, a sub-shielding pattern SSHP may be formed on the base layer BS. The sub-shielding pattern SSHP may correspond to the sub-shielding pattern SSHP shown in FIG. 10B. The sub-shielding pattern SSHP may be disposed below the second drain electrode pattern D2 included in the second pixel driver PDC2 (see FIG. 10B). The sub-shielding pattern SSHP may be connected to the second power supply line VSL within the display area DA (see FIG. 5). However, the present invention is not limited thereto, and the sub-shielding pattern SSHP may be connected to the first power supply line VDL (see FIG. 4A) and may receive the first power supply voltage VDD (see FIG. 4A).

[0266] 13A and 13B, lower conductive layers BCLa, BCLb, and BLCc (e.g., corresponding to BCL1 and BCL2 in FIG. 10B) may be disposed on the sub-shielding pattern SSHP. The lower conductive layers BCLa, BCLb, and BLCc may block light incident on the transistor TR1 or TR2 (see FIG. 9A) at their bottoms.

[0267] 13C, a semiconductor pattern layer ACT may be disposed on the first insulating layer 10. The semiconductor pattern layer ACT may include a silicon semiconductor. For example, the silicon semiconductor may include amorphous silicon, polycrystalline silicon, etc. For example, the semiconductor pattern layer ACT may include low-temperature polysilicon (LTPS). The semiconductor pattern layer ACT may correspond to the second semiconductor pattern SP2 shown in FIG. 9A, for example.

[0268] A reference voltage line VRL, a second light-emitting line ESL2, a first initialization voltage line VIL1, and a second initialization voltage line VIL2 may be further disposed on the first insulating layer 10. The reference voltage line VRL, the second light-emitting line ESL2, the first initialization voltage line VIL1, and the second initialization voltage line VIL2 may each extend in a first direction DR1.

[0269] The reference voltage line VRL may correspond to, for example, the third power supply line VRL in FIG. 4C. For example, the reference voltage VREF (see FIG. 4C) may be provided to the reference voltage line VRL. The reference voltage line VRL may be connected to the third transistor T3 in FIG. 4C.

[0270] The second light emitting line ESL2 may correspond to, for example, the i-th second light emitting line ESL2i in FIG. 4C. The second light emitting signal EM2 (see FIG. 4C) may be provided to the second light emitting line ESL2. The second light emitting line ESL2 may be connected to, for example, the fifth transistor T5a in FIG. 4C.

[0271] The first initialization voltage line VIL1 may correspond to, for example, the fourth power supply line VIL1 in FIG. 4A. For example, the first initialization voltage VINT1 (see FIG. 4A) may be provided to the first initialization voltage line VIL1. The first initialization voltage line VIL1 may be connected to, for example, the fourth transistor T4 in FIG. 4A.

[0272] The second initialization voltage line VIL2 may correspond to, for example, the fifth power supply line VIL2 of FIG. 4A. For example, the second initialization voltage VINT2 (see FIG. 4A) may be provided to the second initialization voltage line VIL2. The second initialization voltage line VIL2 may be connected to, for example, the eighth transistor T8 of FIG. 4A.

[0273] 13C and 13D, a second insulating layer 20 may be disposed on the first insulating layer 10, covering the semiconductor pattern layer ACT. A gate pattern layer GAT may be disposed on the second insulating layer 20. The gate pattern layer GAT may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like. For example, the gate pattern layer GAT may include, but is not limited to, silver (Ag), a silver-containing alloy, molybdenum (Mo), a molybdenum-containing alloy, aluminum (Al), an aluminum-containing alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), or the like.

[0274] The gate pattern layer GAT may include second gate electrodes GE2, reset scan lines GRL, horizontal lines HL, first light-emitting lines ESL1, and compensation scan lines GCL, which may extend in a first direction DR1.

[0275] The second gate electrode GE2 may be arranged in an island shape, and together with a semiconductor pattern layer ACT (see FIG. 13C), may form, for example, the second transistor T2 of FIG. 9A.

[0276] The reset scan line GRL may correspond to, for example, the i-th fifth scan line GRLi in FIG. 4C. For example, the reset scan signal GR (see FIG. 4C) may be provided to the reset scan line GRL. The reset scan line GRL may be connected to, for example, the third transistor T3 in FIG. 4C.

[0277] The horizontal line HL may correspond to one configuration of the i-th write scan line GWLi in Figure 4C. For example, the write scan signal GW (see Figure 4C) may be provided to the horizontal line HL. The horizontal line HL may be connected to the second transistor T2 in Figure 4C.

[0278] The first light emitting line ESL1 may correspond to the i-th first light emitting line ESL1i in FIG. 4C. The first light emitting signal EM1 (see FIG. 4C) may be provided to the first light emitting line ESL1. The first light emitting line ESL1 may be connected to the fourth transistor T4a in FIG. 4C.

[0279] The compensation scan line GCL may correspond to the i-th second scan line GCLi in Figure 4C. For example, the compensation scan signal GC (see Figure 4C) may be provided to the compensation scan line GCL. The compensation scan line GCL may be connected to the sixth transistor T6a in Figure 4C.

[0280] 13E, a data pattern layer SD may be disposed on the fourth insulating layer 40. For example, the data pattern layer SD may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, or the like.

[0281] The data pattern layer SD may include a second drain electrode pattern D2, connecting patterns CNEP1 and CNEP2, a data line DL, a second power line VSL, and a vertical line VL, and the data line DL, second power line VSL, and vertical line VL may each extend in a second direction DR2.

[0282] The second drain electrode pattern D2 may correspond to the second drain electrode pattern D2 in Fig. 9A. The second drain electrode pattern D2 may be connected to the second gate electrode GE2 through a contact hole.

[0283] The connecting patterns CNEP1 and CNEP2 may include a first connecting pattern CNEP1 and a second connecting pattern CNEP2, which may correspond to the second source electrode pattern S2 of FIG.

[0284] The data line DL may correspond to one configuration of the j-th data line DLj in Figure 4C. For example, a data signal DATA (see Figure 4C) may be provided to the data line DL. The data line DL may be connected to the second transistor T2 in Figure 4C.

[0285] The second power supply line VSL may correspond to the second power supply line VSL in FIG. 4C. For example, the second power supply voltage VSS (see FIG. 4C) may be provided to the second power supply line VSL. The second power supply line VSL may be arranged in a mesh pattern within the display area DA (see FIG. 5) of the display panel DP. The second power supply line VSL may be connected to the fifth transistor T5a and the second capacitor C2 shown in FIG. 4C through a contact portion.

[0286] The vertical line VL may correspond to one configuration of the i-th write scan line GWLi in FIG. 4C. For example, the write scan signal GW (see FIG. 4C) may be provided to the vertical line VL. The vertical line VL may be connected to the second transistor T2 in FIG. 4C. The vertical line VL may be electrically connected to the horizontal line HL (see FIG. 13D) through a contact hole CNTa.

[0287] 13E and 13F, a shielding pattern SHP may be disposed on the fifth insulating layer 50. For example, the shielding pattern SHP may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. The shielding pattern SHP may be disposed in an island shape. The shielding pattern SHP may overlap the vertical line VL and at least a portion of the second drain electrode pattern D2 in a plan view. However, the present invention is not limited thereto, and the shielding pattern SHP may extend along the vertical line VL.

[0288] The shielding pattern SHP may be connected to the second power line VSL through a contact hole CNTo. The shielding pattern SHP may receive the second power voltage VSS (see FIG. 4C) through the second power line VSL. By shielding the vertical line VL and the second drain electrode pattern D2 using the shielding pattern SHP to which a constant voltage is supplied, coupling noise formed between the vertical line VL and the second drain electrode pattern D2 may be reduced or eliminated.

[0289] 13E and 13G, as another manufacturing method of FIG. 13F, a shielding pattern SHPa may be disposed on the fifth insulating layer 50. For example, the shielding pattern SHP may include a metal, an alloy, a conductive metal oxide, a transparent conductive material, etc. The shielding pattern SHP may be disposed in an island shape. The shielding pattern SHP may overlap the vertical line VL and at least a portion of the second drain electrode pattern D2 in a plan view. However, the present invention is not limited thereto, and the shielding pattern SHP may overlap the entire second drain electrode pattern D2.

[0290] The shielding pattern SHPa may be connected to the reference voltage line VRL (see FIG. 13C) through a contact hole CNTp. The shielding pattern SHPa may receive a reference voltage VREF (see FIG. 4C) through the reference voltage line VRL. By shielding the vertical line VL and the second drain electrode pattern D2 using the shielding pattern SHPa to which a constant voltage is supplied, coupling noise formed between the vertical line VL and the second drain electrode pattern D2 may be reduced or eliminated.

[0291] Fig. 14 is a perspective view of an electronic device according to an embodiment of the present invention, and Fig. 15 is a view showing a folded state of the electronic device shown in Fig. 14.

[0292] 14, the electronic device ED according to an embodiment of the present invention may have a rectangular shape having a short side extending in a first direction DR1 and a long side extending in a second direction DR2 intersecting the first direction DR1. However, the electronic device ED is not limited thereto and may have various shapes such as a circle and a polygon. The electronic device ED may be flexible.

[0293] The electronic device ED may include a folding area FA and a plurality of non-folding areas NFA1, NFA2. The non-folding areas NFA1, NFA2 may include a first non-folding area NFA1 and a second non-folding area NFA2. The folding area FA may be disposed between the first non-folding area NFA1 and the second non-folding area NFA2. The folding area FA, the first non-folding area NFA1, and the second non-folding area NFA2 may be arranged in a first direction DR1.

[0294] Although one folding area FA and two non-folding areas NFA1 and NFA2 are illustrated by way of example, the number of folding areas FA and non-folding areas NFA1 and NFA2 is not limited thereto. For example, the electronic device ED may include more than two non-folding areas and multiple folding areas disposed between the non-folding areas.

[0295] The top surface of the electronic device ED may be defined as a display surface DS, and the display surface DS may have a plane defined by a first direction DR1 and a second direction DR2. An image IM generated by the electronic device ED may be provided to a user through the display surface DS.

[0296] The display surface DS may include a display area DA and a non-display area NDA surrounding the display area DA. The display area DA may display an image, while the non-display area NDA may not display an image. The non-display area NDA may surround the display area DA and define a border of the electronic device ED that is printed in a predetermined color.

[0297] Referring to FIG. 15 , the electronic device ED may be a foldable electronic device ED that can be folded or unfolded. For example, the folding area FA may be folded based on a folding axis FX that is parallel to the second direction DR2, thereby folding the electronic device ED. The folding axis FX may be defined as a major axis that is parallel to the long side of the electronic device ED. When folding the electronic device ED, the first non-folding area NFA1 and the second non-folding area NFA2 face each other, and the electronic device ED may be in-folded so that the display surface DS is not exposed to the outside. However, embodiments of the present invention are not limited thereto. For example, although not shown, the electronic device ED may be out-folded so that the display surface DS is exposed to the outside around the folding axis FX. Also, although not shown, the electronic device ED may be in-folded and out-folded simultaneously.

[0298] FIG. 16 is an exploded perspective view of the electronic device shown in FIG.

[0299] 16, the electronic device ED may include a display device DD, an electronic module EM, a power supply module PSM, and a hinge module EDC. Although not shown, the electronic device ED may further include a fixture structure (e.g., a hinge) for controlling the folding operation of the display device DD.

[0300] The display device DD can generate an image and sense an external input. The display device DD can include a window module WM and a display module DM. The window module WM can provide a front surface of the electronic device ED. The window module WM is disposed on the display module DM to protect the display module DM. The window module WM can transmit light generated by the display module DM to provide it to a user.

[0301] The display module DM may include a display panel DP. Although only the display panel DP is illustrated in Fig. 16 among the laminated structure of the display module DM, the display module DM may actually further include a plurality of components disposed above and below the display panel DP. The display panel DP may include a display area DA and a non-display area NDA corresponding to the display area DA and non-display area NDA of the electronic device ED in Fig. 14.

[0302] The display module DM may include a data driver DDC disposed on the non-display area NDA of the display panel DP. The data driver DDC may be directly manufactured in the form of a circuit chip and mounted on the non-display area NDA. However, the present invention is not limited thereto, and the data driver DDC may be mounted on a flexible circuit board connected to the display panel DP.

[0303] The electronic module EM and the power supply module PSM may be disposed within the hinge module EDC. For example, FIG. 16 illustrates a state in which the electronic module EM and the power supply module PSM are exposed to the outside from the hinge module EDC. Although not shown, the electronic module EM and the power supply module PSM may be connected to each other via another flexible circuit board. The electronic module EM may control the operation of the display device DD. The power supply module PSM may supply power to the electronic module EM.

[0304] The hinge module EDC can accommodate the display device DD, the electronic module EM, and the power module PSM. The hinge module EDC can include two housings, first and second housings HS1 and HS2, for folding the display device DD. The first and second housings HS1 and HS2 can extend in a second direction DR2 and be arranged in a first direction DR1.

[0305] The hinge module EDC may include a housing assembly HS. The housing assembly HS may include a first housing HS1 and a second housing HS2 spaced apart in a first direction DR1, and a hinge housing HGH disposed between the first housing HS1 and the second housing HS2. The hinge module EDC may further include hinges HG1 and HG2 for connecting the first and second housings HS1 and HS2, a plurality of main plates, and a plurality of moving plates.

[0306] FIG. 17 is a block diagram of the electronic device shown in FIG.

[0307] 17, the electronic device ED may include an electronic module EM, a power supply module PSM, and a display device DD. The electronic module EM may include a control module 10, a wireless communication module 20, an image input module 30, an audio input module 40, an audio output module 50, a memory 60, and an external interface module 70. The modules may be mounted on a circuit board or electrically connected via a flexible circuit board. The electronic module EM may be electrically connected to the power supply module PSM.

[0308] The control module 10 can control the overall operation of the electronic device ED. For example, the control module 10 can activate or deactivate the display device DD in response to user input. The control module 10 can control the image input module 30, the audio input module 40, and the audio output module 50 in response to user input. The control module 10 can include at least one microprocessor.

[0309] The wireless communication module 20 can transmit / receive wireless signals to / from other terminals using a Bluetooth® or WIFI line. The wireless communication module 20 can transmit / receive audio signals using a general communication line. The wireless communication module 20 can include a transmitting circuit 22 that modulates and transmits signals to be transmitted, and a receiving circuit 24 that demodulates received signals.

[0310] The image input module 30 processes image signals and converts them into image data that can be displayed on the display device DD. The audio input module 40 receives external audio signals through a microphone in a recording mode or a voice recognition mode and converts them into electrical audio data. The audio output module 50 converts audio data received from the wireless communication module 20 or audio data stored in the memory 60 and outputs the converted data to the outside.

[0311] The external interface module 70 can act as an interface connected to an external charger, a wired / wireless data port, a card socket (for example, a memory card, a SIM / UIM card), and the like.

[0312] The power supply module PSM is capable of supplying the power required for the overall operation of the electronic device ED, and can include a conventional battery device.

[0313] FIG. 18 is a diagram illustrating an electronic device according to an embodiment of the present invention.

[0314] 18, an electronic device 1000 according to an embodiment of the present invention can output various information (e.g., images, text, music, etc.) through a display module 1140, which can correspond to the display device DD described above. When the processor 1110 executes an application stored in the memory 1120, the display module 1140 can provide application information to a user through a display panel 1141.

[0315] In one embodiment, the electronic device 1000 may be configured as, for example, a smartphone, a camera, a smart TV, a monitor, a smart watch, a tablet, an automobile display, or an AR / VR headset. For example, the electronic device 1000 may be a smartphone including a touch-sensitive display area DA for interaction and a non-display area NDA including sensors and circuits for enhanced functionality. For example, the electronic device 1000 may be a television or monitor including a large display area DA for high-resolution video playback and a non-display area NDA including a driver circuit or connection module for external input. For example, the electronic device 1000 may be a smart watch including a display area DA optimized for small, clear images and a non-display area NDA including a biometric sensor for health monitoring. In some cases, the electronic device 1000 may be an AR / VR headset.

[0316] In one embodiment, memory 1120 includes volatile memory 1121, non-volatile memory 1122, and application programs 1123, and may store information such as software code for operating the application programs 1123. The application programs 1123 may include software designed to perform specific tasks or provide functionality to a user. The application programs 1123 operate under the control of the processor 1110 and utilize data stored in memory 1120 to provide various functions such as productivity tools, multimedia streaming and playback, file or email transfer, and communication services. The application programs 1123 may interact seamlessly with the user interface 1161 or touchscreen 1142 to allow a user to run, navigate, and use the programs through user input such as touch, tab, gesture, or voice interaction.

[0317] When a user selects an application through the touch screen 1142 or the user interface 1161, the processor 1110 executes the application program 1123 corresponding to the selected application searched for in the memory 1120 to perform the function of the selected application. For example, when a user tabs on an icon (or a camera application icon) displayed on the display panel 1141 and selects the camera application, the processor 1110 can activate the camera module. The processor 1110 can transmit image data corresponding to a captured image acquired through the camera module to the display module 1140. The display module 1140 can display an image corresponding to the captured image on the display panel 1141.

[0318] In one embodiment, when a user wishes to make a call, the user may tab to a telephone icon displayed on display module 1140, and processor 1110 may execute a telephone application program stored in memory 1120. A telephone keypad may be displayed on display panel 1141 to allow the user to enter a telephone number.

[0319] In one embodiment, the display module 1140 may be integrated into the electronic device 1000, such as a laptop, smart TV, or tablet. A user wishing to connect to a multimedia streaming application (e.g., to watch a music video or movie) can do so by tabbing on the corresponding icon. This action activates the application and allows the user to view the streamed content.

[0320] The processor 1110 may include a main processor 1111 and an auxiliary processor or coprocessor 1112. The main processor 1111 may include a central processing unit (CPU), and may further include one or more of a graphics processing unit (GPU), a communication processor (CP), and an image signal processor (ISP).

[0321] The processor 1112 may include a controller 1112-1. The controller 1112-1 may include an interface conversion circuit and a timing control circuit. The controller 1112-1 may receive an image signal from the main processor 1111, convert the data format of the image signal to conform to the interface specifications with the display module 1140, and output the image data. The controller 1112-1 may output various control signals to drive the display module 1140. For example, the controller 1112-1 may drive the display module 1140 to display user-selectable icons on the display screen and execute the application program 1123.

[0322] The display module 1140 can output visual information (images) to a user. The display module 1140 can include a display panel 1141, a gate driver, a source driver, a voltage generating circuit, and a touch screen 1142. The display module 1140 can further include a window, a chassis, and a bracket for protecting the display panel 1141. The display module 1140 can include at least a portion of the components of the display device DD described above.

[0323] The user interface 1161 serves as an interaction medium between a user and the electronic device 1000. The user interface 1161 can sense input from a part of the user's body (e.g., a finger) or input from a pen or mouse, and generate an electrical signal or data value corresponding to the input. The user interface 1161 can include a fingerprint sensor 1162, an input sensor 1163, and a digitizer 1164.

[0324] The fingerprint sensor 1162 can sense a fingerprint for biometric recognition of a user and may measure one or more biometric signals such as blood pressure, hydration, or weight.

[0325] The input sensors 1163 can sense user interactions including touch, tab, gesture, movement, voice command, eye movement, etc. The input sensors 1163 can include optical sensors for image capture, eye tracking, or movement and gesture detection. The optical sensors can be infrared or semiconductor photodetectors. The input sensors 1163 can include audio and acoustic sensors such as MEMS microphones for voice recognition or sound-based interaction. The audio and acoustic sensors can be located as part of the user interface 1161 or embedded in the display panel 1141.

[0326] The digitizer 1164 can generate data values ​​corresponding to the coordinate information of a pen or mouse input to control the movement of a screen cursor. The digitizer 1164 can generate data values ​​based on the amount of change in electromagnetic waves caused by the input. The digitizer can sense input from a manual pen or can send and receive data via an active pen or remote control.

[0327] At least one of the fingerprint sensor 1162, the input sensor 1163, or the digitizer 1164 can be implemented as a sensor layer formed on the top layer of the display panel 1141 through a process continuous with the process of forming elements (e.g., light-emitting elements, transistors, etc.) included in the display panel 1141.

[0328] The user interface 1161 may also include, for example, a gesture sensor, a gyro sensor for detecting rotational movement, an acceleration sensor for tracking translational movement, a grip sensor, a pressure sensor, a proximity sensor, a color sensor, an infrared (IR) emitter and camera sensor for tracking gaze direction and eye movement, a temperature sensor, or a light sensor. For example, the gyro sensor, acceleration sensor, IR emitter, and camera may be particularly suitable for AR / VR headset functionality.

[0329] The touch screen 1142 includes a touch sensor embedded in the semiconductor layer of the display panel 1141 and can sense pressure applied to the top layer (screen) of the display panel 1141. The touch sensor can be capacitive or resistive. The touch screen 1142 can serve as the primary interface through which a user can select and explore applications, control the electronic device 1000, and interact with the electronic device 1000.

[0330] The display panel 1141 (or display) may include, for example, a liquid crystal display panel, an organic light-emitting display panel, or an inorganic light-emitting display panel. However, the type of the display panel 1141 is not particularly limited. The display panel 1141 may be rigid or flexible, so that it can be rolled or folded. The display module 1140 may further include a support, bracket, heat dissipation member, etc., that support the display panel 1141. The display panel 1141 may include the display device DD described above.

[0331] The power supply module 1150 can supply power to each component of the electronic device 1000. The power supply module 1150 can include a battery that charges a power supply voltage. The battery can include a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell. The power supply module 1150 can include a power management integrated circuit (PMIC). The PMIC can supply optimized power to each component described above, including the display module 1140.

[0332] Although the present invention has been described above with reference to preferred embodiments, it will be understood that a person skilled in the art or having ordinary knowledge in the art can make various modifications and changes to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

[0333] Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims. [Explanation of symbols]

[0334] DD display device BS Base Layer GDC Gate driver GWL Scanline HL Horizontal Line VL Vertical Line SHP Shielding Pattern

Claims

1. a base layer including a display area in which a plurality of pixels are arranged and a non-display area arranged around the display area; a gate driver disposed in the non-display area and outputting a write scan signal; scan lines that apply the write scan signal to the pixels and include vertical lines extending in a first direction from the gate driver and horizontal lines electrically connected to the vertical lines and extending in a second direction crossing the first direction; a shielding pattern that overlaps the vertical line on a plane;

2. Each of the plurality of pixels is a pixel driver disposed on the base layer and including at least one transistor; a light-emitting element disposed on the transistor, the light-emitting element including a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; The display device of claim 1 , wherein the shielding pattern is disposed between the vertical line and the first electrode.

3. a voltage line extending in the first direction and applying a constant voltage; The display device according to claim 2 , wherein the constant voltage is applied to the shielding pattern.

4. The display device according to claim 3 , wherein the voltage lines are arranged on the same layer as the vertical lines.

5. The display device according to claim 3 , further comprising a lower conductive layer disposed under the transistor, and a sub-shielding pattern disposed on the same layer as the lower conductive layer and overlapping the vertical line in a plane.

6. The display device according to claim 5 , wherein the constant voltage is applied to the sub-shielding pattern.

7. The transistor is a first transistor connected to the second electrode; a second transistor for transmitting the write scan signal; The display device of claim 2 , wherein the shielding pattern overlaps at least a portion of the drain pattern of the second transistor in a plan view.

8. The display device of claim 7 , further comprising a metal pattern overlapping the source pattern of the second transistor in a plane and receiving a constant voltage.

9. The display device of claim 7 , wherein the drain pattern is disposed on the same layer as the vertical lines.

10. The pixels arranged in the first row among the plurality of pixels are defined as first row pixels, 2. The display device of claim 1, wherein the horizontal line is connected to each of the first row pixels to apply the write scan signal to each of the first row pixels.

11. 11. The display device of claim 10, further comprising: a light-emitting line that applies a light-emitting signal from the gate driver to the plurality of pixels, the light-emitting line including a light-emitting vertical line extending from the gate driver in the first direction and a light-emitting horizontal line electrically connected to the light-emitting vertical line and extending in the second direction.

12. The pixels arranged in a second row among the plurality of pixels are defined as second row pixels, The display device of claim 11 , wherein the light-emitting horizontal line is connected to each of the first row pixels and the second row pixels to apply the light-emitting signal to each of the first row pixels and the second row pixels.

13. 12. The display device of claim 11, further comprising: a compensation scan line through which the gate driver applies a compensation scan signal to the plurality of pixels; and a reset scan line through which the gate driver applies a reset scan signal to the plurality of pixels.

14. The vertical line is a first vertical line connected to one end of the horizontal line; a second vertical line connected to the other end of the horizontal line opposite to the one end, The display device of claim 10 , wherein the write scan signal is applied to each of the first vertical line and the second vertical line.

15. 2. The display device of claim 1, wherein the horizontal lines are disposed on a different layer from the vertical lines and are electrically connected to the vertical lines through contact holes.

16. Each of the plurality of pixels is a pixel driver disposed on the base layer and including at least one transistor; a light-emitting element disposed on the transistor, the light-emitting element including a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; The display device of claim 1 , further comprising a connection electrode electrically connecting the transistor and the second electrode to each other.

17. a pixel defining layer having an opening defined therein that exposes at least a portion of the first electrode; a separator disposed on the pixel defining film, The display device of claim 16 , wherein a lower surface of the second electrode contacts an upper surface of the connecting electrode in a contact region adjacent to the separator.

18. The display device of claim 16 , wherein the shielding pattern is disposed on the same layer as the connecting electrode.

19. a base layer including a display area and a non-display area disposed around the display area; a driving element layer disposed on the base layer; a plurality of light-emitting elements, each including a first electrode disposed on the driving element layer, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer; a gate driver disposed in the non-display area and outputting a write scan signal; The driving element layer a scan line electrically connected to the gate driver; a first transistor connected to the second electrode; a shielding pattern for transmitting the write scan signal from the scan line to a second transistor and overlapping at least a portion of the scan line and the drain pattern of the second transistor in a plane;

20. A display device; an electronic module overlying the display device; a housing that houses the display device; The display device includes: a base layer including a display area in which a plurality of pixels are arranged and a non-display area arranged around the display area; a gate driver disposed in the non-display area and outputting a write scan signal; scan lines that apply the write scan signal to the pixels and include vertical lines extending in a first direction from the gate driver and horizontal lines electrically connected to the vertical lines and extending in a second direction crossing the first direction; and a shielding pattern overlapping the vertical line on a plane.

Images