Vector data calculation method and apparatus, electronic device, and storage medium

Abstract

Disclosed are a vector data calculation method and apparatus, an electronic device and a storage medium.SOLUTION: Determining a target vector operation array and a target operation data path corresponding to the target vector operation array from at least one preset vector operation unit according to the first operation type, the preset vector operation unit supporting at least one operation data path, each operation data path corresponding to a calculation function, and controlling the target vector operation array to calculate the vector data to be calculated through the target operation data path to obtain a calculation result corresponding to the vector data to be calculated. The embodiments of the present disclosure can improve the diversity of computing functions and the computing efficiency.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to computer technology, and more particularly to a method, device, electronic device, and storage medium for calculating vector data. [Background technology]

[0002] With the increasing popularity of transformer network architectures, vector computing is gradually becoming an important computational mode other than matrix computation. Vector computing is characterized by a large number of operators and a diverse combination of functions. Related technologies typically accelerate vector computing using vector accelerators or GPUs (general-purpose computing on graphics processing units, abbreviated as GPGPUs). However, traditional vector accelerators have a single function, lack flexibility, and have low computational efficiency for general-purpose GPU computing. Summary of the Invention [Problem to be solved by the invention]

[0003] The embodiments of the present disclosure provide a vector data calculation method, device, electronic device, and storage medium, which can realize various vector calculation functions and improve calculation efficiency. [Means for solving the problem]

[0004] A vector data calculation method according to a first aspect of the present disclosure includes the steps of: determining vector data to be calculated and a corresponding first operation type; determining a target vector operation array and a target operation data path corresponding to the target vector operation array from at least one pre-set vector operation unit based on the first operation type, wherein the pre-set vector operation unit supports at least one type of operation data path, and any one of the operation data paths corresponds to one type of calculation function; and controlling the target vector operation array to calculate the vector data to be calculated using the target operation data path, and obtaining a calculation result corresponding to the vector data to be calculated.

[0005] A vector data calculation device according to a second aspect of the present disclosure includes: a first processing module for determining vector data to be calculated and a corresponding first operation type; a second processing module for determining a target vector operation array and a target operation data path corresponding to the target vector operation array from at least one pre-set vector operation unit based on the first operation type, wherein the pre-set vector operation unit supports at least one type of operation data path, and any one of the operation data paths corresponds to one type of calculation function; and a third processing module for controlling the target vector operation array to calculate the vector data to be calculated using the target operation data path, and obtaining a calculation result corresponding to the vector data to be calculated.

[0006] A vector processor according to a third aspect of the present disclosure includes the vector data calculation device according to any one of the above embodiments and at least one preset vector operation unit.

[0007] A computer-readable storage medium according to a fourth aspect of the present disclosure stores a computer program for executing the vector data calculation method according to any one of the above embodiments of the present disclosure.

[0008] An electronic device according to a fifth aspect of the present disclosure includes a processor and a storage device for storing instructions executable by the processor, and the processor is used to read and execute the executable instructions from the storage device to realize a vector data calculation method described in any one of the above embodiments of the present disclosure.

[0009] A sixth aspect of the present disclosure provides a computer program product, wherein instructions in the computer program product, when executed by a processor, perform the vector data calculation method according to any one of the above embodiments of the present disclosure. [Effects of the Invention]

[0010] According to the vector data calculation method, device, electronic device, and storage medium of the above embodiments of the present disclosure, when vector data needs to be calculated, it is possible to determine the vector data to be calculated and the corresponding operation type, and based on the operation type, it is possible to determine a target vector operation array and a target operation data path corresponding to the target vector operation array from at least one preset vector operation unit, and further control the target vector operation array to calculate the vector data to be calculated using the target operation data path, thereby obtaining a calculation result corresponding to the vector data to be calculated. The preset vector operation unit can support at least one operation data path, and each operation data path corresponds to one calculation function. Therefore, multiple vector calculation functions can be realized by the at least one preset vector operation unit, thereby improving the diversity of calculation functions. The preset vector operation unit is equivalent to an accelerator for vector calculation, and can effectively improve the calculation efficiency of vector calculations implemented by GPGPU programming. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is an exemplary application scenario of a vector data calculation method according to the present disclosure. [Figure 2] 1 is a flowchart of a vector data calculation method according to an exemplary embodiment of the present disclosure. [Figure 3] 10 is a flowchart of a vector data calculation method according to another exemplary embodiment of the present disclosure. [Figure 4] 10 is a flowchart of a vector data calculation method according to yet another exemplary embodiment of the present disclosure. [Figure 5] 10 is a flowchart of a vector data calculation method according to yet another exemplary embodiment of the present disclosure. [Figure 6] 10 is a flowchart of a vector data calculation method according to yet another exemplary embodiment of the present disclosure. [Figure 7] FIG. 2 is a schematic diagram of a pre-configured vector processing unit according to one exemplary embodiment of the present disclosure. [Figure 8] FIG. 2 is a schematic diagram of a vector computation data path of a softmax operator according to one exemplary embodiment of the present disclosure. [Figure 9] FIG. 1 is a schematic diagram of a vector computation data path of a layernorm operator according to one exemplary embodiment of the present disclosure. [Figure 10] FIG. 1 is a schematic diagram of a pipelined computation principle according to one exemplary embodiment of the present disclosure. [Figure 11] 1 is a structural schematic diagram of a vector data calculation device according to an exemplary embodiment of the present disclosure; [Figure 12] FIG. 10 is a structural schematic diagram of a vector data calculation device according to another exemplary embodiment of the present disclosure; [Figure 13] FIG. 10 is a structural schematic diagram of a vector data calculation device according to yet another exemplary embodiment of the present disclosure; [Figure 14] FIG. 10 is a structural schematic diagram of a vector data calculation device according to yet another exemplary embodiment of the present disclosure; [Figure 15] 1 is a structural diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0012] In order to explain the present disclosure, exemplary embodiments of the present disclosure will be described in detail below with reference to the drawings. Obviously, the described embodiments are not all embodiments but only some embodiments of the present disclosure, and the present disclosure is not limited to the exemplary embodiments.

[0013] It should be noted that the relative arrangement of parts and steps, formulas and numerical values ​​described in these examples do not limit the scope of the present disclosure unless specifically stated otherwise.

[0014] Summary of the Disclosure In the process of implementing this disclosure, the inventors discovered the following: With the continued popularity of transformer network structures, vector computation is gradually becoming an important computation mode other than matrix computation. Vector computation is characterized by a wide variety of operators and diverse combinations of functions. For example, vector computation may include complex calculations such as the softmax (normalized exponent) operator, the layernorm (layer normalization) operator, and the LUT (Look-Up-Table) operator, as well as various common operators such as mult (multiplication), add (addition), reduce (reduction operation), and logic (logical operation). Related technologies generally accelerate vector computation using vector accelerators or general-purpose computing on graphics processing units (GPUs) (abbreviated as GPGPUs). However, conventional vector accelerators have a single function and lack flexibility. While GPU general-purpose computing is flexible to program and can implement general-purpose vector computation using a programmable pipeline, its programming dependency results in lower computational efficiency than vector accelerators.

[0015] Illustrative Overview FIG. 1 illustrates an exemplary application scenario of the vector data calculation method according to the present disclosure. As shown in FIG. 1, the vector data calculation method according to the present disclosure can be executed by a vector data calculation device 11. A vector calculation instruction may be generated by a central processing unit (CPU) or another processing device requiring vector calculation and transmitted to the vector data calculation device 11. The vector calculation instruction may include vector data to be calculated or index information of the vector data to be calculated. The index information may be, for example, address information of the vector data to be calculated. Alternatively, the vector calculation instruction may include feature data to be calculated or index information of the feature data to be calculated, and one or more vectors to be calculated are determined based on the feature data to be calculated. The vector calculation instruction may further include an operation type (referred to as a first operation type) corresponding to the vector data to be calculated. The vector data calculation device 11 can determine the vector data to be calculated and the corresponding first operation type based on the vector calculation instruction. The operation types may include point-to-point types such as addition, subtraction, multiplication, division, comparison, quantization, inverse quantization, logical operations, and lookup tables, as well as reduction operation types such as maximum value, minimum value, summation, and logical operations. The operation types may also include complex operation types combined with simple operations, such as softmax and layernorm. A reduction operation type is an operation type that reduces the length of a vector by a corresponding operation. For example, a maximum value operation is to find the maximum element among all elements in a vector and reduce the vector length to 1 (i.e., the operation result contains only one element).Furthermore, the vector data calculation device 11 can determine, based on the first operation type, a target vector operation array that can be used for vector calculation of the target vector data from at least one preset vector operation unit (e.g., preset vector operation unit 121, preset vector operation unit 122, ..., preset vector operation unit 12n in FIG. 1, where n is a positive integer) and a target operation data path for realizing vector calculation of the first operation type in the target vector operation array. The target vector operation array may include one or more preset vector operation units, and each preset vector operation unit may include one or more operation subunits. For example, the preset vector operation unit 121 includes m operation subunits from operation subunit 1211 to operation subunit 121m, the preset vector operation unit 122 includes s operation subunits, and the preset vector operation unit 12n includes t operation subunits, where m, s, and t are all positive integers. The target computation data path may include a computation data path composed of one or more computation subunits of each preset vector computation unit in the target vector computation array. Any two preset vector computation units may be the same or different vector accelerators. That is, any two preset vector computation units may have the same structure or different structures. For example, the type and number of computation subunits included in the preset vector computation unit 121 may be the same as or different from those included in the preset vector computation unit 122. Each computation subunit can complete one type of computation. After determining the target vector computation array and the corresponding target computation data path, the target vector computation array is controlled to calculate the vector data to be calculated using the target computation data path, thereby obtaining a calculation result corresponding to the vector data to be calculated.For example, by enabling each arithmetic subunit in the target arithmetic data path, the target arithmetic data path can be put into an operating state, the vector data to be calculated can be transmitted to the initiating arithmetic subunit of the target arithmetic data path, and an operating clock can be provided to each arithmetic subunit of the target arithmetic data path to control the operation timing of each arithmetic subunit, so that each arithmetic subunit cooperates to perform calculations on the vector data to be calculated and obtain a calculation result. The preset vector arithmetic unit can support at least one arithmetic data path, and each arithmetic data path corresponds to one calculation function. Therefore, various vector calculation functions can be realized by at least one preset vector arithmetic unit, which can effectively improve the diversity of calculation functions. The preset vector arithmetic unit is equivalent to an accelerator for vector calculation, which can effectively improve the calculation efficiency of vector calculations realized by programming the GPGPU.

[0016] The vector data calculation device 11 of the present disclosure and each preset vector operation unit constitute a vector processor of the present disclosure, which can be used for vector calculation of various operation types for various scenes.

[0017] Exemplary Methods 2 is a flowchart of a vector data calculation method according to an exemplary embodiment of the present disclosure. This embodiment can be applied to a chip for accelerating calculations in electronic devices, such as an in-vehicle computing platform, a mobile phone, a tablet terminal, and other terminal devices. As shown in FIG. 2, the method according to the embodiment of the present disclosure may include the following steps 201 to 203.

[0018] In step 201, the vector data to be calculated and the corresponding first operation type are determined.

[0019] Here, the vector data to be calculated may include one or more vectors (i.e., vectors) to be calculated, and the first operation type is the type of operator used to calculate the vector data to be calculated. The operator type (i.e., operation type) may include point-to-point types such as addition, subtraction, multiplication, division, comparison, quantization, inverse quantization, logical operations, and lookup tables, as well as reduction operation types such as maximum value search, minimum value search, sum search, and logical operations. The operator type may further include complex operation types combined with simple operations, such as softmax, layernorm, and LUT.

[0020] In some selectable embodiments, a vector calculation task (or a vector calculation instruction) can be obtained from a component capable of generating a vector calculation task (or a vector calculation instruction), such as a CPU or a microcontroller, and the vector data to be calculated and the corresponding first operation type can be determined from the vector calculation task (or the vector calculation instruction). For example, in the process of performing inference on a neural network model, the CPU generates a vector calculation task (or a vector calculation instruction) for an operator in the neural network model that can perform vector calculation using the method of the embodiment of the present disclosure, and sends it to a vector data calculation device of the embodiment of the present disclosure, thereby achieving calculation of the vector data using the method of the embodiment of the present disclosure.

[0021] In some selectable embodiments, the number of vector data to be calculated may be one or more. When multiple vector data to be calculated are included, the multiple vector data to be calculated may be of the same operation type or different operation types. Each of the vector data to be calculated may have a corresponding first operation type. The multiple vector data to be calculated may be from the same vector calculation task or from different vector calculation tasks, and are not specifically limited.

[0022] In step 202, a target vector operation array and a target operation data path corresponding to the target vector operation array are determined from at least one preset vector operation unit based on the first operation type.

[0023] Here, the preset vector processing unit supports at least one type of processing data path, and any one of the processing data paths corresponds to one type of calculation function.

[0024] In some alternative embodiments, each pre-configured vector arithmetic unit may include one or more arithmetic subunits, and each arithmetic subunit may complete one basic operation. For example, the arithmetic subunit may be a reduce-sum unit for calculating the sum of all elements in a vector, or may be an FMUL unit for performing floating-point multiplication, or may be an FADD unit for performing floating-point addition, etc. The specific arithmetic subunits may be configured according to actual needs. Each arithmetic subunit in the preset vector arithmetic unit may have one or more combination forms, and different combination forms form different arithmetic data paths. Each arithmetic subunit may be used alone, i.e., alone as a arithmetic data path, or some of the arithmetic subunits may be used in combination. For example, a preset vector arithmetic unit includes three arithmetic subunits, arithmetic subunit a, arithmetic subunit b, and arithmetic subunit c. The arithmetic data paths that the preset vector arithmetic unit can support may include at least one of a, b, c, a → b, a → c, b → c, b → a, c → b, c → a, a → b → c, c → b → a, a → c → b, c → a → b, etc. Taking a → b as an example, it shows that calculations are performed by arithmetic subunit a and arithmetic subunit b to realize one arithmetic data path. Thus, the preset vector arithmetic unit can support one or more arithmetic data paths.

[0025] In some alternative embodiments, in the case of a plurality of preset vector operation units, at least two of the plurality of preset vector operation units may be heterogeneous operation units, where the two preset vector operation units being heterogeneous operation units means that at least one of the types, numbers, and supported operation data paths of the operation subunits included in the two preset vector operation units is different.

[0026] In some alternative embodiments, the computation subunits required for the vector calculation and the data dependencies between the computation subunits can be determined based on the first computation type. Furthermore, based on the necessary computation subunits and the data dependencies between the computation subunits, a target vector computation array and a target computation data path corresponding to the target vector computation array can be determined from each preset vector computation unit in combination with the computation data paths supported by the preset vector computation unit. The target vector computation array is an array composed of one or more preset vector computation units involved in the first computation type. That is, the target vector computation array may include one or more preset vector computation units. The target computation data path is a computation data path specifically involved in the first computation type in each preset vector computation unit in the target vector computation array, and the target computation data path may include one or more computation subunits in the target vector computation array, and these computation subunits are connected to each other to form the target computation data path.

[0027] In some selectable embodiments, a plurality of preset vector operation units may be used in combination to realize complex or continuous vector operation, and interconnected operation data paths may be preset between the plurality of preset vector operation units. The interconnection configuration between the preset vector operation units may be set according to the actual needs of the vector operation, and the embodiments of the present disclosure are not limited thereto.

[0028] In step 203, the target vector calculation array is controlled to calculate the vector data to be calculated through the target calculation data path, and a calculation result corresponding to the vector data to be calculated is obtained.

[0029] Here, calculating the vector data to be calculated using the target calculation data path may mean controlling each calculation subunit constituting the target calculation data path to operate at a fixed operation timing and complete the calculation for the vector data to be calculated. The calculation result corresponding to the vector data to be calculated is the vector calculation result for the vector data to be calculated. For example, when an addition operation is performed on the vector data to be calculated, the calculation result is the addition operation result.

[0030] In some alternative embodiments, a control form corresponding to each of the different calculation data paths may be set in advance, and after determining the target calculation data path, the target vector calculation array may be controlled to calculate the vector data to be calculated by the target calculation data path based on the control form corresponding to the target calculation data path.

[0031] In some alternative embodiments, a single target operation data path may perform serial or pipeline calculations on multiple target vector data of the same operation type to obtain calculation results corresponding to each target vector data. In order to further improve calculation efficiency when there are sufficient calculation resources, a parallel calculation may be performed on multiple target operation data paths to obtain calculation results corresponding to each target vector data.

[0032] The vector data calculation method according to this embodiment can determine, when calculating vector data, vector data to be calculated and an operation type corresponding to the vector data to be calculated, determine a target vector operation array and a target operation data path corresponding to the target vector operation array from at least one preset vector operation unit based on the operation type, and control the target vector operation array to calculate the vector data to be calculated via the target operation data path, thereby obtaining a calculation result corresponding to the vector data to be calculated. The preset vector operation unit can support at least one operation data path, and each operation data path corresponds to one calculation function. Therefore, multiple vector calculation functions can be realized by the at least one preset vector operation unit, thereby improving the diversity of calculation functions. The preset vector operation unit serves as an accelerator for vector calculation, which can effectively improve the calculation efficiency of GPGPUs that implement vector calculations through programming.

[0033] In some alternative embodiments, in the embodiment shown in Figure 2 above, the step of determining the vector data to be calculated in step 201 may include the steps of obtaining feature data to be calculated, determining at least one vector based on the feature data to be calculated according to a predetermined vector dimension, and determining each vector as vector data to be calculated.

[0034] Here, the feature data to be calculated may be input feature data when performing neural network calculations or feature data generated during the inference process, and is not specifically limited. The predetermined vector dimension may be the dimension of an input vector supported by the predetermined vector calculation unit, i.e., the number of elements included in the input vector (i.e., the length of the input vector). For example, if the input vector supported by the predetermined vector calculation unit is a vector containing 512 elements, the predetermined vector dimension is 512.

[0035] In some alternative embodiments, the feature data to be calculated may be obtained from a component that executes the model inference process, such as a CPU, or may be obtained by reading from a memory space designated by the CPU or the like that stores the feature data to be calculated.

[0036] In some selectable embodiments, a transformation form for transforming the calculation target feature data into at least one vector can be preset, and the calculation target feature data can be determined as at least one vector according to the preset vector dimension based on the transformation form. If the number of elements in the calculation target feature data is greater than the preset vector dimension, the calculation target feature data can be determined as multiple vectors according to the preset vector dimension. Note that, in general, the calculation target feature data is determined as multiple vectors only when vector calculation can be performed by dividing the calculation target feature data.

[0037] In this embodiment, for the feature data to be calculated of the neural network model, at least one vector can be determined as the vector data to be calculated according to the preset vector dimension supported by the preset vector operation unit, thereby enabling the preset vector operation unit to realize vector calculation of feature data of different neural network models, which helps to improve the utilization rate of the preset vector operation unit.

[0038] In some alternative embodiments, each preset vector operation unit can be coupled to a preset storage device so as to read input vector data from the preset storage device during the operation process and / or output vector calculation results to the preset storage device.

[0039] Here, the preset storage device may be any type of storage device. For example, the preset storage device may be a memory (mem). The connection between the preset vector processing units and the preset storage device may include connecting the preset vector processing units to the preset storage device via a bus, or connecting the preset vector processing units to the preset storage device indirectly via an intermediate device. For example, the preset vector processing units may be connected to the preset storage device via direct memory access (DMA). By connecting all the preset vector processing units to the preset storage device, data transmission between the preset vector processing units via the preset storage device is easily realized. For example, when the vector calculation result of preset vector processing unit A needs to be input data to preset vector processing unit B, preset vector processing unit A can output the calculation result to the preset storage device, and preset vector processing unit B can read the calculation result of preset vector processing unit A from the preset storage device and continue the calculation.

[0040] In this embodiment, by coupling each of the preset vector operation units to a preset storage device, the preset vector operation units can be interconnected and data transmission between the preset vector operation units can be realized, so that complex vector calculations or continuous vector calculations can be realized by multiple preset vector operation units, which is useful for expanding more vector calculation functions with a fixed number of preset vector operation units and further improving the utilization rate of the preset vector operation units.

[0041] FIG. 3 is a flowchart of a vector data calculation method according to another exemplary embodiment of the present disclosure.

[0042] In some alternative embodiments, in any one of the above embodiments, as shown in FIG. 3 , step 202 of determining a target vector operation array and a target operation data path corresponding to the target vector operation array from at least one preset vector operation unit based on a first operation type may include the following steps 2021 and 2022.

[0043] In step 2021, based on the first operation type, a sequence of operation subunits corresponding to the first operation type is determined.

[0044] Here, the arithmetic subunit sequence may include arithmetic subunit information of one or more arithmetic subunits required to complete the operation of the first arithmetic type and the operation order of the arithmetic subunits (which may also be referred to as data dependency between the arithmetic subunits). The arithmetic subunit information may be, for example, the name, type, etc. of the arithmetic subunit. For example, the vector operation of the softmax operator requires the use of multiple arithmetic subunits, which perform calculations cooperatively according to a certain operation order to achieve the complete operation of softmax.

[0045] In some alternative embodiments, for each type of operation type, an operation subunit sequence corresponding to each of the various operation types can be pre-set, and a mapping relationship between the operation type and the operation subunit sequence can be stored. Then, after determining a first operation type corresponding to the vector data to be calculated, the operation subunit sequence corresponding to the first operation type can be determined based on the mapping relationship.

[0046] In step 2022, a target vector operation array and a target operation data path corresponding to the target vector operation array are determined from each preset vector operation unit based on the operation subunit sequence.

[0047] After determining the operation subunit sequence, the target operation subunits in the target vector operation unit that need to be involved in the operation from each of the preset vector operation units are determined based on the operation subunit information of the operation subunits included in each preset vector operation unit and the data path information between the operation subunits, and the target vector operation array is configured with the target vector operation units, and the target operation subunits in the target vector operation unit and their interconnection structure form a target operation data path. Since each preset vector operation unit can include one or more operation subunits, the preset vector operation unit can support at least one operation data path. When the preset vector operation unit is used as the target vector operation unit, if the preset vector operation unit supports multiple operation data paths, the current operation may only use one of the operation data paths. Therefore, the target vector operation array configured with the target vector operation unit may include operation subunits that are not involved in the current operation, and these operation subunits are scheduled to be used for other vector calculation tasks, thereby realizing integrated scheduling of multiple calculation tasks.

[0048] In some alternative embodiments, the operation subunit corresponding to the operation subunit information is determined based on the operation subunit information in the operation subunit sequence, and a target vector operation array is constructed with pre-set vector operation units that satisfy the operation order of the operation subunits, and the operation data path of each operation subunit corresponding to the operation subunit sequence in the target vector operation array can be set as the target operation data path.

[0049] In this embodiment, by determining the operation subunit sequence corresponding to the first operation type, the target vector operation array and the target operation data path involved in the operation can be accurately obtained, thereby ensuring accurate calculation of the vector data to be calculated.

[0050] FIG. 4 is a flowchart of a vector data calculation method according to yet another exemplary embodiment of the present disclosure.

[0051] In some alternative embodiments, as shown in FIG. 4, step 2022 of determining a target vector operation array and a target operation data path corresponding to the target vector operation array from each preset vector operation unit based on the operation subunit sequence may include the following steps 20221 to 20223.

[0052] In step 20221, based on the operation subunit sequence and the operation data paths between the operation subunits corresponding to each of the preset vector operation units, at least one target vector operation unit, a first operation data path corresponding to each of the target vector operation units, and a second operation data path between each of the target vector operation units are determined.

[0053] Here, for each predetermined vector operation unit in each predetermined vector operation unit, the operation data paths between the operation subunits in this predetermined vector operation unit may be predetermined. That is, during the circuit design stage of the predetermined vector operation unit, an interconnection structure between the operation subunits in the predetermined vector operation unit may be set according to the operation subunits included in the predetermined vector operation unit and the conditions of the operation subunits required for various operation types, and the operation subunits that need to be connected may be connected in a certain order to form operation data paths between the operation subunits. For example, the output terminal of operation subunit a may be connected to the input terminal of operation subunit b, and the output terminal of operation subunit b may be connected to the input terminal of operation subunit c, forming an operation data path between multiple operation subunits with an interconnection structure of a→b→c. The output terminal of one computing subunit may be connected to the input terminal of one or more other computing subunits, and the input terminal of one computing subunit may be connected to the output terminal of one or more other computing subunits. Thus, a preset vector computing unit can support one or more types of computing data paths, and can store information about the computing data paths between the computing subunits supported by the preset vector computing unit. Similarly, corresponding computing data path information for the computing data paths between the preset vector computing units can be pre-set and stored. Alternatively, information about all the computing data paths that each preset vector computing unit can support can be stored in a unified manner. For example, information about all the computing data paths that each preset vector computing unit can support can be stored in list format. The computing data path information may include a sequence displayed by the computing subunit. The control modes of the computing subunits corresponding to various computing data paths can be set, thereby realizing operation control of the corresponding computing data paths and realizing the corresponding vector calculation.In the operation process, after determining the operation subunit sequence corresponding to the first operation type, the operation subunit sequence can be matched with pre-stored operation data path information to determine at least one target vector operation unit that needs to participate in the operation, operation data paths corresponding to each target vector operation unit (referred to as first operation data paths), and operation data paths between each target vector operation unit (referred to as second operation data paths). The operation data paths corresponding to each target vector operation unit are operation data paths that need to participate in the current operation among the operation data paths supported by this target vector operation unit. The operation data paths between target vector operation units are operation data paths configured by an interconnection structure between target vector operation units. Since the operation subunit sequence includes data dependencies between the operation subunits required for the operation, the data dependencies of each target vector operation unit can be determined based on the order in the operation subunit sequence of the target operation subunits involved in the operation in each target vector operation unit, and thereby the interconnection order between the target vector operation units can be determined. For example, if the output terminal of one target vector operation unit is connected to the input terminal of another target vector operation unit, the connection of the target operation subunits involved in the operation in the two target vector operation units can be realized.For example, the calculation subunit sequence includes calculation subunit a → calculation subunit b → calculation subunit c, where calculation subunit a uses the same calculation subunit as calculation subunit a in target vector calculation unit A, calculation subunit b uses the same calculation subunit as calculation subunit b in target vector calculation unit B, and calculation subunit c uses the same calculation subunit as calculation subunit c in target vector calculation unit C. Based on the calculation subunit sequence, it can be determined that the output result of target vector calculation unit A should be input to target vector calculation unit B, and the output result of target vector calculation unit B should be input to target vector calculation unit C, thereby obtaining the calculation order of each target vector calculation unit and obtaining a second calculation data path between each target vector calculation unit, allowing the three target calculation subunits involved in the calculation in target vector calculation units A, B, and C to be connected to perform coordinated calculation.

[0054] In some alternative embodiments, the operation data paths between the preset vector operation units can realize data exchange through an interconnection structure between the preset vector operation units, can realize indirect data exchange through a preset storage device, or can realize data transmission through broadcast exchange between the preset vector operation units, where broadcast exchange means simultaneously transmitting the output result of one preset vector operation unit to multiple other preset vector operation units, and the specific data exchange form is not limited. The output result of the preset vector operation unit can be the output result of any one operation data path in the preset vector operation unit.

[0055] In step 20222, a target vector calculation array is constructed in each target vector calculation unit.

[0056] Here, each target vector calculation unit is interconnected according to the needs of the calculation subunit sequence to form a target vector calculation array. The interconnection form may be direct connection via a transmission line or indirect connection via a preset storage device. For example, the output terminal of target vector calculation unit A is interconnected with the input terminal of target vector calculation unit B.

[0057] In step 20223, a target operation data path corresponding to the target vector operation array is determined based on the first operation data path corresponding to each of the target vector operation units and the second operation data path between each of the target vector operation units.

[0058] Here, the first operation data path is a data path between target operation subunits that need to participate in the operation in the target vector operation unit, and the second operation data path is a data path between the target vector operation units, and the second operation data path is used to connect each first operation data path to form a complete target operation data path, and is used to realize the complete calculation of the vector data to be calculated.

[0059] In some alternative embodiments, if there is only one target vector operation unit, the second operation data path does not exist, and the target operation data path corresponding to the target vector operation array can be obtained based on the first operation data path corresponding to the target vector operation unit.

[0060] In this embodiment, a target operation data path can be formed by a first operation data path between operation subunits within a preset vector operation unit and a second operation data path between the preset vector operation units, thereby enabling vector operation of target vector data to be performed by multiple preset vector operation units, realizing complex vector operation or continuous vector operation, and expanding more vector operation functions. This also helps to unify the scheduling of multiple preset vector operation units, further improving the utilization rate of the preset vector operation units, and improving the application flexibility of the preset vector operation units. Furthermore, when the calculation resources of the preset vector operation units are sufficient, parallel execution of multiple vector operation tasks can be supported, helping to improve the execution efficiency of vector operation tasks.

[0061] In some alternative embodiments, step 202 of determining a target vector operation array and a target operation data path corresponding to the target vector operation array from at least one preset vector operation unit based on a first operation type may include determining a target vector operation array and a target operation data path corresponding to the target vector operation array based on the first operation type and a mapping relationship between the operation type and the preset vector operation unit and operation data path.

[0062] Here, the mapping relationship between the operation type and the preset vector operation units and operation data paths (which may be abbreviated as a mapping relationship corresponding to the operation type) may include preset vector operation units that need to be involved in operations corresponding to various operation types and operation data paths that need to be involved in operations in the preset vector operation units.

[0063] In some alternative embodiments, various operation types may have one or more selectable mapping relationships corresponding to the operation types, i.e., each preset vector operation unit may have one or more vector calculation forms that realize the operation types. For example, the operation data paths between the preset vector operation units and the operation data paths between the operation subunits in each preset vector operation unit may form multiple operation data paths that meet the needs of the operation subunit sequence corresponding to the operation type, and then the vector calculation of the operation type can be realized using any one operation data path that meets the needs. During the actual operation process, a mapping relationship that can currently meet the operation needs of the operation type can be selected according to the availability of each operation subunit in each preset vector operation unit, and a target vector operation array and target operation data path corresponding to the operation type can be obtained.

[0064] In some alternative embodiments, according to various operation types that may need to be implemented, a mapping relationship between the operation type and the preset vector operation unit and operation data path can be pre-established in combination with the operation data path status that the preset vector operation unit can support, so that when performing operation in real time, the target vector operation array and the target operation data path can be directly determined based on the mapping relationship.

[0065] In this embodiment, the target vector operation array and target operation data path corresponding to the operation type currently being calculated can be quickly and accurately determined based on the pre-established mapping relationship between the operation type and the pre-set vector operation unit and operation data path, thereby further improving operation efficiency.

[0066] FIG. 5 is a flowchart of a vector data calculation method according to yet another exemplary embodiment of the present disclosure.

[0067] In some alternative embodiments, in any one of the above embodiments, as shown in FIG. 5 , step 202 of determining a target vector operation array and a target operation data path corresponding to the target vector operation array from at least one preset vector operation unit based on a first operation type may include the following steps 202a and 202b:

[0068] In step 202a, a first number of target vector operation arrays is determined based on the number of vectors included in the vector data to be calculated and the first operation type.

[0069] Here, the number of vectors included in the vector data to be calculated may be one or more, and when the number of vectors is one, one target vector operation array and corresponding target operation data path only need to be determined. When the number of vectors is multiple, one or more target vector operation arrays can be determined based on the specific number of vectors and the first operation type, that is, the first number can be one or more. Each target vector operation array may include one or more preset vector operation units, and a target operation data path corresponding to this target vector operation array can be configured by a designated operation subunit in each preset vector operation unit.

[0070] In some alternative embodiments, if the computation resources of the preset vector computation units are sufficient, the first number of the target vector computation array may be the same as the number of vectors. For example, if the computation type is a simple multiplication operation and h (h is a positive integer) preset vector computation units each include an computation subunit that can complete the multiplication operation, each preset vector computation unit among the plurality of preset vector computation units can form a target vector computation array. If the number of vectors included in the vector data to be calculated is less than or equal to h, it can be determined that the first number of the target vector computation array is the number of vectors.

[0071] In some alternative embodiments, the first number can be determined based on the vector data included in the vector data to be calculated and the number of candidate configurations of preset vector operation units and operation data paths that can support vector operations on the vector data to be calculated. A combination of preset vector operation units that can support vector operations on the vector data to be calculated and a corresponding operation data path that supports the complete vector operation is called one candidate configuration. For example, if the operation type is a complex operation type and operation subunits in multiple preset vector operation units can form multiple operation data paths that complete this operation type in parallel, any combination of preset vector operation units corresponding to the various operation data paths that can complete this operation type in parallel can form one target vector operation array, and the first number of target vector operation arrays is the number of operation data paths that can complete this operation type in parallel.

[0072] In some alternative embodiments, the first number of target vector operation arrays can be determined based on the number of vectors, the first operation type, and a mapping relationship between the operation type and the preset vector operation units and operation data paths. Here, the mapping relationship between the operation type and the preset vector operation units and operation data paths can indicate one or more candidate forms capable of supporting vector calculations of each operation type, and the first number of target vector operation arrays can be determined according to the parallel computation capabilities of each candidate form corresponding to the first operation type. For example, the number of vectors may be multiple, and each candidate form may have I (I is a positive integer) parallel-computable candidate forms capable of implementing vector calculations of the first operation type. If the number of vectors is I or more, the first number may be I, thereby allowing I target operation data paths to perform parallel batch calculations of each vector, or each target operation data path to complete the calculation of each vector in a parallel pipelined manner. If the number of vectors is less than I, the first number may be the number of vectors, and allowing the first number of target operation data paths to complete the calculation of each vector in parallel.

[0073] In some alternative embodiments, any two target vector operation arrays in the first number of target vector operation arrays may have the same preset vector operation unit, which may be determined according to the operation data paths of various candidate forms of the first operation type. For example, the operation data path corresponding to one candidate form of the first operation type includes operation subunit a in the preset vector operation unit A, and the operation data path corresponding to another candidate form includes operation subunit b in the preset vector operation unit A, so that the target vector operation arrays of these two candidate forms both include the preset vector operation unit A.

[0074] In step 202b, a first number of target vector operation arrays from each of the preset vector operation units and a target operation data path corresponding to each of the target vector operation arrays are determined based on the first number.

[0075] If the first number is equal to the number of candidate forms corresponding to the first operation type, various candidate forms corresponding to the first operation type are determined as target vector operation arrays and corresponding target operation data paths. If the first number is smaller than the number of candidate forms corresponding to the first operation type, a first number of candidate forms can be selected from each candidate form, and each candidate form corresponds to one type of target vector operation array and corresponding target operation data path.

[0076] In this embodiment, the number of target vector operation arrays can be determined according to the number of vectors contained in the vector data to be calculated. As a result, when the resources of the preset vector operation unit are sufficient, the calculation of multiple vectors can be performed in parallel using multiple target vector operation arrays and corresponding target operation data paths, thereby further improving calculation efficiency.

[0077] FIG. 6 is a flowchart of a vector data calculation method according to yet another exemplary embodiment of the present disclosure.

[0078] In some optional embodiments, in any one of the above embodiments, as shown in FIG. 6, step 203 of controlling the target vector calculation array to calculate the vector data to be calculated through the target calculation data path and obtaining the calculation result corresponding to the vector data to be calculated may include the following steps 2031 and 2032.

[0079] In step 2031, each target vector calculation array is controlled so that the target calculation data path performs parallel calculation on each vector in the vector data to be calculated, and calculation sub-results corresponding to each vector are obtained.

[0080] Here, the target calculation data path of each target vector calculation array is controlled by a preset control form corresponding to each target vector calculation array, and parallel calculations are performed on each vector in the vector data to be calculated, thereby obtaining calculation sub-results corresponding to each vector.

[0081] In step 2032, a calculation result corresponding to the vector data to be calculated is determined based on the calculation sub-results corresponding to each vector.

[0082] Here, if each vector is a sub-vector obtained by dividing a single high-dimensional (i.e., long) vector (which may also be called a parent vector), the calculation sub-results corresponding to each vector can be processed through post-processing to obtain a calculation result corresponding to the high-dimensional vector, i.e., a calculation result corresponding to the vector data to be calculated. The post-processing can be determined according to the specific operation type. For example, for an operation such as a vector addition operation (i.e., adding corresponding elements of two vectors to be calculated), the elements of the operation result and the vector elements have a correspondence relationship, i.e., the operation result is a vector, and the length of the operation result is the same as the length of the vector to be calculated. In this case, the calculation sub-results can be combined into a high-dimensional operation result according to the vector division order to obtain a calculation result corresponding to the vector data to be calculated. For operations that change the vector length, such as a vector reduction operation (also called a reduction operation), the post-processing method for each calculation sub-result can be determined based on the correlation between the actual calculation result of the high-dimensional vector and the calculation sub-results of each divided vector. For example, reduction operations such as calculating the sum of all elements in a vector or determining the maximum or minimum value of all elements in a vector require further calculation of calculation sub-results corresponding to each vector to obtain a calculation result corresponding to a high-dimensional vector. For example, when calculating the sum of all elements in a high-dimensional vector, the calculation sub-results of each divided vector are obtained, and then the sum of each calculation sub-result is obtained to obtain a calculation result corresponding to the high-dimensional vector. If each vector is an independent vector and not obtained by dividing a high-dimensional vector, the calculation sub-results corresponding to each vector can be determined as the calculation result corresponding to the vector data to be calculated, and this calculation result includes the calculation sub-results corresponding to each vector.

[0083] In this embodiment, the vectors in the vector data to be calculated are calculated in parallel, thereby effectively improving the efficiency of vector calculation.

[0084] In some alternative embodiments, step 203 of controlling the target vector calculation array to calculate the target vector data through the target calculation data path and obtaining a calculation result corresponding to the target vector data includes: The method may include a step of determining the number of operation subunits included in the target operation data path of the target vector operation array, and a step of controlling the target vector operation array in response to the number of operation subunits included in the target operation data path being plural so that the target operation data path calculates the vector data to be calculated in a pipeline manner, thereby obtaining a calculation result corresponding to the vector data to be calculated.

[0085] Here, if the target computation data path includes multiple computation subunits, the multiple computation subunits calculate the vector input to the target computation data path in a specific order to obtain a computation result corresponding to the vector. When the vector data to be calculated includes multiple vectors, or when multiple vector data are consecutive (i.e., multiple vector computation tasks are consecutive, each vector data to be calculated corresponds to one vector computation task, and each vector data to be calculated may include one or more vectors), the multiple computation subunits in the target computation data path of the target vector computation array can be controlled to perform calculations in a pipelined manner to obtain a computation result corresponding to the vector data to be calculated. The pipelined manner means that each computation subunit in the target computation data path can perform related calculations of different vectors at the same time. For example, if the target computation data path includes computation subunit a → computation subunit b → computation subunit c, and the vector data to be calculated includes three vectors represented by r1, r2, and r3, respectively, computation subunit a: First, r1 is calculated, and after the calculation subunit a completes the calculation of r1, it outputs the calculation result s11 of r1 to the calculation subunit b. While the calculation subunit b continues to calculate s11, the calculation subunit a starts calculating r2. After the calculation of r2 is completed and the calculation subunit b completes the calculation related to s11 and outputs the calculation result s12 to the calculation subunit c, the calculation subunit a transmits the calculation result s21 of r2 to the calculation subunit b, and the calculation subunit b continues to perform the calculation related to s21. While the calculation subunit c performs the calculation related to s12, the calculation subunit a starts calculating r3. At this time, the calculation subunit a, the calculation subunit b, and the calculation subunit c are all operating, but executing different vector data streams. This method is called a pipeline method.When there are multiple consecutive vector data to be calculated, there is no need to wait for one calculation task to be completed before executing another calculation task. Instead, multiple calculation subunits in the target calculation data path of the target vector calculation array can execute different data streams of vector data to be calculated in parallel using a pipeline method, and by executing using a multi-task pipeline, processing efficiency can be further improved.

[0086] In this embodiment, when the target calculation data path includes multiple calculation subunits, the target calculation data path can be controlled to be calculated in a pipelined manner, which is equivalent to realizing parallel processing of multiple vectors, thereby contributing to further improving calculation efficiency.

[0087] In some alternative embodiments, pipeline processing can be performed between multiple preset vector operation units. That is, when a target vector operation array includes multiple preset vector operation units, the multiple preset vector operation units of the target vector operation array can be controlled to calculate target vector data in a pipelined manner, thereby obtaining calculation results corresponding to the target vector data. At the same time, each preset vector operation unit in the target vector operation array can execute a different vector data stream.

[0088] In some alternative embodiments, Figure 7 is a schematic diagram of a preset vector processing unit according to an exemplary embodiment of the present disclosure. As shown in Figure 7, the preset storage device is memory 13, and each preset vector processing unit is coupled to memory 13. Each preset vector processing unit may be connected to one or more other preset vector processing units. For example, preset vector processing unit 121 may be connected to preset vector processing unit 122, preset vector processing unit 123, ..., preset vector processing unit 12n (n is a positive integer), respectively, to form a calculation data path between the preset vector processing units. This facilitates cooperative calculation between any preset vector processing units through unified task scheduling, thereby completing vector operations of various types. The figure shows only some of the connections between the preset vector operation units, and in actual applications, each preset vector operation unit may be scheduled independently, or any number of preset vector operation units may be scheduled in any combination, and the possible combinations of each preset vector operation unit are not limited to those shown in the figure. As can be seen from the above, a fixed number of preset vector operation units can be used to realize vector calculations of multiple different operation types, greatly improving the utilization rate of the preset vector operation units and the flexibility of application of the preset vector operation units.

[0089] In some alternative embodiments, Figure 8 is a schematic diagram of a vector computation data path of a softmax operator according to one exemplary embodiment of the present disclosure. As shown in Figure 8, the pre-configured vector operation units required to participate in the softmax operator operation include a pre-configured vector operation unit A, a pre-configured vector operation unit B, and a pre-configured vector operation unit C. The pre-configured vector operation unit A includes a reduction operation maximum (reduce max) operation subunit A11, and the pre-configured vector operation unit B includes a floating-point addition (FADD) operation subunit B11, a floating-point multiplication (FMUL) operation subunit B12, a power-of-two operation (exp2) operation subunit B13, a reduction operation sum (reduce sum) operation subunit B14, and a reciprocal (rcp) operation subunit B15. The pre-configured vector operation unit C includes a floating-point multiplication (FMUL) operation subunit C11. PIPEx represents a pipeline. The memory 13 represents a memory, and is used as a preset storage device for data transmission between preset vector operation units. The vector to be calculated is X=[x1, x2, ..., x N ], where N represents the dimension (also called the length, i.e., the number of elements) of the vector X, and the softmax operator can be expressed as the following equation (1).

number

[0090] Here, i = 1, 2, . . . , N, and max(X) is the maximum element value of X. The maximum element value of X is X max As shown in FIG. 8, the vector X is input to the target calculation data path corresponding to softmax, and the maximum element value X of the vector X is obtained by the reduce max calculation subunit A11. max The preset vector calculation unit A calculates X maxis written to memory13, and the preset vector operation unit B reads X from memory13. max and calculates each element x of X by the FADD calculation subunit B11. i and X max The difference value x i -max(X) is calculated, and x is calculated by the FMUL calculation subunit B12 in the figure. i Multiply -max(X) by 1 / ln2 and use the exponential operation e xi-max(X) is converted to a power of 2 operation, and then the exp2 operation subunit B13 converts it to e xi-max(X) and then, by the pipeline PIPEx, each x i e corresponding to xi-max(X) can be calculated in parallel, and further, by the reduce-sum operation subunit B14,

number

number

number

number

[0091] In some alternative embodiments, Figure 9 is a schematic diagram of a vector calculation data path of the layernorm operator according to one exemplary embodiment of the present disclosure. As shown in Figure 9, the layernorm operator requires preset vector operation units to participate in the operation, including preset vector operation unit D, preset vector operation unit E, and preset vector operation unit F. Here, preset vector operation unit D includes a reduction operation (reduce-sum) operation subunit D11 and a floating-point multiplication (FMUL) operation subunit D12. Preset vector operation unit E includes a floating-point addition (FADD) operation subunit E11, a floating-point multiplication (FMUL) operation subunit E12, a reduction operation (reduce-sum) operation subunit E13, and an inverse square root (rsqrt) operation subunit E14. The preset vector operation unit F includes a floating-point multiplication (FMUL) operation subunit F11, a floating-point addition (FADD) operation subunit F12, and a floating-point multiplication (FMUL) operation subunit F13. PIPEx represents a pipeline. memory13 represents a memory, and memory13 is a preset storage device used for data transmission between the preset vector operation units. The vector to be calculated is X=[x1, x2, ..., x N ], where N represents the dimension (also called the length, i.e., the number of elements) of the vector X, and the layernorm operator can be expressed as the following equation (2).

number

[0092] Here, E(X) represents the expected value (average value) of each element of X,

number

number

number

number

number

number

number

number

number

[0093] In some alternative embodiments, the rsqrt operation subunit in FIG. 9 can be subdivided into a square root (sqrt) operation subunit and a reciprocal (rcp) operation subunit, which allows the preset vector operation unit E to accommodate the operation of more types of operators and further improves the utilization rate of the preset vector operation unit.

[0094] In some alternative embodiments, any one of the preset vector operation units D, E, and F in Fig. 9 may be the same preset vector operation unit as a certain preset vector operation unit in Fig. 8, but this preset vector operation unit has different operation subunits involved in operations in different operators. For example, the preset vector operation unit B and the preset vector operation unit E are the same preset vector operation unit.

[0095] 8 and 9 only show selectable target vector operation arrays and corresponding target operation data paths corresponding to the softmax operator and the layernorm operator, respectively. In actual applications, the target vector operation arrays and target operation data paths corresponding to the softmax operator and the layernorm operator, respectively, may be other selectable forms (candidate forms), and are not limited to the candidate forms shown in the figures. For example, the layernorm operator is

number

number

[0096] In some alternative embodiments, Figure 10 is a schematic diagram of a pipelined computation principle according to one exemplary embodiment of the present disclosure. As shown in Figure 10, the data block portions 1, 2, ..., 16 represent 16 data blocks, each of which is a vector. For example, when feature data for model inference needs to be divided into multiple vectors, the feature data is divided into multiple data blocks so that the number of elements in each data block matches the vector dimension supported by a preset vector computation unit. The preset vector computation unit is represented as a vector accelerator (abbreviated as VAE). 10, the preset vector operation unit includes three vector accelerators, VAE0, VAE1, and VAE2. The timeline indicates a timeline. Each vector accelerator operates under the driving of an operating clock. Data blocks 1 to 16 are sequentially input to VAE0. After VAE0 completes the calculation of data block 1, it inputs the data stream of data block 1 to VAE1. At the same time, VAE0 continues to perform the calculation of data block 2. After completing the calculation of data block 2, it inputs the data stream of data block 2 to VAE1. The data stream of data block 1 is input to VAE1, and VAE0 continues to perform the calculation of data block 3. Similarly, after VAE1 completes the calculation of the data stream of data block 1, it inputs the data stream of data block 1 to VAE2, and so on. VAE0, VAE1, and VAE2 can execute the data stream of multiple data blocks in parallel at the same time. For example, in the figure, at the same time, VAE0 executes the calculation of data blocks 7, 8, 9, and 10, VAE1 executes the calculation of data blocks 3, 4, 5, and 6, and VAE2 executes the calculation of data blocks 1 and 2. Taking VAE0 as an example, at the same time, VAE0 can execute the calculation of multiple data blocks (four data blocks are shown as an example) in parallel in a pipelined manner.As can be seen from the above, the pipeline method may be set inside a predetermined vector operation unit, may be set between predetermined vector operation units, may be set inside a predetermined vector operation unit, may be set between predetermined vector operation units, and is not specifically limited.

[0097] In some alternative embodiments, multiple pre-configured vector processing units can be synchronized by a pre-configured synchronization mechanism to achieve serial pipelined calculations.

[0098] In some alternative embodiments, when only a single simple operator needs to be calculated, multiple preset vector operation units having the function of calculating this simple operator can be set to the same mode to complete the calculation of multiple vector simple operators in parallel, so as to improve calculation efficiency. The same mode may be that multiple sets of the same operation subunits form the same multiple target operation data paths, and each target operation data path is controlled by the same control form to complete the calculation of multiple vectors in parallel.

[0099] The method of the embodiment of the present disclosure allows multiple different types of pre-configured vector processing units to be freely combined to realize cooperative computing and efficiently complete various vector processing tasks. In addition, the pre-configured vector processing units can be interconnected, and multiple data transmission methods, such as transmission via a pre-configured storage device, transmission via a connection line between the pre-configured vector processing units, and broadcast transmission between multiple pre-configured vector processing units, can be used, which contributes to reducing memory access bandwidth. In addition, the calculation pipeline, type and calculation power of the calculation subunits within the pre-configured vector calculation unit can be configured according to the needs of actual calculation applications. The number of pre-configured vector calculation units, interconnection topology, synchronization mechanism, etc. can also be configured. Flexible configuration allows vector calculations of various different calculation types to be realized, further improving the utilization rate and application flexibility of the pre-configured vector calculation unit. In addition, each pre-configured vector calculation unit may include one or more calculation subunits and can support at least one calculation data path. Therefore, each calculation subunit is involved in one or more calculation data paths and can be used to calculate operators of different calculation types, thereby realizing the reuse of calculation subunits. Pre-configured vector calculation units can be interconnected to support the calculation of operators of more calculation types. This allows the number of pre-configured vector calculation units to be reduced, effectively expanding the types of calculations that can be realized and achieving diversification of calculation functions.

[0100] The above-described embodiments of the present disclosure may be implemented alone or in any combination where no contradiction exists, and may be specifically set according to actual needs, and the present disclosure is not limited thereto.

[0101] Any one of the vector data calculation methods according to the embodiments of the present disclosure may be executed by any suitable device having data processing capabilities, including, but not limited to, a terminal device, a server, etc. Alternatively, any one of the vector data calculation methods according to the embodiments of the present disclosure may be executed by a processor, for example, the processor executes any one of the vector data calculation methods mentioned in the embodiments of the present disclosure by calling corresponding instructions stored in a storage device. Hereinafter, the description will not be repeated.

[0102] Exemplary Apparatus 11 is a structural schematic diagram of a vector data calculation device according to an exemplary embodiment of the present disclosure. The device of this embodiment can be used to implement an embodiment of the method according to the present disclosure. The device shown in FIG. 11 includes a first processing module 51, a second processing module 52, and a third processing module 53.

[0103] The first processing module 51 is used to determine the vector data to be calculated and the corresponding first operation type.

[0104] The second processing module 52 is used to determine a target vector operation array and a target operation data path corresponding to the target vector operation array from at least one preset vector operation unit based on the first operation type, where the preset vector operation unit supports at least one type of operation data path, and any one of the operation data paths corresponds to one type of calculation function.

[0105] The third processing module 53 is used to control the target vector calculation array to calculate the target vector data through the target calculation data path, and obtain a calculation result corresponding to the target vector data.

[0106] In some optional embodiments, the first processing module 51 can specifically be used to obtain feature data to be calculated, determine at least one vector based on the feature data to be calculated according to a predetermined vector dimension, and determine each vector as vector data to be calculated.

[0107] In some alternative embodiments, each of the preset vector operation units is coupled to a preset storage device so as to read input vector data from the preset storage device and / or output vector calculation results to the preset storage device during the operation process.

[0108] FIG. 12 is a structural schematic diagram of a vector data calculation device according to another exemplary embodiment of the present disclosure.

[0109] In some alternative embodiments, in any one of the above embodiments, the second processing module 52 may include a first processing unit 521 and a second processing unit 522, as shown in FIG.

[0110] The first processing unit 521 is used for determining, based on the first operation type, an operation sub-unit sequence corresponding to the first operation type.

[0111] The second processing unit 522 is used to determine a target vector operation array from each preset vector operation unit and a target operation data path corresponding to the target vector operation array according to the operation subunit sequence.

[0112] In some alternative embodiments, the second processing unit 522 can be specifically used to determine at least one target vector operation unit, a first operation data path corresponding to each of the target vector operation units, and a second operation data path between each of the target vector operation units based on the operation subunit sequence and the operation data path between each of the operation subunits corresponding to each of the predetermined vector operation units, to configure a target vector operation array with each of the target vector operation units, and to determine a target operation data path corresponding to the target vector operation array based on the first operation data path corresponding to each of the target vector operation units and the second operation data path between each of the target vector operation units.

[0113] In some alternative embodiments, the second processing module 52 can be specifically used to determine a target vector operation array and a target operation data path corresponding to the target vector operation array based on a first operation type, a mapping relationship between the operation type and a preset vector operation unit and an operation data path.

[0114] FIG. 13 is a structural schematic diagram of a vector data calculation device according to yet another exemplary embodiment of the present disclosure.

[0115] In some alternative embodiments, as shown in FIG. 13, the second processing module 52 may include a third processing unit 52a and a fourth processing unit 52b.

[0116] The third processing unit 52a is used to determine the first number of target vector operation arrays based on the number of vectors included in the vector data to be calculated and the first operation type.

[0117] The fourth processing unit 52b is used to determine, based on the first number, a first number of target vector operation arrays from each of the preset vector operation units and target operation data paths corresponding to each of the target vector operation arrays.

[0118] FIG. 14 is a structural schematic diagram of a vector data calculation device according to yet another exemplary embodiment of the present disclosure.

[0119] In some alternative embodiments, as shown in FIG. 14, the third processing module 53 may include a first control unit 531 and a fifth processing unit 532.

[0120] The first control unit 531 is used to control each target vector calculation array to perform parallel calculation on each vector in the vector data to be calculated via the target calculation data path, and obtain calculation sub-results corresponding to each vector.

[0121] The fifth processing unit 532 is used to determine a calculation result corresponding to the vector data to be calculated based on the calculation sub-results corresponding to each vector.

[0122] In some alternative embodiments, the third processing module 53 specifically: The number of operation subunits included in the target operation data path of the target vector operation array is determined, and in response to the number of operation subunits included in the target operation data path being plural, the target vector operation array is controlled so that the target operation data path calculates the vector data to be calculated in a pipelined manner, and the calculation result corresponding to the vector data to be calculated can be obtained.

[0123] In some alternative embodiments, in any one of the above embodiments, the apparatus of the present disclosure may further include the at least one preset vector operation unit.

[0124] The beneficial technical effects corresponding to the exemplary embodiments of the present device may refer to the beneficial technical effects corresponding to the exemplary method parts described above, and the description thereof will be omitted here.

[0125] An embodiment of the present invention further provides a vector processor, and as shown in FIG. 1, the vector processor may include a vector data calculation device according to any one of the above embodiments and at least one preset vector operation unit.

[0126] In some alternative embodiments, the pre-configured vector processing unit can support at least one type of computational data path, with any one computational data path corresponding to one type of computational function.

[0127] In some alternative embodiments, as shown in FIG. 7, each preset vector operation unit is coupled to a preset storage device so as to read input vector data from the preset storage device and / or output vector calculation results to the preset storage device during the operation process.

[0128] In some alternative embodiments, as shown in FIG. 7, an operation data path is formed between any two preset vector operation units to realize interconnection between the preset vector operation units.

[0129] Compared with conventional vector accelerators in the related art, the vector processor of the embodiment of the present disclosure greatly improves the diversity of calculation functions and application flexibility. Compared with GPGPUs, the vector processor of the embodiment of the present disclosure realizes different vector calculation functions through different hardware operation data paths, which helps to improve calculation efficiency.

[0130] Exemplary Electronic Devices FIG. 15 is a structural diagram of an electronic device according to an embodiment of the present disclosure, where an electronic device 90 includes at least one processor 91 and a storage device 92.

[0131] The processor 91 may be a central processing unit (CPU) or other form of processing unit having data processing and / or instruction execution capabilities, and may control other components in the electronic device 90 to perform desired functions.

[0132] The storage device 92 may include one or more computer program products, which may include various forms of computer-readable storage media, such as, for example, volatile and / or non-volatile storage devices. Volatile storage devices may include, for example, random access memory (RAM) and / or cache memory. Non-volatile storage devices may include, for example, read-only memory (ROM), a hard disk, flash memory, etc. One or more computer program instructions may be stored in the computer-readable storage media, and the processor 91 may execute the one or more computer program instructions to implement the methods and / or other desired functions of each embodiment of the present disclosure described above.

[0133] In one example, electronic device 90 may further include input devices 93 and output devices 94, with these components interconnected via a bus system and / or other form of connection (not shown).

[0134] The input device 93 may further include, for example, a keyboard, a mouse, a touch panel, a microphone, various sensors, etc. The sensors may include, for example, a pressure sensor, an air quality sensor, a temperature sensor, etc. The pressure sensor can be used to detect seat pressure. The temperature sensor can be used to detect temperature in the vehicle cabin. The air quality sensor can be used to detect air quality in the vehicle cabin.

[0135] The output device 94 can output various types of information to the outside, and may include, for example, a display, a speaker, a printer, a communication network, and remote output devices connected to these.

[0136] 15 shows only some of the components related to the present disclosure in the electronic device 90, and omits components such as buses, input / output interfaces, etc. The electronic device 90 may further include any other appropriate components depending on the specific application.

[0137] Exemplary Computer Program Products and Computer-Readable Storage Media In addition to the above methods and apparatus, embodiments of the present disclosure may further provide a computer program product including computer program instructions that, when executed by a processor, cause the processor to perform the steps of the methods of various embodiments of the present disclosure described in the "Example Methods" section above.

[0138] The computer program product may have program code for carrying out operations of embodiments of the present disclosure written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may execute entirely on a user's computing device, partially on a user's device, as separate software packages, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0139] Additionally, an embodiment of the present disclosure may be a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, cause the processor to perform the steps of the methods of various embodiments of the present disclosure described in the "Exemplary Methods" section above.

[0140] The computer-readable storage medium may employ any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (non-exhaustive list) of readable storage media include an electrical connection having one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0141] Although the basic principles of the present disclosure have been described above with reference to specific embodiments, the benefits, advantages, effects, etc. mentioned in the present disclosure are not limited but merely illustrative, and these benefits, advantages, effects, etc. do not necessarily exist in each embodiment of the present disclosure. Furthermore, the specific details disclosed above are not limited but merely serve to serve as examples and to facilitate understanding, and the above details do not necessarily limit the present disclosure to be realized by the above specific details.

[0142] Those skilled in the art can make various modifications and variations to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure also intends to include these modifications and variations.

Claims

1. determining vector data to be calculated and a corresponding first operation type; determining a target vector operation array and a target operation data path corresponding to the target vector operation array from at least one preset vector operation unit based on the first operation type, wherein the preset vector operation unit supports at least one type of operation data path, and any one of the operation data paths corresponds to one type of calculation function; controlling the target vector operation array to calculate the target vector data through the target operation data path, and obtaining a calculation result corresponding to the target vector data; A vector data calculation method executed by a vector data calculation device.

2. determining a target vector operation array and a target operation data path corresponding to the target vector operation array from at least one predetermined vector operation unit based on the first operation type, determining, based on the first operation type, an operation sub-unit sequence corresponding to the first operation type; and determining the target vector operation array and the target operation data path corresponding to the target vector operation array from each of the predetermined vector operation units based on the operation subunit sequence.

3. The step of determining the target vector operation array and the target operation data path corresponding to the target vector operation array from each of the predetermined vector operation units based on the operation subunit sequence includes: determining at least one target vector operation unit, a first operation data path corresponding to each of the target vector operation units, and a second operation data path between each of the target vector operation units based on the operation subunit sequence and operation data paths between operation subunits corresponding to each of the predetermined vector operation units; configuring the target vector operation array with each of the target vector operation units; and determining the target operation data path corresponding to the target vector operation array based on a first operation data path corresponding to each of the target vector operation units and a second operation data path between each of the target vector operation units.

4. determining a target vector operation array and a target operation data path corresponding to the target vector operation array from at least one predetermined vector operation unit based on the first operation type, 2. The vector data calculation method according to claim 1, further comprising: determining the target vector operation array and the target operation data path corresponding to the target vector operation array based on the first operation type, a mapping relationship between the operation type and a preset vector operation unit and operation data path.

5. determining a target vector operation array and a target operation data path corresponding to the target vector operation array from at least one predetermined vector operation unit based on the first operation type, determining a first number of the target vector operation arrays based on the number of vectors included in the vector data to be calculated and the first operation type; and determining, based on the first number, the first number of target vector operation arrays from each of the predetermined vector operation units, and the target operation data paths corresponding to each of the target vector operation arrays.

6. The step of controlling the target vector operation array to calculate the target vector data through the target operation data path and obtaining a calculation result corresponding to the target vector data includes: controlling each of the target vector operation arrays to perform parallel calculations on each of the vectors in the vector data to be calculated via the target operation data path, and obtaining calculation sub-results corresponding to each of the vectors; The vector data calculation method according to claim 5 , further comprising: determining the calculation result corresponding to the vector data to be calculated based on the calculation sub-results corresponding to each of the vectors.

7. The step of controlling the target vector operation array to calculate the target vector data through the target operation data path and obtaining a calculation result corresponding to the target vector data includes: determining the number of computing subunits included in the target computation data path of the target vector computation array; a step of controlling the target vector operation array so that the target operation data path calculates the vector data to be calculated in a pipeline manner in response to the number of operation subunits included in the target operation data path being plural, and obtaining the calculation result corresponding to the vector data to be calculated.

8. The step of determining vector data to be calculated includes: A step of obtaining calculation target feature data; determining at least one vector according to a predetermined vector dimension based on the feature data to be calculated; The vector data calculation method according to claim 1, further comprising the step of determining each of the vectors as the vector data to be calculated.

9. The vector data calculation method according to any one of claims 1 to 4, wherein each of the predetermined vector calculation units is coupled to a predetermined storage device, thereby reading input vector data from the predetermined storage device during the calculation process and / or outputting vector calculation results to the predetermined storage device.

10. a first processing module for determining vector data to be calculated and a corresponding first operation type; a second processing module for determining a target vector operation array and a target operation data path corresponding to the target vector operation array from at least one preset vector operation unit based on the first operation type, the preset vector operation unit supporting at least one type of operation data path, and any one of the operation data paths corresponding to one type of calculation function; a third processing module for controlling the target vector calculation array to calculate the target vector data through the target calculation data path, and obtaining a calculation result corresponding to the target vector data; A vector data calculation device.

11. A vector processor comprising the vector data calculation device of claim 10 and at least one of the preset vector operation units.

12. A computer program for carrying out the method according to any one of claims 1 to 4 is stored. A computer-readable storage medium.

13. a processor; a memory device for storing instructions executable by the processor; The processor is adapted to read and execute the executable instructions from the storage device to implement the method of any one of claims 1 to 4. electronic equipment.

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