Display device

Abstract

To reduce a reverse current of a diode. Another object of one embodiment of the present invention is to improve the quality of images displayed by display devices using thin film transistor.SOLUTION: The thin film transistor includes a microcrystalline semiconductor film which is provided over a gate electrode via a gate insulating film in an inner region which does not reach an end portion of the gate electrode, an amorphous semiconductor film which covers an upper surface and a side surface of the microcrystalline semiconductor film, and an impurity semiconductor film which is formed over the amorphous semiconductor film and to which an impurity element which serves as a source region and a drain region is added.SELECTED DRAWING: Figure 16

Description

[Technical Field]

[0001] The present invention relates to a diode and a display device having the same. [Background technology]

[0002] In recent years, semiconductor thin films (thickness of about tens to hundreds of nm) formed on substrates with insulating surfaces have been used. The technology for constructing thin-film transistors is attracting attention. It is widely used in electronic devices such as optical devices, and is particularly used as a switching element in image display devices. Development is being rushed.

[0003] Thin film transistors using amorphous semiconductor films are used as switching elements for image display devices. Thin film transistors using polycrystalline semiconductor films with crystal grain sizes of 100 nm or more are used. The polycrystalline semiconductor film is formed by irradiating a pulsed excimer laser beam through an optical system. The amorphous silicon film is then irradiated with a linear beam while scanning it to crystallize it. The technique is known.

[0004] In addition, as a switching element for an image display device, a fine crystal grain size of about 1 nm to 100 nm is used. Thin film transistors using crystalline semiconductor films are used (Patent Documents 1 and 2). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 4-242724 [Patent Document 2] Japanese Patent Application Laid-Open No. 2005-49832 Summary of the Invention [Problem to be solved by the invention]

[0006] Thin film transistors using polycrystalline semiconductor films are thin film transistors using amorphous semiconductor films. The field effect mobility is two orders of magnitude higher than that of the pixel part of a semiconductor display device and its surrounding driving circuit. However, the amorphous semiconductor film Compared to the case where a semiconductor film is used, the process becomes more complicated due to the crystallization of the semiconductor film, and the yield is accordingly reduced. This results in a decrease in productivity and an increase in costs.

[0007] In addition, an inverted staggered thin film transistor using a microcrystalline semiconductor film in a channel formation region is Compared with an inverted staggered thin film transistor that uses an amorphous semiconductor film in the channel formation region, It is possible to improve the on-current, but the off-current also increases. Display devices using high current thin film transistors have poor contrast and consume less power. There is also the problem of increased power consumption.

[0008] In view of the above-mentioned problems, one of the objects of the present invention is to reduce the off-current of a thin film transistor. Another object is to reduce the reverse current of the diode. One of the objectives is to improve the image quality of the device. [Means for solving the problem]

[0009] One aspect of the present invention is to provide a gate electrode on which a gate insulating film is formed so as not to reach the end of the gate electrode. a microcrystalline semiconductor film provided in a side region and an amorphous film covering the top surface and side surfaces of the microcrystalline semiconductor film; A semiconductor film and a conductive film in which a source region and a drain region are formed on the amorphous semiconductor film. and an impurity semiconductor film to which an impurity element having a conductivity type is added, and the microcrystalline semiconductor film has a donor and The thin film transistor is characterized by containing an impurity element.

[0010] The end portions of the microcrystalline semiconductor film on the source and drain region sides are made of an amorphous semiconductor film and an impurity semiconductor film. In addition, a part of the edge of the microcrystalline semiconductor film may overlap with the source electrode or the drain electrode. The end of the amorphous semiconductor film may be covered with the source electrode and the drain electrode. The conductive layer may be exposed on the outside of the conductive electrode.

[0011] One aspect of the present invention is to provide a gate electrode on which a gate insulating film is formed so as not to reach the end of the gate electrode. a microcrystalline semiconductor film provided in a side region and doped with an impurity element serving as a donor; an amorphous semiconductor film covering the top and side surfaces of the semiconductor film; and a source region on the amorphous semiconductor film. Alternatively, an impurity semiconductor film to which one conductivity type impurity element is added, which forms a drain region, and an impurity semiconductor film to which one conductivity type impurity element is added, The gate electrode and the common line are connected by a conductive film. It is a diode that is used.

[0012] One aspect of the present invention is to provide a gate electrode on which a gate insulating film is formed so as not to reach the end of the gate electrode. a microcrystalline semiconductor film provided in a side region and doped with an impurity element serving as a donor; an amorphous semiconductor film covering the top and side surfaces of the semiconductor film; and a source region on the amorphous semiconductor film. Alternatively, an impurity semiconductor film to which one conductivity type impurity element is added, which forms a drain region, and an impurity semiconductor film to which one conductivity type impurity element is added, The gate electrode and the wiring are connected to the first conductive film. The amorphous semiconductor film or the microcrystalline semiconductor film and the common line are connected by a second conductive film. It is a diode that can be used.

[0013] The end portion of the microcrystalline semiconductor film on the source region or drain region side is made of an amorphous semiconductor film. The amorphous semiconductor film may overlap with the pure semiconductor film. The end of the amorphous semiconductor film may be covered by the source electrode or the drain electrode. The drain electrode may be exposed to the outside.

[0014] In the present invention, an amorphous semiconductor film may be provided so as to overlap the microcrystalline semiconductor film.

[0015] In the present invention, the microcrystalline semiconductor film may be a microcrystalline silicon film, a microcrystalline germanium film, Alternatively, the microcrystalline semiconductor film may be a microcrystalline silicon germanium film. The semiconductor layer may have a stacked structure of a silicon film and a microcrystalline germanium film. The structure is composed of crystal grains doped with impurity elements that act as donors and a germanium film covering the crystal grains. Alternatively, an amorphous germanium film or an amorphous silicon film may be used instead of the microcrystalline semiconductor film. A cone germanium film may also be used.

[0016] The impurity element that serves as a donor is phosphorus, arsenic, or antimony.

[0017] In addition, a thin film transistor (TFT) using a microcrystalline semiconductor film in a channel formation region is used as a pixel portion. The microcrystalline semiconductor film of the present invention is used in a gate insulating film, and further in a driver circuit to manufacture a display device. Since the crystallinity at the interface with the insulating film is high, a thin film transistor using the microcrystalline semiconductor film The field-effect mobility is 2.5 to 10 cm 2 / V·sec and amorphous semiconductor film It has a field effect mobility 5 to 20 times that of thin film transistors, so it can be used as part of a driving circuit or The entire display can be formed on the same substrate as the pixel section, forming a system-on-panel. do.

[0018] The display device also includes a light-emitting device and a liquid crystal display device. The liquid crystal display device includes a liquid crystal element, the luminance of which is controlled by a current or a voltage. This category includes elements, specifically organic electroluminescence (EL) and inorganic Includes electronics.

[0019] The display device also includes a panel in which a display element is sealed, and a controller for the panel. Furthermore, the present invention also includes a module in which an IC or the like including the display device is mounted. Regarding an element substrate corresponding to one form before the display element is completed in the process of manufacturing the device, The element substrate includes means for supplying a current to a display element for each of a plurality of pixels. Specifically, the pixel electrode of the display element may be formed only, or the pixel electrode may be formed only. This was after the conductive film was formed, but before etching to form the pixel electrode. It can be any form, and all forms are applicable.

[0020] In this specification, the term "display device" refers to an image display device, a light-emitting device, or a light It also refers to connectors, such as FPC (Flexible Printed Circuit) integrated circuit) or TAB (Tape Automated Bon ding) tape or TCP (Tape Carrier Package) Modules with printed wiring boards attached to the end of TAB tape or TCP or the display element is mounted on an IC (integrated circuit) by the COG (Chip On Glass) method. The display device also includes all modules in which the display device (circuit) is directly mounted. [Effects of the Invention]

[0021] According to the present invention, the off-current of a thin film transistor can be reduced. It is possible to fabricate a thin film transistor having high field effect mobility and reduced off-current. In addition, the reverse current of the diode can be reduced. It is possible to fabricate diodes with high switching speeds, which improves the image quality of display devices. can be improved. [Brief explanation of the drawings]

[0022] [Figure 1] 1A to 1C are cross-sectional views illustrating a manufacturing process of a thin film transistor of the present invention. [Figure 2] 1A to 1C are cross-sectional views illustrating a manufacturing process of a thin film transistor of the present invention. [Figure 3] 1A to 1C are cross-sectional views illustrating a manufacturing process of a thin film transistor of the present invention. [Figure 4] 1A to 1C are cross-sectional views illustrating a manufacturing process of a thin film transistor of the present invention. [Figure 5] 1A to 1C are plan views illustrating a manufacturing process of a thin film transistor of the present invention. [Figure 6] 1A to 1C are cross-sectional views illustrating a manufacturing process of a thin film transistor of the present invention. [Figure 7] 1A and 1B are diagrams illustrating a multi-tone mask applicable to the present invention. [Figure 8] 1A to 1C are cross-sectional views illustrating a manufacturing process of a thin film transistor of the present invention. [Figure 9] 1A to 1C are plan views illustrating a manufacturing process of a thin film transistor of the present invention. [Figure 10] FIG. 1 is a cross-sectional view illustrating a thin film transistor of the present invention. [Figure 11] FIG. 1 is a cross-sectional view illustrating a thin film transistor of the present invention. [Figure 12] 1A and 1B are a plan view and a cross-sectional view illustrating a diode according to the present invention. [Figure 13] 1A and 1B are a plan view and a cross-sectional view illustrating a diode according to the present invention. [Figure 14] FIG. 2 is a plan view illustrating an element substrate of the present invention. [Figure 15] FIG. 1 is a plan view illustrating a diode according to the present invention. [Figure 16] 1 is a cross-sectional view illustrating a diode according to the present invention. [Figure 17] 1A to 1C are cross-sectional views illustrating a manufacturing process of a diode according to the present invention. [Figure 18] 1 is a cross-sectional view illustrating a diode according to the present invention. [Figure 19] 1A to 1C are cross-sectional views illustrating a manufacturing process of a diode according to the present invention. [Figure 20] FIG. 1 is a plan view illustrating a diode according to the present invention. [Figure 21] 1 is a cross-sectional view illustrating a diode according to the present invention. [Figure 22] 1A to 1C are cross-sectional views illustrating a manufacturing process of a diode according to the present invention. [Figure 23] FIG. 1 is a diagram showing the configuration of a plasma CVD apparatus applicable to the present invention. [Figure 24] FIG. 1 is a diagram showing the configuration of a plasma CVD apparatus applicable to the present invention. [Figure 25] 1 is a diagram showing the configuration of a plasma CVD apparatus applicable to the present invention and a film formation procedure. [Figure 26] FIG. 1 is a plan view illustrating a display device of the present invention. [Figure 27] FIG. 2 is a cross-sectional view illustrating a terminal portion and a pixel portion of the display device of the present invention. [Figure 28] FIG. 1 is a cross-sectional view illustrating a display device of the present invention. [Figure 29] FIG. 1 is a top view illustrating a display device of the present invention. [Figure 30] FIG. 1 is a top view illustrating a display device of the present invention. [Figure 31] 1A and 1B are a cross-sectional view and a top view illustrating a display device of the present invention. [Figure 32] FIG. 1 is a perspective view illustrating a display panel of the present invention. [Figure 33] 1 is a perspective view illustrating an electronic device using a display device of the present invention. [Figure 34] 1A to 1C are diagrams illustrating electronic devices using a display device of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0023] The present invention will be described below with reference to the accompanying drawings. The present invention is not limited to the above, and various modifications and variations in form and detail are possible without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the present invention. The present invention is not limited to the description of the embodiments. In the drawings, the same reference numerals are used to refer to the same parts.

[0024] (Embodiment 1) In this embodiment, a thin film transistor having high mobility, high on-state current, and low off-state current is The manufacturing process will be described below. In this embodiment, the element substrate 1 of the display device shown in FIG. In the top view of 300, the thin film transistors formed in each pixel of the pixel portion 1331, The manufacturing steps of the electrodes and the capacitor element are described below.

[0025] Enlarged view of the area where the thin film transistor and pixel electrode of one pixel of the pixel section 1331 in FIG. 14 are connected 5, cross-sectional views of the QR in FIG. 5 are shown in FIGS. 1 to 3, and a cross-sectional view of the ST is shown in FIG. show.

[0026] As shown in FIG. 1A, a gate electrode 51 and a capacitance wiring 56 are formed on a substrate 50. Gate insulating films 52 a and 52 b are formed on the electrode 51 and the capacitance wiring 56 .

[0027] The substrate 50 is made of barium borosilicate glass, aluminoborosilicate glass, or aluminoborosilicate glass. Alkali-free glass substrates, such as silicate glass, manufactured by the fusion method or float method In addition to ceramic substrates, plastic substrates that are heat resistant and can withstand the processing temperatures of this manufacturing process are also available. Alternatively, an insulating film may be provided on the surface of a metal substrate such as a stainless steel alloy. A substrate having a thickness of 1000 nm may also be used.

[0028] The gate electrode 51 and the capacitance wiring 56 can be formed by sputtering, CVD, plating, printing, liquid crystal display, or the like. The conductive film is formed by a droplet discharge method or the like. Here, a molybdenum film is formed on the substrate 50 by sputtering. The resist mask formed using the first photomask is used to form a film. The conductive film formed on the substrate 50 is then etched to form the gate electrode 51 and the capacitance wiring 56. do.

[0029] The gate electrode 51 is made of a metal material, such as aluminum, chromium, or titanium. The gate electrode 51 is preferably made of aluminum. It is formed by a laminated structure of niobium or aluminum and a barrier metal. For the barrier metal, titanium, molybdenum, chromium, and other high melting point metals are used. It is preferable to provide this in order to prevent hillocks and oxidation of the aluminum.

[0030] The gate electrode 51 is formed to a thickness of 50 nm or more and 300 nm or less. By setting the thickness to 50 nm or more and 100 nm or less, the microcrystalline germanium film and wiring that will be formed later can be easily formed. Furthermore, the thickness of the gate electrode 51 is set to 150 nm or more and 300 nm or less. By making the gate electrode 51 lower, the resistivity of the gate electrode 51 can be reduced, and the area can be increased. is.

[0031] Since a microcrystalline semiconductor film and wiring are formed on the gate electrode 51, the edge is It is desirable to process the part so that it is tapered. Wiring lines connected to the port electrodes, capacitance wiring lines, common lines, etc. can also be formed at the same time.

[0032] The gate insulating films 52a and 52b are each formed by a CVD method, a sputtering method, or the like, to a thickness of 1000 .mu.m. 50 to 150 nm silicon oxide film, silicon nitride film, silicon oxynitride film, or silicon nitride oxide film Here, the gate insulating film 52a is formed of a silicon nitride film or a nitride oxide film. A silicon film is formed, and a silicon oxide film or a silicon oxynitride film is formed as a gate insulating film 52b. The gate insulating film is not made of two layers, but is made of a silicon oxide film, The insulating film can be formed of a single layer of a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. Furthermore, the gate insulating film can have a three-layer structure using the above insulating films.

[0033] The gate insulating film 52a is formed using a silicon nitride film or a silicon nitride oxide film. The adhesion between the substrate 50 and the gate insulating film 52a is increased, and when a glass substrate is used as the substrate 50, It is possible to prevent impurities from the substrate 50 from diffusing into the microcrystalline semiconductor film, and further In addition, oxidation of the gate electrode 51 can be prevented. This can improve the electrical characteristics of the thin film transistor that will be formed later. When the insulating films 52a and 52b each have a thickness of 50 nm or more, the gate electrode 51 is not easily damaged by the unevenness. This is preferable because it is possible to alleviate the reduction in coverage caused by the coating.

[0034] Here, the silicon oxynitride film is a film whose composition contains more oxygen than nitrogen. Rutherford Backscattering (RBS) ering spectrometry and hydrogen forward scattering (HFS) n Forward Scattering (FSc) measurement, the composition range is Oxygen 50-70 atomic %, nitrogen 0.5-15 atomic %, silicon 25-35 atomic %, water The silicon nitride oxide film is a film containing 0.1 to 10 atomic percent of silicon. The composition contains more nitrogen than oxygen, and is measured using RBS and HFS. When the composition is determined, the oxygen content is 5 to 30 atomic percent, the nitrogen content is 20 to 55 atomic percent, and the silicon content is 10 to 20 atomic percent. It refers to a material containing 25 to 35 atomic % of silicon and 10 to 30 atomic % of hydrogen. When the total atoms constituting silicon nitride or silicon oxynitride is taken as 100 atomic % The content ratios of nitrogen, oxygen, silicon and hydrogen are within the above ranges.

[0035] Next, a microcrystalline semiconductor film 45 containing an impurity element serving as a donor is formed on the gate insulating film 52b. The microcrystalline semiconductor film 58 containing an impurity element serving as a donor may include phosphorus, arsenic, ammonium, or the like. Microcrystalline silicon films, microcrystalline germanium films containing impurity elements such as silicon, which act as donors, Examples include microcrystalline silicon germanium.

[0036] The microcrystalline semiconductor film here is an intermediate structure between amorphous and crystalline structures (including single crystal and polycrystal). This semiconductor has a third state that is stable in terms of free energy. It is a semiconductor that has a crystalline structure with short-range order and lattice distortion, and has a grain size of 0. Columnar or needle-like crystals of 5 to 20 nm grow in the normal direction to the substrate surface. A non-single-crystal semiconductor exists between multiple microcrystalline semiconductors. Microcrystalline silicon has a Raman spectrum of 520 cm, which is indicative of single-crystal silicon. -1 than The wave number shifts to the lower side, i.e., 520 cm, which indicates single-crystal silicon. -1 and Amorpha Silicon showing 480cm -1 The Raman spectrum of microcrystalline silicon has a peak between In addition, hydrogen or halogen is used to terminate dangling bonds. In addition, helium, argon, krypton, By adding rare gas elements such as neon to further promote lattice distortion, the stability is improved. Such a microcrystalline semiconductor film can be obtained by, for example, This is disclosed in US Patent No. 4,409,134.

[0037] The thickness of the microcrystalline semiconductor film 58 containing the impurity element serving as a donor is 1 nm or more and 200 nm or less. , preferably 1 nm or more and 100 nm or less, preferably 1 nm or more and 50 nm or less, preferably The microcrystalline semiconductor film containing an impurity element serving as a donor is formed to a thickness of 10 nm to 25 nm. By setting the thickness of 58 to 1 nm or more and 50 nm or less, a fully depleted thin film transistor can be created. It can be manufactured.

[0038] The concentration of the impurity element serving as a donor contained in the microcrystalline semiconductor film is 6×10 15 cm -3 End 3×10 18 cm -3Less than 1 × 10 16 cm -3 3x10 or more 18 cm -3 Less than or equal to 3 x 10 16 cm -3 3x10 or more 17 cm -3 Microcrystalline semi-crystalline By setting the concentration of the impurity element that serves as a donor contained in the conductive film 58 within the above range, It is possible to improve the crystallinity at the interface between the insulating film 52b and the microcrystalline semiconductor film 58. Since the resistivity of the microcrystalline semiconductor film 58 can be reduced, the field effect mobility is high. In this case, a thin film transistor having a high on-state current can be manufactured. The peak concentration of the donor impurity element contained in the 15 cm -3 If it is less than that, Donna The amount of impurity elements that act as a barrier is insufficient, and an increase in field-effect mobility and on-current cannot be expected. In addition, the peak concentration of the impurity element serving as a donor contained in the microcrystalline semiconductor film is set to 3×10 18 c m -3 If the gate voltage is larger than 100 V, the threshold voltage will shift to the negative side of the gate voltage, resulting in a thin film transistor. Since it does not function as a transistor, the concentration of the donor impurity element is 6×10 15 cm -3 3x10 or more 18 cm -3 Less than 1 × 10 16 cm -3 3x10 or more 18 cm -3 Less than or equal to 3 x 10 16 cm -3 3x10 or more 17 cm -3 Below is It is preferable that

[0039] The oxygen concentration and the nitrogen concentration of the microcrystalline semiconductor film 58 containing the impurity element serving as a donor are Less than 10 times the concentration of the donor impurity element, typically 3 x 10 19 atoms / cm 3 less than 3×10 18 atoms / cm 3 less than 3×10 1 8 atoms / cm 3 It is preferable that oxygen, nitrogen, and carbon are contained in the microcrystalline semiconductor. By reducing the concentration of impurity elements mixed into the film, the microcrystalline semiconductor film 58 containing the impurity elements that serve as donors can be formed. Furthermore, the generation of defects can be suppressed. Therefore, the crystallization is difficult when an impurity element that acts as a donor is included in the microcrystalline semiconductor. The oxygen concentration or nitrogen concentration in the film 58 is relatively low, and the film 58 contains impurity elements that act as donors. This can increase the crystallinity of the microcrystalline semiconductor film 58 containing the impurity element serving as a donor. can.

[0040] In addition, the microcrystalline semiconductor film 58 containing the impurity element serving as a donor in this embodiment mode has a Since the microcrystalline semiconductor film 58 containing the impurity element that serves as a donor is By adding impurity elements that act as acceptors to the film during or after film formation, It is possible to control the threshold voltage. Typical impurity elements that act as acceptors are The most preferred is boron, and impurity gases such as B2H6 and BF3 are added at 1 ppm to 1000 ppm. It is advisable to mix boron into silicon hydride at a ratio of 1 to 100 ppm. , about one-tenth of the donor impurity element, e.g., 1×10 14 ~6×10 16 ato ms / cm3 It would be good to say so.

[0041] In the reaction chamber of the plasma CVD device, a deposition gas containing silicon or germanium is and hydrogen are mixed, and a microcrystalline semiconductor film 45 is formed by glow discharge plasma. The flow rate of hydrogen is set to 10 to 2000 times the flow rate of deposition gas containing silicon or germanium. The substrate is heated to a temperature of 1000°C, preferably 50 to 200 times. The reaction is carried out at a temperature of 100 to 300°C, preferably 120 to 220°C. By mixing gases containing phosphorus, arsenic, antimony, etc., impurity elements that act as donors are added. Here, a microcrystalline semiconductor film containing silane, hydrogen, and / or rare gas can be formed. The phosphorus-containing microcrystalline silicon was produced by mixing silicon dioxide with phosphine and using glow discharge plasma. A silicon film can be formed.

[0042] In the process of forming the microcrystalline semiconductor film 45 containing the impurity element serving as a donor, The generation of 3MHz to 30MHz, typically 13.56MHz, 27.12MHz High frequency power in the VHF band, or high frequency power in the VHF band from 30 MHz to about 300 MHz This is done by applying a voltage, typically 60 MHz. Alternatively, a high frequency plasma of 2.45 GHz can be used.

[0043] Representative examples of deposition gases containing silicon or germanium include SiH4, Si 2H6, GeH4, Ge2H6, etc.

[0044] Instead of forming the semiconductor film 47 containing the impurity element that serves as a donor, A semiconductor film containing no pure elements is formed, and an impurity source that becomes a donor is formed as the gate insulating film 52b. For example, an insulating film containing impurity elements (phosphorus, arsenic, or Silicon oxide film, silicon nitride film, silicon oxynitride film, or silicon nitride oxide film containing antimony In addition, when the gate insulating film 52b has a laminated structure, An impurity element that becomes a donor is added to the layer in contact with the crystalline semiconductor film 45 or the layer in contact with the substrate 50. You may do so.

[0045] As a method for forming the insulating film containing the impurity element that serves as a donor as the gate insulating film 52b, If an insulating film is formed using a gas containing an impurity element that acts as a donor together with the raw material gas for the insulating film, For example, a plasma CVD method using silane, ammonia, and phosphine can be used. It is possible to form silicon nitride containing phosphorus. It is also possible to form silicon nitride containing phosphorus by using silane, nitrous oxide, and ammonia. Silicon oxynitride film containing phosphorus was fabricated by plasma CVD using nia and phosphine. can be formed.

[0046] Before forming the gate insulating film 52b, an impurity source serving as a donor is added to the reaction chamber of the film forming apparatus. A gas containing impurity elements is flowed to adsorb impurity elements that act as donors onto the surface of the substrate 50 and the inner wall of the reaction chamber. Thereafter, the gate insulating film 52b is formed to remove the impurity element that serves as a donor. Since the insulating film is deposited while the gate insulating film is being embedded, it forms a gate insulating film containing impurity elements that act as donors. It is possible.

[0047] In addition, before forming the microcrystalline semiconductor film 45 containing the impurity element serving as a donor, A gas containing an impurity element that will be a donor is flowed into the reaction chamber, and the gate insulating film 52b and the wall of the reaction chamber are An impurity element that serves as a donor may be adsorbed onto the surface of the semiconductor layer. Since the microcrystalline semiconductor film is deposited while incorporating the impurity element that becomes the donor, The microcrystalline semiconductor film 45 containing the impurity element can be formed.

[0048] In order to form a microcrystalline semiconductor film containing an impurity element which serves as a donor, silicon or A fluoride gas containing silicon or germanium, together with a deposition gas containing germanium. In this case, the flow rate of silane fluoride is set to 0.1 to 50% of the flow rate of silane. The microcrystalline semiconductor film 45 containing the impurity element serving as a donor is To form silicon or germanium, a deposition gas containing silicon or germanium is added. By using a fluoride gas containing germanium, the crystal growth of the microcrystalline semiconductor film can be improved. The fluorine radicals etch the amorphous semiconductor components, resulting in high crystallinity and crystal growth. That is, a microcrystalline semiconductor film with high crystallinity can be formed.

[0049] In addition, germanium hydrides such as GeH4 and GeF4, and germanium fluorides, etc., are present in gases such as silane. Silicon germanium mixed with silicon to adjust the energy band width from 0.9 to 1.1 eV. Adding germanium to silicon improves the temperature characteristics of thin film transistors. You can change your gender.

[0050] In addition, in the microcrystalline semiconductor film containing the impurity element serving as a donor in this embodiment mode, Because it contains impurity elements, it is a microcrystal that functions as the channel formation region of a thin film transistor. For semiconductor films, impurity elements that become acceptors are added simultaneously with or after film formation. By adding impurity elements, it becomes possible to control the threshold voltage. The typical example is boron, and impurity gases such as B2H6 and BF3 are added at 1 ppm to 10 00 ppm, preferably 1 to 100 ppm, of silicon or germanium. The boron concentration is 10 times that of the impurity element that acts as a donor. For example, 1×10 14 ~6×10 16 atoms / cm 3 It would be good to say so.

[0051] In addition, in the deposition process of a microcrystalline semiconductor film containing an impurity element that serves as a donor, silane and In addition to hydrogen, helium can be added to the reaction gas. Helium has an energy of 24.5 eV, which is higher than all other gases. It has the highest ionization energy of any of the compounds, and is slightly lower than that, at about 2 Since there is a metastable state at the 0 eV level, the difference in ionization is about 4 Therefore, the discharge initiation voltage is the lowest among all gases. Due to these characteristics, helium can maintain a stable plasma. Since a sma can be formed, a microcrystalline semiconductor film containing an impurity element that becomes a donor is deposited. Even if the area of ​​the substrate to be treated is large, the plasma density can be made uniform.

[0052] Next, the first buffer layer 54 is formed. The first buffer layer 54 is made of an amorphous The first buffer layer 54 is formed of a silicon film, an amorphous silicon germanium film, or the like. The thickness is set to 10 to 100 nm, preferably 30 to 50 nm.

[0053] The first buffer layer 54 is formed by a plasma deposition method using a deposition gas containing silicon or germanium. Amorphous semiconductor films can be formed by the CVD method. The deposition gas containing germanium is selected from the group consisting of helium, argon, krypton, and neon. Alternatively, an amorphous semiconductor film can be formed by diluting the gas with one or more rare gas elements. Alternatively, the flow rate is 1 to 10 times, more preferably 1 to 5 times, the flow rate of the silane gas. The hydrogen can be used to form an amorphous semiconductor film containing hydrogen. The semiconductor film may be doped with a halogen such as fluorine, chlorine, bromine, or iodine.

[0054] The first buffer layer 54 is formed by using silicon, germanium, or the like as a target and ionizing hydrogen, Alternatively, an amorphous semiconductor film can be formed by sputtering with a rare gas.

[0055] A first buffer layer 54 is formed on a surface of the microcrystalline semiconductor film 45 containing the impurity element serving as a donor. By this method, an amorphous semiconductor film, and further an amorphous semiconductor film containing hydrogen, nitrogen, or halogen, is formed. By this, the surface of the crystal grains included in the microcrystalline semiconductor film 45 containing the impurity element serving as a donor is It is possible to prevent natural oxidation, especially in the region where the amorphous semiconductor and the microcrystalline grains come into contact. When these cracks come into contact with oxygen, the grains are oxidized, and the oxide However, the microcrystalline semiconductor film 45 containing the impurity element serving as a donor By forming the first buffer layer 54 on the surface, oxidation of the microcrystalline grains can be prevented.

[0056] After forming the microcrystalline semiconductor film 45 containing the impurity element serving as a donor, plasma CVD It is preferable to form the first buffer layer 54 at a temperature of 300° C. to 400° C. by the method. By this film formation process, hydrogen is supplied to the microcrystalline semiconductor film 45, and the microcrystalline semiconductor film 45 is heated to a temperature of 10 ... In other words, the effect is the same as that of a microcrystalline semiconductor containing impurity elements that act as donors. By depositing a first buffer layer 54 on the dielectric film 45, a layer containing an impurity element that serves as a donor is formed. Hydrogen can be diffused into the microcrystalline semiconductor film 45 to terminate the dangling bonds. do.

[0057] Next, a resist is applied onto the first buffer layer 54 and the gate insulating film 52b, and a second photoresist is formed. The resist is exposed and developed in a photolithography process using a photomask. Next, the first buffer layer 54 and the dopant are formed using the resist mask. The microcrystalline semiconductor film 45 containing the impurity element to be the core is etched to form a semiconductor film as shown in FIG. As shown in FIG. 1, the first buffer layer 62 and the microcrystalline semiconductor film 58 containing the impurity element serving as a donor are At this time, as shown in FIG. 4(A), a gate electrode 51 (gate wiring) and a The area where the source wiring intersects with the formed source wiring is also covered with a microcrystalline semiconductor containing an impurity element that acts as a donor. 1B shows the same as that of the Q-type semiconductor layer 59 in FIG. 4(A) corresponds to the cross section of ST in FIG. 5(A).

[0058] Next, as shown in FIG. 1C, a second buffer layer 62 is formed on the first buffer layer 62 and the gate insulating film 52b. The buffer layer 41 and the impurity semiconductor film 55 doped with an impurity element that imparts one conductivity type are Form.

[0059] The second buffer layer 41 can be formed in the same manner as the first buffer layer 54. The second buffer layer 41 is formed in the subsequent process of forming the source and drain regions. In some cases, the second buffer layer 41 is partially etched away, but at that time, a part of the second buffer layer 41 remains. It is preferable to form the film to a thickness of 30 nm or more and 500 nm or less. It is preferable to form the film with a thickness of 50 nm or more and 200 nm or less.

[0060] A display device that applies a high voltage (for example, about 15V) to a thin-film transistor, typically a liquid crystal display In the display device, if the first buffer layer 54 and the second buffer layer 41 are formed thick, The source-drain breakdown voltage is increased, and even if a high voltage is applied to the gate voltage of the thin film transistor, This can reduce the deterioration of the thin film transistor.

[0061] The first buffer layer 54 and the second buffer layer 41 are formed using an amorphous semiconductor film. Alternatively, since the amorphous semiconductor film containing hydrogen or halogen is used, the energy gap The gap is larger than that of the microcrystalline semiconductor film 45 containing an impurity element, and the resistivity is high. The degree of the thin film transistors formed later is as low as 1 / 5 to 1 / 10 of that of the microcrystalline semiconductor film 45. In a transistor, a source region, a drain region, and a microcrystal containing an impurity element that acts as a donor are The first buffer layer and the second buffer layer formed between the crystalline semiconductor film 45 and the The microcrystalline semiconductor film 45 containing the impurity element serving as a donor functions as a channel formation region. Therefore, the off-current of the thin film transistor can be reduced. When a thin film transistor is used as a switching element of a display device, the contrast of the display device is This can improve performance.

[0062] The impurity semiconductor film 55 to which an impurity element that imparts one conductivity type is added is an n-channel thin film. When forming a transistor, phosphorus may be added as a typical impurity element. An impurity gas such as PH3 may be added to a deposition gas containing silicon or germanium. In addition, when forming a p-channel thin film transistor, a typical impurity element is Boron can be added to deposition gas containing silicon or germanium, such as B2H6. The impurity element gas of 1×10 19 ~1×10 21 cm -3 By doing so, ohmic contact with the wirings 71a to 71c can be achieved. These regions can be made of a material that functions as a source region and a drain region. The impurity semiconductor film 55 to which the impurity element is added is a microcrystalline semiconductor film or an amorphous semiconductor film. The impurity semiconductor film can be formed by adding an impurity element that imparts one conductivity type. The layer 55 is formed to a thickness of 2 nm to 50 nm. By thinning the thickness of the impurity semiconductor film, the throughput can be improved. .

[0063] Next, a resist mask is formed on the impurity semiconductor film 55 to which an impurity element that imparts one conductivity type is added. The resist mask is formed by photolithography. Using a third photomask, an impurity semiconductor doped with an impurity element that gives one conductivity type is The resist coated on the film 55 is exposed and developed to form a resist mask.

[0064] Next, a resist mask is used to form the second buffer layer 41 and the impurity layer that imparts one conductivity type. The doped impurity semiconductor film 55 is etched and separated to form island-like regions as shown in FIG. The second buffer layer 42 and the impurity semiconductor film doped with an impurity element that imparts one conductivity type. At this time, as shown in FIG. 4(B), the gate electrode (gate wiring) and the The second buffer layer 44 and the first conductive type are also formed in the region where the source wiring intersects with the first conductive type. An impurity semiconductor film 65 is formed by adding the impurity element. 2(A) corresponds to the cross section of QR in FIG. 5(B), and FIG. 4(B) corresponds to the cross-sectional view of ST in FIG. 5(B).

[0065] The second buffer layer 42 covers the microcrystalline semiconductor film 58 containing the impurity element that serves as a donor. As a result, the microcrystalline semiconductor film 58 containing the impurity element serving as a donor is connected to a wiring to be formed later. Therefore, the wiring formed on the first buffer layer 62 and the microcrystalline semiconductor film 58 are not formed. It is possible to reduce the leakage current.

[0066] Next, as shown in FIG. 2(B), an impurity semiconductor layer is formed by adding an impurity element that gives one conductivity type. Conductive films 65a to 65c are formed on the conductive film 63 and the gate insulating film 52b. The film 65c is formed by using a sputtering method, a CVD method, a printing method, a droplet discharge method, a vapor deposition method, or the like. do.

[0067] The conductive films 65a to 65c are made of aluminum, copper, silicon, titanium, neodymium, or stainless steel. Addition of elements such as candium and molybdenum to improve heat resistance or to prevent hillocks It is preferable to form the layer by a single layer or a multilayer of aluminum alloy. The film on the side in contact with the source and drain regions 72 to which the impurity element is added is made of titanium, tantalum, or the like. It is made of titanium, molybdenum, tungsten, or nitrides of these elements, and aluminum is deposited on it. It may also be a laminated structure formed of aluminum or an aluminum alloy. The upper and lower surfaces of aluminum or aluminum alloy are covered with titanium, tantalum, molybdenum, tungsten A laminated structure in which the conductive film is sandwiched between the conductive film and the nitride of the conductive film may be used. The wiring 71a and 71c are stacked in three layers. The structure using an aluminum film for the conductive film 71b, and titanium for the wiring 71a and 71c 7 shows a structure in which an aluminum film is used for the conductive film 71b.

[0068] Next, a photolithography process is performed using a fourth photomask on the conductive film 65c. Forms a dysplasia mask.

[0069] Next, the conductive films 65a to 65c are etched using a resist mask to form the conductive films 65a to 65c shown in FIG. As shown in the figure, pairs of wirings 71a to 71c (which function as source and drain electrodes) , and the capacitance electrodes 71d to 71f are formed.

[0070] At this time, as shown in FIG. 4C, the second buffer layer 44 and the non-transfer layer for imparting one conductivity type are formed. An impurity semiconductor film 65 to which a pure element is added, a microcrystalline semiconductor containing an impurity element that serves as a donor The gate electrode 51 (gate wiring) and the wiring 71a are connected via the film 59 and the first buffer layer 64. Therefore, the gate electrode 51 (gate wiring) and the wirings 71a to 71c intersect. This can reduce the parasitic capacitance in the crossing area.

[0071] Next, a resist mask is used to form a semiconductor layer containing an impurity element that provides one conductivity type. The film 63 is etched and separated, resulting in a pair of source regions as shown in FIG. and the drain region 72. A part of the buffer layer 42 of the second substrate is also etched. The second buffer layer is referred to as a second buffer layer 43. The step of forming the recess in the second buffer layer and the step of forming the recess in the second buffer layer can be performed in the same step. The depth of the recess of the second buffer layer 43 is set to 1 / 2 to 1 / 3 of the thickness of the thickest region of the second buffer layer 43. By doing so, it is possible to separate the source region and the drain region. The leakage current between the gate and drain regions can be reduced. Remove.

[0072] Next, the exposed second buffer layer 43 is subjected to a thermal treatment without being damaged and the second buffer layer Dry etching may be performed under conditions where the etching rate for 43 is low. This removes etching residues on the second buffer layer 43 between the source and drain regions, and resist. Resist mask residue and contamination sources in the equipment used to remove the resist mask must be removed. This makes it possible to ensure the insulation between the source and drain regions. As a result, it is possible to reduce the leakage current of the thin film transistor, and the off-current is small. This makes it possible to fabricate thin film transistors with high breakdown voltage. For example, chlorine gas may be used.

[0073] Through the above steps, a channel-etch type thin film transistor 74 can be formed.

[0074] 2(C) corresponds to a cross-sectional view of QR in FIG. 5(C), and FIG. 4(C) corresponds to a cross-sectional view of QR in FIG. 5(C). As shown in FIG. 5C, the source and drain regions 72 It can be seen that the end of the wiring 71c is located outside the end of the wiring 71c. The microcrystalline semiconductor film, the first buffer layer 64, the second buffer layer 44, and the layer imparting one conductivity type are then stacked. Since the wiring is overlapped with the impurity semiconductor film 65 to which the impurity element is added, The influence of unevenness on the port electrode is small, and the coverage rate and leakage current can be reduced.

[0075] Next, as shown in FIG. 3A, the wirings 71a to 71c, the source region and the drain region 72 A protective insulating film 76 is formed on the second buffer layer 43 and the gate insulating film 52b. The insulating film 76 can be formed in the same manner as the gate insulating films 52a and 52b. The insulating film 76 prevents the intrusion of polluting impurities such as organic matter, metal matter, and water vapor floating in the air. In addition, the use of a silicon nitride film for the protective insulating film 76 As a result, the oxygen concentration in the second buffer layer 43 is set to 5×10 19 atoms / cm 3 Below, I prefer Or 1 x 10 19 atoms / cm 3 The second buffer layer 43 may be Oxidation can be prevented.

[0076] Next, an insulating film 101 is formed on the protective insulating film 76. Here, a photosensitive organic resin is used. Then, the insulating film 101 is exposed to light using a fifth photomask. After that, development is performed to form the insulating film 102 that exposes the protective insulating film 76. 2 to etch the protective insulating film 76, and as shown in FIG. 3(B), one of the wirings 71c is a contact hole 111 exposing the capacitor electrode 71f; Form 12.

[0077] Next, as shown in FIG. 3(C), the wiring 71c and the capacitor are inserted into the contact holes 111 and 112. A pixel electrode 77 is formed in contact with the capacitor electrode 71f. The capacitance electrodes 71d to 71f and the pixel electrode 77 can form a capacitance element 106. In this example, after forming a conductive film on the insulating film 102, a photolithography process is performed using a sixth photomask. The conductive film is etched using a resist mask formed by a lithography process, and the pixel electrodes are formed. forming pole 77.

[0078] The pixel electrode 77 is made of indium oxide containing tungsten oxide, indium oxide containing tungsten oxide, Indium zinc oxide, indium oxide with titanium oxide, indium with titanium oxide Tin oxide, indium tin oxide, indium zinc oxide, indium doped with silicon oxide A light-transmitting conductive material such as tin oxide can be used.

[0079] The pixel electrode 77 is made of a conductive composition containing a conductive macromolecule (also called a conductive polymer). The pixel electrode formed using the conductive composition can be formed using a sheet resistor. It is preferable that the resistance is 10000Ω / □ or less and the light transmittance at a wavelength of 550 nm is 70% or more. It is also preferable that the resistivity of the conductive polymer contained in the conductive composition is 0.1 Ω cm or less. It is preferable that

[0080] As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0081] Here, the pixel electrode 77 is formed by forming an ITO film by sputtering. Then, a resist is applied on the substrate. Then, the resist is exposed and developed using a sixth photomask. Then, a resist mask is formed. Then, the ITO is etched using the resist mask to form a pattern. The element electrodes 77 are formed.

[0082] In this manner, a thin film transistor can be formed. A device substrate that can be formed can be formed.

[0083] The channel formation region of the thin film transistor manufactured in this embodiment mode is formed using a microcrystalline semiconductor film. Therefore, it is possible to increase the driving frequency of the display device, and the panel size can be increased. It can also be used to increase the area and the density of pixels. The thin film transistor can be fabricated.

[0084] In addition, a buffer layer is provided between the microcrystalline semiconductor film containing the impurity element serving as a donor and the wiring. Therefore, leakage between the microcrystalline semiconductor film containing the impurity element that serves as a donor and the wiring The current can be reduced. In addition, the source and drain regions and impurities that act as donors can be A buffer layer formed of an amorphous semiconductor film is provided between the microcrystalline semiconductor films containing an organic element. Therefore, the buffer layer becomes a high resistance region, and the leakage current can be reduced. Therefore, a thin film transistor having excellent electrical characteristics and high reliability can be manufactured.

[0085] In this embodiment mode, a channel-etched thin film transistor is used. This embodiment can be applied to a panel-protected thin film transistor.

[0086] (Embodiment 2) In this embodiment, the number of photomasks can be reduced compared to the first embodiment. The process for manufacturing a thin film transistor will be described.

[0087] As in the first embodiment, as shown in FIG. 6(A), a conductive film is formed on a substrate 50. A resist is applied on top and formed by a photolithography process using a first photomask. The conductive film is partially etched using the resist mask to form the gate electrode 51 and the capacitor wiring Next, on the gate electrode 51, gate insulating films 52a and 52b are formed. Next, a photolithography process using a second photomask is performed on the gate insulating film 52b. The microcrystalline semiconductor film 58 containing the impurity element serving as a donor and the first buffer layer 62 are formed using the Next, a second buffer layer 41, which is a one-conductivity type buffer layer, is formed on the first buffer layer 62. The impurity semiconductor film 55 to which the impurity element is added and the conductive films 65a to 65c are formed in this order. Next, a resist is applied onto the conductive film 65a.

[0088] The resist may be a positive resist or a negative resist. This is shown using a di-type resist.

[0089] Next, a multi-tone mask is used as a third photomask to irradiate the resist with light. The resist is exposed to light to form a resist mask 81.

[0090] Here, exposure using a multi-tone mask will be described with reference to FIG.

[0091] A multi-tone mask has three exposure levels: exposed, intermediately exposed, and unexposed. This mask can produce multiple (typically two types) Therefore, it is possible to form a resist mask having a region of thickness of 1000 nm. By using a photomask, it is possible to reduce the number of photomasks.

[0092] Typical examples of multi-tone masks include a gray-tone mask 159a as shown in FIG. 7(A), There is a half-tone mask 159b as shown in FIG. 7(C).

[0093] As shown in FIG. 7(A), the gray-tone mask 159a is formed on a light-transmitting substrate 163 and The light-shielding portion 164 and the diffraction grating 165 are formed on the light-shielding portion 164. On the other hand, the diffraction grating 165 has slits, dots, meshes, etc. By setting the spacing between the light transmitting portions of the light source, such as the lens, to be equal to or less than the resolution limit of the light used for exposure, The diffraction grating 165 can control the light transmittance of the slits and dots. , mesh, or non-periodic slits, dots, mesh can be used. .

[0094] The light-transmitting substrate 163 can be a light-transmitting substrate such as quartz. The portion 164 and the diffraction grating 165 are made of a light-shielding material that absorbs light, such as chromium or chromium oxide. It can be formed.

[0095] When the gray-tone mask 159a is irradiated with exposure light, as shown in FIG. 7(B), the light-shielding portion In 164, the light transmittance 166 is 0%, and the light blocking portion 164 and the diffraction grating 165 are provided. In the unobstructed area, the light transmittance 166 is 100%. The light transmittance 166 of the diffraction grating 165 can be adjusted in the range of 10 to 70%. The adjustment can be achieved by adjusting the spacing and pitch of the slits, dots, or mesh of the diffraction grating. It is Noh.

[0096] As shown in FIG. 7(C), the half-tone mask 159b is formed on a light-transmitting substrate 163 and The semi-transmitting portion 167 and the light-shielding portion 168 are formed on the semi-transmitting portion 167. MoSiN, MoSi, MoSiO, MoSiON, CrSi, etc. can be used. The light-shielding portion 168 is formed using a light-shielding material that absorbs light, such as chromium or chromium oxide. It is possible.

[0097] When the halftone mask 159b is irradiated with exposure light, as shown in FIG. 7(D), the light-shielding portion In 168, the light transmittance 169 is 0%, and the light blocking portion 168 and the semi-transmitting portion 167 are provided. In the unshaded area, the light transmittance 169 is 100%. The light transmittance 169 of the semi-transparent portion 167 can be adjusted in the range of 10 to 70%. The adjustment can be made by adjusting the material of the semi-transparent portion 167 .

[0098] By exposing using a multi-tone mask and then developing, different film thicknesses are obtained as shown in Figure 6(A). A resist mask 81 having the following regions can be formed.

[0099] Next, a resist mask 81 is used to cover the second buffer layer 41 and the impurity source for imparting one conductivity type. The impurity semiconductor film 55 to which oxygen is added and the conductive films 65a to 65c are etched and separated. As a result, as shown in FIG. 6(B), the second buffer layer 42 and the impurity imparting one conductivity type are formed. The impurity semiconductor film 63 to which an impurity element is added and the conductive films 85a to 85c can be formed. 6A (excluding the resist mask 81) is the same as that of the UV light of FIG. This corresponds to a cross-sectional view.

[0100] Next, the resist mask 81 is ashed. As a result, the area of ​​the resist is reduced and the thickness is At this time, the resist in the thin film region (the region overlapping with a part of the gate electrode 51) The resist mask 86 is then removed to form a separate resist mask 86, as shown in FIG. 6(C). This can be done.

[0101] Next, the conductive films 85a to 85c are etched and separated using the resist mask 86. As a result, pairs of wirings 92a to 92c can be formed as shown in FIG. 8(A). When the conductive films 89a to 89c are wet-etched using the resist mask 86, As a result, the resist mask 86 is removed. Narrow wirings 92a to 92c can be formed.

[0102] Next, as shown in FIG. 8(B), a resist mask 86 is used to remove impurities that impart one conductivity type. The impurity semiconductor film 63 to which the impurity element is added is etched to form a pair of source and drain regions. In this etching step, a portion of the second buffer layer 42 is The partially etched second buffer layer is then removed as second buffer layer 87. The second buffer layer 87 has a recess formed therein. The formation of the region and the recessed portion of the second buffer layer can be performed in the same process. In other words, a part of the second buffer layer 87 is a resist having a reduced area compared to the resist mask 81. Since the mask 86 is partially etched, the source and drain regions 88 are not exposed. The second buffer layer 87 has a protruding shape. The ends of the source and drain regions 88 are not aligned but are shifted. The outer edges of the source and drain regions 88 are then formed. 86 is removed. Note that FIG. 8B corresponds to the UV cross section of FIG. 9B.

[0103] Next, the exposed buffer layer is etched without being damaged. Dry etching may be performed under low grit conditions. Etching residues on the buffer layer between the drain regions, resist mask residues, and resist It is possible to remove the contamination source in the equipment used to remove the mask, and the source and drain regions As a result, the insulating layer between the lead regions of the thin film transistor can be reliably formed. It is possible to reduce the off-state current, and to create a thin film transistor with a small off-state current and high breakdown voltage. It is possible to fabricate the semiconductor device using a chlorine gas as the etching gas.

[0104] Through the above steps, a channel-etch type thin film transistor 83 can be formed. In addition, a thin film transistor can be formed using two photomasks.

[0105] After that, the same steps as in the first embodiment are carried out, and as shown in FIG. 8(C), the wirings 92a to 92b are formed. c, the source and drain regions 88, the second buffer layer 87, and the gate insulating film 52b A protective insulating film and an insulating film are formed on top, and a photolithography process is performed using a fourth photomask. In this case, the protective insulating film is formed as a protective insulating film 76a. This indicates:

[0106] At this time, the gate insulating film 52b and the protective insulating film 76a are formed of films with different etching selectivity. For example, the gate insulating film 52b is formed of a silicon oxynitride film, and the protective insulating film 76a is formed of a silicon nitride film. The protective insulating film 76a is formed of a base film. The etching for forming the contact hole on the capacitance wiring 56 is stopped at the gate insulating film 52b. Therefore, the capacitance element is formed by the capacitance wiring 56, the gate insulating films 52a and 52b, and and pixel electrode 77.

[0107] In addition, the gate insulating film 52b and the protective insulating film 76a are formed of the same material. a and the gate insulating film 52b are formed with films having different etching selectivity (for example, the gate insulating film The film 52b and the protective insulating film 76a are formed of a silicon nitride film, and the gate insulating film 52a is formed of a silicon oxynitride film. The protective insulating film 76a and the gate insulating film 52b are selectively etched. By using the conditions for forming the contact hole on the capacitance wiring 56, the etching for forming the contact hole on the capacitance wiring 56 can be performed under the conditions for forming the gate electrode. Therefore, the capacitance element can be formed by the capacitance wiring 56, the gate insulating film 52a, and the like. The capacitance element can be formed of two conductive layers. The insulating film (here, the gate insulating film) between the film (here, the capacitance wiring 56 and the pixel electrode 77) The thinner the film thickness of 52a), the higher the capacity that can be carried, which is preferable.

[0108] Next, a pattern is formed on the insulating film 102 by a photolithography process using a fifth photomask. The element electrode 77 can be formed. Note that FIG. 8(C) is a cross-sectional view of the UV of FIG. 9(C). is equivalent to

[0109] In this manner, a thin film transistor can be manufactured. A device substrate that can be formed can be formed.

[0110] The above process makes it possible to reduce the number of photomasks by one compared to the first embodiment. By the above process, an element substrate having a thin film transistor and usable for a display device is formed. It is possible.

[0111] (Embodiment 3) In this embodiment, a thin film transistor different from those in Embodiments 1 and 2 will be described. The following are examples:

[0112] FIG. 10 shows an impurity serving as a donor in the thin film transistors shown in the first and second embodiments. Instead of the microcrystalline semiconductor film containing the element, an impurity element serving as a donor is formed on the gate insulating film 52b. The crystal grains 60 containing the impurity element as a donor and the gate insulating A thin film transistor having a semiconductor film 61 containing germanium as a main component covering the film 52b. The shape of the semiconductor film 61 is also shown. The germanium layer 43 is formed. Since the semiconductor film 61 having germanium as the main component has a higher mobility, the carriers are transported to the semiconductor film 61 having germanium as the main component. Therefore, the gate insulating film 52b is formed on the semiconductor film 61. The semiconductor film 61 mainly composed of ruthenium is used as a channel forming region of a thin film transistor. It works.

[0113] The buffer layer 43 covers the top and side surfaces of the semiconductor film 61 containing germanium as the main component. Therefore, the semiconductor film 61 containing germanium as a main component does not come into contact with the wirings 71a to 71c. Therefore, the on-state current and field effect mobility are high, and the on-state current is high. This results in a thin film transistor with low off-state current.

[0114] The crystal grains 60 containing the impurity element that serves as a donor are formed in the gate insulating film 52 in the same manner as in the first embodiment. A microcrystalline semiconductor film or an amorphous semiconductor film containing an impurity element that serves as a donor is formed on b. Next, a plasma is applied to the microcrystalline semiconductor film or the amorphous semiconductor film containing the impurity element that serves as a donor. The crystal grains 60 are formed by exposing the material to the plasma. The plasma may be any of hydrogen, fluorine, and fluoride. One or more of these are introduced into the reaction chamber of the plasma CVD device, and a high frequency power source is applied to generate plasma. To generate.

[0115] At least one of fluorine, fluoride gas, and hydrogen is introduced and a high frequency power source is applied. Hydrogen plasma and fluorine plasma are generated by introducing hydrogen into the reaction chamber. Fluorine plasma is generated by introducing fluorine or fluoride into the reaction chamber. The fluorides are HF, SiF4, SiHF3, and S. iH2F2, SiH3F, Si2F6, GeF4, GeHF3, GeH2F2, GeH3 F, Ge2F6, etc. In addition to fluorine, fluoride gas, or hydrogen, rare gases can also be used in the reaction. It may be introduced into the reaction chamber to generate a rare gas plasma.

[0116] Hydrogen plasma, fluorine plasma, etc. generate hydrogen radicals, fluorine radicals, etc. in the plasma. The hydrogen radicals are generated in the microcrystalline semiconductor film or the amorphous semiconductor film containing the impurity element serving as a donor. The amorphous component of the semiconductor film is reacted with the amorphous component of the semiconductor film, crystallizing a part of the semiconductor film and forming the amorphous component. The fluorine radicals also etch away the microcrystalline semiconductor containing the impurity element that acts as a donor. The amorphous components of the conductive film or amorphous semiconductor film are etched. The crystal grains can be left. Also, the impurity element acting as a donor can be formed on the gate insulating film 52b. When an amorphous semiconductor film containing Therefore, the interface with the gate insulating film can be crystallized to form crystal grains. Since the amorphous components are also etched by the plasma, crystalline grains are formed on the gate insulating film. It is possible.

[0117] The plasma generation method is in the HF band (3MHz to 30MHz, typically 13.56MHz, 27.12MHz), or the high frequency band of VHF, from 30MHz to about 300MHz This is done by applying a frequency power, typically 60 MHz. GHz or 2.45GHz high frequency plasma can be used. By using high frequency power of 60Hz, it is possible to improve the uniformity of the plasma. Even on large-area substrates from the 19th to 10th generation, highly uniform plasma is exposed to germanium films. This is preferable for mass production.

[0118] Next, a semiconductor film 61 containing germanium as a main component is formed on the crystal grains 60. The adhesion of the semiconductor film 61 containing silicon as a main component can be improved. 0 as a crystal nucleus, and a semiconductor film 61 containing germanium as a main component is formed. A crystalline germanium film can be formed.

[0119] When the semiconductor film 61 containing germanium as a main component is formed by the CVD method, germanium Hydrogen is introduced into the reaction chamber of the plasma CVD apparatus together with a deposition gas containing hydrogen, and high frequency power is applied. A semiconductor film 61 containing germanium as a main component is formed by applying a plasma. Forming a germanium film or a microcrystalline germanium film. By using a deposition gas containing silicon along with hydrogen, amorphous silicon germanium can be obtained. A silicon germanium film or a microcrystalline silicon germanium film is formed.

[0120] An amorphous germanium film is formed as the semiconductor film 61 containing germanium as the main component. In one embodiment, a glow discharge plasma is used in a reaction chamber using a deposition gas containing germanium. Amorphous germanium films can be formed by sintering. The deposition gas is one or more selected from helium, argon, krypton, and neon. and forming an amorphous germanium film by glow discharge plasma. Alternatively, the flow rate of the deposition gas containing germanium can be set to 1 to 10 times, or more. Preferably, the amorphous gate is formed by glow discharge plasma using hydrogen at a flow rate of 1 to 5 times. Furthermore, a germanium film can be formed by using a deposition gas containing germanium, hydrogen, or the like. At the same time, by using a deposition gas containing silicon, it is possible to form a semiconductor containing germanium as the main component. The film 61 can be an amorphous silicon germanium film.

[0121] Further, a microcrystalline germanium film is formed as the semiconductor film 61 containing germanium as the main component. In one embodiment, a deposition gas containing germanium, here germanium, is introduced into the reaction chamber. The germanium is mixed with hydrogen and / or rare gases, and the mixture is heated by glow discharge plasma to form microcrystalline germanium. Germane is diluted 10 to 2000 times with hydrogen and / or rare gases to form a germane film. Therefore, a large amount of hydrogen and / or rare gas is required. The substrate heating temperature is 100°C to 4 The deposition temperature is 0°C, preferably 250°C to 350°C. By using a deposition gas containing silicon along with silicon and hydrogen, a germanium-based The semiconductor film 61 is made of microcrystalline silicon germanium (Si y Ge 1-y , 0 <y<0.5 ) film can be formed.

[0122] Generation of glow discharge plasma in the process of forming semiconductor film 61 mainly composed of germanium High frequency bands from 3MHz to 30MHz, typically 13.56MHz and 27.12MHz Power, or high frequency power in the VHF band greater than 30MHz up to about 300MHz, representative Typically, this is done by applying 60 MHz.

[0123] The microcrystalline semiconductor film 45 containing the impurity element which serves as a donor and the first buffer layer shown in Embodiment 1 Instead of the layer 54, the layer 54 is made of a material mainly composed of crystal grains containing the impurity element as the donor and germanium. After forming the semiconductor film as a component, the same process as in the first embodiment is carried out to form the semiconductor film as shown in FIG. In addition, a thin film transistor can be manufactured by the same process as in Embodiment 2. A film transistor can be formed.

[0124] 11 shows a different embodiment from the first embodiment. As in the first embodiment, the gate insulating film After forming a microcrystalline semiconductor film 45 containing an impurity element serving as a donor on 52, germanium Next, a second photomask is used in the same manner as in the first embodiment. The resist mask formed by the photolithography process is used to form the donor impurity. The microcrystalline semiconductor film 45 containing a pure element and the semiconductor film containing germanium as a main component are etched. The microcrystalline semiconductor film 69 containing an impurity element serving as a donor and the Next, a semiconductor film 61 is formed by the same process as in the first embodiment. In this way, a microcrystalline semiconductor film 69 containing an impurity element serving as a donor is formed on the gate insulating film 52b. A semiconductor film 61 containing germanium as a main component is formed thereon, and an impurity layer serving as a donor is formed. Side surfaces of the microcrystalline semiconductor film 69 containing pure elements and the semiconductor film 61 containing germanium as the main component A thin film transistor having a buffer layer 73 covering the A thin film transistor can be formed by the same process as in the second embodiment.

[0125] The semiconductor film 61 mainly made of germanium is a microcrystalline semiconductor mainly made of silicon. Since the insulating film 69 is in contact with the insulating film 69, the adhesion between them is improved. It is possible to increase the density.

[0126] In addition, the microcrystalline semiconductor film 69 containing the impurity element serving as a donor has microcrystals formed on the film surface. Therefore, the surface of the microcrystalline semiconductor film 69 containing the impurity element serving as a donor has high crystallinity. When a semiconductor film 61 containing germanium as a main component is formed on this, a silicon-based semiconductor film 62 containing germanium as a main component is formed. Since the crystals grow using the crystals on the surface of the microcrystalline semiconductor film 69 as crystal nuclei, the crystals have high crystallinity. A semiconductor film 61 mainly composed of germanium, typically a fine crystal Since the semiconductor film 61 containing germanium as the main component has low resistivity, Carriers preferentially flow through the semiconductor film 61 containing germanium as the main component. The thin film transistor described in this embodiment has high field-effect mobility and high on-state current.

[0127] The buffer layer 73 covers the top and side surfaces of the semiconductor film 61 containing germanium as a main component. Therefore, the semiconductor film 61 containing germanium as a main component does not come into contact with the wirings 71a to 71c. Therefore, the occurrence of leakage current can be suppressed. Therefore, a thin film transistor having high conductivity and low off-state current can be manufactured.

[0128] (Fourth embodiment) In this embodiment mode, the structure of the thin film transistor shown in the above embodiment mode will be described below. .

[0129] FIG. 12(A) shows the top view of a thin film transistor in which the source electrode and the drain electrode are parallel. FIG. 12(B) shows a cross-sectional view of EF in FIG. 12(A).

[0130] FIG. 12B shows a gate electrode 51 and a gate insulating film formed on a substrate 50. A microcrystalline semiconductor film 58 containing an impurity element serving as a donor and a first buffer layer 62 are provided inside the In addition, the microcrystalline semiconductor film 58 containing the impurity element serving as a donor and the first buffer A second buffer layer 43 is formed to cover the silicon layer 62. The source region 72S and the drain region 72D facing each other, the source electrode 71S and the drain electrode 71D is formed.

[0131] In FIG. 12B, an overlapping region 441 of the gate electrode 51 and the drain region 72D, The microcrystalline semiconductor film 58 containing the impurity element serving as a donor and the overlapping region 4 of the drain region 72D 42. In addition, overlapping areas 441 and 442 also overlap.

[0132] The thin film transistor shown in FIGS. 12(A) and 12(B), the gate electrode 51 and the drain region 72 D, and the microcrystalline semiconductor film 58 containing the impurity element serving as a donor and the drain region 72D Because of the overlapping, the thin film transistor has a high on-current and a high field effect mobility. can be done.

[0133] FIG. 12(C) shows the top structure of the thin film transistor, and FIG. 12(D) shows the top structure of FIG. 12(C). A cross-sectional view of EF is shown.

[0134] FIG. 12C shows a gate electrode 51 and a gate insulating film formed on a substrate 50. The microcrystalline semiconductor film 58 containing the impurity element serving as a donor and the first buffer layer 56 are formed so as to cover the end portions of the first buffer layer 56 and the second buffer layer 58. A microcrystalline semiconductor film 58 containing an impurity element serving as a donor and a A second buffer layer 43 is formed to cover the first buffer layer 62. 43, a source region 72S and a drain region 72D, and a source electrode 71S and a drain electrode 71D are provided. A rain electrode 71D is formed.

[0135] In FIG. 12(D), the edge of the gate electrode 51 and the edge of the drain electrode 71D are aligned. , an overlapping region of the microcrystalline semiconductor film 58 containing the impurity element serving as a donor and the drain region 72D It has 444.

[0136] In FIG. 12B, the edge of the gate electrode 51 and the edge of the drain electrode 71D are aligned. On the other hand, the microcrystalline semiconductor film 58 containing the impurity element serving as a donor and the drain region 72 D overlapping region 444.

[0137] The thin film transistors shown in FIGS. 12(C) and 12(D) have a gate electrode 51 and a drain region 7 Since the 2D is not overlapped, the parasitic capacitance can be reduced. Therefore, the thin film transistor using this structure can reduce the voltage drop on the side. In particular, the pixel response speed of a liquid crystal display device can be improved. In the case of thin film transistors formed in the liquid crystal, the voltage drop of the drain voltage can be reduced. It is possible to increase the response speed of the material.

[0138] In FIG. 13(A), the opposing regions of the source electrode and the drain electrode are curved. The top view structure of a thin film transistor when the gate or drain electrode is C-shaped or U-shaped is shown in Fig. 13. (B) shows a cross-sectional view of GH in FIG. 13(A), and FIG. 13(C) shows a cross-sectional view of EF in FIG. 13(A). A cross-sectional view of the above is shown.

[0139] 13B and 13C show a structure in which a gate electrode 51 and a gate insulating film are formed on a substrate 50. The microcrystalline semiconductor film 58 containing the impurity element serving as a donor and the first A buffer layer 62 is formed. In addition, the microcrystalline semiconductor film 58 containing the impurity element serving as a donor A second buffer layer 43 is formed to cover the first buffer layer 62. The source and drain regions 72 and the source electrode 71S and the drain electrode 71C are disposed on the photoresist layer 43. An inner electrode 71D is formed.

[0140] 13B and 13C, the gate electrode 51 and the drain region 72D overlap. The impurity element serving as a donor is included in the microcrystalline semiconductor film 58 and the drain region 7. The overlapping areas 449 and 450 are also overlapping. One of the wirings is shaped to surround the other of the source and drain regions (specifically, U-shaped or C-shaped). Therefore, it is possible to increase the area of ​​the region where carriers move. Therefore, it is possible to increase the amount of current and reduce the area of ​​the thin film transistor. .

[0141] (Embodiment 5) In this embodiment, in an element substrate 1300 shown in FIG. 14, a pixel portion 1331 and an input terminal Configuration and fabrication of the protection circuits 1334 and 1336 formed between 1332 and 1333 The protection circuit shown in this embodiment is a diode with a Schottky junction. It is formed using an oxide.

[0142] An input terminal 1332 on the scanning line side and an input terminal 1333 on the signal line side formed on a substrate 1330 3 and the pixel section 1331 are connected by wiring extending vertically and horizontally, and the wiring is a protection circuit Connected to 1334~1337.

[0143] The pixel section 1331 and the input terminal 1332 are connected by a wiring 1339. The wiring 1334 is disposed between the pixel section 1331 and the input terminal 1332 and is connected to the wiring 1339. The protection circuit 1334 protects the thin film transistor of the pixel portion 1331. It is possible to protect various semiconductor elements such as those mentioned above and to prevent them from being deteriorated or destroyed. Although the line 1339 indicates one wiring in the figure, it is provided in parallel with the wiring 1339. All of the multiple wirings have the same connection relationship as the wiring 1339. functions as a scanning line (gate wiring).

[0144] The protection circuit 1334 on the scanning line side is provided between the input terminal 1332 and the pixel section 1331. In addition to the protection circuit 1334, the pixel section 1331 is sandwiched between the input terminal 1332 and the It may also be provided on the opposite side (see the protection circuit 1335 in FIG. 14).

[0145] The pixel portion 1331 and the input terminal 1333 are connected by a wiring 1338 . The protection circuit 1336 is disposed between the pixel section 1331 and the input terminal 1333. The protection circuit 1336 protects the thin film transistors of the pixel section 1331. It is possible to protect various semiconductor elements such as resistors and prevent deterioration or destruction. Although 1338 indicates one wiring in the figure, it is provided in parallel with the wiring 1338. All of the multiple wirings have the same connection relationship as the wiring 1338. , which functions as a signal line (source wiring).

[0146] The signal line side protection circuit 1336 is provided between the input terminal 1333 and the pixel portion 1331. In addition to the protection circuit 1336, the pixel section 1331 is sandwiched between the input terminal 1333 and the It may also be provided on the opposite side (see the protection circuit 1337 in FIG. 14).

[0147] It is not necessary to provide all of the protection circuits 1334 to 1337, but at least the protection circuit 13 34 is necessary. When an excessive current is generated in the wiring 1339, which is the scanning line, The gate insulating film of the thin film transistor in the portion 1331 may be destroyed, causing point defects. is.

[0148] Furthermore, by providing not only the protection circuit 1334 but also the protection circuit 1336, the wiring which is the signal line Therefore, the protection circuit 133 can prevent an excessive current from being generated in the protection circuit 133. The reliability and yield are improved compared to when only the protection circuit 133 is provided. By having 6, it is possible to prevent static electricity from being generated during the rubbing process after forming the thin film transistor. It can also prevent destruction.

[0149] Furthermore, the protection circuits 1335 and 1337 are provided to further improve reliability. The protection circuit 1335 and the protection circuit 1337 are Since the terminal 1332 and the input terminal 1333 are provided on the opposite side, they are This contributes to preventing deterioration or destruction of various semiconductor elements that occurs during the manufacturing process.

[0150] Next, specific circuits of the protection circuits used for the protection circuits 1334 to 1337 in FIG. An example of the configuration is described below.

[0151] The protection circuit shown in Fig. 15 has a plurality of diodes. 1c (the wiring 1338, which is the signal line shown in FIG. 14) 2. Here, a cross-sectional view of IJ in FIG. 15 is shown in FIG. 16(A), and A cross-sectional view is shown in FIG.

[0152] As shown in FIG. 16A, the signal lines 271a to 271c of the diode 311 are formed by the conductive film 2 01 and is connected to the gate electrode 251 and the source or drain region 26 The second buffer layer 242a of the diode 311 is in contact with the conductive film 202. Here, the common line 256 is connected to the common line 256 via the conductive film 202. The second buffer layer is formed of an amorphous semiconductor film to which no impurity element serving as a donor is added. It contacts the Fab layer 242a, forming a Schottky junction.

[0153] 16B, the gate electrode of the diode 312 is connected to the common line 256. The common line 256 is connected to the second buffer of the diode 312 via the conductive film 203. The signal lines 271a to 271c of the diode 312 are connected to the source layer 242b. The common line 256 contacts the source region or the drain region 263b. 3, the first formed by an amorphous semiconductor film to which no impurity element serving as a donor is added. 2 buffer layer 242a, forming a Schottky junction.

[0154] When a positive voltage with a large absolute value is applied from the input terminals of the signal lines 271a to 271c, the voltage shown in FIG. A positive voltage is applied to the gate electrode 251 of the diode 311 and the signal lines 271a to 271c of FIG. 6(A). When pressure is applied, carriers are generated in the microcrystalline semiconductor film 258a containing the impurity element serving as a donor. A current flows through the common line 256. In addition, absolute current is supplied from the input terminals of the signal lines 271a to 271c. When a large negative voltage is applied, the signal line 271a of the diode 312 in FIG. A negative voltage is applied to the gate electrodes and the signal lines 271a to 271c, and a threshold voltage is applied to the gate electrodes and the signal lines 271a to 271c. Since a potential difference greater than the voltage occurs, the microcrystalline semiconductor film 258b containing the impurity element serving as a donor Carriers are generated and a current flows through the common line 256. For this reason, a thin film provided in the pixel portion Electrostatic breakdown of the transistor can be prevented.

[0155] Next, a manufacturing process of the diode 311 shown in FIG. 16(A) will be described with reference to FIG. 17. Here, the method for manufacturing the diode 311 will be described using the first embodiment. 2 can be used as appropriate.

[0156] By the same process as in the first embodiment, a gate electrode is formed on a substrate 50 as shown in FIG. 17(A). Next, a gate electrode 251 and a common line 256 are formed on the gate electrode 251 and the common line 256. Port insulating films 52a and 52b are formed.

[0157] Next, in the same manner as in the first embodiment, a fine particle containing an impurity element that becomes a donor is formed on the gate insulating film 52b. A crystalline semiconductor film 258a and a first buffer layer 262a are formed.

[0158] Next, similarly to the first embodiment, a second insulating film 52b is formed on the first buffer layer 262a and the gate insulating film 52b. A second buffer layer 242a is formed.

[0159] Next, in the same manner as in the first embodiment, the source or drain region 263a and the signal line 271a In this case, the second barriers that are not covered by the signal lines 271a to 271c are formed. The thickness of the buffer layer 242a is partially reduced.

[0160] Next, similarly to the first embodiment, the protective insulating film 76 and the insulating film 101 are formed.

[0161] Next, as shown in FIG. 17(B), a contact hole 21 exposing the gate insulating film 52b is formed. 1, 214, the contact hole 212 exposing the signal line 271c, the second buffer layer 24 A contact hole 213 is formed to expose 2a.

[0162] Next, as shown in FIG. 17(C), the gate insulating films 52a and 52b are selectively etched. The gate insulating films 52a and 52b are etched under the conditions described above to form the gate electrode 251 and Contact holes 215 and 216 are formed to expose the common line 256 .

[0163] Next, as shown in FIG. 17(D), the pixel electrode 77 is formed, and at the same time, the gate electrode 251 is formed. and the conductive film 201 connecting the signal line 271c, the second buffer layer 242a and the common A conductive film 202 that connects the wiring 256 is formed.

[0164] The diode 311 can be formed by the above steps. The protection circuit can be formed using the same number of masks as the thin film transistor shown in Embodiment 3. can.

[0165] (Sixth embodiment) In this embodiment mode, a structure and a manufacturing method of a protection circuit different from those in Embodiment Mode 5 will be described below. In this embodiment, a microcrystalline semiconductor film containing an impurity element serving as a donor, a first buffer A Schottky diode is used between the first buffer layer and the common line. This is shown.

[0166] Here, a cross-sectional view of IJ in FIG. 15 is shown in FIG. 18(A), and a cross-sectional view of KL in FIG. 15 is shown in FIG. 8(B).

[0167] As shown in FIG. 18A, the signal lines 271a to 271c of the diode 313 are formed by the conductive film 2 01 and is connected to the gate electrode 251 and the source or drain region 26 3a. A microcrystalline semiconductor film containing an impurity element serving as a donor of the diode 313 is in contact with the microcrystalline semiconductor film 314. 258a, the first buffer layer 262a, and the second buffer layer 242a are formed on the conductive film 222. Here, the common line 256 is connected to the common line 256 via the conductive film 222. The first barrier layer is formed of an amorphous semiconductor film to which no impurity element serving as a donor is added. The first buffer layer 262a and the second buffer layer 242a, and the impurity source which becomes a low concentration donor Since the silicon dioxide is in contact with the microcrystalline semiconductor film 258a containing silicon dioxide, a Schottky junction is formed.

[0168] 18(B), the gate electrode of the diode 314 is connected to the common line 256. The common line 256 is connected to the diode 314 via the conductive film 221 as a donor. The microcrystalline semiconductor film 258b containing the impurity element, the first buffer layer 262b, and the second buffer layer The signal lines 271a to 271c of the diode 314 are connected to the buffer layer 242b. , contacts the source region or drain region 263b. Here, the common line 256 is a conductive The amorphous semiconductor film 221 is formed by adding no impurity element to be a donor. The first buffer layer 262b and the second buffer layer 242b are formed by the addition of a low concentration of donors. Since the microcrystalline semiconductor film 258b containing the impurity element is in contact with the microcrystalline semiconductor film 258b, a Schottky junction is formed. do.

[0169] In the case of the protective circuit provided for the wiring 1339 that is the scan line shown in FIG. 15, The signal lines 271a to 271c in FIG. 18 function as common lines, and the common line 256 in FIG. 18 functions as a scanning line. It functions as:

[0170] When a positive high voltage is applied to the input terminals of the signal lines 271a to 271c, the diodes shown in FIG. A positive voltage is applied to the gate electrode 251 of the diode 313 and the signal lines 271a to 271c. Carriers are generated in the microcrystalline semiconductor film 258a containing the impurity element serving as a donor, and the common line 2 A current flows through the input terminals of the signal lines 271a to 271c. When the voltage is applied, the signal lines 271a to 271c of the diode 314 in FIG. 18(B) A negative voltage is applied, and a potential equal to or higher than the threshold voltage is applied to the gate electrodes and the signal lines 271a to 271c. Because of this difference, carriers are generated in the microcrystalline semiconductor film 258b containing the impurity element serving as a donor. This generates a current flowing through the common line 256. This can prevent electrostatic damage.

[0171] Next, a manufacturing process of the diode 313 shown in FIG. 18(A) will be described with reference to FIG. 19. Here, a method for manufacturing the diode 313 will be described using the first embodiment. 2 can be used as appropriate.

[0172] As in the fifth embodiment, as shown in FIG. 19(A), a gate electrode 251 and a A common line 256 is formed. Next, a gate insulating film is formed on the gate electrode 251 and the common line 256. Next, a layer containing an impurity element that will become a donor is formed on the gate insulating film 52b. A microcrystalline semiconductor film 258a including the first buffer layer 262a is formed. A second buffer layer 242a is formed on the layer 262a and the gate insulating film 52b. The lines 271a to 271c and the source or drain region 263a are formed. In this case, the second buffer layer 242a that is not covered by the signal lines 271a to 271c has a thickness of Next, the protective insulating film 76 and the insulating film 101 are formed. It is preferable to use a non-photosensitive resin as the material 101 .

[0173] Next, a resist is applied onto the insulating film 101. Next, a multi-tone mask as shown in the second embodiment is applied. The resist is irradiated with light using a mask, and the resist is exposed and developed to form a plurality of thicknesses. In this example, a resist mask 223 is formed on the gate electrode 251, the signal lines 271a to In the region where the contact hole exposing the common line 256 is formed, the resist It is possible to expose 100% of the photoresist, and the microcrystals containing impurity elements that act as donors are The semiconductor film 258a, the first buffer layer 262a, and the second buffer layer 242a are exposed. In the contact hole formation area, the resist is exposed in the range of 10 to 70%. By using a multi-tone mask that can be used in this way, a resist mask 223 with different thicknesses is formed. It is possible.

[0174] Next, as shown in FIG. 19(B), the insulating film 101 is etched using the resist mask 223. Next, the protective insulating film 76 is etched. Next, the gate insulating films 52a and 52b are As a result, the gate electrode 251 and the common line 256 are exposed. contact holes 224 and 226, and a contact hole 225 exposing the signal line 271c. It can be formed.

[0175] Next, the resist mask 223 is removed by ashing, and the thin film region is separated. Next, the insulating film 101 and the protective film 231 are formed using the mask. The protective insulating film 76 is etched. Next, the microcrystalline semiconductor film 2 containing the impurity element serving as a donor is 58a, and a part of the first buffer layer 262a and a part of the second buffer layer 242a are 19(C) to form a contact hole exposing the gate insulating film 52b. At this time, the insulating film 234 is formed under the condition that the gate insulating film 52b is not etched. the film 101, the protective insulating film 76, the microcrystalline semiconductor film 258a containing the impurity element serving as a donor, and The first buffer layer 262a and the second buffer layer 242a are partially etched. Furthermore, the etching step is preferably performed to form a contact hole as shown in FIG. In the steps 224 to 226, the insulating film 102 and the protective insulating film 76 are partially etched. Contact holes 232, 234, and 235 are formed with a double top surface shape.

[0176] Thereafter, in the same manner as in the fifth embodiment, a pixel electrode is formed, and at the same time, a gate electrode 251 and a signal The conductive film 201 connecting the common line 271c, the second buffer layer 242a, and the common line 2 A conductive film 222 connecting 56 is formed.

[0177] By the above steps, a diode can be formed. The protection circuit can be formed using the same number of masks as the thin film transistor shown in Form 3. .

[0178] (Embodiment 7) In this embodiment mode, a structure and a manufacturing method of a protection circuit different from those in Embodiment Modes 5 and 6 will be described. In this embodiment, a method for forming a microcrystalline semiconductor containing an impurity element that serves as a donor is described below. A diode having a Schottky junction between the dielectric film, the first buffer layer, and the second buffer layer is used. and show.

[0179] Here, a cross-sectional view of MN in FIG. 20 is shown in FIG. 21(A), and a cross-sectional view of OP in FIG. 20 is shown in FIG. 1(B).

[0180] As shown in FIG. 20, the diode 315 of this embodiment includes a common line 256, a donor, and The microcrystalline semiconductor film 231a containing the impurity element, the first buffer layer 232a, and the second The contact hole 245 in contact with the buffer layer 233a contains an impurity element that serves as a donor. a microcrystalline semiconductor film 231a, a first buffer layer 232a, and a second buffer layer 233a The difference from the sixth embodiment is that the diode 316 is formed at the end of the common The first buffer layer 231b includes a first impurity element serving as a donor. The contact hole 246 where the first buffer layer 232b and the second buffer layer 233b are in contact with each other is a microcrystalline semiconductor film 231b containing an impurity element serving as a base, a first buffer layer 232b, and The difference from the sixth embodiment is that the second buffer layer 233b is formed at the end of the second buffer layer 233b.

[0181] As shown in FIG. 21(A), the signal lines 271a to 271c of the diode 315 are formed by the conductive film 2 41 and is connected to the gate electrode 251 and the source or drain region 26 3a. A microcrystalline semiconductor film containing an impurity element serving as a donor of the diode 315 is in contact with the microcrystalline semiconductor film 316. The first buffer layer 231a, the first buffer layer 232a, and the second buffer layer 233a are formed by the conductive film 242. Here, the common line 256 is connected to the common line 256 via the conductive film 242. The first barrier layer is formed of an amorphous semiconductor film to which no impurity element serving as a donor is added. The first buffer layer 232a and the second buffer layer 233a, and the impurity source which becomes a low concentration donor, Since the silicon dioxide is in contact with the microcrystalline semiconductor film 231a containing silicon dioxide, a Schottky junction is formed.

[0182] The gate electrode of the diode 316 is formed by the common line 256. The microcrystalline semiconductor containing the impurity element serving as a donor of the diode 316 is formed through the conductive film 243. The insulating film 231b, the first buffer layer 232b, and the second buffer layer 233b are connected to each other. The signal lines 271a to 271c of the diode 316 are connected to the source region or the drain region. Here, the common line 256 is in contact with the region 263b via the conductive film 243. The first buffer layer 232b is formed of an amorphous semiconductor film to which no impurity element is added. , the second buffer layer 233a, and a microcrystal containing a low concentration of impurity elements that act as donors. It contacts the semiconductor film 231b, forming a Schottky junction.

[0183] In the case of the protective circuit provided for the wiring 1339 that is the scan line shown in FIG. 15, The signal lines 271a to 271c in FIG. 21 function as common lines, and the common line 256 in FIG. It functions as:

[0184] When a positive high voltage is applied to the input terminals of the signal lines 271a to 271c, the diodes shown in FIG. A positive voltage is applied to the gate electrode 251 of the diode 315 and the signal lines 271a to 271c. Carriers are generated in the microcrystalline semiconductor film 231a containing the impurity element serving as a donor, and the common line 2 A current flows through the input terminals of the signal lines 271a to 271c. When the voltage is applied, the signal lines 271a to 271c of the diode 316 in FIG. 21(B) A negative voltage is applied, and a voltage higher than the threshold voltage is applied to the common line 256 and the signal lines 271a to 271c. Because of the potential difference, the carriers are transferred to the microcrystalline semiconductor film 231b containing the impurity element serving as a donor. This generates a current flowing through the common line 256. This can prevent electrostatic damage to the capacitor.

[0185] Next, a manufacturing process of the diode 315 shown in FIG. 21(A) will be described with reference to FIG. 22. Here, a method for manufacturing the diode 315 will be described using the first embodiment. 2 can be used as appropriate.

[0186] As in the fifth embodiment, as shown in FIG. 22(A), a gate electrode 251 and a A common line 256 is formed. Next, a gate insulating film is formed on the gate electrode 251 and the common line 256. Next, a layer containing an impurity element that will become a donor is formed on the gate insulating film 52b. A microcrystalline semiconductor film 258a including the first buffer layer 262a is formed. The second buffer layer 41 is formed on the layer 262a and the gate insulating film 52b. An impurity semiconductor film 55 to which an impurity element imparting one conductivity type is added is formed on the buffer layer 41. Form.

[0187] Next, a resist is applied onto the impurity semiconductor film 55 to which an impurity element that imparts one conductivity type is added. After the deposition, a resist mask is formed by a photolithography process using a photomask. Next, using the resist mask, an impurity layer to which an impurity element that imparts one conductivity type is added is formed. The compound semiconductor film 55, the second buffer layer 44, the first buffer layer 262a, and the impurities that will become donors. The microcrystalline semiconductor film 258a containing the metal element is partially etched to form the microcrystalline semiconductor film 258a shown in FIG. As shown in FIG. 1, the microcrystalline semiconductor film 235 containing the impurity element serving as a donor, the first buffer layer 2 36, the second buffer layer 237, and the impurity layer doped with an impurity element that imparts one conductivity type. A semiconductor film 238 is formed. Here, a microcrystalline semiconductor film 238 containing an impurity element serving as a donor is formed. 35 and the side surfaces of the first buffer layer 236 are covered with a second buffer layer 237, The second buffer layer 237 has a side surface that is approximately aligned with the side surface of the second buffer layer 237 .

[0188] Next, as in the sixth embodiment, the signal lines 271a to 271c and the source region or the drain region are In this case, the second region 263a that is not covered by the signal lines 271a to 271c is formed. The thickness of the buffer layer 239 is partially reduced. Next, the protective insulating film 76 and the insulating film 101 are formed. do.

[0189] Next, in the same manner as in the sixth embodiment, a multi-tone mask is used to form a gate electrode 251 and a common Contact holes are formed to expose the signal line 256 and the signal line 271c. The microcrystalline semiconductor film 231a containing the impurity element to be the core, the first buffer layer 232a, the second buffer layer 232b, and the The buffer layer 233a is partially etched to form a layer containing an impurity element serving as a donor. The side surfaces of the microcrystalline semiconductor film 235, the first buffer layer 236, and the second buffer layer 237 are At the same time, a contact hole 245 is formed that exposes the gate insulating film 52b.

[0190] Thereafter, in the same manner as in the fifth embodiment, a pixel electrode is formed, and at the same time, a gate electrode 251 and a signal The conductive film 241 connecting the wiring 271c and the microcrystalline semiconductor containing the impurity element serving as a donor The main body 231a, the first buffer layer 232a, the second buffer layer 233a, and the common A conductive film 242 that connects the lines 256 is formed.

[0191] Through the above steps, the diode 315 can be formed. The protection circuit can be formed using the same number of masks as the thin film transistor shown in Embodiment 3. can.

[0192] (Embodiment 8) In this embodiment, a film formation apparatus that can be used in the film formation process in the above embodiment and a film formation method therefor will be described. The flow of the board is shown below.

[0193] Next, as an example of a plasma CVD apparatus applicable to the film forming process of this embodiment, an insulating film, a microcrystalline semiconductor film containing an impurity element that serves as a donor, a buffer layer, and a film that provides one conductivity type An example of a structure suitable for forming an impurity semiconductor film to which an impurity element is added will be shown.

[0194] Figure 23 shows an example of a multi-chamber plasma CVD apparatus equipped with multiple reaction chambers. The apparatus includes a common chamber 423, a load / unload chamber 422, a first reaction chamber 400a, a second reaction chamber 400b, and a The reactor is configured to include a first reaction chamber 400b, a second reaction chamber 400c, and a fourth reaction chamber 400d. The substrates loaded into the cassette in the loading / unloading chamber 422 are transferred by a transfer mechanism 426 in the common chamber 423. The wafer is transported in and out of each reaction chamber by a single wafer transport system. The reaction chambers are each provided with a valve 425, and are configured so that the processes carried out in each reaction chamber do not interfere with each other. It is being done.

[0195] Each reaction chamber is divided according to the type of thin film to be formed. For example, the first reaction chamber 400a is The second reaction chamber 400b is used to form an insulating film such as a gate insulating film, and the second reaction chamber 400b is used to form an impurity element that will be a donor. The third reaction chamber 400c is used as a high resistance region of the thin film transistor. The fourth reaction chamber 400d is a one-conductivity type buffer layer for forming the source and drain. The chamber is used as a reaction chamber for forming an impurity semiconductor film to which the impurity element is added. Of course, the number of reaction chambers is not limited to this, and can be increased or decreased as needed. Cut.

[0196] A turbo molecular pump 419 and a dry pump 420 are connected to each reaction chamber as exhaust means. The exhaust means is not limited to the combination of these vacuum pumps, and may be any of approximately 10 -1 Pa to 10 -5 Other vacuum pumps can be used if they can evacuate to a vacuum level of 100 Pa. A butterfly valve 417 is provided between the exhaust means and each reaction chamber. This allows the vacuum pumping to be shut off, and the conductance valve 418 This allows the pumping speed to be controlled, thereby adjusting the pressure in each reaction chamber.

[0197] The second reaction chamber 400b for forming a microcrystalline semiconductor film containing an impurity element serving as a donor is a super A cryopump 421 may be connected to evacuate the chamber to a high vacuum. By using the pump 421, the pressure in the reaction chamber is increased to 10 -5 Ultra-high vacuum with pressures below Pa In this embodiment, the reaction chamber is -5 Ultra-high accuracy with pressures lower than Pa By making the film empty, the oxygen concentration and the nitrogen concentration in the microcrystalline semiconductor film containing the impurity element serving as a donor can be reduced. As a result, the microcrystalline semiconductor film 45 containing the impurity element serving as a donor is effectively reduced. The oxygen concentration in 16 atoms / cm 3 It can be: Donna By reducing the oxygen concentration and nitrogen concentration in the microcrystalline semiconductor film containing the impurity element, It is possible to reduce defects in the film and increase crystallinity, improving carrier mobility. It is possible to do this.

[0198] The gas supply means 408 supplies semiconductor material gases such as silane and germane, or rare gases. A cylinder 410 filled with the gas used in the process, stop valves 411 and 412, The gas supply means 408g is configured with a first reaction chamber 400a, and supplies gas for forming the gate insulating film. 8i is connected to the second reaction chamber 400b, and is a microcrystalline semiconductor film containing an impurity element that serves as a donor. The gas supply means 408b is connected to the third reaction chamber 400c, and supplies the buffer layer The gas supply means 408n is connected to the fourth reaction chamber 400d, and The gas for the semiconductor film is supplied. Also, it is one of the gases containing impurity elements that act as donors. Phosphine is also connected to the first reaction chamber 400a and the second reaction chamber 400b to supply gas. The gas supply means 408a supplies argon, and the gas supply means 408f supplies the gas This is a system that supplies etching gas used for cleaning, and these are common to each reaction chamber. It is configured as an inn.

[0199] Each reaction chamber is connected to a high frequency power supply means 403 for generating plasma. The high frequency power supply means includes a high frequency power supply 404 and a matching box 406 .

[0200] Each reaction chamber can be used depending on the type of thin film to be formed. There is an optimum film formation temperature, so by separating the reaction chambers, the film formation temperature can be controlled. Furthermore, since the same film type can be repeatedly formed, there is no residue related to the film formation history. In particular, the influence of residual impurities can be eliminated by using microcrystalline semiconductors containing impurity elements that act as donors. In the case of a conductive film, it is necessary to avoid mixing impurity elements that will become donors into the buffer layer. As a result, it is possible to reduce the concentration of impurity elements in the buffer layer, The off-state current of the film transistor can be reduced.

[0201] Next, in the same reaction chamber, a gate insulating film and a microcrystalline semiconductor containing impurity elements that act as donors are formed. The semiconductor film, the buffer layer, and the impurity semiconductor film doped with an impurity element that gives one conductivity type are successively formed. One embodiment of a plasma CVD apparatus for forming the above is shown in FIG.

[0202] This device includes a common chamber 423, a load / unload chamber 422, a waiting chamber 401, and a reaction chamber 400. The substrates loaded into the cassette in the load / unload chamber 422 are is a single-wafer type structure in which wafers are transported into and out of each reaction chamber by a transport mechanism 426 in the common chamber 423. A gate valve 425 is provided between the common chamber 423 and each chamber, and the process performed in each reaction chamber is controlled by the gate valve 425. are configured so as not to interfere with each other.

[0203] A turbo molecular pump 419 and a dry pump 420 are connected to the reaction chamber 400a as exhaust means. The exhaust means is not limited to the combination of these vacuum pumps, and generally about 10 -1 Pa to 10 -5 Other vacuum pumps can be used if they can evacuate to a vacuum level of 100 Pa. A butterfly valve 417 is provided between the exhaust means 430 and the reaction chamber. This allows the vacuum pumping to be shut off, and the conductance valve The pumping speed can be controlled by 418 to adjust the pressure in each reaction chamber. In addition, a cryopump 421 may be connected to the reaction chamber 400a.

[0204] The gas supply means 408 supplies semiconductor material gases such as silane and germane, or rare gases. A cylinder 410 filled with the gas used in the process, stop valves 411 and 412, The gas supply means 408g, 408i, and the gas flow controller 413 are also included. 408b, 408n, and 408f are connected to the reaction chamber 400a.

[0205] A high frequency power supply means 403 for generating plasma is connected to the reaction chamber. The high frequency power supply means 403 includes a high frequency power supply 404 and a matching box 406 .

[0206] Next, a process for continuously forming multiple films using the plasma CVD apparatus shown in FIG. This is shown in FIG.

[0207] FIG. 25(A) is a simplified diagram of the plasma CVD apparatus shown in FIG. 24. (B) shows a gate insulating film and a donor impurity element on a substrate on which a gate electrode is formed. A microcrystalline semiconductor film containing - μc-Si film) is continuously formed. The dashed arrows indicate the flow of the substrate, and the solid arrows indicate the flow of the film formation process. vinegar.

[0208] As shown in FIG. 25(B), the inner wall of the reaction chamber 400a is cleaned with fluorine radicals or the like ( S461) to remove residual impurities from the reaction chamber 400a. Next, the inner wall of the reaction chamber 400a is Then, a film similar to the gate insulating film is coated on the surface (S462). This prevents the metals constituting the reaction chamber 400a from being mixed into the gate insulating film as impurities. This can be done.

[0209] Next, the substrate to be loaded into the cassette in the load / unload chamber 422 is Then, the substrate is transported to the reaction chamber 400a by the transport mechanism 426 of the common chamber 423. At step 0a, a gate insulating film, here a silicon oxynitride film, is formed on the substrate (S463).

[0210] Next, the substrate on which the gate insulating film has been formed is transferred to the transfer mechanism in the common chamber 423 as shown by the arrow a2. The substrate is transported to the waiting chamber 401 by the mechanism 426, and is kept waiting (S464). The inner wall of the reaction chamber 400a is cleaned with fluorine radicals or the like (S465). After removing the remaining impurities, the inner wall of the reaction chamber 400a is coated with an amorphous semiconductor film ( By this cleaning and coating, a film is formed on the inner wall of the reaction chamber 400a. The components of the gate insulating film (oxygen, nitrogen, etc.) and the metals that make up the reaction chamber act as impurities and are later It is possible to prevent the impurity element that will become a donor from being mixed into the microcrystalline semiconductor film that contains the impurity element to be formed. As a result, the crystallinity of the microcrystalline semiconductor film can be improved. The transfer mechanism 426 in the common chamber 423 transfers the donor to the reaction chamber 400a. A microcrystalline semiconductor film containing an impurity element that will be a donor is formed (S467). The microcrystalline semiconductor film containing the impurity element is formed by using silane, hydrogen, and phosphine as a raw material gas. A microcrystalline silicon film containing phosphorus is formed using the silicon dioxide as a source.

[0211] Next, a substrate on which a microcrystalline semiconductor film containing an impurity element serving as a donor is formed is shown by an arrow a2. As shown in FIG. 1, the transfer mechanism 426 in the common chamber 423 transfers the sample to the waiting chamber 401 and waits there (S47 After that, the inner wall of the reaction chamber 400a is cleaned with fluorine radicals or the like (S468 ), after removing the remaining impurities in the reaction chamber 400a, an amorphous semiconductor film is formed on the inner wall of the reaction chamber 400a. By this cleaning and coating, the reaction chamber 4 The microcrystalline semiconductor film containing impurities that act as donors and the reaction Prevents the metals that make up the chamber from being mixed as impurities into the amorphous semiconductor film that will be formed later. Therefore, the amorphous semiconductor film can function as a high resistance region. Next, as shown by arrow a3, the transfer mechanism 426 of the common chamber 423 transfers the reaction chamber 400a The wafer is transported to the reaction chamber 400a, where an amorphous semiconductor film is formed as a first buffer layer (S4 71) Here, silane and hydrogen are used as source gases to form an amorphous semiconductor film. An amorphous silicon film is formed.

[0212] Next, the substrate on which the first buffer layer has been formed is transferred to the common chamber 423 as shown by the arrow a4. The wafer is loaded into the cassette in the load / unload chamber 422 by the transport mechanism 426. The gate insulating film and the fine crystals containing impurity elements that act as donors are formed on the substrate on which the gate electrode is formed. The crystalline semiconductor film and the first buffer layer can be successively formed. The inner wall of the reaction chamber 400a is cleaned with fluorine radicals or the like (S472), and the remaining After removing impurities, the inner wall of the reaction chamber 400a is coated with a film similar to that of the gate insulating film. Next, another substrate loaded in a cassette in the load / unload chamber 422 is The substrate is transported to the reaction chamber 400a, and the gate insulating film is formed (S463) and the process is the same as that described above. a gate insulating film, a microcrystalline semiconductor film containing an impurity element serving as a donor, and a first buffer layer are continuously deposited.

[0213] All the substrates loaded in the cassette of the load / unload chamber 422 are coated with a gate insulating film, a donor, and After the microcrystalline semiconductor film containing the impurity element and the first buffer layer are formed, the cassette is The substrate is then transported out of the load / unload chamber 422 and sent to the next process.

[0214] Here, the gate insulating film, n ― The substrate on which the μc-Si film is formed is placed in waiting room 401. However, it may be allowed to wait in the load / unload chamber 422. The CVD equipment can be simplified, which allows for cost reduction.

[0215] Also, n ― As a method for forming the μc-Si film, here, phosphites are added to the source gas in S467. Instead, phosphine was introduced into the reaction chamber after coating S466. After phosphorus is adsorbed onto the inner wall of the reaction chamber, the substrate waiting in the waiting chamber 401 is transferred to the reaction chamber 400a. The microcrystalline silicon film is formed by using silane and hydrogen as raw material gases. Since the film is formed while absorbing phosphorus adsorbed in the chamber, it contains impurity elements that act as donors. A microcrystalline semiconductor film can be formed.

[0216] In addition, when forming a gate insulating film using S463, phosphine is mixed into the source gas to After forming a gate insulating film containing silane, a micro-electrode was formed in S467 using silane and hydrogen as source gases. By depositing crystalline silicon, a microcrystalline silicon film containing phosphorus can be formed.

[0217] Next, referring to FIG. 25(B), a microcrystalline semiconductor containing an impurity element that will become a donor and is formed in an island shape is formed. A second buffer layer and an impurity element imparting one conductivity type are formed on the conductive film and the first buffer layer. An impurity semiconductor film (here, n + a-Si film) is continuously formed. The dashed arrows indicate the flow of the substrate, and the solid arrows indicate the flow of the film formation process. vinegar.

[0218] As shown in FIG. 25(C), the inner wall of the reaction chamber 400a is cleaned with fluorine radicals or the like ( S481) to remove residual impurities from the reaction chamber 400a. Next, the inner wall of the reaction chamber 400a is The second buffer layer is coated on the surface of the amorphous silicon substrate (S482). This coating process allows the metal that makes up the reaction chamber 400a to be coated with a silicon film. This can prevent the gate insulating film from being contaminated with impurities.

[0219] Next, the substrate to be loaded into the cassette in the load / unload chamber 422 is Then, the substrate is transported to the reaction chamber 400a by the transport mechanism 426 of the common chamber 423. In step 0a, a second buffer layer, an amorphous silicon film in this case, is formed on the substrate (S483 )do.

[0220] Next, an impurity element that imparts one conductivity type is added to the substrate on which the second buffer layer is formed. The impurity semiconductor film (here, n + Here, a film of a-Si is formed. Rufus silicon film and n + The main components of the a-Si film are the same, and the amorphous silicon In the + It does not contain any contaminants that can contaminate a-Si films, so + a-Si film A coating step may not be necessary before forming the film.

[0221] Next, n + The substrate on which the a-Si film is formed is transported to the common chamber 423 as shown by the arrow a4. The cassette in the load / unload chamber 422 is loaded by the mechanism 426. , island-shaped n ― A second buffer layer is formed on the substrate on which the μc-Si film and the first buffer layer are formed. Layer and n + Next, the inner wall of the reaction chamber 400a is Cleaning with fluorine radicals or the like (S485) removes residual impurities from the reaction chamber 400a. After that, the inner wall of the reaction chamber 400a is coated with a film similar to the second buffer layer (S4 86). Next, another substrate loaded in a cassette in the load / unload chamber 422 is transferred to the reaction chamber 400a, and the second buffer layer is formed (S483) in the same manner as described above. The second buffer layer and + The a-Si film is continuously formed.

[0222] All the substrates loaded in the cassette in the load / unload chamber 422 are coated with the second buffer layer and n + After the a-Si film is formed, the cassette is removed from the load / unload chamber 422 and the next Put it into the process.

[0223] By the above process, multiple films can be formed continuously without being exposed to the atmosphere. Films can be formed without introducing contaminants.

[0224] (Embodiment 9) In this embodiment mode, a thin film transistor and a diode having a structure different from those in the above embodiment mode will be described. The following are examples:

[0225] In any of the first to eighth embodiments, a microcrystalline semiconductor containing an impurity element serving as a donor is Although a first buffer layer 62 is provided on the film 58, the first buffer layer 62 may be omitted. That is, the top surface and the side surface of the microcrystalline semiconductor film 58 containing the impurity element serving as a donor may be The second buffer layer 42 covers the gate insulating film 52b and the donor. The microcrystalline semiconductor film 58 containing the impurity element may be in contact with the surface of the semiconductor substrate 51 at the outer edge thereof. This makes it possible to reduce the number of film formation steps, thereby enabling cost reduction.

[0226] (Embodiment 10) In this embodiment, the scanning line (gate wiring) input provided in the peripheral portion of the substrate 50 shown in FIG. The structure of the input terminal and the signal line (source wiring) input terminal is shown below using Figure 27. 27 shows the scanning line input terminal section and the signal line input terminal section provided on the periphery of the substrate 50. 1A and 1B show cross-sectional views of a thin film transistor in a pixel portion.

[0227] A display device 300 shown in FIG. 26 is provided with a pixel section 301, and the pixel section 301 and the periphery of a substrate 50 Between the portions, protection circuits 302 and 322, signal lines 303, and scanning lines 323 are provided. Although not shown, a signal line 303 and a scanning line 304 are connected from the pixel section 301 and the protection circuits 302 and 322 to the peripheral section. The signal lines 303 and the scanning lines 323 are formed at their ends with signal line input terminal portions 306. , and a scanning line input terminal section 326 are provided. The 26 terminals are connected to FPC304 and 324, respectively, and the FPC304 and 324 have signal The pixel portion 301 is provided with a scanning line driver circuit 305 and a scanning line driver circuit 325. However, pixels 327 are arranged in a matrix.

[0228] In FIG. 27A, the scanning line input terminal 306a is connected to the gate of the thin film transistor 330. It is connected to a scanning line 323 formed in the same layer as the electrode 331. A gate electrode 331 of the transistor 330 may be formed. a is formed in the same layer as the source electrode or drain electrode 337 of the thin film transistor 330. The signal line 303 is connected to the source of the thin film transistor 330. A source electrode or a drain electrode 337 may be formed.

[0229] The scanning line input terminal 306a and the signal line input terminal 316a are connected to the thin film transistors of the pixel section. The pixel electrodes 340 of the gate electrodes 330 are formed in the same layer as the scanning line input terminals 306a and 306b. The line input terminal 316a is formed on an insulating film 339 formed on the signal line 303. On the insulating film 339, the scanning line input terminal 306a and the signal line input terminal 316a are anisotropically Conductive adhesive 307, 327 and conductive particles 308, 328 are used to connect the FPC 304, 324. are connected to the wiring 309 and 329.

[0230] Here, the scanning line 323 and the scanning line input terminal 306a are connected. Between the signal line 303 and the scanning line input terminal 306a, a conductive film formed in the same layer as the signal line 303 is provided. Also, the signal line 303 and the signal line input terminal 316a are connected, but the signal line 303 A conductive film formed in the same layer as the scanning line 323 may be provided between the signal line input terminal 316a and the scanning line 323. good.

[0231] In FIG. 27B, the scanning line input terminal 306b is connected to the gate of the thin film transistor 330. It is connected to a scanning line 323 formed in the same layer as the electrode 331. A gate electrode 331 of the transistor 330 may be formed. b is formed in the same layer as the source electrode or drain electrode 337 of the thin film transistor 330. The signal line 303 is connected to the source of the thin film transistor 330. A source electrode or a drain electrode 337 may be formed.

[0232] The scanning line input terminal 306b and the signal line input terminal 316b are connected to the thin film transistors of the pixel section. The pixel electrodes 340 of the gate electrodes 330 are formed in the same layer as the scanning line input terminals 306b and the signal The line input terminal 316b is formed on the insulating film 339 and the protective insulating film 338. On the substrate 50, the scanning line input terminal 306b and the signal line input terminal 316b are connected by anisotropic conductive adhesive. The wiring 30 of the FPC 304, 324 is connected via the conductive particles 308, 328 of the adhesive 307, 327. 9,329.

[0233] In this example, the scanning line 323 is connected to the scanning line input terminal 306b. A conductive film formed in the same layer as the signal line 303 may be provided between the scanning line input terminal 306b and the signal line 303. Furthermore, the signal line 303 and the signal line input terminal 316b are connected. A conductive film formed in the same layer as the scanning line 323 may be provided between the signal line input terminals 316b. .

[0234] In FIG. 27(C), the scanning line input terminal 306c is connected to the gate of the thin film transistor 330. It is connected to a scanning line 323 formed in the same layer as the electrode 331. A gate electrode 331 of the transistor 330 may be formed. c is formed in the same layer as the source electrode or drain electrode 337 of the thin film transistor 330. The signal line 303 is connected to the source of the thin film transistor 330. A source electrode or a drain electrode 337 may be formed.

[0235] The scanning line input terminal 306c and the signal line input terminal 316c are connected to the thin film transistors of the pixel section. The pixel electrodes 340 of the gate electrodes 330 are formed in the same layer as the scanning line input terminals 306b and the signal The line input terminal 316b is formed on the insulating film 339. In FIG. The openings in the insulating film 339 are for the scanning line input terminal 306b and the signal line input terminal 316b. The end of the scanning line 323 is exposed. In the openings of 39, conductive particles 308, 328 of the anisotropic conductive adhesive 307, 327 are The FPCs 304 and 324 are connected to the wiring 309 and 329 via the wiring 309 and 329 .

[0236] In this example, the scanning line 323 is connected to the scanning line input terminal 306b. A conductive film formed in the same layer as the signal line 303 may be provided between the scanning line input terminal 306b and the signal line 303. Furthermore, the signal line 303 and the signal line input terminal 316b are connected. A conductive film formed in the same layer as the scanning line 323 may be provided between the signal line input terminals 316b. .

[0237] (Embodiment 11) In this embodiment mode, the thin film transistor described in the above embodiment mode is used as one mode of a display device. The following describes a liquid crystal display device having a VA (Vertical Alignment) The VA type liquid crystal display device will be described with reference to FIGS. 28 to 30. The VA type LCD is a type of display that controls the alignment of liquid crystal molecules in the LCD panel. In the liquid crystal display device of the present invention, when no voltage is applied, the liquid crystal molecules are oriented in a direction perpendicular to the panel surface. In this embodiment, pixels are divided into several regions (sub-pixels). The molecules are divided into small molecules (called "multi-domains"), each of which is designed to tilt in a different direction. In the following explanation, multi-domain design is taken into consideration. A liquid crystal display device having such a configuration will now be described.

[0238] 28 and 29 show the pixel structure of a VA type liquid crystal panel. FIG. 28 is a plan view showing a cross-sectional structure corresponding to the cutting line YZ shown in the figure. The explanation will be given with reference to both figures.

[0239] This pixel structure has a plurality of pixel electrodes 624 and 626 in one pixel. Thin film transistors 628 and 629 are connected to electrodes 624 and 626 via a planarization film 622. The thin film transistors 628 and 629 are configured to be driven by different gate signals. That is, in a pixel with a multi-domain design, each pixel electrode 624 , 626 are configured to independently control the signals applied to the respective inputs.

[0240] The pixel electrode 624 is connected to the thin film transistor 618 through the contact hole 623 . The pixel electrode 626 is connected to the wiring 628 through the contact hole 627. 619 is connected to a thin film transistor 629. Gate wiring of the thin film transistor 628 602 and the gate wiring 603 of the thin film transistor 629 are given different gate signals. On the other hand, the wiring 616 that functions as a data line is made of thin film. It is commonly used in the transistor 628 and the thin film transistor 629. The thin film transistor 628 and the thin film transistor 629 are manufactured by the method shown in the above embodiment mode. can be done.

[0241] The pixel electrode 624 and the pixel electrode 626 have different shapes and are separated by a slit 625. A pixel electrode 626 is formed so as to surround the outside of the pixel electrode 624 that spreads in a V shape. The timing of the voltages applied to the pixel electrodes 624 and 626 is controlled by a thin film transistor. The alignment of the liquid crystal is controlled by changing the polarity of the pixel electrode 628 and the thin film transistor 629. The gate wiring 602 and the gate wiring 603 are provided with different gate signals, and the thin film transistor The operation timing of the transistor 628 and the thin film transistor 629 can be made different. In addition, an alignment film 648 is formed on the pixel electrodes 624 and 626 .

[0242] On the counter substrate 601, a light-shielding film 632, a colored film 636, and a counter electrode 640 are formed. In addition, a flattening film 637 is formed between the colored film 636 and the counter electrode 640, and the alignment of the liquid crystal is prevented from being disturbed. In addition, an alignment film 646 is formed on the counter electrode 640. The counter electrode 640 is an electrode that is shared between different pixels. The slit 641 is formed on the pixel electrode 624. By arranging the slits 625 on the 26 side so that they interdigitate with each other, the oblique electric field can be effectively This allows the liquid crystal to be oriented in a specific direction. This allows the display to be varied depending on the screen brightness, widening the viewing angle.

[0243] Here, the substrate, the colored film, the light-shielding film, and the planarizing film constitute a color filter. Either or both of the light-shielding film and the planarizing film may not be formed on the substrate.

[0244] In addition, the colored film transmits light components in a given wavelength range preferentially within the wavelength range of visible light. Usually, light in the red wavelength range, light in the blue wavelength range, and light in the green wavelength range are used. By combining colored films that transmit light preferentially, they can be used as color filters. However, the combination of colored films is not limited to this.

[0245] The pixel electrode 624, the liquid crystal layer 650, and the counter electrode 640 are overlapped to form a first liquid crystal element. In addition, the pixel electrode 626, the liquid crystal layer 650, and the counter electrode 640 are overlapped with each other. The first liquid crystal element and the second liquid crystal element are formed in one pixel. It is a multi-domain structure with multiple children.

[0246] Here, the liquid crystal display device is a VA (Vertical Alignment) The liquid crystal display device of the FFS type has been shown, but the element substrate formed by the above embodiment can be used for the liquid crystal display device of the FFS type. Liquid crystal display devices, IPS type liquid crystal display devices, TN type liquid crystal display devices, and other liquid crystal display devices It can be used for.

[0247] Through the above steps, a liquid crystal display device can be manufactured. The off-state current is small and the inverted staggered thin film transistor with excellent electrical characteristics is used. Therefore, a liquid crystal display device with high contrast and high visibility can be manufactured.

[0248] (Embodiment 12) In this embodiment mode, the thin film transistor described in the above embodiment mode is used as one mode of a display device. The structure of a pixel in a light-emitting device will be described below. FIG. 31(A) shows one mode of a top view of a pixel, and FIG. 31(B) shows a top view of the pixel shown in FIG. 1 shows one example of a cross-sectional structure of a pixel corresponding to AB in FIG.

[0249] The light-emitting device is a display having a light-emitting element that utilizes electroluminescence. The light-emitting element that uses electroluminescence is made of organic light-emitting material. Generally, the former is used in organic EL devices, The latter is called an inorganic EL element. The above embodiment can be used.

[0250] In an organic EL element, electrons and holes are released from a pair of electrodes by applying a voltage to the light-emitting element. are injected into the layers containing the light-emitting organic compounds, causing a current to flow. The recombination of the electrons and holes creates an excited state in the light-emitting organic compound. The excited state is then converted to the ground state, at which point light is emitted. Such a light-emitting element is called a current-excited light-emitting element.

[0251] Inorganic EL elements are divided into dispersion-type inorganic EL elements and thin-film-type inorganic EL elements depending on the element structure. Dispersion-type inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The emission mechanism is a donor-acceptor interaction that utilizes the donor and acceptor levels. Thin-film inorganic EL devices sandwich the light-emitting layer between dielectric layers. Furthermore, this structure is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. In this example, the light emitting element is an organic EL element. Also, a thin film transistor for switching is used to control the input of a signal to the first electrode. and a channel-etched thin-film transistor for controlling the driving of the light-emitting element. Although the present invention will be described using a thin film transistor of the type described above, a channel protection thin film transistor may be used as appropriate. This can be done.

[0252] In FIG. 31(A) and FIG. 31(B), the first thin film transistor 74a has a first electrode A switching thin film transistor for controlling the input of a signal, and a second thin film transistor The transistor 74b is a driving thin film for controlling the supply of current or voltage to the light emitting element 94. It corresponds to a membrane transistor.

[0253] The gate electrode of the first thin film transistor 74a is connected to the scanning line 51a, and the source or drain One of the terminals is connected to the wirings 71a to 71c which function as signal lines, and the other terminal is connected to the source or drain. The other end is connected to the gate electrode 51b of the second thin film transistor 74b. One of the source and drain of the resistor 74b is connected to the power supply lines 93a to 93c. The other of the drains is connected to the first electrode 79 of the display device. The gate electrode of the first capacitor 74b, the gate insulating film, and the power supply line 93a constitute a capacitance element 96. The other of the source and the drain of the thin film transistor 74 a is connected to a capacitance element 96 .

[0254] The capacitance element 96 is connected to the second thin film transistor 74a when the first thin film transistor 74a is turned off. The gate-source voltage or gate-drain voltage of the transistor 74b (hereinafter referred to as the gate voltage) This corresponds to a capacitance element for holding the voltage Vcc (assumed to be 0 V), and is not necessarily provided.

[0255] In this embodiment, the first thin film transistor 74a and the second thin film transistor 74b are The first thin film transistor can be formed using the thin film transistor described in the above embodiment. The first thin film transistor 74a and the second thin film transistor 74b are n-channel thin film transistors. The first thin film transistor 74a is an n-channel thin film transistor. The first thin film transistor 74b is formed of a p-channel thin film transistor. Furthermore, the first thin film transistor 74a and the second thin film transistor 74b may be It may be formed of a p-channel thin film transistor.

[0256] A protective insulating film 76 is formed on the first thin film transistor 74a and the second thin film transistor 74b. A planarizing film 78 is formed on the protective insulating film 76, and the planarizing film 78 and the protective insulating film 67 are In the contact hole, a first electrode 79 is formed to connect to the wiring 93f. The planarization film 78 is made of an organic resin such as acrylic, polyimide, or polyamide, or a siloxane. It is preferable to form the contact hole using a thin film polymer. Since the electrode 79 has irregularities, a partition wall 91 is provided to cover the irregularities and to have an opening. An EL layer 92 is formed in the opening of the wall 91 so as to be in contact with the first electrode 79. A second electrode 93 is formed to cover the partition wall 92, and a second electrode 93 is formed to cover the partition wall 91. A protective insulating film 95 is formed.

[0257] Here, a light emitting element 94 having a top emission structure is shown as the light emitting element. 94 also emits light on the first thin film transistor 74a and the second thin film transistor 74b. However, since the EL layer 9 If the undercoat film of the second electrode 93 has irregularities, the film thickness distribution becomes non-uniform at the irregularities. The first electrode 79 is short-circuited, resulting in a display defect. It is preferable to provide such a function.

[0258] The region where the EL layer 92 is sandwiched between the first electrode 79 and the second electrode 93 corresponds to the light emitting element 94. In the case of the pixel shown in FIG. 31(B), the light emitted from the light emitting element 94 is As shown by the mark, the light is emitted toward the second electrode 93 side.

[0259] The first electrode 79, which functions as a cathode, is a conductive film that has a small work function and reflects light. Any known material can be used, such as Ca, Al, CaF, MgAg, and Al. The EL layer 92 may be composed of a single layer or a plurality of layers. When it is made up of multiple layers, it functions as a cathode. The first electrode 79 is formed of an electron injection layer, an electron transport layer, a light emitting layer, a hole transport layer, and a hole injection layer. It is not necessary to provide all of these layers. The electrode 93 is formed using a light-transmitting conductive material, such as tungsten oxide. Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium, indium tin oxide containing titanium oxide, ITO, indium A light-transmitting conductive film such as indium zinc oxide or indium tin oxide added with silicon oxide is used. You can use it.

[0260] Here, we have shown a light-emitting element with a top emission structure that emits light from the surface opposite the substrate. However, there are light emitting elements with a bottom emission structure that emits light from the surface on the substrate side, and light emitting elements on the substrate side and the opposite side to the substrate. A light emitting element having a double-sided emission structure in which light is emitted from the side surface can be appropriately applied.

[0261] Although organic EL elements have been described as light-emitting elements here, inorganic EL elements may also be used as light-emitting elements. It is also possible to provide an L element.

[0262] In this embodiment, a thin film transistor (a driving thin film transistor) that controls driving of a light emitting element is used. In the example shown here, the driving thin film transistor and the light emitting element are electrically connected. A current control thin film transistor may be connected between the light emitting element and the light emitting element.

[0263] Through the above steps, a light-emitting device can be manufactured. The use of inverted staggered thin-film transistors with low current and excellent electrical characteristics allows A light-emitting device with high reliability and high visibility can be manufactured.

[0264] (Embodiment 13) Next, a structure of a display panel, which is one mode of a display device of the present invention, will be described below.

[0265] In FIG. 32, only a signal line driver circuit 6013 is separately formed, and a pixel formed on a substrate 6011 6 shows the form of a display panel connected to a pixel portion 6012. 6014 is formed using a thin film transistor using a microcrystalline semiconductor film in the channel formation region. A higher field effect than that of a thin film transistor using a microcrystalline semiconductor film in a channel formation region is achieved. By forming the signal line driver circuit using a transistor that can obtain high mobility, This makes it possible to stabilize the operation of the signal line driver circuit, which requires the highest possible driving frequency. The signal line driver circuit 6013 includes a transistor using a single crystal semiconductor for a channel formation region, Thin film transistors that use polycrystalline semiconductors in the channel formation region, or SOI as the channel The pixel portion 6012 and the signal line driver circuit 60 may be the same transistor as those used in the formation region. The potential of the power supply, various signals, etc. are respectively supplied to the FPC 6013 and the scanning line driving circuit 6014. 15. Furthermore, between the signal line driver circuit 6013 and the FPC 6015, Alternatively, a protection circuit may be provided between the signal line driver circuit 6013 and the pixel portion 6012. The circuit is made of one or more elements selected from a thin film transistor, a diode, a resistor element, a capacitor element, etc. The diode is composed of a plurality of elements. A diode with a Kettke junction can also be used.

[0266] The signal line driver circuit and the scanning line driver circuit may be formed on the same substrate as the pixel portion. .

[0267] In addition, when a driver circuit is formed separately, the substrate on which the driver circuit is formed is not necessarily the same as the substrate on which the pixel portion is formed. It is not necessary to attach it to a substrate that has been fabricated, and it can be attached to an FPC, for example. In FIG. 32(B), only the signal line driver circuit 6023 is separately formed on the substrate 6021. The pixel portion 6022 and the scanning line driver circuit 6024 are connected to the display panel. The pixel portion 6022 and the scanning line driver circuit 6024 are formed by using a microcrystalline semiconductor film as a channel type. The signal line driver circuit 6023 is formed using the thin film transistor used in the FPC The pixel portion 6022 is connected to the signal line driver circuit 6025. The potential of the power supply, various signals, etc. are respectively supplied to the FPC 6023 and the scanning line driver circuit 6024. Further, the signal line driver circuit 6023 and the FPC 6025 are connected to each other. Alternatively, a protective circuit may be provided between the signal line driver circuit 6023 and the pixel portion 6022 .

[0268] Further, only a part of the signal line driver circuit or a part of the scanning line driver circuit is formed using a microcrystalline semiconductor film. The thin film transistors used in the panel formation area are formed on the same substrate as the pixel area, and the rest are formed on a separate substrate. The signal line driving circuit may be formed in the signal line driving circuit so as to be electrically connected to the pixel portion. The analog switch 6033a of the circuit is connected to the pixel portion 6032 and the scanning line driver circuit 6034. A shift register 6033b of the signal line driver circuit is formed on the same substrate 6031. The display panel is formed on different substrates and bonded together. The scan line driver circuit 6034 is a thin film transistor using a microcrystalline semiconductor film in a channel formation region. The shift register 6033b of the signal line driver circuit is formed using FPC 603 5, the pixel portion 6032 is connected to the signal line driver circuit. The power supply potential and various signals are transmitted to the scanning line driving circuit 6034 via the FPC 6035. Furthermore, between the signal line driver circuit 6033 and the FPC 6035 or between the signal line A protective circuit may be provided between the driver circuit 6033 and the pixel portion 6032 .

[0269] As shown in FIG. 32, in the display device of this embodiment, a part or all of the driver circuits are connected to the pixel A thin film transistor using a microcrystalline semiconductor film in a channel formation region is used on the same substrate as the It can be formed.

[0270] The method for connecting the separately formed substrate is not particularly limited, and may be a known COG method. , wire bonding method, TAB method, etc. can be used. The position is not limited to the position shown in FIG. 28 as long as electrical connection is possible. The controller, CPU, memory, etc. may be separately formed and connected.

[0271] The signal line driver circuit used in the present invention has a shift register and an analog switch. In addition to shift registers and analog switches, buffers, level shifters, and source filters are also included. It may have other circuits such as a shift register and an analog switch. For example, instead of a shift register, there is no need to provide a decoder circuit or the like. You can use another circuit that can select, or use a latch instead of an analog switch. is also good.

[0272] (Embodiment 14) The display device obtained by the present invention can be used for an active matrix display panel. That is, the present invention can be applied to all electronic devices that incorporate such a display unit. do.

[0273] Such electronic devices include cameras such as video cameras and digital cameras, head-mounted cameras, displays (goggle-type displays), car navigation systems, projectors, car Stereos, personal computers, personal digital assistants (mobile computers, mobile phones, etc.) Examples of such devices are shown in Figure 33.

[0274] Fig. 33(A) shows a television device. As shown in Fig. 33(A), the display panel is enclosed in a housing. The display panel can be used to display the main screen. 2003 is formed, and other auxiliary equipment includes a speaker unit 2009 and an operation switch. In this way, the television device can be completed.

[0275] As shown in FIG. 33(A), a display panel 2002 using a display element is mounted on a housing 2001. The receiver 2005 receives general television broadcasts, and the modem 2004 By connecting to a wired or wireless communication network via It can also be used for two-way (sender-receiver) or two-way (sender-receiver or receiver-receiver-receiver) information communication. The television set is operated by a switch built into the housing or a separate remote control. 2006, and the remote control device also has a table that displays the information to be output. A display unit 2007 may be provided.

[0276] In addition to the main screen 2003, the television device also has a sub-screen 2008 as a second display panel. It may be formed by a display unit, and a configuration for displaying the channel, volume, etc. may be added. The main screen 2003 is formed by a liquid crystal display panel, and the sub-screen 2008 is formed by a light-emitting display panel. Alternatively, the main screen 2003 may be formed by a light-emitting display panel, and the sub-screen 2008 may be formed by a light-emitting display panel. The sub-screen may be formed of a light-emitting display panel and may be configured to be able to blink.

[0277] FIG. 34 is a block diagram showing the main components of a television device. A pixel portion 921 is formed on the display panel 920. A signal line driver circuit 922 and a scanning line driver circuit 923 are connected to the display panel 920. The display panel 900 may be mounted using the COG method.

[0278] As for the configuration of other external circuits, on the video signal input side, a signal received by a tuner 924 Among these, a video signal amplifier circuit 925 amplifies the video signal, and a signal output from the video signal amplifier circuit 925 is used to amplify the video signal. A video signal processing circuit 926 converts the video signal into a color signal corresponding to each color of green and blue, and It has a control circuit 927 for converting the input specifications of the driver IC. The control circuit 927 outputs signals to the scanning line side and the signal line side. In this case, a signal dividing circuit 928 is provided on the signal line side to divide the input digital signal into m parts. It may be configured to supply the

[0279] Of the signals received by the tuner 924, the audio signal is sent to an audio signal amplifier circuit 929, The output is supplied to a speaker 933 via an audio signal processing circuit 930. The control information for the receiving station (receiving frequency) and the volume is received from the input unit 932, and the tuner 924 and the sound A signal is sent to the voice signal processing circuit 930.

[0280] Of course, the present invention is not limited to television devices, but can be applied to a variety of devices including monitors of personal computers. Therefore, it is suitable for large-area displays such as information display boards at train stations and airports, and advertising display boards on the street. It can also be used as a display medium for a variety of purposes.

[0281] The display device described in the above embodiment is applied to the main screen 2003 and the sub-screen 2008. This will increase the mass production efficiency of television sets with improved image quality, such as contrast. can.

[0282] FIG. 33(B) shows an example of a mobile phone 2301. This mobile phone 2301 has a display The display unit 2302 includes an operation unit 2303. By applying the display device described in the above embodiment, image quality such as contrast can be improved. This will improve the mass production of mobile phones.

[0283] The portable computer shown in FIG. 33(C) includes a main body 2401, a display unit 2402, etc. By applying the display device described in the above embodiment to the display portion 2402, The mass productivity of computers with improved image quality such as contrast can be improved.

[0284] FIG. 33(D) shows a table lamp, which includes a lighting unit 2501, a shade 2502, and an adjustable arm 2503. 2501, a support 2504, a base 2505, and a power supply 2506. The lighting fixtures are either ceiling-mounted or wall-mounted. By applying the display device described in the above embodiment, This can improve productivity and provide an inexpensive desk lighting fixture.

Claims

[Claim 1] a first conductive layer above the substrate; a second conductive layer above the substrate; a first insulating layer over the first conductive layer and over the second conductive layer; a semiconductor layer above the first insulating layer; a third conductive layer above the semiconductor layer; a fourth conductive layer above the semiconductor layer; a second insulating layer above the third conductive layer and above the fourth conductive layer; a fifth conductive layer above the second insulating layer; the third conductive layer has an area that intersects with the second conductive layer; the first conductive layer has a region that functions as a gate electrode; the second conductive layer has a region that functions as a wiring; the second insulating layer has a first opening; the second insulating layer has a second opening; the fifth conductive layer has a region that functions as a pixel electrode, the fifth conductive layer has a region electrically connected to the fourth conductive layer through the first opening, The display device, wherein the fifth conductive layer has a region that overlaps with the second conductive layer through the first insulating layer in the second opening.

Images