Image forming apparatus and light emitting device

Abstract

To provide a technique capable of suppressing the capacity of a memory provided in an exposure device.SOLUTION: An exposure device mounted on an image forming apparatus includes a plurality of light emitting elements, a synchronization signal periodically transmitted from the image forming apparatus, and image data corresponding to each of the plurality of light emitting elements transmitted from the image forming apparatus within a period of the synchronization signal. At least one light emitting chip including an output unit configured to output a drive signal corresponding to each of the plurality of light emitting elements for driving the plurality of light emitting elements, and a drive unit configured to drive the plurality of light emitting elements based on the drive signal corresponding to each of the plurality of light emitting elements, the output unit includes a plurality of latch circuits corresponding to the plurality of light emitting elements, respectively, for latching the image data corresponding to each of the plurality of light emitting elements and outputting a driving signal corresponding to each of the plurality of light emitting elements.SELECTED DRAWING: Figure 10

Description

[Technical Field]

[0001] The present invention relates to an exposure device having a plurality of light-emitting elements, and an image forming apparatus that forms an image using the exposure device. [Background technology]

[0002] Electrophotographic image forming apparatuses expose a rotating photoconductor to light to form an electrostatic latent image on the photoconductor, and then develop the electrostatic latent image with toner to form an image. The direction parallel to the rotational axis of the photoconductor is referred to as the main scanning direction. Patent Document 1 discloses an image forming apparatus that performs exposure using an exposure device in which multiple light-emitting elements are arranged in a main scanning direction, and multiple light-emitting element rows are arranged in a sub-scanning direction corresponding to the rotational direction of the photoconductor. In Patent Document 1, multiple light-emitting chips are mounted on a substrate, each chip having electrodes, an organic electroluminescence (EL) film, and a circuit unit for illuminating the organic EL film formed on a silicon wafer. The circuit unit includes flip-flop circuits for transferring input image data in the main scanning direction and flip-flop circuits for holding the image data, each corresponding to the number of light-emitting elements. When image data is held in all of the flip-flop circuits for holding the image data, the light-emitting elements are simultaneously controlled. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-35765 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, flip-flop circuits for transferring input image data in the main scanning direction are provided in the same number as the light-emitting units, which results in an increase in the size and cost of the light-emitting chip.

[0005] In view of the above problems, an object of the present invention is to suppress the increase in size and cost of light-emitting chips. [Means for solving the problem]

[0006] According to one aspect of the present disclosure, an exposure device implemented in an image forming apparatus has one or more light-emitting chips that include a plurality of light-emitting elements, an output means that receives a synchronization signal that is periodically transmitted from the image forming apparatus, and image data corresponding to each of the plurality of light-emitting elements that is transmitted from the image forming apparatus within the period of the synchronization signal, and outputs a drive signal corresponding to each of the plurality of light-emitting elements to drive the plurality of light-emitting elements, and a drive means that drives the plurality of light-emitting elements based on the drive signal corresponding to each of the plurality of light-emitting elements, and the output means has a plurality of latch circuits corresponding to each of the plurality of light-emitting elements for latching the image data corresponding to each of the plurality of light-emitting elements and outputting a drive signal corresponding to each of the plurality of light-emitting elements. [Effects of the Invention]

[0007] According to the present disclosure, it is possible to prevent the light-emitting chip from becoming large. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic diagram of an image forming apparatus according to an embodiment. [Figure 2] FIG. 2 illustrates an exposure head and photoreceptor, according to one embodiment. [Figure 3] FIG. 2 illustrates a printed circuit board for an exposure head, according to one embodiment. [Figure 4] 1 is an illustration of the arrangement of light emitting elements within a light emitting chip according to one embodiment. [Figure 5] 1 is a plan view of a light-emitting chip according to one embodiment. [Figure 6] 1 is a cross-sectional view of a light-emitting chip according to one embodiment. [Figure 7] FIG. 2 is a control configuration diagram of a light-emitting chip according to an embodiment. [Figure 8] 10A and 10B are diagrams showing examples of signals on each signal line when accessing a register of a light-emitting chip according to one embodiment. [Figure 9] 10A and 10B are diagrams showing examples of signals on signal lines when transmitting image data to a light-emitting chip according to an embodiment. [Figure 10] FIG. 2 is a functional block diagram of a light-emitting chip, according to one embodiment. [Figure 11] FIG. 2 is a block diagram of a forwarding unit according to one embodiment. [Figure 12] FIG. 2 is a diagram illustrating the configuration of a latch unit according to one embodiment. [Figure 13] FIG. 10 is a block diagram of another latch unit according to one embodiment. [Figure 14] 4 is a timing chart of each signal in a circuit section according to one embodiment. [Figure 15] FIG. 2 is a block diagram of a current driver according to one embodiment. [Figure 16] 10 is a flowchart of a process performed by an image controller, according to one embodiment. [Figure 17] 10 is another timing chart of each signal in the circuit section according to one embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted.

[0010] First Embodiment 1 is a schematic diagram of an image forming apparatus according to this embodiment. A reading unit 100 optically reads an original placed on a platen and generates image data representing the reading result. An image creating unit 103 forms an image on a sheet based on the image data generated by the reading unit 100 or based on image data received from an external device via a network, for example.

[0011] The image forming unit 103 includes image forming units 101a, 101b, 101c, and 101d. The image forming units 101a, 101b, 101c, and 101d form black, yellow, magenta, and cyan toner images, respectively. The image forming units 101a, 101b, 101c, and 101d have the same configuration and are collectively referred to as the image forming unit 101 below. The photoconductor 102 of the image forming unit 101 is rotated clockwise in the drawing during image formation. The charger 107 charges the photoconductor 102. The exposure head 106, which is an exposure device, exposes the photoconductor 102 to light according to image data, forming an electrostatic latent image on the photoconductor 102. The developer 108 develops the electrostatic latent image on the photoconductor 102 with toner. The toner image on the photoreceptor 102 is transferred onto a sheet transported on a transfer belt 111. Note that by transferring the toner images of the photoreceptors 102 onto a sheet in an overlapping manner, it is possible to reproduce colors other than black, yellow, magenta, and cyan.

[0012] The conveying unit 105 controls the feeding and transport of sheets. Specifically, the conveying unit 105 feeds a sheet from a designated unit among the internal storage units 109a and 109b, the external storage unit 109c, and the manual feed unit 109d to a transport path of the image forming apparatus. The fed sheet is transported to the registration rollers 110. The registration rollers 110 transport the sheet onto the transfer belt 111 at a predetermined timing so that the toner images on the photoconductors 102 are transferred to the sheet. As described above, the toner image is transferred to the sheet while it is transported on the transfer belt 111. The fixing unit 104 fixes the toner image to the sheet by applying heat and pressure to the sheet onto which the toner image has been transferred. After the toner image is fixed, the sheet is discharged to the outside of the image forming apparatus by the discharge rollers 112.

[0013] 2(A) and 2(B) show the photoconductor 102 and the exposure head 106. The exposure head 106 has a light-emitting point group 201, a printed circuit board 202 on which the light-emitting point group 201 is mounted, a rod lens array 203, and a housing 204 that holds the rod lens array 203 and the printed circuit board 202. The rod lens array 203 focuses the light emitted from the light-emitting point group 201 onto the photoconductor 102, and forms an imaging spot of a predetermined size on the photoconductor 102.

[0014] 3(A) and 3(B) show the printed circuit board 202. FIG. 3(A) shows the surface on which the connector 305 is mounted, and FIG. 3(B) shows the surface on which the light-emitting point group 201 is mounted (the surface opposite to the surface on which the connector 305 is mounted). In this embodiment, the light-emitting point group 201 includes 20 light-emitting chips 400-1 to 400-20. The light-emitting chips 400-1 to 400-20 are arranged in two staggered rows along the main scanning direction. In the following description, the light-emitting chips 400-1 to 400-20 will also be collectively referred to as light-emitting chips 400. Each light-emitting chip 400 has a plurality of light-emitting points (light-emitting elements). Each light-emitting chip 400 on the printed circuit board 202 is connected to an image controller 700 (FIG. 7) serving as a control unit via a connector 305.

[0015] FIG. 4 is an explanatory diagram of a light-emitting chip 400 and the arrangement of light-emitting points 602 provided on the light-emitting chip 400. One light-emitting chip 400 has multiple sets of 748 light-emitting points 602 arranged along the main scanning direction. The multiple sets are arranged along the sub-scanning direction perpendicular to the main scanning direction. In this manner, the light-emitting chip 400 is arranged two-dimensionally along both the main scanning direction and the sub-scanning direction. In the following description, the number of sets is assumed to be four as an example. That is, in the following exemplary embodiment, the light-emitting chip 400 has four sets of 748 light-emitting points 602 arranged along the main scanning direction, that is, a total of 2992 light-emitting points 602. The pitch between adjacent light-emitting points 602 in the main scanning direction is approximately 21.16 μm, which corresponds to a resolution of 1200 dpi. Therefore, the length of one set of 748 light-emitting points 602 in the main scanning direction is approximately 15.8 mm. The pitch between adjacent light-emitting points 602 in the sub-scanning direction (length P in FIG. 4) is also approximately 21.16 μm, which corresponds to a resolution of 1200 dpi. Furthermore, the pitch between the light-emitting points 602 of two adjacent light-emitting chips 400 in the main scanning direction (length L in FIG. 4) is also approximately 21.16 μm, which corresponds to a resolution of 1200 dpi.

[0016] 5 is a plan view of the light-emitting chip 400. The light-emitting chip 400 has a plurality of light-emitting points 602 formed on a light-emitting substrate 402, which is, for example, a silicon substrate. A circuit unit 406 for controlling the light-emitting points 602 is formed on the light-emitting substrate 402. Signal lines for communicating with the image controller 700, power lines for connecting to a power source, and ground lines for connecting to ground are connected to the pads 408-1 to 408-9. The signal lines, power lines, and ground lines are, for example, wires made of gold.

[0017] FIG. 6 shows a portion of the cross section taken along line AA in FIG. 5. A plurality of lower electrodes 504 are formed on the light-emitting substrate 402. A gap of length d is provided between two adjacent lower electrodes 504. A light-emitting layer 506 is provided on the lower electrodes 504, and an upper electrode 508 is provided on the light-emitting layer 506. The upper electrode 508 is a common electrode for the plurality of lower electrodes 504. When a predetermined voltage is applied between the lower electrode 504 and the upper electrode 508, a current flows from the lower electrode 504 to the upper electrode 508, causing the light-emitting layer 506 to emit light. Therefore, the region of the light-emitting layer 506 corresponding to the region of one lower electrode 504 corresponds to one light-emitting point 602. That is, in this embodiment, the light-emitting substrate 402 includes a plurality of light-emitting points. The light-emitting points may also be called light-emitting portions.

[0018] The light-emitting layer 506 may be made of, for example, an organic EL film. Alternatively, the light-emitting layer 506 may be made of, for example, an inorganic EL film. The upper electrode 508 is made of a transparent electrode such as indium tin oxide (ITO) so as to transmit the emission wavelength of the light-emitting layer 506. In this embodiment, the entire upper electrode 508 transmits the emission wavelength of the light-emitting layer 506, but it is not necessary for the entire upper electrode 508 to transmit the emission wavelength. Specifically, it is sufficient that the region through which light from each light-emitting point 602 is emitted transmits the emission wavelength.

[0019] 6 shows one continuous light-emitting layer 506, but multiple light-emitting layers 506 each having a width equal to the width W of the lower electrode 504 may be formed on the lower electrode 504. Also, in FIG. 6, the upper electrode 508 is a single common electrode for the multiple lower electrodes 504, but multiple upper electrodes 508 each having a width equal to the width W of the lower electrode may be formed corresponding to each lower electrode 504. Also, among the lower electrodes 504 of each light-emitting chip 400, a first plurality of lower electrodes 504 may be covered with a first light-emitting layer 506, and a second plurality of lower electrodes 504 may be covered with a second light-emitting layer 506. Also, among the lower electrodes 504 of each light-emitting chip 400, a first upper electrode 508 may be commonly formed corresponding to the first plurality of lower electrodes 504, and a second upper electrode 508 may be commonly formed corresponding to the second plurality of lower electrodes 504. In such a configuration, one lower electrode 504 and the region of the light-emitting layer 506 and upper electrode 508 corresponding to the lower electrode 504 form one light-emitting point (light-emitting element) 602 .

[0020] 7 shows the control configuration of the light-emitting chip 400. The data switching unit 705 and each light-emitting chip 400 are connected by a plurality of signal lines (wires). Specifically, the data switching unit 705 and the light-emitting chip 400-n (n is an integer from 1 to 20) are connected by a signal line DATAn and a signal line WRITEn. The signal line DATAn is used by the data switching unit 705 to transmit image data to the light-emitting chip 400-n. The signal line WRITEn is used by the data switching unit 705 to write control data to a register of the light-emitting chip 400-n.

[0021] The data switching unit 705 and all the light-emitting chips 400 are connected by one signal line CLK, one signal line SYNC, and one signal line EN. The signal line CLK is used to transmit a clock signal for transmitting data on the signal lines DATAn and WRITEn. The data switching unit 705 outputs a clock signal generated based on a reference clock signal from the clock generating unit 702 to the signal line CLK. The signals transmitted to the signal lines SYNC and EN will be described later.

[0022] The CPU 701 controls the entire image forming apparatus. The image data generation unit 703 performs various image processing such as halftoning on image data received from the reading unit 100 or an external device, and generates image data for controlling the on / off of light emission of the light-emitting points 602 of each light-emitting chip 400. The image data generation unit 703 transmits the generated image data to the data switching unit 705. The register access unit 704 receives control data to be written to the register in each light-emitting chip 400 from the CPU 701 and transmits it to the data switching unit 705.

[0023] FIG. 8 shows the signals on each signal line when control data is written to the register of the light-emitting chip 400. An enable signal that is at a high level during communication and indicates that communication is in progress is output to the signal line EN. The data switching unit 705 transmits a start bit to the signal line WRITEn in synchronization with the rising edge of the enable signal. Next, the data switching unit 705 transmits a write identification bit indicating a write operation, and then transmits the address of the register to which the control data is to be written (4 bits in this example) and the control data (8 bits in this example). When writing to the register, the data switching unit 705 sets the frequency of the clock signal transmitted to the signal line CLK to, for example, 3 MHz.

[0024] FIG. 9 shows signals on each signal line when image data is transmitted to each light-emitting chip 400. A periodic line synchronization signal indicating the exposure timing of one line on the photosensitive element 102 is output to the signal line SYNC. If the peripheral speed of the photosensitive element 102 is 200 mm / s and the resolution in the sub-scanning direction is 1200 dpi (approximately 21.16 μm), the line synchronization signal is output at a cycle of approximately 105.8 μs. The data switching unit 705 transmits image data to the signal lines DATA1 to DATA20 in synchronization with the rising edge of the line synchronization signal. In this embodiment, each light-emitting chip 400 has 2992 light-emitting points 602, and therefore, image data indicating whether each of the 2992 light-emitting points 602 is emitting or not emitting light must be transmitted to each light-emitting chip 400 within a cycle of approximately 105.8 μs. In this example, in order to transmit image data for a total of 2,992 light-emitting points 602 within a period of approximately 105.8 μs, as shown in FIG. 9, when transmitting image data, the data switching unit 705 sets the frequency of the clock signal transmitted to the signal line CLK to 30 MHz.

[0025] FIG. 10 is a functional block diagram of one light-emitting chip 400-n. As also shown in FIG. 5, the light-emitting chip 400 has nine pads 408-1 to 408-9. The pads 408-1 and 408-2 are connected to a power supply voltage VCC via a power supply line. Power is supplied from this power supply voltage VCC to each circuit of the circuit unit 406 of the light-emitting chip 400. The pads 408-3 and 408-4 are connected to ground via a ground line. Each circuit of the circuit unit 406 and the upper electrode 508 are connected to ground via the pads 408-3 and 408-4. The signal line CLK is connected to the transfer unit 1003, the register 1102, and the latch units 1004-001 to 1004-748 via the pad 408-5. The signal lines SYNC and DATAn are connected to the transfer unit 1003 via the pads 408-6 and 408-7. The signal lines EN and WRITEn are connected via pads 408-8 and 408-9 to the register 1102. As described above, control data indicating control information is stored in the register 1102. The control information will be described in detail later.

[0026] 11 to 14, the operation of the transfer unit 1003 and latch units 1004-001 to 1004-748 (collectively referred to as the latch unit 1004) will be described below. The transfer unit 1003 receives image data D1, D2, D3, ... D2992, each indicating whether one light-emitting point 602 is lit or not, in synchronization with the clock signal, starting from a line synchronization signal from the signal line SYNC. Fig. 14(A) shows the state in which the transfer unit 1003 has received image data D1 to D12.

[0027] FIG. 11 is a configuration diagram of the transfer unit 1003. The transfer unit 1003 receives a clock signal from a signal line CLK, a line synchronization signal from a signal line SYNC, and image data from a signal line DATAn. The D flip-flops 1101-1 to 1101-8 operate in accordance with the clock signal. The D flip-flop 1101-1 sequentially outputs the image data received from DATAn to a signal line PDATA4. The D flip-flop 1101-2 delays the image data received from DATAn by one clock from the image data output by the D flip-flop 1101-1, and outputs it to a signal line PDATA3. Similarly, the D flip-flops 1101-3 and 1101-4 delay the image data received from DATAn by two clocks and three clocks from the image data output by the D flip-flop 1101-1, and output it to signal lines PDATA2 and PDATA1.

[0028] 14(B) shows image data that the transfer unit 1003 outputs to signal lines PDATA1 to PDATA4. As shown in FIG. 14(B), at the timing when the transfer unit 1003 outputs image data D4 to signal line PDATA4, the transfer unit 1003 outputs image data D3, D2, and D1 to signal lines PDATA3, PDATA2, and PDATA1. More generally, at the timing when the transfer unit 1003 outputs image data D(4m) (m is an integer from 1 to 748) to signal line PDATA4, the transfer unit 1003 outputs image data D(4m-1), D(4m-2), and D(4m-3) to signal lines PDATA3, PDATA2, and PDATA1.

[0029] The transfer unit 1003 delays the line synchronization signal using the D flip-flops 1101-5 to 1101-8, and outputs the first latch signal to the signal line LAT1 at the timing when the transfer unit 1003 outputs D4 to the signal line PDATA4.

[0030] FIG. 12 is a configuration diagram of the latch unit 1004-001. D flip-flops 1202-1 to 1202-4 and latch circuits 1201-1 to 1201-4 operate in accordance with a clock signal from a signal line CLK. Image data from signal lines PDATA4 to PDATA1 and a first latch signal from signal line LAT1 are input to the latch circuits 1201-1 to 1201-4. When the latch circuits 1201-1 to 1201-4 receive the first latch signal from signal line LAT1, they latch the values ​​currently being output to signal lines PDATA4 to PDATA1, and output drive signals based on the latched values ​​to signal lines PON1-4 to PON1-1, as shown in FIG. 14(C). According to FIG. 14(C), signal lines PON1-1 to PON1-4 output drive signals based on image data D1 to D4. In this embodiment, as described with reference to FIG. 4, one light-emitting chip 400 has a structure in which four sets of 748 light-emitting points 602 are arranged in the sub-scanning direction, each set being a set of 748 light-emitting points 602 arranged in the main scanning direction. For example, the light-emitting points 602 in each set are numbered from 1 to 748 along the X direction (corresponding to the main scanning direction) in FIG. 5. In this case, the drive signals output to the signal lines PON1-4 to PON1-1 are drive signals for the first light-emitting point 602 in each of the four sets. The drive signals are input to the current driver 1104. The latch unit 1004-001 continues to output drive signals based on the image data D1 to D4 until it receives a first latch signal based on the next line synchronization signal. In other words, the drive signals based on the image data D1 to D4 are output for the period of two consecutive line synchronization signals (approximately 105.8 μs in this example). Furthermore, the latch unit 1004-001 delays the first latched signal using the D flip-flops 1202-1 to 1202-4, and outputs the second latched signal to the signal line LAT2 at the timing when the transfer unit 1003 outputs D8 to the signal line PDATA4.

[0031] FIG. 13 is a configuration diagram of the latch unit 1004-002. The D flip-flops 1302-1 to 1302-4 and latch circuits 1301-1 to 1301-4 operate in accordance with a clock signal from a signal line CLK. The latch circuits 1301-1 to 1301-4 receive image data from signal lines PDATA4 to PDATA1 and a second latch signal from signal line LAT2. When the latch circuits 1301-1 to 1301-4 receive the second latch signal from signal line LAT2, they latch the values ​​currently being output to signal lines PDATA4 to PDATA1, and output drive signals based on the latched values ​​to signal lines PON2-4 to PON2-1, as shown in FIG. 14(D). The drive signals output to the signal lines PON2-4 to PON2-1 are drive signals for the light-emitting point 602 adjacent in the main scanning direction (to the right in FIG. 5) to the light-emitting point 602 driven by the drive signals output to the signal lines PON1-4 to PON1-1. That is, the drive signals output to the signal lines PON2-4 to PON2-1 are drive signals for the second light-emitting point 602 in each of the four sets. As shown in FIG. 14(D), the signal lines PON2-1 to PON2-4 output drive signals based on image data D5 to D8. The drive signals are input to the current driver 1104. The latch unit 1004-002 continues to output drive signals based on image data D5 to D8 until it receives a second latch signal based on the next line synchronization signal. That is, the drive signals based on image data D5 to D8 are output for the period of two consecutive line synchronization signals (approximately 105.8 μs in this example). Furthermore, the latch unit 1004-002 delays the second latch signal using the D flip-flops 1302-1 to 1302-4, and outputs a third latch signal to the signal line LAT3 at the timing when the transfer unit 1003 outputs image data D12 to the signal line PDATA4.

[0032] The latch units 1004-003 to 1004-748 operate in a similar manner. In summary, each of the latch units 1004-m (m is an integer from 1 to 748) has four latch circuits. The four latch circuits of the latch unit 1004-m latch image data D(4m), D(4m-1), D(4m-2), and D4(m-3) based on the m-th latch signal, respectively, and output a drive signal based on the latched image data to the current driver 1104 for the duration of two consecutive line synchronization signals. The four latch circuits of the latch unit 1004-m correspond to the m-th light-emitting point 602 among the 748 light-emitting points 602 arranged along the main scanning direction in each of the first to fourth sets. That is, the four latch circuits of the latch unit 1004-m output a drive signal for the m-th light-emitting point 602 in each of the first to fourth sets. Furthermore, latch units 1004-m other than m=748 generate the (m+1)th latch signal based on the mth latch signal and output it to latch unit 1004-(m+1). In this way, latch units 1004-001 to 1004-748 each output a drive signal that controls whether each light-emitting point 602 emits light to the current driver 1104 for the period of two consecutive line synchronization signals.

[0033] FIG. 17 shows the relationship between the line synchronization signal on the signal line SYNC, the first and second latch signals on the signals LAT1 and LAT2, and the drive signals output to the signal lines PON1-1 to PON1-4 and PON2-1 to PON2-4. As described above, the period of the line synchronization signal is approximately 105.8 μs. The periods of the first and second latch signals are the same as that of the line synchronization signal, approximately 105.8 μs. The timing of the second latch signal is four clocks later than the first latch signal. More generally, the timing of the q+1th latch signal (q is an integer from 1 to 747) is four clocks later than the qth latch signal.

[0034] The transfer unit 1003 sequentially receives image data D1[1] to D2992[1] in synchronization with the first line synchronization signal in FIG. 17. The transfer unit 1003 also sequentially receives image data D1[2] to D2992[2] in synchronization with the second line synchronization signal in FIG. 17. The four latch circuits of the latch unit 1004-001 output drive signals based on the image data D1[1] to D4[1] to the signal lines PON1-1 to PON1-4 from the timing of the first latch signal based on the first line synchronization signal in FIG. 17. The output of drive signals based on the image data D1[1] to D4[1] continues until the first latch signal based on the second line synchronization signal is received. When the four latch circuits of the latch unit 1004-001 receive the first latch signal based on the second line synchronization signal, they output drive signals based on the image data D1[2] to D4[2] to the signal lines PON1-1 to PON1-4. Similarly, the four latch circuits of the latch unit 1004-002 output drive signals based on image data D5[1] to D8[1] to the signal lines PON2-1 to PON2-4 from the timing of the second latch signal based on the first line synchronization signal. The output of drive signals based on image data D5[1] to D8[1] continues until the second latch signal based on the second line synchronization signal is received. When the four latch circuits of the latch unit 1004-002 receive the second latch signal based on the second line synchronization signal, they output drive signals based on image data D5[2] to D8[2] to the signal lines PON2-1 to PON2-4. The same applies to the latch units 1004-003 to 1004-748.

[0035] In this embodiment, the transfer unit 1003 and the latch unit 1004 constitute an output unit that receives image data corresponding to each of the multiple light-emitting points 602 and outputs drive signals for the corresponding light-emitting points 602 based on the received image data. More specifically, each of the 748 latch units 1004-001 to 1004-748 in this embodiment has four latch circuits, and therefore the output unit has a total of 2992 latch circuits. Each latch circuit corresponds to one of the 2992 light-emitting points 602 included in one light-emitting chip 400. Each latch circuit latches image data for the corresponding light-emitting point 602 and outputs a drive signal for the corresponding light-emitting point 602 based on the latched image data.

[0036] FIG. 15 shows the configuration of the current driver 1104. Note that FIG. 15 shows only a circuit portion corresponding to one light-emitting point 602. The light-emitting chip 400 according to this embodiment has a total of 2992 light-emitting points 602, and therefore, the light-emitting chip 400 has 2992 circuit portions as shown in FIG. 15. The DAC 1501 outputs an analog voltage corresponding to a digital value indicated by control data stored in the register 1102. The FET 1502 is a P-channel MOSFET, and its source terminal is connected to a power supply voltage VCC and its drain terminal is connected to the source terminal of the FET 1503. The analog voltage output by the DAC 1501 is applied to the gate terminal of the FET 1502. The FET 1503 is also a P-channel MOSFET, and its drain terminal is connected to the lower electrode 504. A drive signal output from the image data storage unit 1103 is input to the gate terminal of the FET 1503 via the switching circuit 1504. The drive signal is a binary signal of high level or low level, and when it is at high level, the FET 1503 is on, and when it is at low level, the FET 1503 is off.

[0037] While FET 1503 is on, a current flows from the power supply voltage VCC to the light-emitting layer 506 via FET 1502 and FET 1503, causing the light-emitting points 602 to emit light. The light emission intensity of the light-emitting points 602 changes according to the current flowing through the light-emitting layer 506, and the value of this current is controlled by the analog voltage output by DAC 1501. In other words, the light emission intensity of each light-emitting point 602 is controlled by control data stored in register 1102. Note that the control data may individually indicate the digital values ​​of DAC 1501 corresponding to each light-emitting point 602, or may indicate one digital value for each group of multiple light-emitting points 602.

[0038] The switching circuit 1504 is provided to switch between a normal state in which a drive signal is applied to the gate terminal of the FET 1503 and a test state. In the test state, the switching circuit 1504 applies a high-level signal to the gate terminal of the FET 1503 to forcibly turn on the FET 1503. The switching between the normal state and the test state is also performed based on the control data stored in the register 1102. The test state can be used to, for example, cause any light-emitting point 602 to emit light when the exposure head 106 is manufactured.

[0039] FIG. 16 is a flowchart of the process executed by the image controller 700 when a print request is received from a user. In S10, the image controller 700 writes control data to the register 1102 of each light-emitting chip 400 to set each switching circuit 1504 to a normal state. In S11, the image controller 700 sets the digital value to be set in the DAC 1501 corresponding to each light-emitting point 602 in the register 1102 of each light-emitting chip 400. Next, when it is time to start image formation, the image controller 700 transmits image data in S12 and starts exposing the photoconductor 102. In S13, the image controller 700 determines whether image formation is complete. If image formation is not complete, the process repeats from S12. On the other hand, if image formation is complete, the image controller 700 ends the process of FIG. 13.

[0040] When each light-emitting point 602 is to be made to emit light during manufacturing of the exposure head 106, the image controller 700 first sets in the register 1102 a digital value to be set in the DAC 1501 corresponding to the target light-emitting point 602. The image controller 700 then writes control data to the register 1102 for changing the state of the switching circuit 1504 to a test state. After the test is completed, the image controller 700 writes control data for changing the state of the switching circuit 1504 to a normal state. The light-emitting points 602 to be put into the test state may be specified independently for each light-emitting point 602, or may be specified for each light-emitting point group including two or more light-emitting points 602, for example, all of the light-emitting points 602 may be specified collectively.

[0041] As described above, in this embodiment, the latch unit 1004-m latches the image data D(4m), D(4m-1), D(4m-2), and D4(m-3) when the m-th latch signal is input, and outputs a drive signal based on the latched image data to the current drive unit 1104. With this configuration, it is possible to light up multiple light-emitting points 602 based on image data transmitted via serial communication, without providing flip-flop circuits for transferring the input image data in the main scanning direction corresponding to the number of light-emitting units. In other words, it is possible to prevent the light-emitting chip from becoming larger and the cost of the light-emitting chip from increasing, which would be caused by providing flip-flop circuits for transferring the input image data in the main scanning direction corresponding to the number of light-emitting units. In other words, it is possible to prevent the light-emitting chip from becoming larger and the cost from increasing compared to conventional methods.

[0042] Generally, the amount of light emitted by an organic EL film is smaller than that of an LED formed of, for example, gallium arsenide. In this embodiment, a drive signal that controls whether each light-emitting point 602 emits light is output to the current driver 1104 only during the period of two consecutive line synchronization signals. That is, in this embodiment, the light-emitting points 602 can be made to emit light during the period of two consecutive line synchronization signals. As a result, the exposure time of the photoconductor 102 can be extended compared to a configuration in which the light-emitting points 602 emit light only during a portion of the period of two consecutive line synchronization signals. As a result, the photoconductor 102 can be exposed to light for the amount of time necessary to form a toner image, and the toner image is properly formed on the photoconductor 102. In other words, it is possible to prevent the photoconductor 102 from being underexposed for the amount of time necessary to form a toner image due to the light-emitting points 602 emitting light only during a portion of the period of two consecutive line synchronization signals.

[0043] When the FET 1503 is turned on, the voltage of the power supply line fluctuates due to the current output from the power supply VCC being supplied to the light-emitting points 602, which may result in radiation noise from the power supply line. In this embodiment, all of the light-emitting points 602 provided on the light-emitting chip 400 are not lit simultaneously, but the light-emitting points 602 are sequentially lit in groups of four. As a result, fluctuations in the voltage of the power supply line are suppressed compared to when the FETs 1503 corresponding to the respective light-emitting points 602 are simultaneously turned on to simultaneously light up all of the light-emitting points 602 provided on the light-emitting chip 400. As a result, radiation noise generated from the power supply line can be reduced.

[0044] In this embodiment, each light-emitting chip 400 has four sets of 748 light-emitting points 602 arranged along the main scanning direction. Therefore, a total of 2,992 latch circuits corresponding to each light-emitting point 602 are grouped into 748 groups of four, each corresponding to the number of sets, and one latch unit 1004 is provided for each group. Since each group includes four latch circuits, the transfer unit 1003 sequentially transfers image data to four signal lines PDATA1 to PDATA4. However, for example, the number of latch circuits included in each group may be an integer multiple of the number of sets. For example, for a light-emitting chip 400 having four sets of 748 light-emitting points 602 arranged along the main scanning direction, if the number of latch circuits included in each group is double the number of sets, the number of groups becomes 374, and the number of latch units 1004 also becomes 374. In this case, the transfer unit 1003 sequentially transfers image data to eight signal lines. Note that the present invention is not limited to setting the number of latch circuits included in one group to an integer multiple of the number of sets, and may also set it to, for example, one integer division of the number of sets. The number of latch circuits included in one group may also be set independently of the number of sets. Furthermore, the number of light-emitting points 602 (or the number of latch circuits) included in each group does not have to be the same. In other words, the number of light-emitting points 602 (or the number of latch circuits) included in each group can be any number equal to or greater than one.

[0045] In the above embodiment, specific numerical values ​​are used for explanation purposes. However, these specific numerical values ​​are merely examples, and the present invention is not limited to the specific numerical values ​​used in the embodiment. Specifically, the number of light-emitting chips 400 provided on one printed circuit board 202 is not limited to 20 and can be any number equal to or greater than one. Furthermore, the number of light-emitting points 602 included in each light-emitting chip 400 is not limited to 2992 and can be any number. In this embodiment, one light-emitting chip 400 has four sets of 748 light-emitting points arranged along the main scanning direction, but the number of sets can be any number equal to or greater than one. Furthermore, the light-emitting points 602 are arranged in the main scanning direction at a pitch of approximately 21.16 μm, which corresponds to a resolution of 1200 dpi. However, the arrangement interval of the light-emitting points 602 may also be other values.

[0046] In the above embodiment, the image forming apparatus transfers the toner images formed on the photoconductors 102 onto a sheet conveyed on the transfer belt 111. However, the image forming apparatus may transfer the toner images on the photoconductors 102 onto a sheet via an intermediate transfer body. The image forming apparatus may be a color image forming apparatus that forms an image using toners of multiple colors, or a monochrome image forming apparatus that forms an image using toner of one color.

[0047] [Other embodiments] The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program.The present invention can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0048] The disclosure of this embodiment includes the following configuration. (Configuration 1) An exposure device mounted in an image forming apparatus, A plurality of light-emitting elements; an output unit that receives a synchronization signal periodically transmitted from the image forming apparatus and image data corresponding to each of the plurality of light-emitting elements transmitted from the image forming apparatus within the period of the synchronization signal, and outputs a drive signal corresponding to each of the plurality of light-emitting elements to drive the plurality of light-emitting elements; a driving means for driving the plurality of light-emitting elements based on the driving signals corresponding to the plurality of light-emitting elements; One or more light-emitting chips each having The output means has a plurality of latch circuits corresponding to the plurality of light-emitting elements, respectively, for latching the image data corresponding to each of the plurality of light-emitting elements and outputting a drive signal corresponding to each of the plurality of light-emitting elements. (Configuration 2) 2. The exposure device according to configuration 1, wherein the synchronization signal is a signal indicating exposure timing for one line of a photosensitive member mounted in the image forming device. (Configuration 3) 3. The exposure apparatus according to configuration 1 or 2, wherein the output means outputs the drive signal corresponding to each of the plurality of light-emitting elements for a period equal to the cycle of the synchronization signal. (Configuration 4) the image data corresponding to each of the plurality of light-emitting elements is input to the plurality of latch circuits in order; 4. The exposure apparatus according to any one of configurations 1 to 3, wherein the output means generates latch signals corresponding to the plurality of latch circuits, each of which indicates a timing for latching the image data to the plurality of latch circuits, based on the synchronization signal. (Configuration 5) 5. The exposure apparatus according to configuration 4, wherein the period of the latch signal corresponding to each of the plurality of latch circuits is equal to the period of the synchronization signal. (Configuration 6) the plurality of latch circuits are grouped into a plurality of groups, each group including two or more latch circuits; 6. The exposure apparatus according to configuration 4 or 5, wherein the output means generates the latch signals corresponding to the two or more latch circuits included in the same group at the same timing based on the synchronization signal. (Configuration 7) the number of the two or more latch circuits included in each of the plurality of groups is the same; the output means includes a transfer means for receiving the image data corresponding to each of the plurality of light-emitting elements, and outputting the image data to each of a plurality of signal lines, the number of which is the same as the number of the two or more latch circuits included in each of the plurality of groups, in order; 7. The exposure apparatus according to configuration 6, wherein each of the two or more latch circuits included in each of the plurality of groups receives the image data from one signal line of the plurality of signal lines. (Configuration 8) 8. The exposure apparatus according to configuration 7, wherein the light emitting elements corresponding to the image data output by the transfer means to each of the plurality of signal lines at the same timing are different. (Configuration 9) the plurality of light-emitting elements are two-dimensionally arranged along both a main scanning direction parallel to a rotation axis of a photosensitive member mounted in the image forming apparatus and a sub-scanning direction perpendicular to the main scanning direction, 9. The exposure apparatus according to configuration 7 or 8, wherein the number of the two or more latch circuits included in each of the plurality of groups is an integer multiple of the number of light-emitting elements arranged along the sub-scanning direction. (Configuration 10) the light-emitting chip further comprises a storage means for storing control information; An exposure apparatus according to any one of configurations 1 to 9, wherein the driving means is provided with a switching means for switching, based on the control information, whether to drive the light-emitting element corresponding to the driving signal using the driving signal, or to drive the light-emitting element corresponding to the driving signal regardless of the driving signal. (Configuration 11) 11. The exposure apparatus according to configuration 10, wherein the control information causes the light emitting element corresponding to the drive signal to emit light when the light emitting element is driven regardless of the drive signal. (Configuration 12) 12. The exposure apparatus according to configuration 10 or 11, wherein the control information collectively indicates one or more of the plurality of light-emitting elements that are to be driven without using the drive signal. (Configuration 13) 13. The exposure apparatus according to any one of configurations 1 to 12, wherein the plurality of light-emitting elements include an organic EL film. (Configuration 14) A photoreceptor; an exposure device according to any one of configurations 1 to 13 that exposes the photosensitive member; An image forming apparatus comprising:

[0049] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0050] 602: Light emitting point, 1003: Transfer unit, 1004-001 to 1004-748: Latch unit

Claims

1. An exposure device mounted in an image forming apparatus, A plurality of light-emitting elements; an output unit that receives a synchronization signal periodically transmitted from the image forming apparatus and image data corresponding to each of the plurality of light-emitting elements transmitted from the image forming apparatus within the period of the synchronization signal, and outputs a drive signal corresponding to each of the plurality of light-emitting elements to drive the plurality of light-emitting elements; a driving means for driving the plurality of light-emitting elements based on the driving signals corresponding to the plurality of light-emitting elements; One or more light-emitting chips each having The output means has a plurality of latch circuits corresponding to the plurality of light-emitting elements, respectively, for latching the image data corresponding to each of the plurality of light-emitting elements and outputting a drive signal corresponding to each of the plurality of light-emitting elements.

2. 2. The exposure device according to claim 1, wherein the synchronization signal is a signal indicating exposure timing for one line of a photosensitive member mounted in the image forming apparatus.

3. 2. The exposure apparatus according to claim 1, wherein said output means outputs said drive signals corresponding to said plurality of light-emitting elements for a period equal to the cycle of said synchronization signal.

4. the image data corresponding to each of the plurality of light-emitting elements is input to the plurality of latch circuits in order; 2. The exposure apparatus according to claim 1, wherein said output means generates, based on said synchronization signal, latch signals corresponding to said plurality of latch circuits, each of which indicates a timing for latching said image data to said plurality of latch circuits.

5. 5. The exposure apparatus according to claim 4, wherein the period of the latch signal corresponding to each of the plurality of latch circuits is equal to the period of the synchronization signal.

6. the plurality of latch circuits are grouped into a plurality of groups, each group including two or more latch circuits; 5. The exposure apparatus according to claim 4, wherein said output means generates said latch signals corresponding to said two or more latch circuits included in the same group at the same timing based on said synchronization signal.

7. the number of the two or more latch circuits included in each of the plurality of groups is the same; the output means includes a transfer means for receiving the image data corresponding to each of the plurality of light-emitting elements, and outputting the image data to each of a plurality of signal lines, the number of which is the same as the number of the two or more latch circuits included in each of the plurality of groups, in order; 7. The exposure apparatus according to claim 6, wherein each of the two or more latch circuits included in each of the plurality of groups receives the image data from one signal line of the plurality of signal lines.

8. 8. The exposure apparatus according to claim 7, wherein the light emitting elements corresponding to the image data output by the transfer means to each of the plurality of signal lines at the same timing are different.

9. the plurality of light-emitting elements are two-dimensionally arranged along both a main scanning direction parallel to a rotation axis of a photosensitive member mounted in the image forming apparatus and a sub-scanning direction perpendicular to the main scanning direction, 8. The exposure apparatus according to claim 7, wherein the number of the two or more latch circuits included in each of the plurality of groups is an integer multiple of the number of light-emitting elements arranged along the sub-scanning direction.

10. the light-emitting chip further comprises a storage means for storing control information; The exposure apparatus according to claim 1, wherein the driving means is provided with a switching means for switching, based on the control information, whether to drive the light-emitting element corresponding to the drive signal using the drive signal or to drive the light-emitting element corresponding to the drive signal regardless of the drive signal.

11. The exposure apparatus according to claim 10 , wherein the control information causes the light emitting element corresponding to the drive signal to emit light when the light emitting element is driven regardless of the drive signal.

12. 11. The exposure apparatus according to claim 10, wherein the control information collectively indicates one or more of the plurality of light-emitting elements that are to be driven independently of the drive signal.

13. The exposure apparatus according to claim 1 , wherein the plurality of light-emitting elements include an organic EL film.

14. A photoreceptor; an exposure device according to any one of claims 1 to 13 that exposes the photosensitive member; An image forming apparatus comprising:

Images