Information processing system, quantum circuit generation method, and program

Abstract

To provide a method and a program for generating an approximate quantum circuit which is easily executed on a quantum computer.SOLUTION: The processor acquires a model V1 and a degree set {p} that is a set of candidates of a degree p of a piecewise polynomial V1 approximately representing the model V2, and divides a continuous section in which an upper bound indicating an upper bound of a maximum value of a difference between the model V1 and the piecewise polynomial V2 in the continuous section is equal to or less than a permissible error δ into a number of divided sections equal to or less than the 2m. A piecewise polynomial p1 is calculated by optimizing a p1 degree polynomial corresponding to a specific degree V1 to model functions V2 for each divided section using predetermined spline interpolation, and a quantum circuit representing diagonalized unitary operators corresponding to the piecewise polynomial V2 is generated based on the calculated piecewise polynomial V2.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to an information processing system, a quantum circuit generation method, and a program. [Background technology]

[0002] Non-Patent Document 1 discloses an example of a technique for approximately implementing a function as a quantum circuit using a diagonal unitary matrix. [Prior art documents] [Non-patent literature]

[0003] [Non-Patent Document 1] Welch et.al., New J. Phys. 16, 2014 Summary of the Invention [Problem to be solved by the invention]

[0004] However, increasing the accuracy of the function approximation increases the computational load required to obtain a quantum circuit that approximately represents the function and the circuit depth of the quantum circuit, which may result in a quantum circuit that is not practical to run on a quantum computer. [Means for solving the problem]

[0005] According to one aspect of the present invention, there is provided an information processing system comprising at least one processor configured to execute a program for executing the following steps: in the acquisition step, a model function V1, a tolerance δ required for a piecewise polynomial V2 that approximately represents the model function V1, and a degree set {p} that is a set of candidates for the degree p of the piecewise polynomial V2 are acquired, the model function V1 outputs a scalar value in response to an input and is defined by at least one continuous interval; in the division step, two continuous intervals are selected based on one specific degree p1 selected from the degree set {p} and a division parameter m that indicates an upper limit of the number of divisions of the continuous intervals, such that an upper bound function that indicates an upper bound of the maximum value of the difference between the model function V1 and the piecewise polynomial V2 in the continuous intervals is equal to or smaller than the tolerance δ; m The upper bound function is independent of the variables for determining the piecewise polynomial V2, and is determined by the tolerance δ and the (p1+1)th derivative V1 of the model function V1 corresponding to the specific order p1. (p1+1) and a division parameter m, wherein in the approximation formula calculation step, a piecewise polynomial V2 is calculated by optimizing a p1-degree polynomial corresponding to a specific degree p1 to a model function V1 for each division interval using a predetermined spline interpolation, and in the circuit generation step, a quantum circuit representing a diagonalized unitary operator corresponding to the piecewise polynomial V2 is generated based on the calculated piecewise polynomial V2, wherein the quantum circuit is configured to operate on n computation qubits encoded to represent positions in continuous intervals, and the operation amount of a quantum gate operation included in the quantum circuit is determined based on the coefficients of the piecewise polynomial V2.

[0006] According to this information processing system, it is possible to obtain an approximate quantum circuit that is easy to execute on a quantum computer within an appropriate tolerance range depending on the approximation accuracy of the function. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a configuration diagram illustrating an information processing system 1. FIG. [Figure 2]FIG. 2 is a block diagram showing a hardware configuration of an information processing device 2. [Figure 3] FIG. 2 is a block diagram showing the hardware configuration of a quantum computer 3. [Figure 4] FIG. 2 is a block diagram showing the hardware configuration of a user terminal 4. [Figure 5] FIG. 2 is a block diagram showing the functional configuration of a processor 23. [Figure 6] 1 is an activity diagram showing an overview of information processing executed in the information processing system 1. FIG. [Figure 7] FIG. 10 is an activity diagram showing an example of the flow of processing (activity A4) based on high-order piecewise polynomials. [Figure 8] FIG. 10 is a diagram showing an example of a quantum circuit when the value of the specific degree p1 is fixed to 2 or more. [Figure 9] FIG. 10 is a diagram illustrating a configuration example of a polynomial phase gate 511 when n=4 and p1=2. [Figure 10] FIG. 10 is a diagram illustrating an example of the configuration of a quantum comparator 512 using quantum Fourier transform (QFT) operations. [Figure 11] FIG. 10 illustrates an example of the results of processing based on high-order piecewise polynomials. [Figure 12] FIG. 10 is an activity diagram showing an example of the flow of processing (activity A5) based on a linear piecewise polynomial. [Figure 13] 10 is a diagram illustrating an example of a quantum circuit when the value of a specific degree p1 is fixed to 1. FIG. [Figure 14] FIG. 10 is a diagram showing an example of the configuration of a differential action operation 62. [Figure 15] FIG. 10 is a diagram illustrating an example of the configuration of an increment operator U+1. [Figure 16] FIG. 2 is a diagram illustrating an example of the configuration of a quantum circuit 7 corresponding to a Walsh operator. [Figure 17] FIG. 10 illustrates an example of the results of processing based on a linear piecewise polynomial. [Figure 18] FIG. 1 is an activity diagram illustrating an example of a process flow based on variable piecewise polynomials. DETAILED DESCRIPTION OF THE INVENTION

[0008] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the accompanying drawings. Various features shown in the following embodiments can be combined with each other.

[0009] Incidentally, the program for realizing the software appearing in one embodiment may be provided as a non-transitory computer-readable medium, or may be provided so that it can be downloaded from an external server, or may be provided so that the program is started on an external computer and its functions are realized on a client terminal (so-called cloud computing).

[0010] Furthermore, various information processing according to an embodiment may realize input and output corresponding to the input. Here, the form of information referenced in such information processing (hereinafter referred to as reference information) is not limited as long as an output is obtained as a result of the input. The reference information may be, for example, rule-based information such as a database, a lookup table, or a predetermined function (including a decision formula such as a regression formula constructed using a statistical method), a trained model that has previously trained the correlation between input and output, or a large-scale language model that can output a desired result by inputting a prompt.

[0011] In one embodiment, a "unit" may include, for example, a combination of hardware resources implemented by a circuit in the broad sense and software information processing that can be specifically realized by these hardware resources. In one embodiment, various information is handled, and this information is represented, for example, by physical values ​​of signal values ​​representing voltage and current, high and low signal values ​​as a binary bit set consisting of 0 or 1, or quantum superposition (so-called quantum bits), and communication and calculations can be performed on a circuit in the broad sense.

[0012] Furthermore, a circuit in the broad sense is a circuit realized by at least an appropriate combination of a circuit, circuitry, processor, memory, etc. The processor may be a general-purpose processor or a dedicated circuit. That is, it includes an application specific integrated circuit (ASIC), a programmable logic device (e.g., a simple programmable logic device (SPLD), a complex programmable logic device (CPLD), and a field programmable gate array (FPGA)), etc.

[0013] 1. Hardware Configuration In this section, the hardware configuration of the information processing system 1 according to this embodiment will be described. <Information Processing System 1> FIG. 1 is a configuration diagram showing an information processing system 1. The information processing system 1 includes an information processing device 2, at least one quantum computer 3, and a user terminal 4. The information processing device 2, the quantum computer 3, and the user terminal 4 are configured to be able to communicate with each other via a telecommunications line. In one embodiment, the information processing system 1 is made up of one or more devices or components. For example, if the information processing system 1 is made up of only the information processing device 2, the information processing system 1 can be the information processing device 2. These components will be described below.

[0014] <Information processing device 2> 2 is a block diagram showing the hardware configuration of the information processing device 2. The information processing device 2 includes a communication unit 21, a storage unit 22, and a processor 23, and these components are electrically connected via a communication bus 20 inside the information processing device 2. Each component will be further described.

[0015] <Communications Department 21> The communication unit 21 is preferably a wired communication means such as USB, IEEE1394, Thunderbolt (registered trademark), wired LAN network communication, etc., but may also include wireless LAN network communication, mobile communication such as 3G / LTE / 5G, BLUETOOTH (registered trademark) communication, etc. as needed. In other words, it is more preferable to implement it as a collection of multiple communication means. In other words, the information processing device 2 may communicate various information from the outside via the communication unit 21 and the network.

[0016] <Storage section 22> The storage unit 22 stores various pieces of information defined above. This can be implemented, for example, as a storage device such as a solid state drive (SSD) that stores various programs and the like related to the information processing device 2 executed by the processor 23, or as a memory such as a random access memory (RAM) that stores temporarily required information (arguments, arrays, etc.) related to the program operations. The storage unit 22 stores various programs, variables, etc. related to the information processing device 2 executed by the processor 23.

[0017] <Processor 23> The processor 23 processes and controls the overall operations related to the information processing device 2. The processor 23 is, for example, a central processing unit (CPU) not shown. The processor 23 realizes various functions related to the information processing device 2 by reading out predetermined programs stored in the storage unit 22. In other words, information processing by software stored in the storage unit 22 is specifically realized by the processor 23, which is an example of hardware, and can be executed as each functional unit included in the processor 23. These will be described in more detail in the next section. Note that the processor 23 is not limited to being single, and multiple processors 23 may be provided for each function. A combination of these may also be used.

[0018] The processor 23 is configured as an acquisition unit to acquire various pieces of information related to quantum computing from the quantum computer 3 and the user terminal 4. The acquisition unit 231 can be configured to acquire various pieces of information by reading out various pieces of information stored in a storage area that is at least a part of the memory unit 22 and writing the read out information into a working area that is at least a part of the memory unit 22. The storage area is, for example, an area of ​​the memory unit 22 that is implemented as a storage device such as an SSD. The working area is, for example, an area that is implemented as a memory such as a RAM.

[0019] The processor 23 is configured as a quantum operation unit to be able to perform various quantum operations on the quantum bits 320. The circuit generation unit 234 may be configured to perform quantum operations directly on the quantum bits 320, or may be configured to send a command to cause the quantum processor 33 to perform a quantum operation. The circuit generation unit 234 of this embodiment causes the quantum processor 33 to perform a quantum operation by sending various quantum circuits to the quantum processor 33.

[0020] The processor 23, as a display processing unit, is configured to be able to display various types of information. The information can be presented to a user via the display unit 44 or another device. In such a case, for example, the processor 23 controls the display unit 44 to display visual information such as a screen, an image including a still image or a video, an icon, or a message. The processor 23 may generate only rendering information for displaying the visual information on the display unit 44. Note that the processor 23 may present the output information to a user without going through the display unit 44 or another device user.

[0021] <Quantum computer 3> FIG. 3 is a block diagram showing the hardware configuration of the quantum computer 3. As shown in FIG. 3, the quantum computer 3 has a communication unit 31, a quantum memory 32, and a quantum processor 33, and these components are connected via a communication bus 30 inside the quantum computer 3. Note that the quantum computer 3 may include an error-tolerant quantum computer, an NISQ device, or both. The quantum computer 3 of this embodiment is a gate type. Each component will be further described below.

[0022] <Communications Department 31> The communication unit 31 is used by the quantum computer 3 to communicate information with other information processing devices (including classical computers, quantum computers, or computers that combine these) or peripheral devices.

[0023] <Quantum Memory 32> The quantum memory 32 stores various pieces of information defined above. In particular, the quantum memory 32 stores various programs that can be read by the quantum processor 33, which will be described next. For example, the quantum memory 32 stores, as needed, information on the physical properties of a specific material related to calculations by the quantum computer 3. The quantum memory 32 includes a plurality of quantum bits 320. The quantum bits 320 can be implemented using any method, such as nuclear spins, photons, ions, atoms, quantum dots, or superconducting Josephson devices. The quantum bits 320 include a computational quantum bit 321 and an ancillary bit 322. The computational quantum bit 321 functions as a quantum bit that represents the configuration of electrons contained in a material, for example. The quantum memory 32 may also include a classical memory device.

[0024] <Quantum Processor 33> The quantum processor 33 processes and controls the overall operations related to the quantum computer 3. The quantum processor 33 realizes various functions related to the quantum computer 3 by reading out a program stored in the quantum memory 32 or a predetermined program input via the communication unit 31. Note that although FIG. 3 shows a single quantum processor 33, in practice this is not limited to this, and multiple quantum processors 33 may be provided for each function. A combination of these may also be used.

[0025] Quantum processor 33 is configured to perform various quantum operations on qubits 320 that can be implemented on a quantum circuit. For example, the quantum circuit is configured to define a set of quantum operations on qubits 320. Quantum operations include, for example, quantum gate operations and observation operations. Quantum gate operations correspond to unitary operations on the quantum state of qubits 320. Observation operations correspond to projection operations on the quantum state of qubits 320.

[0026] <User terminal 4> Next, a description will be given of the hardware configuration of the user terminal 4. Fig. 4 is a block diagram showing the hardware configuration of the user terminal 4. The user terminal 4 includes a communication unit 41, a memory 42, a processor 43, a display unit 44, and an input unit 45, and these components are electrically connected via a communication bus 40 inside the user terminal 4. The description of the communication unit 41, the memory 42, and the processor 43 will be omitted as they are the same as the description of each unit in the information processing device 2.

[0027] <Display section 44> The display unit 44 may be included in the housing of the user terminal 4 or may be externally attached. The display unit 44 displays a graphical user interface (GUI) screen that can be operated by the user. This is preferably implemented by selectively using display devices such as a CRT display, a liquid crystal display, an organic EL display, or a plasma display depending on the type of user terminal 4.

[0028] <Input section 45> The input unit 45 may be included in the housing of the user terminal 4, or may be externally attached. For example, the input unit 45 may be implemented as a touch panel integrated with the display unit 44. The touch panel allows the user to input tapping, swiping, and the like. Of course, switch buttons, a mouse, a QWERTY keyboard, and the like may be used instead of the touch panel. That is, the input unit 45 accepts an operation input made by the user. The input is transferred as a command signal to the processor 43 via the communication bus 40, and the processor 43 can execute predetermined control or calculation as necessary.

[0029] 2. Functional configuration of processor 23 In this section, a functional configuration of the processor 23 of the information processing device 2 according to this embodiment will be described. Fig. 5 is a block diagram showing the functional configuration of the processor 23. The processor 23 includes an acquisition unit 231, a division unit 232, a calculation unit 233, a circuit generation unit 234, and an output unit 235.

[0030] <Acquisition part 231> The acquisition unit 231 is configured to be able to acquire various pieces of information related to quantum computing from the quantum computer 3 and the user terminal 4. The acquisition unit 231 is configured to be able to acquire various pieces of information by reading out various pieces of information stored in a storage area that is at least a part of the memory unit 22 and writing the read out information into a working area that is at least a part of the memory unit 22. The storage area is, for example, an area of ​​the memory unit 22 that is implemented as a storage device such as an SSD. The working area is, for example, an area that is implemented as a memory such as a RAM.

[0031] <Divided part 232> The dividing unit 232 is configured to divide a continuous interval in which a certain function is defined into a plurality of partial intervals based on various information.

[0032] <Calculation unit 233> The calculation unit 233 is configured to calculate parameters necessary for generating a quantum circuit, such as a division parameter, based on various information and conditions.

[0033] <Circuit generation section 234> The circuit generation unit 234 is configured to generate various quantum circuits based on the information calculated by the calculation unit and the like.

[0034] <Output section 235> The output unit 235 is configured to be able to output various types of information. The information can be presented to the user via the display unit 44 of the user terminal 4 or another device. In such a case, for example, the output unit 235 controls the display unit 44 of the user terminal 4 to display visual information such as a screen, an image including a still image or a video, an icon, or a message. The output unit 235 may generate only rendering information for displaying the visual information on the user terminal 4. Note that the output unit 235 may present the output information to the user without going through the user terminal 4 or another device.

[0035] 3. Information Processing In this chapter, the flow of information processing executed in the information processing system 1 described above will be explained.

[0036] 3.1. Overview of Information Processing 6 is an activity diagram showing an overview of information processing executed in the information processing system 1. Note that the information processing may include any exception processing not shown in the activity diagram. Exception processing includes interruption of the information processing or omission of each process. Selection or input performed in the information processing may be based on a user operation or may be performed automatically without relying on a user operation.

[0037] [Activity A1] First, in activity A1, the acquisition unit 231 acquires a model function V1, a tolerance δ, and an order set {p}.

[0038] The model function V1 outputs a scalar value for an input and is defined in at least one continuous interval. The model function V1 may be a continuous function throughout the continuous interval or a function with discontinuities. For convenience of explanation, the model function V1 is assumed to be a one-variable function expressed as y = V1(x), in which an output y is obtained based on one variable x, and is a continuous function (e.g., a local function) whose domain is one continuous interval [0, L] defined by the variable x. L denotes the interval length of the continuous interval [0, L].

[0039] The degree set {p} is a set of candidates for the degree p of the piecewise polynomial V2, and can be obtained in the form of, for example, a sequence or a list. The piecewise polynomial V2 is an approximation function of the model function V1 obtained by dividing the domain of the model function V1 into at least one partial interval (hereinafter also referred to as a divided interval) and performing polynomial approximation based on spline interpolation for each partial interval.

[0040] The allowable error δ is a scalar value required for the piecewise polynomial V2 that approximately represents the model function V1, and is set to a value equal to or greater than an upper bound function depending on the analysis target for performing analysis using the model function V1. The upper bound function is a function (value) that indicates the upper bound of the error between the model function V1 and the piecewise polynomial V2. The upper bound function may be defined using one or more mathematical expressions, or may be defined using a lookup table or the like. An example of a method for defining the upper bound function will be described later.

[0041] [Activity A2] Next, in activity A2, processor 23 determines the number of elements in degree set {p}. Thereafter, processor 23 advances the process to activity A100 if the number of elements is 1, and advances the process to activity A6 if the number of elements is 2 or more. First, the process when the process advances to activity A100 will be described. Activity A100 is a process for applying spline interpolation so that the degree of each piecewise polynomial V2 in the divided intervals divided from the continuous interval [0, L] becomes a common value (specific degree p1). As a result, piecewise polynomial V2 is obtained as a constant-degree polynomial. Activity A100 includes activities A3 to A5.

[0042] [Activity A3] In activity A3, processor 23 selects the only order p included in order set {p} as the only candidate for specific order p1. In other words, if the number of elements in order set {p} is 1, calculation unit 233 fixes specific order p1 to the value of the only candidate order p throughout the entire continuous interval [0, L]. Thereafter, processor 23 determines whether the value of specific order p is 1 or 2 or greater. Note that if the value of the candidate for specific order p is 0, processor 23 determines that there is an error in the manner in which the candidate order p was obtained, and may discontinue this information processing, for example.

[0043] [Activity A4] If the value of specific order p1 is 2 or greater, in activity A4, processor 23 performs processing based on a high-order piecewise polynomial having terms of order 2 or greater. As a result, output unit 235 outputs information (e.g., coefficients for each order) that defines piecewise polynomial V2 having terms of order 2 or greater that is approximated to model function V1 within a range that satisfies tolerance δ. Then, circuit generation unit 234 generates a quantum circuit configured to output the state of computation qubit 321 that represents piecewise polynomial V2, based on the output information.

[0044] [Activity A5] On the other hand, if the value of the specific degree p1 is 1, in activity A5, processor 23 performs processing based on a linear piecewise polynomial that does not have any higher-order terms than second order. As a result, output unit 235 outputs information (e.g., values ​​at the endpoints of the divided intervals of model function V1) that defines a linear piecewise polynomial V2 that is approximated to model function V1 within a range that satisfies the tolerance δ. Then, based on the output information, circuit generation unit 234 generates a quantum circuit configured to output the state of computation qubit 321 that represents piecewise polynomial V2. As described below, in this embodiment, the algorithm for generating a quantum circuit in activity A4 is different from the algorithm for generating a quantum circuit in activity A5, but the algorithm for generating a quantum circuit in activity A5 can also be the same as the algorithm for generating a quantum circuit in activity A4.

[0045] [Activity A7] After processing activity A4 or activity A5, processor 23 executes processing based on the generated quantum circuit in activity A7. This allows computation qubit 321 of quantum computer 3 to assume a quantum state corresponding to piecewise polynomial V2 to be obtained. Processor 23 may further perform a quantum operation corresponding to a physical quantity on computation qubit 321 assuming such a quantum state, and perform a quantum operation (projection operation) such as observing the state after the quantum operation.

[0046] [Activity A8] Then, in activity A8, the acquiring unit 231 acquires the result of the processing in activity A7. Based on the acquired result, the calculating unit 233 may calculate various information about the quantum state corresponding to the piecewise polynomial V2 (for example, the expected value of the physical quantity in the state). Then, the information processing system 1 ends this information processing.

[0047] [Activity A6] On the other hand, if the number of elements in the degree set {p} determined in activity A2 is two or more, processor 23 proceeds to activity A6 and performs processing based on the variable piecewise polynomial. Activity A100 obtains a piecewise polynomial V2 with a common degree for each divided interval, whereas activity A6 selects an optimal specific degree p1 for each interval to obtain a piecewise polynomial V2 in which the degree is allowed to differ for each interval. By performing activity A6, output unit 235 outputs information for identifying piecewise polynomial V2 (e.g., the division manner of the continuous interval [0, L], the specific degree p1 for each divided interval, the coefficients of piecewise polynomial V2 for each divided interval, etc.), and circuit generation unit 234 generates a quantum circuit configured to output the state of computation qubit 321 representing piecewise polynomial V2 based on the information for identifying piecewise polynomial V2. Note that in this embodiment, the algorithm for generating the quantum circuit used in activity A6 is the same as the algorithm for generating the quantum circuit used in activity A4.

[0048] After activity A6, processor 23 sequentially executes the processing of activity A7 and activity A8, in the same way as if activity A100 had been executed, and then information processing system 1 ends this information processing.

[0049] 3.2. An example of processing based on high-order piecewise polynomials (Activity A4) Next, an example of processing based on a high-order piecewise polynomial (activity A4) will be described. Figure 7 is an activity diagram showing an example of the flow of processing based on a high-order piecewise polynomial (activity A4). This processing can be performed when the number of elements in the degree set {p} is 1 and the specific degree p1 is fixed to a value of 2 or more.

[0050] As shown in FIG. 7, first, in activity A41, the calculation unit 233 calculates an upper bound function, a tolerance δ, and a (p1+1)-th derivative V1 of the model function V1. (p1+1)and the norm of the division parameter m. With this configuration, the calculation load for obtaining the division parameter m can be reduced.

[0051] The upper bound function indicates the upper bound of the maximum difference between the model function V1 and the piecewise polynomial V2 in the continuous interval [0, L]. The upper bound function does not depend on the variables for determining the piecewise polynomial V2, but on the tolerance δ and the (p1+1)th derivative V1 of the model function V1 corresponding to a specific order p1. (p1+1) and the division parameter m.

[0052] Here, an example of an upper bound function will be described. First, a method for evaluating the error between the model function V1 and the piecewise polynomial V2 will be described. For convenience of explanation, let x_j be the representative value of the variable x in the j-th division interval, and let N be the number of division intervals.

[0053] For example, if the tolerance δ represents the degree to which local deviation between the model function V1 and the piecewise polynomial V2 is tolerated, the error evaluation between the model function V1(x) and the piecewise polynomial V2 can be formulated as the maximum value of the representative values ​​{x_j: j=0, 1, 2, 3, ..., N-1}, for example, as follows:

number

[0054] The left side of the above equation represents the error between V1 and V2, and the right side of the above equation represents the error between V1 and V2 converted into an error as a continuous function.

[0055] It is preferable to set an upper bound function so that the right-hand side of the above formula is guaranteed to be equal to or smaller than the tolerance δ. When the piecewise polynomial V2 is obtained using spline interpolation, the upper bound function is determined by the interval length L of the continuous interval [0, L] and the infinity norm ||| ∞ and the optimal constant C of the spline interpolation corresponding to a specific degree p1 p1 Using this, it can be expressed as the following equation (1).

number

[0056] The optimal constant C that minimizes the value of the upper bound function p1 The value of is analytically obtained according to the spline interpolation algorithm to obtain the piecewise polynomial V2. Therefore, the optimal constant C p1 is set to a value equal to or greater than the value at which the value of the upper bound function is smallest. The allowable error δ can be set to a value equal to or greater than the upper bound function defined in equation (1). In other words, the upper bound function does not need to coincide with the upper limit of the error between V1 and V2.

[0057] Here, when there is one candidate for the order p and the value of the order p is substantially fixed, the minimum division parameter m that satisfies the above formula (1)=allowable error δ can be expressed as follows:

number

[0058] Here, ceil[·] in equation (2) represents a ceiling function. As a result, the division parameter m is minimized within a range that satisfies the allowable error δ, and therefore, a division with appropriate approximation accuracy for the allowable error δ can be obtained. In this embodiment, the calculation unit 233 calculates the division parameter m using the above equation (2).

[0059] [Activity A42] Next, in activity A42, the dividing unit 232 may divide the continuous interval [0, L] into M equal primary divided intervals based on the calculated division parameter m. The number M of primary divided intervals is 2 m It is arbitrary as long as it is configured to be equal to or smaller than the allowable error δ. Preferably, the number of primary division sections M=2 m is.

[0060] [Activity A43] Then, in activity A42, the dividing unit 232 may merge two adjacent linear divided intervals if the values ​​of the upper bound function in the two adjacent linear divided intervals are equal to or smaller than the allowable error δ. This divides the continuous interval [0, L] into divided intervals. With this configuration, the model function V1 can be approximately implemented on a quantum circuit as a piecewise polynomial of a smaller number of divided intervals.

[0061] As an example, the dividing unit 232 obtains the final divided interval from the primary divided interval by integrating the primary divided intervals according to the following procedure. Note that, here, it is assumed that each primary divided interval is obtained by equally dividing the continuous interval [0, L]. It is also assumed that indexes from 0 to M-1 are assigned in order to each point at which the continuous interval [0, L] is divided. For convenience of explanation, the point corresponding to each index j is referred to as the j-th division point. (Step 1) Let j_1=0 and j_2=1. (Step 2) Increase the value of j_2 by 1. (Step 3) Section [j_1×L / 2 m ,j_2×L / 2 m ] the maximum norm of the (p1+1)th derivative of the model function V1 at ||V1 j_1,j_2 (p1+1) || ∞ Calculate. (Step 4) Determine whether the uniform norm satisfies the following relational expression (3).

number

[0062] This allows us to calculate the number of divisions M corresponding to the division parameter m. ~ ≦2m In other words, the dividing unit 232 divides the continuous interval [0, L] into 2 intervals where the upper bound function is equal to or smaller than the allowable error δ, based on one specific order p1 selected from the order set {p} and the division parameter m indicating the upper limit of the number of divisions of the continuous interval [0, L]. m Divide into the following number of intervals:

[0063] [Activity A44] Next, in activity A44, the calculation unit 233 calculates a piecewise polynomial V2 by optimizing a p1-degree polynomial corresponding to a specific degree p1 to the model function V1 for each divided section using a predetermined spline interpolation. Here, a common specific degree p1 is obtained for each divided section. For example, the calculation unit 233 calculates a piecewise polynomial V2 by optimizing a p1-degree polynomial corresponding to a specific degree p1 to the model function V1 for each divided section using a predetermined spline interpolation. ~ As knots, M ~ of the divided sections (M ~ +1) division points are used to calculate the coefficients of the polynomial for each division interval by applying the p1-degree spline method. [Activity A45] Based on the calculated piecewise polynomial V2, the circuit generation unit 234 generates a quantum circuit representing a diagonalized unitary operator corresponding to the piecewise polynomial V2. The quantum circuit is configured to operate on n computation qubits 321 encoded to represent positions in a continuous interval [0, L], and the operation quantities of quantum gate operations included in the quantum circuit are determined based on the coefficients of the piecewise polynomial V2. This configuration makes it possible to obtain a quantum circuit that implements the piecewise polynomial V2 approximated by an appropriate division interval according to the tolerance δ, thereby improving the efficiency of the process for obtaining a quantum circuit, such as reducing computational resources and shortening computation time. The number n of computation qubits 321 corresponds to the resolution for approximately representing the continuous interval [0, L] as a discrete value, and is also referred to as a grid parameter.

[0064] Here, it is assumed that the value of the specific order p1 is fixed to 2 or more, and the circuit generation unit 234 generates quantum circuit 5 as a first quantum circuit. Fig. 8 is a diagram showing an example of a quantum circuit that is generated when the value of the specific order p1 is fixed to 2 or more. For convenience of explanation, it is assumed here that n computation qubits 321 are allocated from quantum memory 32, and each of the observable states of a group of qubits constituted by n computation qubits 321 is encoded to represent a position in the continuous interval [0, L], and at least some of these are encoded to correspond to the division points of the primary division interval (and at least some of these are encoded to correspond to the division points of the final division interval).

[0065] As shown in Fig. 8, the quantum circuit 5 is configured to operate on n computation qubits 321 and one auxiliary bit 322. The auxiliary bit 322 is used to indicate a partial continuous interval [0, L] in the continuous interval [0, L] as an entire state together with the n computation qubits 321. The quantum circuit 5 operates by repeatedly executing M ~ Quantum Operations 51 (51-1~51-M ~ ) Each quantum operation 51 is configured to adjust the weight of the state of a group of quantum bits constituted by the computation quantum bit 321 based on the coefficient of the calculated piecewise polynomial V2. As an example, each quantum operation 51 includes a phase gate operation 511 and a quantum comparator 512. For convenience of explanation, the phase gate operation 511 will be referred to as a polynomial phase gate 511 hereinafter.

[0066] The polynomial phase gate 511 is configured to operate on n computation quantum bits 321 corresponding to each of the divided intervals. Note that in this embodiment, the polynomial phase gate 511 operates only on the n computation quantum bits 321, and does not operate on the auxiliary bits 322. The polynomial phase gate 511 is configured to adjust the weights of states corresponding to a partial continuous interval [0, L] that is specified in consideration of the auxiliary bits 322, in accordance with the calculated coefficient of each interval. Here, the polynomial phase gate 511 is configured to adjust the weights of states corresponding to a partial continuous interval [0, L] from an end point (e.g., 0 or L) of the continuous interval [0, L] to one of the division points that defines the final divided interval, which is expressed using the auxiliary bits 322. This configuration can reduce the processing load on the quantum circuit 5 compared to adjusting the weights of states corresponding to each of the final divided intervals. For example, the operation amount of the polynomial phase gate 511 is the value of the section corresponding to the polynomial phase gate 511 in the piecewise polynomial V2 and the value of the section adjacent to the section (function f j ) and the difference (f j-1 -f j ) This configuration allows for more efficient implementation of high-order piecewise polynomial approximation on a quantum circuit within the range of the tolerance δ.

[0067] 9 is a diagram showing an example of the configuration of the polynomial phase gate 511 when n=4 and p1=2. In this case, the piecewise polynomial V2 is approximated by a second-order polynomial, so the coefficient a k (k=0, 1, 2). The global phase of the state of the computation qubit 321 shown in FIG. 9 is exp(-i×a0), where i is the imaginary unit. As shown in FIG. 9, the polynomial phase gate 511 is expressed using Z-gate operations (and control Z-gate operations), and the operation amount is expressed by a coefficient a k and the unit of length represented by the computational qubit 321, l=L / N (where N=2 n ) The polynomial phase gate 511 can be determined by, for example, the unitary operator U ph It is expressed as:

number

[0068] |j> represents the j-th state among the eigenstates formed by n computation qubits 321. g represents a piecewise polynomial V2 in a certain interval, and its coefficients are a j In the formula, x is a variable representing a position in the continuous interval [0, L]. For example, when p=2, the polynomial phase gate 511 is expressed as follows:

number

[0069] As shown in FIG. 9, the polynomial phase gate 511 converts the Z gate operation into a Z rotation gate operation R z can be implemented as an approximate polynomial phase gate 511a when the global phase is negligible by replacing

[0070] The quantum comparator 512 is configured to operate on m computation qubits 321, which are the value of the division parameter m, among the n computation qubits 321, and one auxiliary bit 322. The quantum comparator 512 is configured to change the state of the auxiliary bit 322 in accordance with the states of the m computation qubits 321 (e.g., eigenstates of a quantum bit group composed of the m computation qubits 321), thereby causing the polynomial phase gate 511 to operate on components of the states of the n computation qubits 321 corresponding to each of the final division intervals. With this configuration, high-order piecewise polynomial approximation can be implemented on a quantum circuit more efficiently within the range of the allowable error δ.

[0071] 10 is a diagram showing an example of the configuration of a quantum comparator 512 using quantum Fourier transform (QFT) operations. As shown in FIG. 10, the quantum comparator 512 includes a first gate operation 5121 that operates on multiple computation qubits 321 and one ancillary bit 322, and a second gate operation 5122 that operates only on the multiple computation qubits 321 after the first gate operation 5121. Each of the gate operations 5121 and 5122 is a pair of QFT operations U QFT ,U † QFT and the pair of QFT operations U QFT ,U † QFT The Z-gate operation is performed between the parameter k l =y l / (L / M) (where l is between 0 and M) ~ Quantum comparator 512 determines the state of the output computation qubit 321 by comparing it with the state of the input computation qubit 321 (|j ~ >) and j ~ <k l If j, then ~ ≧k l Change the state of the auxiliary bit 322 (|j ~ <k l >). That is, the comparison result of the two values ​​is configured to be output as the state of the auxiliary bit 322. This makes it possible to adjust the weight of the state corresponding to a specific section by using a control gate operation in which the polynomial phase gate 511 operates according to the state of the auxiliary bit 322.

[0072] In addition, processor 23 may function as an abort unit to abort the generation of a quantum circuit (e.g., quantum circuit 5) when the calculated division parameter m is greater than the number n of computation qubits 321. Such a configuration can prevent the waste of forcibly generating a quantum circuit when computational resources are insufficient. In this case, processor 23 may further compare the division parameter m with the number n of allocated computation qubits 321, and, as an allocator, may reallocate computation qubits 321 when the division parameter m is greater than the number n of computation qubits 321 so that the number n of computation qubits 321 is equal to or greater than the division parameter m. Such a configuration can improve the efficiency of generating quantum circuits. Furthermore, the processing based on the high-order piecewise polynomial described in this section can also be applied when p1=1.

[0073] Next, an example of the division intervals and the comparison results between the model function V1 and the piecewise polynomial V2 when processing based on a high-order piecewise polynomial is described. FIG. 11 is a diagram showing an example of the results of processing based on a high-order piecewise polynomial. In the figure, "Exact" corresponds to the model function V1, "Approx." corresponds to the piecewise polynomial V2, and "sample." corresponds to the division point of the final division interval. The interval between two division points corresponds to one division interval. As shown in FIG. 11, the model function V1 and the piecewise polynomial V2 can be obtained with relatively good approximation accuracy. Furthermore, in a region where the amount of change in the model function V1 is small, the length of the division interval is shorter than in a region where the change in the model function V1 is large (e.g., x = 7.5 to 12.5). In this way, according to this information processing, it is possible to obtain a piecewise polynomial V2 with good approximation accuracy within the range of the allowable error δ while reducing the number of division intervals (in other words, the number of divisions).

[0074] 3.3. An example of processing based on linear piecewise polynomials (Activity A5) Next, we will explain an example of processing based on a linear piecewise polynomial (activity A5) that is performed when the value of the specific degree p1 is fixed to 1. Fig. 12 is an activity diagram showing an example of the flow of processing based on a linear piecewise polynomial (activity A5).

[0075] [Activity A51] 12, first, in activity A51, the calculation unit 233 calculates the division parameter m in the same procedure as in activity A41.

[0076] [Activity A52] Next, in activity A52, the dividing unit 232 divides the continuous section [0, L] into equal divided sections. Here, the dividing unit 232 divides the continuous section [0, L] into 2 m Divide it into equal intervals.

[0077] [Activity A53] After that, the circuit generation unit 234 generates quantum circuit 6 as a second quantum circuit.

[0078] Fig. 13 is a diagram showing an example of a quantum circuit when the value of the specific degree p1 is fixed to 1. As shown in Fig. 13, the quantum circuit 6 includes a diagonal unitary operation 61 and a differential action operation 62 as (nm) control gate operations.

[0079] The diagonal unitary operation 61 is an oracle operator that implements a diagonal unitary matrix, for example, the operator U M It can be defined as:

number

[0080] In the above formula, V means the model function V1, and x ~ k =kL / 2 m represents the position of a point (e.g., the kth division point) in the kth continuous interval [0, L].

[0081] The differential action operation 62 sets each of (nm) computation qubits 321 out of the n computation qubits 321 as a control bit, and sets the other m computation qubits 321 as target bits. Each differential action operation 62 (62-1 to 62-(nm)) acts on a state corresponding to a portion of the divided interval, thereby linearly interpolating the phase of the diagonal components represented by the m computation qubits 321 in accordance with the value of the model function V1 at the endpoint of the divided interval (e.g., the value at the divided interval). This configuration can further improve the calculation efficiency when obtaining a piecewise polynomial using a linear function. For example, each differential action operation 62 acts on a state corresponding to a portion of the divided interval, thereby adjusting the states of the 2nd, 4th, 6th, and 8th divided intervals in accordance with the value of the model function V1 at the divided interval, in the case of n=3 and m=1, when the control bit is the top bit, and adjusting the states of the 3rd, 4th, 7th, and 8th divided intervals in accordance with the value of the model function V1 at the divided interval.

[0082] 14 is a diagram showing a configuration example of the differential action operation 62. As shown in FIG. 14, the differential action operation 62 is, for example, an operator U M (j) ,U M (j)† and an increment operator U as a control gate operation acting on m computation qubits 321 depending on the states of the nm computation qubits 321. +1 and the decrement operator U +1 † In FIG. 14, the difference operation 62 can be defined using the operator W j (j=1~nm).

[0083] Operator U M (j) ,U M (j)† is the operator U M is an oracle operator that implements diagonal unitary matrices similarly to

number

[0084] Increment operator U +1 and the decrement operator U +1 † is a gate operation that transitions the states of n computation qubits 321 from the k-th state to the k+1-th state or the k-1-th state, respectively, and is defined as follows:

number

[0085] Figure 15 shows the increment operator U +1 As shown in FIG. 15, the increment operator U +1 is a pair of QFT operations U QFT ,U † QFT and the Z-gate operation acting on each computation qubit 321. The amount of operation of the Z-gate operation is determined independently of the coefficients of the piecewise polynomial V2. Also, as shown in FIG. 15, the increment operator U +1 In the case where the global phase can be ignored, the Z-rotation gate operation R z It can also be implemented using the decrement operator U -1 is the increment operator U +1 Since it can be implemented as a Hermitian operator, the explanation will be omitted.

[0086] The quantum circuit 6 configured in this way can adjust the weights of the states corresponding to each divided section all at once, unlike the quantum circuit 5 obtained from the processing based on the above-mentioned high-order piecewise polynomial. Therefore, when the allowable error δ is relatively large in the case of p1=1, it is possible to reduce the number of gate operations and the circuit depth compared to when the quantum circuit 5 is used. Note that the order of the circuit depth is O(δ -1 / 2 ) In this case, the auxiliary bit 322 is not required, so it is also possible to reduce the number of quantum bits 320.

[0087] Note that quantum circuit 6 may operate on auxiliary bits 322. In this case, a piecewise polynomial V2 corresponding to a more general model function V1 can be output as a quantum state. Furthermore, processor 23, as an aborting unit, may abort the generation of a quantum circuit (e.g., quantum circuit 6) when the calculated partitioning parameter m is greater than the number n of computation qubits 321. This configuration can prevent the waste of forcibly generating a quantum circuit when computational resources are insufficient. In this case, processor 23 may further compare the partitioning parameter m with the number n of allocated computation qubits 321, and, as an allocating unit, may reallocate computation qubits 321 when the partitioning parameter m is greater than the number n of computation qubits 321 so that the number n of computation qubits 321 is equal to or greater than the partitioning parameter m. This configuration can improve the efficiency of generating quantum circuits.

[0088] Furthermore, in processing based on a linear piecewise polynomial, processor 23 may generate quantum circuit 6 according to the above-described procedure if (number n of computational qubits 321)>(partition parameter m), and may generate quantum circuit 7 that outputs a quantum state corresponding to piecewise polynomial V2 using a Walsh operator if (number n of computational qubits 321)≦(partition parameter m). Figure 16 is a diagram showing an example configuration of quantum circuit 7 corresponding to a Walsh operator.

[0089] Next, an example of the comparison result between the model function V1 and the piecewise polynomial V2 when processing based on a linear piecewise polynomial is described. FIG. 17 is a diagram showing an example of the result of processing based on a linear piecewise polynomial. In the figure, "Exact" corresponds to the model function V1, and "Approx." corresponds to the piecewise polynomial V2. In this processing, the continuous interval is 2 mSince the model function V1 is divided into equal intervals, the division points are omitted. Portions of the model function V1 corresponding to each of the intervals are approximated using linear functions. As shown in FIG. 17, the model function V1 and the piecewise polynomial V2 can be obtained with relatively good approximation accuracy. In this way, according to this information processing, it is possible to obtain the piecewise polynomial V2 with good approximation accuracy within the range of the allowable error δ while reducing the number of intervals (in other words, the number of divisions).

[0090] 3.4. An example of processing based on variable piecewise polynomials (Activity A6) Next, we will explain an example of processing based on a variable piecewise polynomial (activity A6) that is performed when the number of elements in the degree set {p} is 2 or more. Figure 18 is an activity diagram showing an example of the flow of processing based on a variable piecewise polynomial.

[0091] [Activity A61] First, in activity A61, acquisition unit 231 acquires candidates for division parameter m that are equal to or less than the number n of computational quantum bits 321. The candidates for division parameter m may be specified in the form of a sequence or list, for example, {m}={1, 2, 3, ..., n}. Processor 23 then executes the processing of activities A62 to A64, described below, for each of the acquired candidates for division parameter m.

[0092] [Activity A62] First, in activity A62, the processor 23 identifies an allowable value of the degree p of the piecewise polynomial V2 from among the candidate degrees p, based on the allowable error δ and the like, for each candidate for the division parameter m. The allowable value of the degree p is a candidate value of the degree p at which the value of the upper bound function is equal to or less than the allowable error δ. The allowable value of the degree p is the upper limit of the degree p of the entire piecewise polynomial V2. In this embodiment, the processor 23 determines the smallest degree pk at which the value of the upper bound function is equal to or less than the allowable error δ as the only allowable value of the degree p. In the k-th division interval, the smallest degree pk can be defined, for example, as follows:

number

[0093] [Activity A63] Next, the dividing unit 232 divides the continuous section [0, L] into two m At this time, if the number of elements in the degree set {p} is two or more and there is only one allowable value of the degree p for each interval (for example, as described above, when the smallest degree pk is determined as the only allowable value of the degree p), the dividing unit 232 may first divide the continuous interval [0, L] into equal primary divided intervals.

[0094] Thereafter, the dividing unit 232 may divide the continuous interval [0, L] into divided intervals by merging two adjacent primary divided intervals if the allowable values ​​of the degree p in the two adjacent primary divided intervals are the same and the value of the upper bound function is equal to or less than the allowable error δ. With this configuration, it is possible to generate a quantum circuit that implements a piecewise polynomial with a smaller number of divided intervals within a range that satisfies the allowable error δ. Note that the merging of the primary divided intervals is performed, for example, according to a procedure similar to the procedure described above.

[0095] [Activity A64] Next, in activity A64, the division unit 232 calculates the value of the objective function F based on the division parameter m, the continuous interval [0, L], and the degree pk. The objective function F is calculated by selecting the optimal division parameter m from among the candidates for the division parameter m. * The objective function F is a function for determining the degree p, and is specified so that the input variables are the tolerance of the specified degree p, the division parameter m, and the division mode of the continuous interval [0, L]. A specific embodiment of the objective function F is a function for determining the degree p, the division parameter m * is optimal, for example, depending on the calculation time, processing load, tolerance δ, etc. In this way, the processor 23 determines the order pk and the division interval for a certain division parameter m, and obtains the value of the objective function for these elements.

[0096] [Activity A65] After the value of the objective function F is obtained for each candidate of the division parameter m in this way, in activity A65, the processor 23 selects the optimum division parameter m from among the candidates of the division parameter m based on the objective function. * Determine.

[0097] [Activity A66] Next, in activity A66, the calculation unit 233 calculates the optimal division parameter m * and the division interval corresponding to m * For example, the calculation unit 233 calculates a piecewise polynomial V2 based on the determined division parameters m * The calculation unit 233 determines a degree p equal to or greater than pk as a tolerance corresponding to pk as a specific degree p1 of the piecewise polynomial in each divided interval. Thereafter, the calculation unit 233 calculates a piecewise polynomial V2 by optimizing the p1-degree polynomial corresponding to the specific degree p1 to the model function V1 for each divided interval using spline interpolation. With this configuration, it is possible to obtain a piecewise polynomial in which the optimal specific degree p1 is set for each interval from among the candidate degrees p, and therefore it is possible to generate a quantum circuit capable of implementing a piecewise polynomial with higher qualitative approximation accuracy within a range that satisfies the tolerance δ.

[0098] [Activity A67] Thereafter, based on information about piecewise polynomial V2 calculated in activity A66 (for example, coefficients in each divided interval of piecewise polynomial V2, etc.), processor 23 generates quantum circuit 5 that can output piecewise polynomial V2 as the quantum state of computational qubit 321. Note that the algorithm for generating quantum circuit 5 based on piecewise polynomial V2 obtained by processing based on a variable piecewise polynomial is similar to the algorithm for generating quantum circuit 5 based on piecewise polynomial V2 obtained by processing based on a high-order piecewise polynomial, and therefore detailed description thereof will be omitted.

[0099] <Other> The above-described embodiment can be implemented as appropriate in the following manners, for example, within the scope of technical inconsistency.

[0100] The model function V1 is not limited to this and may be any function, for example, a multivariate function that explicitly depends on multiple variables x1 and x2. In this case, the piecewise polynomial V2 can be obtained by sequentially performing the above-mentioned single-variable processing on each of the multiple variables x1 and x2.

[0101] A part of the processing of the processor 23 may be converted into a calculation algorithm that can be executed by a quantum computer, and then the quantum computer 3 may be made to execute the calculation algorithm.

[0102] The information processing device 2 may be a classical computer, a quantum computer, or a combination thereof.

[0103] The information processing system 1 can be applied to various information processes related to quantum computation such as quantum measurement and quantum communication.

[0104] The above embodiment is not limited to the information processing system 1, and may be an information processing method or an information processing program. The information processing method includes each step of the information processing system 1. The information processing program causes at least one computer to execute each step of the information processing system 1.

[0105] The information processing system 1 and the like may be provided in the following aspects.

[0106] (1) An information processing system, comprising at least one processor, configured to execute a program that performs the following steps: in the acquisition step, a model function V1, a tolerance δ required for a piecewise polynomial V2 that approximately represents the model function V1, and an order set {p} that is a set of candidates for the order p of the piecewise polynomial V2, where the model function V1 outputs a scalar value in response to an input and is defined by at least one continuous interval; in the division step, based on one specific order p1 selected from the order set {p} and a division parameter m that indicates an upper limit of the number of divisions of the continuous interval, the continuous intervals are divided into two such that an upper bound function that indicates an upper bound of the maximum value of the difference between the model function V1 and the piecewise polynomial V2 in the continuous interval is equal to or smaller than the tolerance δ; m The upper bound function is independent of the variables for determining the piecewise polynomial V2, and is determined by the tolerance δ and the (p1+1)th derivative V1 of the model function V1 corresponding to the specific order p1. (p1+1) and the division parameter m, wherein in the approximation formula calculation step, for each of the division intervals, a p1-degree polynomial corresponding to the specific degree p1 is optimized to the model function V1 using a predetermined spline interpolation to calculate the piecewise polynomial V2, and in the circuit generation step, a quantum circuit representing a diagonalized unitary operator corresponding to the piecewise polynomial V2 is generated based on the calculated piecewise polynomial V2, wherein the quantum circuit is configured to operate on n computation qubits encoded to represent positions in the continuous intervals, and an operation amount of a quantum gate operation included in the quantum circuit is determined based on a coefficient of the piecewise polynomial V2.

[0107] With this configuration, it is possible to obtain a quantum circuit that implements the piecewise polynomial V2 that is approximated in an appropriate division interval according to the allowable error δ, thereby making it possible to improve the efficiency of the process for obtaining a quantum circuit, such as reducing computational resources and shortening computation time.

[0108] (2) In the information processing system described in (1) above, when the number of elements of the order set {p} is 1, the division parameter calculation step further fixes the specific order p1 to the value of the only candidate order p throughout the entire continuous section, and calculates the upper bound function, the allowable error δ, and the (p1+1)th derivative V1 of the model function V1. (p1+1) and a norm of

[0109] According to this configuration, the calculation load for obtaining the division parameter m can be reduced.

[0110] (3) In the information processing system described in (2) above, when the value of the specific order p1 is fixed to 2 or more, the circuit generation step generates a first quantum circuit as the quantum circuit, and the first quantum circuit includes a phase gate operation that acts on the n computation quantum bits corresponding to each of the division intervals, and a quantum comparator that acts on m computation quantum bits, which are the value of the division parameter m, among the n computation quantum bits, and one auxiliary bit, and the quantum comparator is configured to change the state of the auxiliary bit in accordance with the state of the m computation quantum bits, thereby causing the phase gate operation to act on the n computation quantum bits having states corresponding to the division interval.

[0111] With this configuration, high-order piecewise polynomial approximation can be implemented on a quantum circuit more efficiently within the range of the allowable error δ.

[0112] (4) In the information processing system described in (3) above, the amount of operation of the phase gate operation is set based on the difference between the value of the interval corresponding to the phase gate operation in the piecewise polynomial V2 and the value of the interval adjacent to the interval.

[0113] With this configuration, high-order piecewise polynomial approximation can be implemented on a quantum circuit more efficiently within the range of the allowable error δ.

[0114] (5) In the information processing system described in (3) or (4) above, when the specific order p1 is fixed to a value of 2 or more, the division step divides the continuous interval into equal primary division intervals, and when the value of the upper bound function in two adjacent primary division intervals is equal to or less than the allowable error δ, the two primary division intervals are merged to divide the continuous interval into the division intervals.

[0115] According to this configuration, the model function V1 can be approximately implemented on the quantum circuit as a piecewise polynomial with a smaller number of divided intervals.

[0116] (6) In the information processing system described in any one of (3) to (5) above, the abort step further aborts the generation of the first quantum circuit if the calculated division parameter m is greater than the number n of computational quantum bits.

[0117] With this configuration, it is possible to prevent the waste of forcibly generating quantum circuits when there is a shortage of computational resources.

[0118] (7) In the information processing system described in any one of (3) to (6) above, in the allocation step, when the division parameter m is greater than the number n of the computational quantum bits, the computational quantum bits are allocated so that the number n of the computational quantum bits is equal to or greater than the division parameter m.

[0119] With this configuration, it is possible to improve the efficiency of generating quantum circuits.

[0120] (8) In the information processing system according to any one of (2) to (4) above, when the value of the specific order p1 is fixed to 1, the division step divides the continuous interval into equal divided intervals, and the circuit generation step generates a second quantum circuit as the quantum circuit, the second quantum circuit having (nm) control gate operations with each of (nm) computational quantum bits out of the n computational quantum bits as control bits and m computational quantum bits other than the (nm) control gate operations as target bits, each of which acts on a state corresponding to a part of the divided interval, thereby linearly interpolating the phases of diagonal elements represented by the m computational quantum bits in accordance with the value of the model function V1 at an end point of the divided interval.

[0121] According to this configuration, it is possible to further improve the calculation efficiency when obtaining a piecewise polynomial using a linear function.

[0122] (9) In the information processing system according to any one of (1) to (8) above, when the number of elements of the degree set {p} is 2 or more, the candidate acquisition step further acquires candidates for the division parameter m that are equal to or less than the number n of the computational quantum bits, and in the division step, for each of the candidates for the division parameter m, divide the continuous section into 2 man interval order determination step of determining an optimum partitioning parameter m from among the candidates for the partitioning parameter m based on an objective function having as input variables the specified allowable value of the order p, the partitioning parameter m, and a partitioning mode of the continuous intervals; a specific order determination step of determining the order p that is equal to or greater than the allowable value and that corresponds to the determined partitioning parameter m as a specific order p1 of the piecewise polynomial in the partitioned interval; and a specific order calculation step of calculating the piecewise polynomial V2 by optimizing a p1-degree polynomial corresponding to the specific order p1 to the model function V1 using the spline interpolation for each partitioned interval.

[0123] With this configuration, it is possible to obtain a piecewise polynomial in which the optimal specific degree p1 is set for each interval from among the candidate degrees p, and thus it is possible to generate a quantum circuit that can implement a piecewise polynomial with higher qualitative approximation accuracy within a range that satisfies the allowable error δ.

[0124] (10) In the information processing system described in (9) above, when the number of elements in the degree set {p} is two or more and there is only one allowable value of the degree p for each interval, the division step divides the continuous interval into equal primary divided intervals, and when the allowable values ​​of the degree p in two adjacent primary divided intervals are the same and the value of the upper bound function is less than or equal to the allowable error δ, the information processing system divides the continuous interval into the divided intervals by merging the two primary divided intervals.

[0125] With this configuration, it is possible to generate a quantum circuit that implements a piecewise polynomial with a smaller number of divided intervals within a range that satisfies the tolerance δ.

[0126] (11) In the information processing system according to any one of (1) to (10), the upper bound function is a function of the interval length L of the continuous interval and the infinity norm ||·|| ∞ and the optimal constant C of the spline interpolation corresponding to the specific order p1. p1 The information processing system is expressed as the following equation (1) using [Equation 1]. TIFF2026016265000012.tif1051

[0127] (12) A method for generating a quantum circuit, the method including each step of the information processing system described in any one of (1) to (11) above.

[0128] (13) A program that causes at least one computer to execute each step of the information processing system according to any one of (1) to (11) above. Of course, this is not the case.

[0129] Finally, while various embodiments of the present invention have been described, these are presented by way of example only and are not intended to limit the scope of the invention. The novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. Such embodiments and modifications are intended to be included within the scope and spirit of the invention, as well as within the scope of the inventions and their equivalents as defined in the accompanying claims. [Explanation of symbols]

[0130] 1: Information processing system 2: Information processing equipment 20: Communication bus 21: Communications Department 22: Storage section 23: Processor 231: Acquisition Department 232 :Divided part 233: Calculation section 234:Circuit generation section 235: Output section 3:Quantum computer 30: Communication bus 31: Communications Department 32: Quantum memory 320: Quantum Bit 321: Computational qubits 322: Auxiliary bit 33: Quantum processor 4: User terminal 40: Communication bus 41: Communications Department 42: Memory 43: Processor 44: Display section 45: Input section 5:Quantum circuit 51:Quantum operation 511: Polynomial Phase Gate 511a: Polynomial Phase Gate 512: Quantum Comparator 5121: First gate operation 5122: Second gate operation 521: Quantum Comparator 6:Quantum circuit 61: Diagonal unitary operations 62 :Difference action operation 7:Quantum circuit δ: Tolerance

Claims

1. An information processing system, At least one processor is provided, the processor being configured to execute a program that performs the following steps: In the acquisition step, a model function V1, a tolerance δ required for a piecewise polynomial V2 that approximately represents the model function V1, and a degree set {p} that is a set of candidates for the degree p of the piecewise polynomial V2 are acquired, where: The model function V1 outputs a scalar value for an input and is defined over at least one continuous interval; In the division step, based on one specific order p1 selected from the order set {p} and a division parameter m indicating an upper limit of the number of divisions of the continuous section, the continuous section is divided into two sections such that an upper bound function indicating an upper limit of the maximum value of the difference between the model function V1 and the piecewise polynomial V2 in the continuous section is equal to or less than the allowable error δ. ｍ Divide it into the following number of intervals: The upper bound function does not depend on the variables for determining the piecewise polynomial V2, and is determined by the allowable error δ and the (p1+1)th derivative V1 of the model function V1 corresponding to the specific order p1. （ｐ１＋１） and the division parameter m, In the approximation equation calculation step, a p1-degree polynomial corresponding to the specific degree p1 is optimized to the model function V1 for each of the divided sections using a predetermined spline interpolation, thereby calculating the piecewise polynomial V2; In the circuit generation step, a quantum circuit representing a diagonalized unitary operator corresponding to the calculated piecewise polynomial V2 is generated based on the piecewise polynomial V2; Here, the quantum circuit is configured to operate on n computational quantum bits encoded to represent positions in the continuous interval, and the operation amount of the quantum gate operation included in the quantum circuit is determined based on the coefficients of the piecewise polynomial V2.

2. 2. The information processing system according to claim 1, When the number of elements in the degree set {p} is 1, Furthermore, in the division parameter calculation step, Fixing the specific order p1 to the value of the only candidate order p throughout the continuous section; the upper bound function, the tolerance δ, and the (p1+1)th derivative V1 of the model function V1 （ｐ１＋１） and a norm of

3. 3. The information processing system according to claim 2, When the value of the specific order p1 is fixed to 2 or more, In the circuit generation step, a first quantum circuit is generated as the quantum circuit; The first quantum circuit comprises: a phase gate operation acting on the n computation qubits corresponding to each of the divided sections; a quantum comparator that operates on m computation quantum bits, which are the value of the division parameter m, among the n computation quantum bits and one auxiliary bit; The quantum comparator is configured to change the state of the ancillary bit according to the state of the m computation quantum bits, thereby applying the phase gate operation to the n computation quantum bits having states according to the division interval.

4. 4. The information processing system according to claim 3, An information processing system, wherein the amount of operation of the phase gate operation is set based on the difference between the value of a section corresponding to the phase gate operation in the piecewise polynomial V2 and the value of a section adjacent to the section.

5. 4. The information processing system according to claim 3, When the specific order p1 is fixed to a value of 2 or more, In the dividing step, Dividing the continuous section into equal primary division sections; an information processing system that divides the continuous section into the divided sections by merging two adjacent primary divided sections when the value of the upper bound function in the two primary divided sections is equal to or less than the allowable error δ.

6. 4. The information processing system according to claim 3, Furthermore, in the aborting step, generation of the first quantum circuit is aborted if the calculated division parameter m is greater than the number n of computational quantum bits.

7. 4. The information processing system according to claim 3, Furthermore, in the allocating step, if the division parameter m is greater than the number n of computational quantum bits, the information processing system allocates the computational quantum bits so that the number n of computational quantum bits is equal to or greater than the division parameter m.

8. 3. The information processing system according to claim 2, When the value of the specific order p1 is fixed to 1, In the dividing step, the continuous section is divided into equal divided sections; In the circuit generation step, a second quantum circuit is generated as the quantum circuit; The second quantum circuit includes (nm) control gate operations in which each of (nm) computational qubits among the n computational qubits is a control bit, and m computational qubits other than the (nm) computational qubits are target bits; each of the control gate operations acts on a state corresponding to a respective portion of the divided interval, thereby linearly interpolating the phases of the diagonal elements represented by the m computation qubits according to the values ​​of the model function V1 at the endpoints of the divided interval.

9. 2. The information processing system according to claim 1, When the number of elements of the degree set {p} is 2 or more, Furthermore, in the candidate acquisition step, candidates for the division parameter m that are equal to or less than the number n of computational quantum bits are acquired, In the dividing step, for each candidate of the division parameter m, the continuous section is divided into two ｍ Divide it into not more than 100 division intervals, In the interval degree determination step, for each candidate of the division parameter m, an allowable value of the degree p of the piecewise polynomial V2 is specified; the allowable value of the order p is a candidate value of the order p at which the value of the upper bound function is equal to or smaller than the allowable error δ, In the division parameter determination step, an optimal division parameter m is determined from the candidates for the division parameter m based on an objective function having the specified allowable value of the order p, the division parameter m, and a division mode of the continuous interval as input variables for each of the candidates for the division parameter m; In the specific degree determination step, the degree p that is equal to or greater than the allowable value and corresponds to the determined division parameter m is determined as a specific degree p1 of the piecewise polynomial in the division interval; In the approximation equation calculation step, the piecewise polynomial V2 is calculated by optimizing a p1-degree polynomial corresponding to the specific degree p1 to the model function V1 for each divided interval using the spline interpolation.

10. 10. The information processing system according to claim 9, When the number of elements of the degree set {p} is two or more, and when there is only one permissible value of the degree p for each interval, In the dividing step, Dividing the continuous section into equal primary division sections; An information processing system that divides the continuous interval into the divided intervals by merging two adjacent primary divided intervals if the allowable values ​​of the order p in the two adjacent primary divided intervals are the same and the value of the upper bound function is less than or equal to the allowable error δ.

11. 2. The information processing system according to claim 1, The upper bound function is a function of the interval length L of the continuous interval and the infinity norm ||·|| ∞ and the optimal constant C of the spline interpolation corresponding to the specific order p1. ｐ１ The information processing system is expressed as the following equation (1) using [Equation 1]

12. A method for generating a quantum circuit, comprising: A method comprising the steps of the information processing system according to any one of claims 1 to 11.

13. A program, A program that causes at least one computer to execute each step of the information processing system according to any one of claims 1 to 11.

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