Pixel circuit, display device, and electronic device

Abstract

To provide a pixel circuit having a small area and a high degree of integration.SOLUTION: A first transistor including a control electrode connected to a first node, a first electrode to which a first drive voltage is applied, and a second electrode connected to a second node; a second transistor that applies a data voltage to a third node in response to a write gate signal; A third transistor connecting the first node and the second node, a first capacitor including a first electrode connected to the third node and a second electrode connected to the first node, and a light emitting element including a first electrode connected to the second node and a second electrode to which a second driving voltage is applied, wherein the first driving voltage and the second driving voltage have a driving high voltage or a driving low voltage, and the compensation gate signal is a global signal applied to two pixel rows at the same timing.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a pixel circuit, a display device, and an electronic device, and more particularly to a pixel circuit, a display device, and an electronic device with improved light emission reliability and improved integration. [Background technology]

[0002] In general, a display device includes a display panel, a gate driver, a data driver, and a drive controller. The display panel includes a plurality of gate lines, a plurality of data lines, and a plurality of pixel circuits electrically connected to the gate lines and the data lines. The gate driver provides gate signals to the gate lines, the data driver provides data voltages to the data lines, and the drive controller controls the gate driver and the data driver.

[0003] Recently, display devices that provide virtual reality (VR) or augmented reality (AR) have been attracting attention. To achieve this, display devices are required to have a small area and high integration. In this case, the pitch occupied by pixel circuits becomes narrower, which imposes restrictions on the number of transistors constituting the pixel circuits and the number of signals applied to the pixel circuits. Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a pixel circuit with a small area and high integration.

[0005] Another object of the present invention is to provide a display device including the pixel circuit.

[0006] Another object of the present invention is to provide an electronic device including the pixel circuit.

[0007] However, the object of the present invention is not limited to the above object, and can be expanded in various ways without departing from the spirit and scope of the present invention. [Means for solving the problem]

[0008] A display device according to one embodiment of the present invention includes a display panel including a plurality of pixel circuits, and a display panel driver for driving the display panel, wherein the pixel circuits include: a first transistor including a control electrode connected to a first node, a first electrode to which a first drive voltage is applied, and a second electrode connected to a second node; a second transistor for applying a data voltage to a third node in response to a write gate signal; a third transistor for connecting the first node and the second node in response to a compensation gate signal; a first capacitor including a first electrode connected to the third node and a second electrode connected to the first node; and a light-emitting element including a first electrode connected to the second node and a second electrode to which a second drive voltage is applied, wherein the first drive voltage has a high drive voltage or a low drive voltage, the second drive voltage has the high drive voltage or the low drive voltage, and the compensation gate signal is a global signal applied to at least two pixel rows at the same timing.

[0009] The pixel circuit may further include a fourth transistor that applies an initialization voltage to the second node in response to an initialization gate signal, and the initialization gate signal may be the global signal.

[0010] The pixel circuit may further include a second capacitor including a first electrode to which the initialization voltage is applied and a second electrode connected to the third node.

[0011] The pixel circuit may further include a fourth transistor that applies an initialization voltage to the second node in response to an initialization gate signal, and a frame period in which the pixel circuit is driven may include first to seventh periods, and in the first period, the compensation gate signal has an inactive level, the initialization gate signal has an inactive level, the write gate signal has an inactive level, and the second driving voltage may be the driving high voltage.

[0012] In the second interval after the first interval, the compensation gate signal may have an activation level, the initialization gate signal may have an activation level, the write gate signal may have an activation level, the data voltage may have a reference data voltage, and the first driving voltage may have the low driving voltage.

[0013] In the third period after the second period, the compensation gate signal may have the activation level, the initialization gate signal may have the deactivation level, the write gate signal may have the deactivation level, and the first driving voltage may have the driving high voltage.

[0014] In the fourth period after the third period, the compensation gate signal may have the inactive level, the initialization gate signal may have the inactive level, the write gate signal may have the inactive level, and the first driving voltage may have the low driving voltage.

[0015] In the fourth period after the third period, the compensation gate signal may have the inactive level, the initialization gate signal may have the inactive level, the write gate signal may have the inactive level, and the first driving voltage may have the driving high voltage.

[0016] In the fifth interval after the fourth interval, the write gate signal may have the activation level, the data voltage may have a pixel data voltage, and the first driving voltage may have the low driving voltage.

[0017] In the fifth interval after the fourth interval, the write gate signal may have the activation level, the data voltage may have a pixel data voltage, and the first driving voltage may have the high driving voltage.

[0018] In the sixth period after the fifth period, the compensation gate signal may have the inactive level, the initialization gate signal may have the active level, the write gate signal may have the inactive level, and the first driving voltage may have the high driving voltage.

[0019] In the sixth period after the fifth period, the compensation gate signal may have the inactive level, the initialization gate signal may have the active level, the write gate signal may have the inactive level, and the first driving voltage may have the low driving voltage.

[0020] In the seventh period after the sixth period, the compensation gate signal may have the inactive level, the initialization gate signal may have the inactive level, the write gate signal may have the inactive level, the first driving voltage may have the high driving voltage, and the second driving voltage may have the low driving voltage.

[0021] The pixel circuit may further include a fourth transistor that applies an initialization voltage to the second node in response to an initialization gate signal, the first transistor may be a p-type transistor, and the second to fourth transistors may be n-type transistors.

[0022] The pixel circuit may further include a fourth transistor that applies an initialization voltage to the second node in response to an initialization gate signal, and a second capacitor including a first electrode to which the initialization voltage is applied and a second electrode connected to the third node, wherein the second transistor includes a control electrode to which the write gate signal is applied, a first electrode to which the data voltage is applied, and a second electrode connected to the third node, the third transistor includes a control electrode to which the compensation gate signal is applied, a first electrode connected to the second node, and a second electrode connected to the first node, and the fourth transistor includes a control electrode to which the initialization gate signal is applied, a first electrode to which the initialization voltage is applied, and a second electrode connected to the second node.

[0023] The pixel circuit may be disposed on a silicon-based substrate.

[0024] A pixel circuit according to an embodiment of the present invention includes a first transistor including a control electrode connected to a first node, a first electrode to which a first driving voltage is applied, and a second electrode connected to a second node; a second transistor including a control electrode to which a write gate signal is applied, a first electrode to which a data voltage is applied, and a second electrode connected to a third node; a third transistor including a control electrode to which a compensation gate signal is applied, a first electrode connected to the second node, and a second electrode connected to the first node; a fourth transistor including a first electrode, a first electrode to which an initialization voltage is applied, and a second electrode connected to the second node; a first capacitor including a first electrode connected to the third node and a second electrode connected to the first node; a second capacitor including a first electrode to which a reference voltage is applied and a second electrode connected to the third node; and a light emitting element including a first electrode connected to the second node and a second electrode to which a second driving voltage is applied, wherein the first driving voltage and the second driving voltage change during a frame period.

[0025] The frame period in which the pixel circuit is driven includes a first initialization period, a compensation period, a writing period, a second initialization period, and a light-emitting period, and in the first initialization period, the compensation gate signal has an activation level, the initialization gate signal has an activation level, the writing gate signal has an activation level, the data voltage has a reference data voltage, the first driving voltage has a low driving voltage, and the second driving voltage has a high driving voltage, and in the compensation period, the compensation gate signal has an activation level, the initialization gate signal has a deactivation level, and the first driving voltage The first driving voltage may have the high driving voltage, and the second driving voltage may have the high driving voltage; in the write period, the write gate signal may have an activation level, the data voltage may be a pixel data voltage, the first driving voltage may have the low driving voltage, and the second driving voltage may have the high driving voltage; in the second initialization period, the initialization gate signal may have an activation level, the first driving voltage may have the low driving voltage, and the second driving voltage may have the high driving voltage; and in the light emitting period, the first driving voltage may have the high driving voltage, and the second driving voltage may have the low driving voltage.

[0026] The first transistor may be a p-type transistor, and the second to fourth transistors may be n-type transistors.

[0027] The reference voltage may be the initialization voltage.

[0028] an input control signal for driving the display panel based on the input control signal; and a processor for outputting the input control signal. The pixel circuits include a first transistor including a control electrode connected to a first node, a first electrode to which a first drive voltage is applied, and a second electrode connected to a second node; a second transistor for applying a data voltage to a third node in response to a write gate signal; a third transistor for connecting the first node and the second node in response to a compensation gate signal; a first capacitor including a first electrode connected to the third node and a second electrode connected to the first node; and a light-emitting element including a first electrode connected to the second node and a second electrode to which a second drive voltage is applied. The first drive voltage has a high drive voltage or a low drive voltage, the second drive voltage has the high drive voltage or the low drive voltage, and the compensation gate signal is a global signal applied to at least two pixel rows at the same time.

[0029] The pixel circuit may further include a fourth transistor that applies an initialization voltage to the second node in response to an initialization gate signal, and the initialization gate signal may be the global signal.

[0030] The pixel circuit may further include a second capacitor including a first electrode to which the initialization voltage is applied and a second electrode connected to the third node. [Effects of the Invention]

[0031] According to such a pixel circuit and a display device including the same, the pixel circuit has a 4T2C structure. The threshold voltage of the drive transistor is compensated for by the compensation transistor of the pixel circuit. This improves the drive reliability of the pixel circuit. Also, the light emission reliability of the light-emitting element is improved. Furthermore, since the pixel circuit has a 4T2C structure, the integration degree of the pixel circuit can be improved.

[0032] Furthermore, the first driving voltage has a high driving voltage or a low driving voltage in the frame period, and the second driving voltage has a high driving voltage or a low driving voltage in the frame period. In the light-emitting period of the frame period, the first driving voltage has a high driving voltage, and the second driving voltage has a low driving voltage. This allows multiple pixel rows to emit light. For example, multiple pixel rows can emit light simultaneously. For example, multiple pixel rows can be driven to emit light simultaneously.

[0033] However, the effects of the present invention are not limited to the effects mentioned above, and can be expanded in various ways without departing from the spirit and scope of the present invention. [Brief explanation of the drawings]

[0034] [Figure 1] FIG. 1 is a block diagram showing a display device according to an embodiment of the present invention. [Figure 2] FIG. 2 is a block diagram showing an example of signals applied to pixel circuits included in the display device of FIG. [Figure 3] FIG. 3 is a circuit diagram showing an example of a pixel circuit included in the display device of FIG. [Figure 4] FIG. 4 is a timing diagram showing an example of signals applied to the pixel circuit of FIG. [Figure 5] FIG. 5 is a circuit diagram showing the operation of the pixel circuit of FIG. 3 in the first interval of FIG. [Figure 6] FIG. 6 is a circuit diagram showing the operation of the pixel circuit of FIG. 3 in the second interval of FIG. [Figure 7] FIG. 7 is a circuit diagram showing the operation of the pixel circuit of FIG. 3 in the third interval of FIG. [Figure 8] FIG. 8 is a circuit diagram showing the operation of the pixel circuit of FIG. 3 in the fifth interval of FIG. [Figure 9] FIG. 9 is a circuit diagram showing the operation of the pixel circuit in the sixth interval of FIG. [Figure 10] FIG. 10 is a circuit diagram showing the operation of the pixel circuit in the seventh section of FIG. [Figure 11]FIG. 11 is a timing diagram showing an example of signals applied to the pixel circuit of FIG. [Figure 12] FIG. 12 is a timing diagram showing an example of signals applied to the pixel circuit of FIG. [Figure 13] FIG. 13 is a timing chart showing an example of signals applied to the pixel circuit of FIG. [Figure 14] FIG. 14 is a circuit diagram showing an example of a pixel circuit included in the display device of FIG. [Figure 15] FIG. 15 is a timing chart showing an example of signals applied to the pixel circuit of FIG. [Figure 16] FIG. 16 is a circuit diagram showing an example of a pixel circuit included in the display device of FIG. [Figure 17] FIG. 17 is a diagram showing an example in which pixel circuits included in the display device of FIG. 1 are arranged on a substrate. [Figure 18] FIG. 18 is a block diagram illustrating an electronic device according to one embodiment of the present invention. [Figure 19] FIG. 19 is a diagram illustrating an example in which the electronic device of FIG. 18 is implemented as a smartphone. [Figure 20] FIG. 20 is a diagram illustrating an example in which the electronic device of FIG. 18 is implemented in a virtual reality display system. DETAILED DESCRIPTION OF THE INVENTION

[0035] The present invention will now be described in more detail with reference to the accompanying drawings, in which: Figure 1 is a block diagram showing a display device 1 according to an embodiment of the present invention.

[0036] 1, the display device 1 includes a display panel 100 and a display panel driver. The display panel driver includes a driver control unit 200, a gate driver 300, a gamma reference voltage generator 400, a data driver 500, and a voltage output unit 600.

[0037] The display panel 100 includes a display section that displays an image and a peripheral section that is disposed adjacent to the display section.

[0038] The display panel 100 includes gate lines (GL), data lines (DL), and pixel circuits (PX) electrically connected to the gate lines (GL) and the data lines (DL). The gate lines (GL) extend in a first direction (D1). The data lines (DL) extend in a second direction (D2) that intersects with the first direction (D1).

[0039] The drive control unit 200 receives input image data (IMG) and input control signals (CONT) from an external device. For example, the input image data (IMG) includes red image data, green image data, and blue image data. The input image data (IMG) includes white image data. The input image data (IMG) includes magenta image data, yellow image data, and cyan image data. The input control signals (CONT) include a master clock signal and a data enable signal. The input control signals (CONT) further include a vertical synchronization signal and a horizontal synchronization signal.

[0040] The drive control unit 200 generates a first control signal (CONT1), a second control signal (CONT2), a third control signal (CONT3), a fourth control signal (CONT4), and a data signal (DATA) based on input image data (IMG) and an input control signal (CONT).

[0041] The driving control unit 200 generates a first control signal (CONT1) for controlling the operation of the gate driver 300 based on the input control signal (CONT), and outputs the first control signal (CONT1) to the gate driver 300. The first control signal (CONT1) includes a vertical start signal and a gate clock signal.

[0042] The driving control unit 200 generates a second control signal (CONT2) for controlling the operation of the data driver 500 based on the input control signal (CONT), and outputs the second control signal (CONT2) to the data driver 500. The second control signal (CONT2) includes a horizontal start signal and a load signal.

[0043] The driving control unit 200 generates a data signal (DATA) based on the input image data (IMG), and outputs the data signal (DATA) to the data driver 500.

[0044] The drive control unit 200 generates a third control signal (CONT3) for controlling the operation of the gamma reference voltage generation unit 400 based on the input control signal (CONT), and outputs the third control signal to the gamma reference voltage generation unit 400.

[0045] The drive control section 200 generates a fourth control signal (CONT4) for controlling the operation of the voltage output section 600 based on the input control signal (CONT), and outputs the fourth control signal to the voltage output section 600.

[0046] The gate driver 300 generates gate signals for driving the gate lines GL in response to a first control signal CONT1 input from the driving control unit 200. The gate driver 300 outputs the gate signals to the gate lines GL. For example, the gate signals include an initialization gate signal GI, a compensation gate signal GC, and a write gate signal GW[n].

[0047] In one embodiment of the present invention, the gate driver 300 is integrated in the periphery of the display panel 100. In one embodiment of the present invention, the gate driver 300 is mounted in the periphery of the display panel 100.

[0048] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to a third control signal CONT3 input from the driving control unit 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF may have a value corresponding to each data signal DATA.

[0049] For example, the gamma reference voltage generator 400 may be disposed in the driving control unit 200 or the data driver 500 .

[0050] The data driver 500 receives the second control signal (CONT2) and the data signal (DATA) from the drive control unit 200 and receives the gamma reference voltage (VGREF) from the gamma reference voltage generator 400. The data driver 500 converts the data signal (DATA) into an analog data voltage using the gamma reference voltage (VGREF). The analog data voltage is a pixel data voltage (PVDATA in FIG. 4). The pixel data voltage (PVDATA in FIG. 4) is a voltage corresponding to the data signal (DATA). The data driver 500 outputs a data voltage (VDATA) to the data line (DL). The data voltage (VDATA) includes a reference data voltage (DVREF) and a pixel data voltage (PVDATA).

[0051] In one embodiment of the present invention, the data driver 500 is integrated in the periphery of the display panel 100. In one embodiment of the present invention, the data driver 500 is implemented in the periphery of the display panel 100.

[0052] The voltage output unit 600 generates the driving voltage (DV) in response to a fourth control signal (CONT4) input from the driving control unit 200. The voltage output unit 600 outputs the driving voltage (DV) in response to the fourth control signal (CONT4). The voltage output unit 600 outputs a high driving voltage (VDD in FIG. 4) or a low driving voltage (VSS in FIG. 4) as a first driving voltage (DV1) based on the fourth control signal (CONT4). The voltage output unit 600 outputs a high driving voltage (VDD in FIG. 4) or a low driving voltage (VSS in FIG. 4) as a second driving voltage (DV2) based on the fourth control signal (CONT4). The high driving voltage (VDD in FIG. 4) is higher than the low driving voltage (VSS in FIG. 4). In one embodiment of the present invention, the driving voltage (DV) further includes an initialization voltage (VINT in FIG. 3) and a reference voltage (VREF in FIG. 3).

[0053] FIG. 2 is a block diagram showing an example of signals applied to pixel circuits (PX) included in the display device 1 of FIG.

[0054] As shown in FIGS. 1 and 2, the display panel 100 includes a plurality of pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]). A pixel row refers to a plurality of pixel circuits (PX) connected to the same write gate line. For example, the pixel circuits (PX) included in a pixel row are applied with the same write gate signal (GW[n]). The pixel circuits (PX) in the first pixel row (PX-R[1]) are applied with the first write gate signal (GW[1]). The pixel circuits (PX) in the second pixel row (PX-R[2]) are applied with the second write gate signal (GW[2]). The pixel circuits (PX) in the Nth pixel row (PX-R[n]) are applied with the Nth write gate signal (GW[n]).

[0055] In one embodiment of the present invention, the compensation gate signal (GC) is a global signal. The global signal refers to a signal that is applied to at least two pixel rows of a plurality of pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]) at the same timing. For example, the global signal refers to a signal that is applied to all pixel circuits (PX) included in the display panel 100 at the same timing. In one embodiment of the present invention, the initialization gate signal (GI) is the global signal.

[0056] In one embodiment of the present invention, the write gate signal (GW[n]) is a sequential signal. The sequential signal refers to a signal that is applied to multiple pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]) at different timings. In one embodiment of the present invention, the write gate signal (GW[n]) is applied sequentially to multiple pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]).

[0057] In one embodiment of the present invention, the write gate signal (GW[n]) is the sequential signal, and the compensation gate signal (GC) and the initialization gate signal (GI) are the global signals. Since the compensation gate signal (GC) is the global signal, the number of stages for generating the compensation gate signal (GC) is reduced. Also, since the initialization gate signal (GI) is the global signal, the number of stages for generating the initialization gate signal (GI) is reduced. This improves the integration density of the gate driver 300. Also, the power consumption of the display device 1 is reduced.

[0058] FIG. 3 is a circuit diagram showing an example of a pixel circuit (PX) included in the display device 1 of FIG.

[0059] As shown in Figures 1 to 3, the pixel circuit (PXA) includes a first transistor (T1A), a second transistor (T2A), a third transistor (T3A), a fourth transistor (T4A), a first capacitor (C1A), a second capacitor (C2A), and a light-emitting element (EE).

[0060] The first transistor (T1A) includes a control electrode connected to a first node (N1A), a first electrode to which a first drive voltage (DV1) is applied, and a second electrode connected to a second node (N2A). The first transistor (T1A) generates a drive current (ID) based on the voltage of the first node (N1A). The first transistor (T1A) outputs the drive current (ID) to a second node (N2A) based on the voltage of the first node (N1A). For example, the first transistor (T1A) is referred to as a drive transistor.

[0061] The second transistor (T2A) includes a control electrode to which a write gate signal (GW[n]) is applied, a first electrode to which a data voltage (VDATA) is applied, and a second electrode connected to a third node (N3A). The second transistor (T2A) applies the data voltage (VDATA) to the third node (N3A) in response to the write gate signal (GW[n]). For example, the second transistor (T2A) can be referred to as a write transistor.

[0062] The third transistor (T3A) includes a control electrode to which a compensation gate signal (GC) is applied, a first electrode connected to the second node (N2A), and a second electrode connected to the first node (N1A). The third transistor (T3A) connects the third node (N3A) and the first node (N1A) in response to the compensation gate signal (GC). For example, the third transistor (T3A) diode-connects the first transistor (T1A). For example, the third transistor (T3A) can be referred to as a compensation transistor.

[0063] The fourth transistor (T4A) includes a control electrode to which an initialization gate signal (GI) is applied, a first electrode to which an initialization voltage (VINT) is applied, and a second electrode connected to the second node (N2A). The fourth transistor (T4A) applies the initialization voltage (VINT) to the second node (N2A) in response to the initialization gate signal (GI). For example, the fourth transistor (T4A) can be referred to as an initialization transistor.

[0064] In one embodiment of the present invention, the first to fourth transistors (T1A, T2A, T3A, T4A) are p-type transistors.

[0065] The first capacitor (C1A) has a first electrode connected to the third node (N3A) and a second electrode connected to the first node (N1A), and couples a change in voltage at the third node (N3A) to apply the coupled voltage to the first node (N1A).

[0066] The second capacitor (C2A) includes a first electrode to which the reference voltage (VREF) is applied and a second electrode connected to the third node (N3A).

[0067] The light-emitting element (EE) includes a first electrode connected to the second node (N2A) and a second electrode to which a second driving voltage (DV2) is applied. The light-emitting element (EE) emits light based on the driving current (ID). In one embodiment of the present invention, the light-emitting element (EE) is an organic light-emitting diode (OLED), but is not limited thereto. In other embodiments, the light-emitting element (EE) is a nano light-emitting diode (NED), a quantum dot (QD) light-emitting diode, a micro light-emitting diode, an inorganic light-emitting diode, or any other suitable light-emitting element.

[0068] In one embodiment of the present invention, the pixel circuit (PXA) has a 4T2C structure. In one embodiment of the present invention, the third transistor (T3A) of the pixel circuit (PXA) compensates for the threshold voltage of the first transistor (T1A). This improves the driving reliability of the pixel circuit (PXA). Also, the light emission reliability of the light-emitting element (EE) is improved. Furthermore, since the pixel circuit (PXA) has a 4T2C structure, the integration degree of the pixel circuit (PXA) is improved.

[0069] FIG. 4 is a timing diagram showing an example of signals applied to the pixel circuit (PXA) of FIG. 3. FIG. 5 is a circuit diagram showing the operation of the pixel circuit (PXA) of FIG. 3 in a first interval (TP1A) of FIG. 4. FIG. 6 is a circuit diagram showing the operation of the pixel circuit (PXA) of FIG. 3 in a second interval (TP2A) of FIG. 4. FIG. 7 is a circuit diagram showing the operation of the pixel circuit (PXA) of FIG. 3 in a third interval (TP3A) of FIG. 4. FIG. 8 is a circuit diagram showing the operation of the pixel circuit (PXA) of FIG. 3 in a fifth interval (TP5A) of FIG. 4. FIG. 9 is a circuit diagram showing the operation of the pixel circuit (PXA) in a sixth interval (TP6A) of FIG. 4. FIG. 10 is a circuit diagram showing the operation of the pixel circuit (PXA) in a seventh interval (TP7A) of FIG. 4.

[0070] As shown in FIGS. 1 to 10, the frame period in which the pixel circuit (PXA) is driven includes first to seventh periods (TP1A, TP2A, TP3A, TP4A, TP5A, TP6A, and TP7A).

[0071] In the first section (TP1A), the compensation gate signal (GC) has an inactive level, the initialization gate signal (GI) has an inactive level, the data voltage (VDATA) has a reference data voltage (DVREF), the write gate signal (GW[n]) has an inactive level, the first drive voltage (DV1) has a low drive voltage (VSS), and the second drive voltage (DV2) has a high drive voltage (VDD).

[0072] In the first section (TP1A), the first driving voltage (DV1) has the driving low voltage (VSS), so that the first transistor (T1A) can stop generating the driving current (ID). Also, the second driving voltage (DV2) has the driving high voltage (VDD), so that the light emitting element (EE) can stop emitting light. For example, the first section (TP1A) can be referred to as a light emission interruption section.

[0073] In the second section (TP2A), the compensation gate signal (GC) has an activation level, the initialization gate signal (GI) has an activation level, the data voltage (VDATA) has a reference data voltage (DVREF), the write gate signal (GW[n]) has an activation level, the first drive voltage (DV1) has a low drive voltage (VSS), and the second drive voltage (DV2) has a high drive voltage (VDD).

[0074] During the second interval (TP2A), the fourth transistor (T4A) is turned on in response to the initialization gate signal (GI). Furthermore, the third transistor (T3A) is turned on in response to the compensation gate signal (GC). Since the third transistor (T3A) and the fourth transistor (T4A) are turned on, the initialization voltage (VINT) is applied to the first node (N1A). This initializes the first node (N1A) to the initialization voltage (VINT). During the second interval (TP2A), the second transistor (T2A) is turned on in response to the write gate signal (GW[n]). Since the second transistor (T2A) is turned on, the reference data voltage (DVREF) is applied to the third node (N3A). For example, the second interval (TP2A) can be referred to as a first initialization interval.

[0075] In the third section (TP3A), the compensation gate signal (GC) has an activation level, the initialization gate signal (GI) has a deactivation level, the data voltage (VDATA) has a reference data voltage (DVREF), the write gate signal (GW[n]) has an activation level, the first drive voltage (DV1) has a drive high voltage (VDD), and the second drive voltage (DV2) has a drive high voltage (VDD).

[0076] In the third interval (TP3A), the fourth transistor (T4A) is turned off in response to the initialization gate signal (GI). Also, the third transistor (T3A) is turned on in response to the compensation gate signal (GC). In the third interval (TP3A), the first drive voltage (DV1) has the drive high voltage (VDD). Since the first drive voltage (DV1) has the drive high voltage (VDD), the first transistor (T1A) is turned on. The third transistor (T3A) diode-connects the first transistor (T1A). As a result, a voltage compensated for the threshold voltage of the first transistor (T1A) is applied to the first node (N1A). For example, in the third interval (TP3A), the voltage of the first node (N1A) is the sum of the drive high voltage (VDD) and the threshold voltage of the first transistor (T1A). For example, the third section (TP3A) can be referred to as a compensation section.

[0077] In the fourth period (TP4A), the compensation gate signal (GC) has an inactive level, the initialization gate signal (GI) has an inactive level, the data voltage (VDATA) has a reference data voltage (DVREF), the write gate signal (GW[n]) has an inactive level, the first drive voltage (DV1) has a high drive voltage (VDD), and the second drive voltage (DV2) has a high drive voltage (VDD). For example, the fourth period (TP4A) can be referred to as a write standby period.

[0078] In the fifth section (TP5A), the compensation gate signal (GC) has an inactive level, the initialization gate signal (GI) has an inactive level, the data voltage (VDATA) has a pixel data voltage (PVDATA), the write gate signal (GW[n]) has an active level, the first drive voltage (DV1) has a low drive voltage (VSS), and the second drive voltage (DV2) has a high drive voltage (VDD).

[0079] During the fifth interval (TP5A), the third transistor (T3A) is turned off in response to the compensation gate signal (GC). Furthermore, the fourth transistor (T4A) is turned off in response to the initialization gate signal (GI). During the fifth interval (TP5A), the pixel data voltage (PVDATA) is applied to the third node (N3A) in response to the write gate signal (GW[n]). The first capacitor (C1A) couples the voltage change at the third node (N3A) and applies the coupled voltage to the first node (N1A). For example, during the fifth interval (TP5A), the voltage at the first node (N1A) is the difference between the pixel data voltage (PVDATA) and the reference data voltage (DVREF) plus the voltage at the first node (N1A) during the third interval (TP3A). Also, since the first driving voltage (DV1) has the driving low voltage (VSS), the first transistor (T1A) does not output the driving current (ID). In the fifth section (TP5A), a data voltage (VDATA) is applied to the plurality of pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]). For example, the fifth section (TP5A) can be referred to as a write section.

[0080] In the sixth section (TP6A), the compensation gate signal (GC) has an inactive level, the initialization gate signal (GI) has an active level, the data voltage (VDATA) has a reference data voltage (DVREF), the write gate signal (GW[n]) has an inactive level, the first drive voltage (DV1) has a low drive voltage (VSS), and the second drive voltage (DV2) has a high drive voltage (VDD).

[0081] In the sixth interval (TP6A), the second transistor (T2A) is turned off in response to the write gate signal (GW[n]). Also, the third transistor (T3A) is turned off in response to the compensation gate signal (GC). In the sixth interval (TP6A), the fourth transistor (T4A) is turned on in response to the initialization gate signal (GI). Since the fourth transistor (T4A) is turned on, the initialization voltage (VINT) is applied to the second node (N2A). For example, the second node (N2A) is initialized to the initialization voltage (VINT). For example, the sixth interval (TP6A) can be referred to as a second initialization interval.

[0082] In the seventh section (TP7A), the compensation gate signal (GC) has an inactive level, the initialization gate signal (GI) has an inactive level, the data voltage (VDATA) has a reference data voltage (DVREF), the write gate signal (GW[n]) has an inactive level, the first drive voltage (DV1) has a high drive voltage (VDD), and the second drive voltage (DV2) has a low drive voltage (VSS).

[0083] In the seventh section (TP7A), the first driving voltage (DV1) has the driving high voltage (VDD). Because the first driving voltage (DV1) has the driving high voltage (VDD), the first transistor (T1A) outputs the driving current (ID) based on the voltage of the first node (N1A). Also, the second driving voltage (DV2) has the driving low voltage (VSS). This causes the light-emitting element (EE) to emit light based on the driving current (ID). For example, the seventh section (TP7A) can be referred to as an emission section.

[0084] In one embodiment of the present invention, the pixel circuit (PXA) has a 4T2C structure. In one embodiment of the present invention, the third transistor (T3A) of the pixel circuit (PXA) compensates for the threshold voltage of the first transistor (T1A). This improves the driving reliability of the pixel circuit (PXA). Also, the light emission reliability of the light emitting element (EE) is improved. Furthermore, since the pixel circuit (PXA) has a 4T2C structure, the integration degree of the pixel circuit (PXA) can be improved.

[0085] In addition, in one embodiment of the present invention, the first driving voltage (DV1) has a high driving voltage (VDD) or a low driving voltage (VSS) during the frame period, and the second driving voltage (DV2) has a high driving voltage (VDD) or a low driving voltage (VSS) during the frame period. During the light-emitting period, the first driving voltage (DV1) has a high driving voltage (VDD), and the second driving voltage (DV2) has a low driving voltage (VSS). This causes multiple pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]) to emit light. For example, multiple pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]) can emit light simultaneously. For example, multiple pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]) can be driven to emit light simultaneously. Since multiple pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]) are driven to emit light simultaneously, the display device 1 does not include a driver for generating a light emission signal, which further improves the integration density of the display device 1.

[0086] FIG. 11 is a timing diagram showing an example of signals applied to the pixel circuit (PXA) of FIG.

[0087] The timing diagram of Figure 11 includes first to seventh periods (TP1B, TP2B, TP3B, TP4B, TP5B, TP6B, TP7B). The timing diagram of Figure 11 is substantially the same as the timing diagram of Figure 4, except that the first driving voltage (DV1) of the timing diagram of Figure 11 has the high driving voltage (VDD) in the fifth period (TP5B) and the sixth period (TP6B). Therefore, the same reference numerals are used to refer to the same or similar components, and redundant descriptions will be omitted.

[0088] As shown in FIGS. 1 to 3 and 11, the first driving voltage (DV1) has the driving high voltage (VDD) in the third to seventh sections (TP3B, TP4B, TP5B, TP6B, TP7B).

[0089] In one embodiment of the present invention, the first driving voltage (DV1) has a high driving voltage (VDD) or a low driving voltage (VSS) during the frame period, and the second driving voltage (DV2) has a high driving voltage (VDD) or a low driving voltage (VSS) during the frame period. During the light-emitting period, the first driving voltage (DV1) has a high driving voltage (VDD), and the second driving voltage (DV2) has a low driving voltage (VSS). This causes multiple pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]) to emit light. For example, multiple pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]) can emit light simultaneously. For example, multiple pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]) can be driven to emit light simultaneously. Since multiple pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]) are driven to emit light simultaneously, the display device 1 does not include a driver for generating a light emission signal, which further improves the integration density of the display device 1.

[0090] FIG. 12 is a timing diagram showing an example of signals applied to the pixel circuit (PXA) of FIG.

[0091] The timing diagram of Figure 12 includes first to seventh periods (TP1C, TP2C, TP3C, TP4C, TP5C, TP6C, and TP7C). The timing diagram of Figure 12 is substantially the same as the timing diagram of Figure 4, except that the first driving voltage (DV1) of the timing diagram of Figure 12 has a low driving voltage (VSS) in the fourth period (TP4C). Therefore, the same or similar elements are designated by the same reference numerals, and redundant descriptions will be omitted.

[0092] As shown in FIGS. 1 to 3 and 12, the first driving voltage (DV1) has the driving low voltage (VSS) in the fourth section (TP4C).

[0093] In one embodiment of the present invention, the first driving voltage (DV1) has a high driving voltage (VDD) or a low driving voltage (VSS) during the frame period, and the second driving voltage (DV2) has a high driving voltage (VDD) or a low driving voltage (VSS) during the frame period. During the light-emitting period, the first driving voltage (DV1) has a high driving voltage (VDD), and the second driving voltage (DV2) has a low driving voltage (VSS). This causes multiple pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]) to emit light. For example, multiple pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]) can emit light simultaneously. For example, multiple pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]) can be driven to emit light simultaneously. Since multiple pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]) are driven to emit light simultaneously, the display device 1 does not include a driver for generating a light emission signal, which further improves the integration density of the display device 1.

[0094] FIG. 13 is a timing diagram showing an example of signals applied to the pixel circuit (PXA) of FIG.

[0095] The timing diagram of Figure 13 includes first to seventh periods (TP1D, TP2D, TP3D, TP4D, TP5D, TP6D, and TP7D). The timing diagram of Figure 13 is substantially the same as the timing diagram of Figure 4, except that the first driving voltage (DV1) of the timing diagram of Figure 13 has the high driving voltage (VDD) in the sixth period (TP6D). Therefore, the same or similar elements are designated by the same reference numerals, and redundant descriptions will be omitted.

[0096] As shown in FIGS. 1 to 3 and 13, the first driving voltage (DV1) has the driving high voltage (VDD) in the sixth section (TP6D).

[0097] In one embodiment of the present invention, the first driving voltage (DV1) has a high driving voltage (VDD) or a low driving voltage (VSS) during the frame period, and the second driving voltage (DV2) has a high driving voltage (VDD) or a low driving voltage (VSS) during the frame period. During the light-emitting period, the first driving voltage (DV1) has a high driving voltage (VDD), and the second driving voltage (DV2) has a low driving voltage (VSS). This causes multiple pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]) to emit light. For example, multiple pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]) can emit light simultaneously. For example, multiple pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]) can be driven to emit light simultaneously. Since multiple pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]) are driven to emit light simultaneously, the display device 1 does not include a driver for generating a light emission signal, which further improves the integration density of the display device 1.

[0098] Fig. 14 is a circuit diagram showing an example of a pixel circuit (PXB) included in the display device 1 of Fig. 1. Fig. 15 is a timing chart showing an example of signals applied to the pixel circuit (PXB) of Fig. 14.

[0099] As shown in FIGS. 14 and 15, the pixel circuit (PXB) includes first to fourth transistors (T1A, T2B, T3B, T4B), first and second capacitors (C1A, C2A), and a light-emitting element (EE).

[0100] The second transistor (T2B) includes a control electrode to which a write gate signal (GWA[n]) is applied, a first electrode to which a data voltage (VDATA) is applied, and a second electrode connected to the third node (N3A). The third transistor (T3B) includes a control electrode to which a compensation gate signal (GCA) is applied, a first electrode connected to the second node (N2A), and a second electrode connected to the first node (N1A). The fourth transistor (T4B) includes a control electrode to which an initialization gate signal (GIA) is applied, a first electrode to which an initialization voltage (VINT) is applied, and a second electrode connected to the second node (N2A). In one embodiment of the present invention, the second to fourth transistors (T2B, T3B, T4B) are n-type transistors.

[0101] The pixel circuit (PXB) of FIG. 14 is substantially the same as the pixel circuit (PXA) of FIG. 3, except that the second to fourth transistors (T2B, T3B, and T4B) are n-type transistors. Therefore, the same reference numerals are used to designate the same or similar components, and redundant descriptions will be omitted. The timing diagram of FIG. 15 is substantially the same as the timing diagram of FIG. 4, except that the initialization gate signal (GIA) has an opposite phase to the initialization gate signal (GI) of FIG. 4, the compensation gate signal (GCA) has an opposite phase to the compensation gate signal (GC) of FIG. 4, and the write gate signal (GWA[n]) has an opposite phase to the write gate signal (GW[n]) of FIG. 4. Therefore, the same reference numerals are used to designate the same or similar components, and redundant descriptions will be omitted.

[0102] In one embodiment of the present invention, the pixel circuit (PXB) has a 4T2C structure. In one embodiment of the present invention, the threshold voltage of the first transistor (T1A) is compensated for by the third transistor (T3B) of the pixel circuit (PXB). This improves the driving reliability of the pixel circuit (PXB). Also, the light emission reliability of the light emitting element (EE) is improved. Furthermore, since the pixel circuit (PXB) has a 4T2C structure, the integration degree of the pixel circuit (PXB) can be improved.

[0103] In addition, in one embodiment of the present invention, the first driving voltage (DV1) has a high driving voltage (VDD) or a low driving voltage (VSS) during the frame period, and the second driving voltage (DV2) has a high driving voltage (VDD) or a low driving voltage (VSS) during the frame period. During the light-emitting period, the first driving voltage (DV1) has a high driving voltage (VDD), and the second driving voltage (DV2) has a low driving voltage (VSS). This causes multiple pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]) to emit light. For example, multiple pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]) can emit light simultaneously. For example, multiple pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]) can be driven to emit light simultaneously. Since multiple pixel rows (PX-R[1], PX-R[2], ..., PX-R[n]) are driven to emit light simultaneously, the display device 1 does not include a driver for generating a light emission signal, which further improves the integration density of the display device 1.

[0104] In one embodiment of the present invention, the second to fourth transistors (T2B, T3B, T4B) are n-type transistors. Because the second to fourth transistors (T2B, T3B, T4B) are n-type, current leakage is reduced, improving the driving stability of the pixel circuit (PXB) even when a relatively low power supply voltage is used. Furthermore, because the second to fourth transistors (T2B, T3B, T4B) are n-type transistors, the switching characteristics of the second to fourth transistors (T2B, T3B, T4B) are improved. This further improves the driving reliability of the pixel circuit (PXB).

[0105] FIG. 16 is a circuit diagram showing an example of a pixel circuit (PX) included in the display device 1 of FIG.

[0106] As shown in FIG. 16, the pixel circuit (PXC) includes first to fourth transistors (T1A, T2A, T3A, T4A), first and second capacitors (C1A, C2C), and a light-emitting element (EE).

[0107] The pixel circuit (PXC) of Figure 16 is substantially the same as the pixel circuit (PXA) of Figure 3, except that an initialization voltage (VINT) is applied to the first electrode of the second capacitor (C2C). Therefore, the same or similar components are denoted by the same reference numerals, and redundant descriptions will be omitted.

[0108] In one embodiment of the present invention, the pixel circuit (PXC) has a 4T2C structure. In one embodiment of the present invention, the threshold voltage of the first transistor (T1A) is compensated for by the third transistor (T3A) of the pixel circuit (PXC). This improves the driving reliability of the pixel circuit (PXC). It also improves the light emission reliability of the light emitting element (EE). Furthermore, since the pixel circuit (PXC) has a 4T2C structure, the integration degree of the pixel circuit (PXC) can be improved.

[0109] FIG. 17 is a diagram showing an example in which pixel circuits (PX) included in the display device 1 of FIG.

[0110] As shown in FIGS. 1 and 17, the pixel circuit (PX) is disposed on a substrate 101. In one embodiment of the present invention, the substrate 101 is a silicon-based substrate. In one embodiment of the present invention, the pixel circuit (PX) is disposed on a silicon-based substrate. Because the pixel circuit (PX) is disposed on a silicon-based substrate, the voltage level of the input signal applied to the pixel circuit (PX) can be set with higher precision. For example, the first drive voltage is stably output between the high drive voltage and the low drive voltage. Also, the second drive voltage is stably output between the high drive voltage and the low drive voltage.

[0111] The silicon-based substrate includes a single-crystal silicon wafer, a polycrystalline silicon wafer, or an amorphous silicon wafer. A semiconductor layer is formed on the silicon-based substrate by a semiconductor process. For example, the silicon-based substrate on which the semiconductor layer is formed is a silicon-based semiconductor substrate.

[0112] In one embodiment of the present invention, the semiconductor layer is formed on a silicon-based substrate by a CMOS (Complementary Metal Oxide Semiconductor) process. The semiconductor layer includes a CMOS-type pixel circuit. For example, the pixel circuit (PX) includes a CMOS circuit including a p-type transistor and an n-type transistor. As a result, the display device 1 is a DOS (Display on Silicon) or LEDoS (Light Emitting Diode on Silicon) device having a light-emitting structure on a silicon-based semiconductor substrate.

[0113] In one embodiment of the present invention, at least one of the transistors included in the pixel circuit (PX) is an n-type transistor. Since the pixel circuit (PX) is disposed on a silicon-based substrate, the at least one transistor included in the pixel circuit (PX) can be stably formed as an n-type transistor.

[0114] Fig. 18 is a block diagram illustrating an electronic device 1000 according to an embodiment of the present invention. Fig. 19 is a diagram illustrating an example in which the electronic device 1000 of Fig. 18 is implemented as a smartphone.

[0115] 18, the electronic device 1000 includes a processor 1010, a memory device 1020, a storage device 1030, an input / output device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 is the display device of FIG. 1. The electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a USB device, etc., or for communicating with other systems.

[0116] 19, according to an embodiment of the present invention, the electronic device 1000 may be embodied as a smartphone. However, this is merely an example, and the electronic device 1000 is not limited thereto. For example, the electronic device 1000 may be embodied as a mobile phone, a video phone, a smart pad, a smart watch, a tablet PC, a vehicle navigation system, a computer monitor, a laptop computer, a head-mounted display device, etc.

[0117] The processor 1010 may perform specific calculations or tasks. Depending on the embodiment, the processor 1010 may be a microprocessor, a central processing unit, an application processor, etc. The processor 1010 may be connected to other components via an address bus, a control bus, a data bus, etc. Depending on the embodiment, the processor 1010 may also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus.

[0118] The processor 1010 can output the input image data (IMG) and the input control signal (CONT) to the drive control unit 200 of FIG.

[0119] The memory device 1020 may store data necessary for the operation of the electronic device 1000. For example, the memory device 1020 may include non-volatile memory devices such as erasable programmable read-only memory (ERPOM) devices, electrically erasable programmable read-only memory (EERPOM) devices, flash memory devices, phase change random access memory (PRAM) devices, resistance random access memory (RRAM) devices, nano floating gate memory (NFGM) devices, polymer random access memory (PoRAM) devices, magnetic random access memory (MRAM), ferroelectric random access memory (FRAM) devices, etc., and / or volatile memory devices such as dynamic random access memory (DRAM) devices, static random access memory (SRAM) devices, mobile DRAM devices, etc.

[0120] The storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc. The input / output device 1040 may include input means such as a keyboard, a keypad, a touchpad, a touch screen, a mouse, etc., and output means such as a speaker, a printer, etc. Depending on the embodiment, a display device 1060 may also be included in the input / output device 1040. The power supply 1050 may provide power necessary for operation of the electronic device 1000. The display device 1060 may be connected to other components via the bus or other communication link.

[0121] 19 shows the electronic device of the present invention embodied as a smartphone, but the present invention is not limited thereto. The electronic device may be a television, a monitor, a laptop, a tablet, or a car.

[0122] FIG. 20 is a diagram illustrating an example in which the electronic device 1000 of FIG. 18 is implemented in a virtual reality display system.

[0123] 18 and 20, the virtual reality display system includes a lens unit 10, a display device 20, and a housing 30. The display device 20 is disposed adjacent to the lens unit 10. The housing 30 accommodates the lens unit 10 and the display device 20. Although FIG. 20 shows that the lens unit 10 and the display device 20 are accommodated on a first side of the housing 30, the present invention is not limited thereto. For example, the lens unit 10 may be accommodated on a first side of the housing 30, and the display device 20 may be accommodated on a second side of the housing 30 opposite to the first side of the housing 30. When the lens unit 10 and the display device 20 are accommodated on different sides of the housing 30, the housing 30 has a transmissive portion for transmitting light.

[0124] For example, the virtual reality display system is a head-mounted display system worn on the user's head. Although not shown, the virtual reality display system further includes a headband portion for wearing on the user's head.

[0125] Alternatively, the virtual reality display system may have a smart glass form embodied in the shape of glasses.

[0126] The electronic device may also be implemented as an augmented reality display system, a mixed reality display system, or an augmented reality display system. [Industrial Applicability]

[0127] The present invention can be applied to a display device and an electronic device including the same. For example, the display device of the present invention can be applied to a computer, a laptop, a mobile phone, a smartphone, a smart pad, a smart watch, a PMP, a PDA, an MP3 player, etc.

[0128] Although the present invention has been described with reference to the above embodiments, those skilled in the art will understand that various modifications and variations can be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below. [Explanation of symbols]

[0129] 100: Display panel 200: Drive control unit 300: Gate driver 400: Gamma reference voltage generator 500: Data drive unit 600: Voltage output section

Claims

1. a display panel including a plurality of pixel circuits; a display panel driver that drives the display panel, The pixel circuit a first transistor including a control electrode connected to a first node, a first electrode to which a first drive voltage is applied, and a second electrode connected to a second node; a second transistor for applying a data voltage to a third node in response to a write gate signal; a third transistor connecting the first node and the second node in response to a compensation gate signal; a first capacitor including a first electrode connected to the third node and a second electrode connected to the first node; a light-emitting element including a first electrode connected to the second node and a second electrode to which a second driving voltage is applied, the first driving voltage has a high driving voltage or a low driving voltage, and the second driving voltage has the high driving voltage or the low driving voltage; The display device, wherein the compensation gate signal is a global signal that is applied to at least two pixel rows at the same timing.

2. the pixel circuit further includes a fourth transistor that applies an initialization voltage to the second node in response to an initialization gate signal; The display device according to claim 1 , wherein the initialization gate signal is the global signal.

3. 3. The display device according to claim 2, wherein the pixel circuit further includes a second capacitor including a first electrode to which the initialization voltage is applied and a second electrode connected to the third node.

4. the pixel circuit further includes a fourth transistor that applies an initialization voltage to the second node in response to an initialization gate signal; The frame period in which the pixel circuit is driven includes first to seventh periods, 2. The display device of claim 1, wherein in the first period, the compensation gate signal has an inactive level, the initialization gate signal has an inactive level, the write gate signal has an inactive level, and the second driving voltage has the driving high voltage.

5. 5. The display device of claim 4, wherein in the second period after the first period, the compensation gate signal has an activation level, the initialization gate signal has an activation level, the write gate signal has an activation level, the data voltage has a reference data voltage, and the first driving voltage has the low driving voltage.

6. 6. The display device of claim 5, wherein in the third period after the second period, the compensation gate signal has the activation level, the initialization gate signal has the inactivation level, the write gate signal has the inactivation level, and the first driving voltage has the driving high voltage.

7. 7. The display device of claim 6, wherein in the fourth period after the third period, the compensation gate signal has the inactive level, the initialization gate signal has the inactive level, the write gate signal has the inactive level, and the first driving voltage has the low driving voltage.

8. 7. The display device of claim 6, wherein in the fourth period after the third period, the compensation gate signal has the inactive level, the initialization gate signal has the inactive level, the write gate signal has the inactive level, and the first driving voltage has the high driving voltage.

9. 9. The display device of claim 8, wherein in the fifth period after the fourth period, the write gate signal has the activation level, the data voltage has a pixel data voltage, and the first driving voltage has the low driving voltage.

10. 9. The display device of claim 8, wherein in the fifth period after the fourth period, the write gate signal has the activation level, the data voltage has a pixel data voltage, and the first driving voltage has the driving high voltage.

11. 11. The display device of claim 10, wherein in the sixth period after the fifth period, the compensation gate signal has the inactive level, the initialization gate signal has the active level, the write gate signal has the inactive level, and the first driving voltage has the high driving voltage.

12. 11. The display device of claim 10, wherein in the sixth period after the fifth period, the compensation gate signal has the inactive level, the initialization gate signal has the active level, the write gate signal has the inactive level, and the first driving voltage has the low driving voltage.

13. 13. The display device of claim 12, wherein in the seventh period after the sixth period, the compensation gate signal has the inactive level, the initialization gate signal has the inactive level, the write gate signal has the inactive level, the first driving voltage has the high driving voltage, and the second driving voltage has the low driving voltage.

14. the pixel circuit further includes a fourth transistor that applies an initialization voltage to the second node in response to an initialization gate signal; 2. The display device according to claim 1, wherein the first transistor is a p-type transistor, and the second to fourth transistors are n-type transistors.

15. The pixel circuit a fourth transistor for applying an initialization voltage to the second node in response to an initialization gate signal; a second capacitor including a first electrode to which the initialization voltage is applied and a second electrode connected to the third node; the second transistor includes a control electrode to which the write gate signal is applied, a first electrode to which the data voltage is applied, and a second electrode connected to the third node; the third transistor includes a control electrode to which the compensation gate signal is applied, a first electrode connected to the second node, and a second electrode connected to the first node; 2. The display device according to claim 1, wherein the fourth transistor includes a control electrode to which the initialization gate signal is applied, a first electrode to which the initialization voltage is applied, and a second electrode connected to the second node.

16. The display device according to claim 1 , wherein the pixel circuit is disposed on a silicon-based substrate.

17. a first transistor including a control electrode connected to a first node, a first electrode to which a first drive voltage is applied, and a second electrode connected to a second node; a second transistor including a control electrode to which a write gate signal is applied, a first electrode to which a data voltage is applied, and a second electrode connected to a third node; a third transistor including a control electrode to which a compensation gate signal is applied, a first electrode connected to the second node, and a second electrode connected to the first node; a fourth transistor including a control electrode to which an initialization gate signal is applied, a first electrode to which an initialization voltage is applied, and a second electrode connected to the second node; a first capacitor including a first electrode connected to the third node and a second electrode connected to the first node; a second capacitor including a first electrode to which a reference voltage is applied and a second electrode connected to the third node; a light-emitting element including a first electrode connected to the second node and a second electrode to which a second driving voltage is applied, The pixel circuit, wherein the first drive voltage and the second drive voltage vary during a frame period.

18. the frame period in which the pixel circuit is driven includes a first initialization period, a compensation period, a writing period, a second initialization period, and a light-emitting period; In the first initialization period, the compensation gate signal has an activation level, the initialization gate signal has an activation level, the write gate signal has an activation level, the data voltage has a reference data voltage, the first driving voltage has a low driving voltage, and the second driving voltage has a high driving voltage; In the compensation period, the compensation gate signal has an activation level, the initialization gate signal has a deactivation level, the first driving voltage has the high driving voltage, and the second driving voltage has the high driving voltage; In the write period, the write gate signal has an activation level, the data voltage has a pixel data voltage, the first driving voltage has the low driving voltage, and the second driving voltage has the high driving voltage; In the second initialization period, the initialization gate signal has an activation level, the first driving voltage has the low driving voltage, and the second driving voltage has the high driving voltage; The pixel circuit of claim 17 , wherein in the light-emitting section, the first driving voltage has the high driving voltage, and the second driving voltage has the low driving voltage.

19. 18. The pixel circuit of claim 17, wherein the first transistor is a p-type transistor, and the second to fourth transistors are n-type transistors.

20. The pixel circuit of claim 17 , wherein the reference voltage is the initialization voltage.

21. a display panel including a plurality of pixel circuits; a display panel driver that drives the display panel based on an input control signal; a processor that outputs the input control signal; The pixel circuit a first transistor including a control electrode connected to a first node, a first electrode to which a first drive voltage is applied, and a second electrode connected to a second node; a second transistor for applying a data voltage to a third node in response to a write gate signal; a third transistor connecting the first node and the second node in response to a compensation gate signal; a first capacitor including a first electrode connected to the third node and a second electrode connected to the first node; a light-emitting element including a first electrode connected to the second node and a second electrode to which a second driving voltage is applied, the first driving voltage has a high driving voltage or a low driving voltage, and the second driving voltage has the high driving voltage or the low driving voltage; The electronic device, wherein the compensation gate signal is a global signal that is applied to at least two pixel rows at the same timing.

22. the pixel circuit further includes a fourth transistor that applies an initialization voltage to the second node in response to an initialization gate signal; 22. The electronic device of claim 21, wherein the initialization gate signal is the global signal.

23. 23. The electronic device of claim 22, wherein the pixel circuit further comprises a second capacitor including a first electrode to which the initialization voltage is applied and a second electrode connected to the third node.

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