Display device and method of manufacturing the same

Abstract

To improve the yield of a display device.SOLUTION: According to an embodiment, a display device includes a substrate having a display region configured to display an image, a plurality of pixels arranged in the display region, a dummy pixel region including a plurality of dummy pixels configured not to display an image and surrounding the display region, a first partition wall surrounding each of the plurality of pixels and the plurality of dummy pixels, and a second partition wall arranged in a first region surrounding the dummy pixel region and a second region surrounding the first region and having a plurality of openings. Each of the first partition wall and the second partition wall may include a conductive lower portion and an upper portion having an end protruding from a side surface of the lower portion. Further, a first opening pattern of the second partition wall in the first region and a second opening pattern of the second partition wall in the second region are different from each other.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] FIELD An embodiment of the present invention relates to a display device and a manufacturing method thereof. [Background technology]

[0002] In recent years, display devices that use organic light-emitting diodes (OLEDs) as display elements have come into practical use. Techniques for improving the yield of such display devices are needed. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2000-195677 [Patent Document 2] Japanese Patent Application Laid-Open No. 2004-207217 [Patent Document 3] Japanese Patent Application Laid-Open No. 2008-135325 [Patent Document 4] Japanese Patent Application Laid-Open No. 2009-32673 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-118191 [Patent Document 6] International Publication No. 2018 / 179308 [Patent Document 7] US Patent Application Publication No. 2022 / 0077251 Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a display device and a manufacturing method thereof that can improve yield. [Means for solving the problem]

[0005] Generally, according to an embodiment, a display device includes a substrate having a display area for displaying an image, a plurality of pixels arranged in the display area, each of the pixels including a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode that emits light in response to application of a voltage, a dummy pixel area surrounding the display area and including a plurality of dummy pixels that do not display an image, a first partition surrounding each of the pixels and the dummy pixels, and a second partition having a plurality of openings, arranged in a first area surrounding the dummy pixel area and a second area surrounding the first area. The first partition and the second partition each include a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion. Furthermore, a first opening pattern of the second partition in the first area is different from a second opening pattern of the second partition in the second area.

[0006] According to an embodiment, a method for manufacturing a display device includes forming a first partition wall surrounding each of a plurality of pixels in a display region and a plurality of dummy pixels in a dummy pixel region surrounding the display region, forming a second partition wall having a plurality of openings in a first region surrounding the dummy pixel region and a second region surrounding the first region, forming a frame-shaped outer resin layer surrounding the display region so as to overlap at least the second region, and forming an inner resin layer covering an inner region of the outer resin layer. Furthermore, a first opening pattern of the second partition wall in the first region and a second opening pattern of the second partition wall in the second region are different from each other. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing an example of the configuration of a display device according to an embodiment. [Figure 2] FIG. 2 is a schematic plan view showing an example of a layout of sub-pixels. [Figure 3] FIG. 3 is a schematic cross-sectional view of the display device taken along line III-III in FIG. [Figure 4] FIG. 4 is a schematic plan view of a display device according to an embodiment. [Figure 5]FIG. 5 is a schematic cross-sectional view of a peripheral region of a display device according to an embodiment. [Figure 6] FIG. 6 is a schematic plan view showing an enlarged view of the area enclosed by the frame VI in FIG. [Figure 7] FIG. 7 is a schematic plan view showing an example of an opening pattern of the partition walls in the display region. [Figure 8] FIG. 8 is a schematic plan view showing an example of an opening pattern of the partition wall in the dummy pixel region. [Figure 9A] FIG. 9A is a schematic plan view showing an example of an opening pattern of the partition wall in the first region. [Figure 9B] FIG. 9B is a schematic plan view showing another example of the opening pattern of the partition wall in the first region. [Figure 10A] FIG. 10A is a schematic plan view showing an example of an opening pattern of the partition wall in the second region. [Figure 10B] FIG. 10B is a schematic plan view showing another example of the opening pattern of the partition wall in the second region. [Figure 10C] FIG. 10C is a schematic plan view showing still another example of the opening pattern of the partition wall in the second region. [Figure 11] FIG. 11 is a schematic diagram for explaining an example of a method for measuring the aperture ratio. [Figure 12] FIG. 12 is a schematic plan view of a motherboard according to an embodiment. [Figure 13] FIG. 13 is a schematic plan view of a panel unit according to one embodiment. [Figure 14] FIG. 14 is a flowchart showing an example of a manufacturing method of a display device according to an embodiment. [Figure 15A] FIG. 15A is a schematic cross-sectional view showing a manufacturing process of a display device. [Figure 15B] FIG. 15B is a schematic cross-sectional view showing a step subsequent to FIG. 15A. [Figure 15C] FIG. 15C is a schematic cross-sectional view showing a step subsequent to FIG. 15B. [Figure 15D]FIG. 15D is a schematic cross-sectional view showing a step subsequent to FIG. 15C. [Figure 15E] FIG. 15E is a schematic cross-sectional view showing a step subsequent to FIG. 15D. [Figure 15F] FIG. 15F is a schematic cross-sectional view showing a step subsequent to FIG. 15E. [Figure 15G] FIG. 15G is a schematic cross-sectional view showing a step subsequent to FIG. 15F. [Figure 16A] FIG. 16A is a schematic view illustrating a step of forming a resin layer. [Figure 16B] FIG. 16B is a schematic diagram for explaining the step subsequent to FIG. 16A. [Figure 17] FIG. 17 is a schematic plan view showing an example of a coating area of ​​the outer resin layer. [Figure 18] FIG. 18 is a schematic plan view of a partition wall according to a comparative example. [Figure 19A] FIG. 19A is a schematic cross-sectional view showing how droplets are discharged when a resin layer is formed. [Figure 19B] FIG. 19B is a schematic cross-sectional view showing the droplet shown in FIG. 19A attached to the sealing layer. [Figure 19C] FIG. 19C is a schematic cross-sectional view showing the spreading of the droplet shown in FIG. 19B. DETAILED DESCRIPTION OF THE INVENTION

[0008] Some embodiments will be described with reference to the drawings. The disclosure is merely an example, and appropriate modifications that a person skilled in the art can easily make while maintaining the gist of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may be schematic in terms of the width, thickness, shape, etc. of each part compared to the actual embodiment for the sake of clarity, but these are merely examples and are not intended to limit the interpretation of the present invention. Furthermore, in this specification and each drawing, components that perform the same or similar functions as those described above with reference to the previous drawings are designated by the same reference numerals, and redundant detailed descriptions may be omitted as appropriate.

[0009] In the drawings, mutually orthogonal X, Y, and Z axes are shown as necessary to facilitate understanding. The direction along the X axis is referred to as the X direction, the direction along the Y axis is referred to as the Y direction, and the direction along the Z axis is referred to as the Z direction. The Z direction is the normal direction of a plane including the X and Y directions. Viewing various elements parallel to the Z direction is referred to as planar view.

[0010] The display device according to each embodiment is an organic electroluminescence display device having an organic light-emitting diode (OLED) as a display element, and can be installed in various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0011] 1 is a diagram showing an example of the configuration of a display device DSP according to this embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA surrounding the display area DA. The substrate 10 may be made of glass or a flexible resin film.

[0012] In this embodiment, the shape of the substrate 10 and the display area DA in a plan view is circular. However, the shape of the substrate 10 and the display area DA in a plan view is not limited to circular, and may be other shapes such as rectangular, square, or elliptical.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the X and Y directions. Each pixel PX includes a plurality of subpixels SP that display different colors. In this embodiment, it is assumed that the pixel PX includes a blue subpixel SP1, a green subpixel SP2, and a red subpixel SP3. The pixel PX may include subpixels SP of other colors, such as white, in addition to or instead of the subpixels SP1, SP2, and SP3.

[0014] The display device DSP further includes a terminal section T arranged in the peripheral area SA. To the terminal section T, for example, a flexible circuit board is connected that supplies voltages and signals for driving the display device DSP.

[0015] The subpixel SP includes a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 includes a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements formed of, for example, thin film transistors.

[0016] In the display area DA, a plurality of scanning lines G that supply scanning signals to the pixel circuits 1 of each subpixel SP, a plurality of signal lines S that supply video signals to the pixel circuits 1 of each subpixel SP, and a plurality of power supply lines PL are arranged. In Fig. 1, the scanning lines G and the power supply lines PL extend in the X direction, and the signal lines S extend in the Y direction, but this is not limiting.

[0017] The gate electrode of the pixel switch 2 is connected to the scanning line G. One of the source electrode and drain electrode of the pixel switch 2 is connected to the signal line S, and the other is connected to the gate electrode of the drive transistor 3 and the capacitor 4. In the drive transistor 3, one of the source electrode and drain electrode is connected to the power line PL and the capacitor 4, and the other is connected to the display element DE.

[0018] The configuration of the pixel circuit 1 is not limited to the example shown in the drawing. For example, the pixel circuit 1 may include more thin film transistors and capacitors.

[0019] Fig. 2 is a schematic plan view showing an example of the layout of subpixels SP1, SP2, and SP3 that constitute one pixel PX. In the example of Fig. 2, the subpixels SP1 and SP3 are aligned in the Y direction. Furthermore, the subpixels SP1 and SP3 are aligned with the subpixel SP2 in the X direction.

[0020] When the subpixels SP1, SP2, and SP3 are laid out in this manner, the display area DA is formed with columns in which the subpixels SP1 and SP3 are alternately arranged in the Y direction, and columns in which multiple subpixels SP2 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of the subpixels SP1, SP2, and SP3 is not limited to the example in FIG. 2.

[0021] A rib layer 5 is disposed in the display area DA. The rib layer 5 has pixel openings AP1, AP2, and AP3 in the subpixels SP1, SP2, and SP3, respectively. In the example of FIG. 2, the pixel openings AP1, AP2, and AP3 are all rectangular. The area of ​​the pixel opening AP1 is larger than the area of ​​the pixel opening AP3. The area of ​​the pixel opening AP2 is also larger than the area of ​​the pixel opening AP1. However, the shapes of the pixel openings AP1, AP2, and AP3 are not limited to this example.

[0022] Subpixel SP1 includes a lower electrode LE1, an upper electrode UE1, and an organic layer OR1 that overlap pixel aperture AP1. Subpixel SP2 includes a lower electrode LE2, an upper electrode UE2, and an organic layer OR2 that overlap pixel aperture AP2. Subpixel SP3 includes a lower electrode LE3, an upper electrode UE3, and an organic layer OR3 that overlap pixel aperture AP3.

[0023] The lower electrode LE1, upper electrode UE1, and organic layer OR1 form the display element DE1 of subpixel SP1. The lower electrode LE2, upper electrode UE2, and organic layer OR2 form the display element DE2 of subpixel SP2. The lower electrode LE3, upper electrode UE3, and organic layer OR3 form the display element DE3 of subpixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0024] A conductive partition wall 6A (first partition wall) is disposed above the rib layer 5. The partition wall 6A serves as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3. The partition wall 6A entirely overlaps the rib layer 5 and has the same planar shape as the rib layer 5. The partition wall 6A surrounds the subpixels SP1, SP2, and SP3.

[0025] The partition 6A has a plurality of slits SLa extending in the Y direction. In the example of FIG. 2, the subpixels SP1, SP2, and SP3 that make up one pixel PX are arranged between two slits SLa in the X direction. Furthermore, the partition 6A has connecting portions CT that connect the portions separated by the slits SLa. Note that the arrangement of the slits SLa and the connecting portions CT is not limited to the example of FIG. 2. For example, there may be slits SLa that are continuous between both ends of the display area DA in the Y direction.

[0026] Sealing layers SE11, SE12, and SE13 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the display element DE1 and the partition wall 6A around it. The sealing layer SE12 continuously covers the display element DE2 and the partition wall 6A around it. The sealing layer SE13 continuously covers the display element DE3 and the partition wall 6A around it.

[0027] 2, the sealing layers SE11, SE12, and SE13 do not overlap with the slit SLa. As another example, at least one of the sealing layers SE11, SE12, and SE13 may overlap with the slit SLa.

[0028] 3 is a schematic cross-sectional view of the display device DSP taken along line III-III in FIG. 2. A circuit layer 11 is disposed on the above-described substrate 10. The circuit layer 11 includes various circuits and wirings such as the pixel circuits 1, scanning lines G, signal lines S, and power supply lines PL shown in FIG. 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens unevenness caused by the circuit layer 11.

[0029] The lower electrodes LE1, LE2, and LE3 are disposed on the organic insulating layer 12. The rib layer 5 is disposed on the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The peripheral edges of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross section of FIG. 3 , the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through a contact hole provided in the organic insulating layer 12.

[0030] The partition wall 6A includes a conductive lower portion 61 disposed on the rib layer 5 and an upper portion 62 disposed on the lower portion 61. The upper portion 62 has a width greater than that of the lower portion 61. That is, the partition wall 6A has an overhanging shape in which both ends of the upper portion 62 protrude beyond the side surfaces of the lower portion 61.

[0031] In the example of FIG. 3, the lower part 61 has a bottom layer 63 disposed on the rib layer 5 and a shaft layer 64 disposed on the bottom layer 63. For example, the bottom layer 63 is formed thinner than the shaft layer 64. In the example of FIG. 3, both ends of the bottom layer 63 protrude from the side surfaces of the shaft layer 64.

[0032] 3, the upper portion 62 includes a first top layer 65 and a second top layer 66 disposed on the first top layer 65. For example, the width of the second top layer 66 is slightly smaller than the width of the first top layer 65. However, the present invention is not limited to this, and the first top layer 65 and the second top layer 66 may have the same width.

[0033] The organic layer OR1 covers the lower electrode LE1 through the pixel opening AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel opening AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel opening AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6A.

[0034] Display element DE1 includes a cap layer CP1 that covers the upper electrode UE1. Display element DE2 includes a cap layer CP2 that covers the upper electrode UE2. Display element DE3 includes a cap layer CP3 that covers the upper electrode UE3. The cap layers CP1, CP2, and CP3 serve as optical adjustment layers to improve the extraction efficiency of light emitted by the organic layers OR1, OR2, and OR3, respectively.

[0035] In the following description, the multilayer body including the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the laminate film FL1, the multilayer body including the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the laminate film FL2, and the multilayer body including the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the laminate film FL3.

[0036] Sealing layers SE11, SE12, and SE13 are disposed in the subpixels SP1, SP2, and SP3, respectively. The sealing layer SE11 continuously covers the stacked film FL1 and the surrounding partition wall 6A. The sealing layer SE12 continuously covers the stacked film FL2 and the surrounding partition wall 6A. The sealing layer SE13 continuously covers the stacked film FL3 and the surrounding partition wall 6A.

[0037] 3, the sealing layer SE11 on the partition wall 6A between the subpixels SP1 and SP2 is spaced apart from the sealing layer SE12 on the partition wall 6A. Also, the sealing layer SE11 on the partition wall 6A between the subpixels SP1 and SP3 is spaced apart from the sealing layer SE13 on the partition wall 6A. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact with each other above the partition wall 6A.

[0038] For example, gaps are formed between the sealing layers SE11, SE12, and SE13 and the upper portion 62 of the partition wall 6A. The stacked films FL1, FL2, and FL3 may be disposed in at least a part of these gaps.

[0039] The sealing layers SE11, SE12, and SE13 are covered with a resin layer RS1. The resin layer RS1 is covered with a sealing layer SE2. The sealing layer SE2 is covered with a resin layer RS2. The resin layers RS1 and RS2 and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0040] 3, a touch panel electrode TP for detecting a touch operation by a user is disposed on the sealing layer SE2. The touch panel electrode TP is made of, for example, a metal material, and has the same shape as the partition wall 6A in plan view.

[0041] A cover member such as a polarizing plate, a protective film, or a cover glass may be further disposed above the resin layer RS2. Such a cover member may be adhered to the resin layer RS2 via an adhesive layer such as OCA (Optical Clear Adhesive).

[0042] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, and SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, and SE2 are formed of silicon nitride. The resin layers RS1 and RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0043] The lower electrodes LE1, LE2, and LE3 each include a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0044] The upper electrodes UE1, UE2, UE3 are formed of a metal material such as an alloy of magnesium and silver (MgAg). For example, the lower electrodes LE1, LE2, LE3 correspond to anodes, and the upper electrodes UE1, UE2, UE3 correspond to cathodes.

[0045] The organic layers OR1, OR2, and OR3 are each composed of a plurality of thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in this order in the Z direction. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including a plurality of emissive layers.

[0046] The cap layers CP1, CP2, and CP3 have a laminated structure in which, for example, multiple transparent layers are stacked. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. These transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from the refractive indices of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. At least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0047] The bottom layer 63 and the shaft layer 64 of the partition wall 6A are formed of a metal material. Examples of the metal material for the bottom layer 63 include molybdenum, titanium, titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), and a molybdenum-niobium alloy (MoNb). Examples of the metal material for the shaft layer 64 include aluminum, an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), and an aluminum-silicon alloy (AlSi). The shaft layer 64 may be formed of an insulating material.

[0048] The first top layer 65 of the partition wall 6A is formed of, for example, a metal material. The second top layer 66 of the partition wall 6A is formed of, for example, a conductive oxide. Examples of the metal material that can be used to form the first top layer 65 include titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, and a molybdenum-niobium alloy. Examples of the conductive oxide that can be used to form the second top layer 66 include ITO or IZO. The upper portion 62 may include three or more layers or may be formed of a single layer. Furthermore, the upper portion 62 may include a layer formed of an insulating material.

[0049] A common voltage is supplied to the partition wall 6A. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3 in contact with the lower portion 61. A pixel voltage corresponding to the video signal on the signal line S is supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively.

[0050] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of the organic layer OR1 emits light in the blue wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of the organic layer OR2 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of the organic layer OR3 emits light in the red wavelength range.

[0051] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include color filters that convert the light emitted by the light-emitting layers into light of the colors corresponding to the subpixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the colors corresponding to the subpixels SP1, SP2, and SP3.

[0052] 4 is a schematic plan view of the display device DSP. In the example of this figure, a dummy pixel region DMY, a partition wall 6B (second partition wall), a sealing layer SE1x, and a dam structure DS1 are arranged in the peripheral region SA. For example, the dummy pixel region DMY, the partition wall 6B, the sealing layer SE1x, and the dam structure DS1 are all circular and concentric with the display region DA.

[0053] The dummy pixel region DMY surrounds the display region DA. The partition wall 6B is located outside the dummy pixel region DMY (on the side farther from the display region DA) and surrounds the display region DA and the dummy pixel region DMY.

[0054] In this embodiment, the partition 6B has a first region A1 surrounding the dummy pixel region DMY and a second region A2 surrounding the first region A1. The second region A2 is connected to the underlying relay layer RL and the power supply line PW (see FIG. 5) via a plurality of contact portions CN1. The power supply line PW is connected to the terminal portion T and supplies a common voltage to the partition 6B. The partition 6A arranged in the display region DA is connected to the partition 6B. That is, the common voltage of the power supply line PW is supplied to the partition 6A via the partition 6B and further to the upper electrodes UE1, UE2, and UE3 in contact with the partition 6A. In the example of FIG. 4, a plurality of contact portions CN1 are arranged in an arc shape on the terminal portion T side.

[0055] The sealing layer SE1x covers the entire partition wall 6B, i.e., the first area A1 and the second area A2. In the example of Fig. 4, the sealing layer SE1x surrounds the display area DA. The sealing layer SE1x is made of the same inorganic insulating material as the sealing layers SE11, SE12, and SE13.

[0056] The dam structure DS1 is located outside the partition wall 6B and surrounds the display area DA, the dummy pixel area DMY, the partition wall 6B, and the sealing layer SE1x. The terminal portion T is located outside the dam structure DS1.

[0057] 5 is a schematic cross-sectional view of the peripheral area SA of the display device DSP. The partition wall 6B has the same structure as the partition wall 6A. That is, the partition wall 6B includes a lower portion 61 and an upper portion 62. The lower portion 61 includes a bottom layer 63 and an axis layer 64, and the upper portion 62 includes a first top layer 65 and a second top layer 66. At the end of the partition wall 6B, the upper portion 62 protrudes beyond the side surface of the lower portion 61.

[0058] The circuit layer 11 shown in FIG. 3 includes inorganic insulating layers 31, 32, and 33 formed of an inorganic insulating material, an organic insulating layer 34 formed of an organic insulating material, and metal layers 41, 42, and 43. The inorganic insulating layer 31 covers the upper surface of the substrate 10. The metal layer 41 is disposed on the inorganic insulating layer 31. The inorganic insulating layer 32 covers the metal layer 41. The metal layer 42 is disposed on the inorganic insulating layer 32. The inorganic insulating layer 33 covers the metal layer 42. The organic insulating layer 34 covers the inorganic insulating layer 33. The metal layer 43 is disposed on the organic insulating layer 34 and is covered by the organic insulating layer 12.

[0059] For example, the dam structure DS1 includes a dam portion DM1, a dam portion DM2 surrounding the dam portion DM1, and a dam portion DM3 surrounding the dam portion DM2. For example, the dam portions DM1, DM2, and DM3 are circular and surround the display area DA. The number of dam portions included in the dam structure DS1 is not limited to three.

[0060] Dam portions DM1, DM2, and DM3 all protrude above the substrate 10. In the example of FIG. 5, dam portion DM1 is formed from organic insulating layers 12 and 34. Dam portions DM2 and DM3 are also formed from organic insulating layers 12 and 34. That is, in this embodiment, dam portions DM1, DM2, and DM3 are formed from the same material as organic insulating layers 12 and 34 and in the same layer as organic insulating layers 12 and 34.

[0061] A power supply line PW to which a common voltage is applied is disposed below the dam portions DM1 and DM2. The power supply line PW has a first wiring W1 formed by the metal layer 42 and a second wiring W2 formed by the metal layer 43.

[0062] 5, the first wiring W1 and the second wiring W2 are in contact with each other at a contact portion CN0 located between the dam portions DM1 and DM2. In each of the dam portions DM1 and DM2, a portion of the second wiring W2 is located between the organic insulating layers 12 and 34.

[0063] The peripheral area SA is further provided with a conductive relay layer RL that connects the partition wall 6B and the power supply line PW, and a rib layer 5. The relay layer RL is formed, for example, from the same material and by the same process as the above-described lower electrodes LE1, LE2, and LE3.

[0064] The relay layer RL is located closer to the display area DA side (left side in the drawing) than the dam portion DM1, and covers the organic insulating layer 12. The rib layer 5 continuously covers the relay layer RL and the dam portions DM1, DM2, and DM3.

[0065] The partition wall 6B is disposed on the rib layer 5. The partition wall 6B is in contact with the relay layer RL at the contact portion CN1, which is also shown in FIG. 4. Specifically, the rib layer 5 has an opening at the contact portion CN1, and a lower portion 61 (specifically, a bottom layer 63) of the partition wall 6B is in contact with the relay layer RL through this opening. The contact portion CN1 is located above the organic insulating layer 12.

[0066] The relay layer RL is in contact with the second wiring W2 of the power supply line PW at the contact portion CN2, which is located between the end E0 of the organic insulating layer 12 and the dam portion DM1 in plan view.

[0067] A stacked film FLx is disposed on the partition wall 6B. The partition wall 6B and the stacked film FLx are covered with a sealing layer SE1x. The stacked film FLx is formed by the same process and from the same material as any one of the stacked films FL1, FL2, and FL3 shown in FIG. 3. The sealing layer SE1x is formed by the same process and from the same material as any one of the sealing layers SE11, SE12, and SE13 shown in FIG. 3. In this embodiment, it is assumed that the stacked film FLx and the sealing layer SE1x are formed by the same process and from the same material as the stacked film FL3 and the sealing layer SE13, respectively. That is, the stacked film FLx includes an upper electrode UE3, an organic layer OR3, and a cap layer CP3.

[0068] Above the sealing layer SE1x, the resin layer RS1, the sealing layer SE2, and the resin layer RS2 shown in Fig. 3 are arranged. Also, above the sealing layer SE2, the touch panel wiring TPL connected to the touch panel electrodes TP shown in Fig. 3 is arranged. For example, the touch panel wiring TPL is made of the same material as the touch panel electrodes TP.

[0069] The resin layer RS1 covers the sealing layer SE1x and the rib layer 5. The dam portions DM1, DM2, and DM3 serve to block the resin layer RS1 before hardening during the manufacturing of the display device DSP. In the example of FIG. 5, the end portion Er1 of the resin layer RS1 is located above the dam portion DM2. That is, the resin layer RS1 covers the dam portion DM1 and a part of the dam portion DM2. However, the position of the end portion Er1 is not limited to this example.

[0070] The sealing layer SE2 covers the end portion Er1 of the resin layer RS1. The sealing layer SE2 is in contact with the rib layer 5 in an area outside the end portion Er1 (to the right in the figure). In the example of FIG. 5, the sealing layer SE2 is removed near the dam portion DM3. The resin layer RS1 is surrounded by the sealing layer SE1x, the rib layer 5, and the sealing layer SE2. This prevents moisture from penetrating the resin layer RS1.

[0071] 5, the organic insulating layer 12 may have a first portion PN1 and a second portion PN2 that is thinner than the first portion PN1. The second portion PN2 is formed on the periphery of the first portion PN1. That is, the second portion PN2 surrounds the first portion PN1 in a plan view. The partition wall 6B, the stacked film FLx, and the sealing layer SE1x are all located above the first portion PN1.

[0072] 5, the organic insulating layer 34 is disposed below the first portion PN1, and the organic insulating layer 34 is not disposed below the second portion PN2. A step portion 12a is formed in the organic insulating layer 12 near the end of the organic insulating layer 34. For example, the portion of the organic insulating layer 12 closer to the dam portion DM1 than the step portion 12a corresponds to the second portion PN2.

[0073] The relay layer RL covers the first portion PN1, the second portion PN2, and the step portion 12a. If the organic insulating layer 12 did not have the second portion PN2, the step portion 12a would be steeper. If the relay layer RL were formed to cover such a steep step portion 12a, an abnormal shape of the relay layer RL could occur. In contrast, if the second portion PN2 is provided, the step portion 12a can be reduced, and the relay layer RL can be formed well.

[0074] The cross-sectional structure shown in FIG. 5 can be applied to any position in the peripheral area SA except for the vicinity of the terminal portion T. However, the structure of the peripheral area SA is not necessarily limited to that shown in FIG. 5. For example, the organic insulating layer 12 does not necessarily have to have the second portion PN2. Furthermore, the structure for connecting the partition wall 6B and the power supply line PW can be modified as appropriate based on the position of the power supply line PW, the layer configuration of the circuit layer 11, etc.

[0075] 6 is a schematic plan view showing an enlarged view of the area enclosed by the frame VI in FIG. 4. A plurality of dummy pixels DPX are arranged in the dummy pixel area DMY. For example, the dummy pixel DPX includes dummy subpixels DP1, DP2, and DP3. The dummy subpixels DP1, DP2, and DP3 have structures similar to those of the subpixels SP1, SP2, and SP3 shown in FIG. 2, respectively.

[0076] That is, the dummy subpixel DP1 includes a lower electrode LE1, an organic layer OR1, an upper electrode UE1, and a sealing layer SE11. The dummy subpixel DP2 includes a lower electrode LE2, an organic layer OR2, an upper electrode UE2, and a sealing layer SE12. The dummy subpixel DP3 includes a lower electrode LE3, an organic layer OR3, an upper electrode UE3, and a sealing layer SE13.

[0077] However, the dummy subpixels DP1, DP2, and DP3 are configured not to emit light. Such a configuration can be achieved, for example, by cutting a part of the pixel circuit 1 in each of the dummy subpixels DP1, DP2, and DP3. Alternatively, the pixel openings AP1, AP2, and AP3 may be omitted from each of the dummy subpixels DP1, DP2, and DP3. This intervenes between the organic layers OR1, OR2, and OR3 and the lower electrodes LE1, LE2, and LE3, and prevents the application of a voltage to the organic layers OR1, OR2, and OR3 to cause them to emit light.

[0078] A part of the partition wall 6A is located in the dummy pixel region DMY and surrounds each of the dummy pixels DPX. More specifically, the partition wall 6A surrounds each of the dummy subpixels DP1, DP2, and DP3.

[0079] The partition walls 6A and 6B are formed continuously. For example, the partition wall 6B corresponds to a portion of the partition walls formed continuously in this manner that overlaps with the sealing layer SE1x. In Fig. 5, the sealing layer SE1x is indicated by a dashed line pattern.

[0080] The lower electrodes LE1, LE2, LE3 and pixel circuits PC are arranged in the display area DA and the dummy pixel area DMY, but are not arranged in the first area A1 and the second area A2. Therefore, the partition 6B can be said to be a portion of the partition formed continuously across the display area DA and the peripheral area SA where the lower electrodes LE1, LE2, LE3 and pixel circuits PC are not provided.

[0081] In this embodiment, the display area DA, dummy pixel area DMY, first area A1, and second area A2 all have circular outer shapes. Such outer shapes can be achieved by forming stepped boundaries between the display area DA and dummy pixel area DMY, between the dummy pixel area DMY and first area A1, and between the first area A1 and second area A2, as shown in FIG.

[0082] In each of the first region A1 and the second region A2, the partition 6B has a plurality of openings. In this embodiment, the opening pattern in the first region A1 (first opening pattern) is different from the opening pattern in the second region A2 (second opening pattern). Furthermore, the opening pattern in the second region A2 is also different from the opening pattern (third opening pattern) of the partition 6A in the display region DA and the dummy pixel region DMY.

[0083] As will be described in detail later, the opening patterns in the first region A1 and the second region A2 can affect the quality of the shape of the resin layer RS1. From the viewpoint of forming a resin layer RS1 with a good shape, it is preferable that the second region A2 has a shape that makes it more difficult for the resin material of the resin layer RS1 to wet and spread before hardening than the first region A1. This relationship can be achieved, for example, by making the opening ratio of the partition walls 6B in the second region A2 lower than the opening ratio of the partition walls 6B in the first region A1.

[0084] Examples of configurations applicable to the opening patterns of the partitions 6A and 6B in the display area DA, dummy pixel area DMY, first area A1, and second area A2 will be described below with reference to Figures 7, 8, 9A, 9B, 10A, 10B, and 10C. The opening patterns of the partitions 6A and 6B refer to patterns formed by openings and slits shown in these figures.

[0085] 7 is a schematic plan view showing an example of an opening pattern of the partition wall 6A in the display area DA. The partition wall 6A shown in this figure has the same shape as that shown in FIG. 2, and has openings 71, 72, and 73 in each pixel PX. The openings 71, 72, and 73 are rectangular and surround the subpixels SP1, SP2, and SP3, respectively. Furthermore, the partition wall 6A has a plurality of slits SLa located between adjacent pixels PX. Connections CT are formed between the slits SLa aligned in the Y direction.

[0086] 8 is a schematic plan view showing an example of an opening pattern of the partition 6A in the dummy pixel region DMY. The partition 6A has openings 81, 82, and 83 in each of the dummy pixels DPX. The openings 81, 82, and 83 are rectangular and surround the dummy sub-pixels DP1, DP2, and DP3, respectively. Furthermore, the partition 6A has a plurality of slits SLa located between adjacent dummy pixels DPX. Connections CT are formed between the slits SLa aligned in the Y direction.

[0087] The openings 81, 82, and 83 shown in Fig. 8 have the same shapes as the openings 71, 72, and 73 shown in Fig. 7. The shape of the slits SLa shown in Fig. 8 and their positional relationship with the openings 81, 82, and 83 are the same as the shape of the slits SLa and their positional relationship with the openings 71, 72, and 73 shown in Fig. 7. That is, in the examples of Fig. 7 and Fig. 8, the opening patterns of the partitions 6A in the display region DA and the dummy pixel region DMY are the same.

[0088] As another example, the shapes of the openings 81, 82, and 83 may be different from the shapes of the openings 71, 72, and 73. Furthermore, the shapes of the slits SLa may be different between the display region DA and the dummy pixel region DMY. In these cases, the opening patterns of the partition walls 6A will be different between the display region DA and the dummy pixel region DMY.

[0089] 9A is a schematic plan view showing an example of an opening pattern of the partition wall 6B in the first region A1. In the example shown in this figure, the partition wall 6B has a plurality of openings 91, 92, and 93 (first openings) and a plurality of slits SLa (first slits) provided between the openings 91, 92, and 93 adjacent to each other in the X direction. Connections CT are formed between the slits SLa aligned in the Y direction.

[0090] The openings 91, 92, and 93 shown in Fig. 9A have the same shapes as the openings 71, 72, and 73 shown in Fig. 7, respectively. The shape of the slit SLa shown in Fig. 9A and its positional relationship with the openings 91, 92, and 93 are the same as those of the slit SLa shown in Fig. 7 and their positional relationship with the openings 71, 72, and 73. That is, in the examples of Figs. 7 and 9A, the opening pattern of the partitions 6A in the display region DA is the same as the opening pattern of the partitions 6B in the first region A1. When the configuration of Fig. 8 is applied to the dummy pixel region DMY, the opening pattern of the partitions 6A in the dummy pixel region DMY is the same as the opening pattern of the partitions 6B in the first region A1.

[0091] 9B is a schematic plan view showing another example of the opening pattern of the partition wall 6B in the first region A1. In this example, the partition wall 6B has a plurality of openings 91, 92, 93 and a slit SLa, similar to FIG. 9A. However, the slit SLa shown in FIG. 9B is formed longer than the slit SLa shown in FIG. 9A.

[0092] 9A is equal to the length of the slit SLa in the display region DA and the dummy pixel region DMY, and more specifically, is approximately equal to the width in the Y direction of the opening 93. On the other hand, the length of the slit SLa shown in FIG. 9B is approximately twice the width in the Y direction of the opening 93.

[0093] The shapes of the slits SLa in the display region DA, the dummy pixel region DMY, and the first region A1 are not limited to those shown in Figures 7, 8, 9A, and 9B. As another example, the slits SLa in the first region A1 may be shorter than the slits SLa in the display region DA and the dummy pixel region DMY. Furthermore, continuous slits SLa may be provided across the display region DA, the dummy pixel region DMY, and the first region A1.

[0094] 10A is a schematic plan view showing an example of an opening pattern of the partition wall 6B in the second region A2. In the example shown in this figure, the partition wall 6B has a plurality of openings 101 (second openings) and a plurality of slits SLx (second slits) extending in the X direction. The plurality of openings 101 are arranged at regular intervals in both the X direction and the Y direction. The openings 101 are, for example, rectangular and elongated in the Y direction, but may have other shapes. The slit SLx connects two openings 101 arranged side by side in the X direction.

[0095] From another perspective, in the example of Figure 10A, one unit pattern 100 is formed by one slit SLx and two openings 101 connected by the slit SLx. Furthermore, multiple unit patterns 100 are arranged at intervals in the X direction and the Y direction. For example, the arrangement pitch of the unit patterns 100 in the X direction is the same as the arrangement pitch of the pixels PX in the X direction. Furthermore, the arrangement pitch of the unit patterns 100 in the Y direction is the same as the arrangement pitch of the pixels PX in the Y direction.

[0096] 10B is a schematic plan view showing another example of the opening pattern of the partition wall 6B in the second region A2. As in the example of FIG. 10A, the partition wall 6B has a plurality of openings 101 and a plurality of slits SLx extending in the X direction. Furthermore, the partition wall 6B has a plurality of slits SLy (third slits) extending in the Y direction and intersecting with the slits SLx.

[0097] 10B, the unit pattern 100 is composed of two openings 101, one slit SLx, and one slit SLy. The slits SLy of adjacent unit patterns 100 in the Y direction are spaced apart from each other. That is, a connection portion CT is formed between these slits SLy.

[0098] Fig. 10C is a schematic plan view showing yet another example of the opening pattern of the partition 6B in the second region A2. As in the example of Fig. 10B, the partition 6B has a plurality of openings 101 and a plurality of slits SLx, SLy. However, in the example of Fig. 10C, the openings 101 are longer in the Y direction than those shown in Fig. 10B.

[0099] For example, the length in the Y direction of the opening 101 shown in Fig. 10B is smaller than the length in the Y direction of the opening 73 shown in Fig. 7. On the other hand, the length in the Y direction of the opening 101 shown in Fig. 10C is equal to that of the opening 73.

[0100] 7, 8, 9A, 9B, 10A, 10B, and 10C are merely examples. In addition to these, various opening patterns can be applied to the display area DA, the dummy pixel area DMY, the first area A1, and the second area A2.

[0101] As described above, the aperture ratio of the partition walls 6B in the second region A2 is lower than the aperture ratio of the partition walls 6B in the first region A1. An example of a method for measuring these aperture ratios will be described below.

[0102] 11 is a schematic diagram illustrating an example of a method for measuring the aperture ratio. A plurality of signal lines S (see FIG. 1) are arranged in the display area DA. These signal lines S include signal lines S1, S2, and S3 that supply video signals to the pixel circuits 1 of the subpixels SP1, SP2, and SP3, respectively. The signal lines S1, S2, and S3 are aligned in this order in the X direction.

[0103] The distance between two adjacent signal lines S1, the distance between two adjacent signal lines S2, and the distance between two adjacent signal lines S3 all correspond to the width of the pixel PX in the X direction. For example, the signal lines S1, S2, and S3 are bent before reaching the first region A1 and the second region A2 and are connected to the terminal portion T.

[0104] 11, virtual lines Va and Vb are defined as extensions of two adjacent signal lines S1. The portion of the first region A1 between these virtual lines Va and Vb is called sub-region As1. The portion of the second region A2 between these virtual lines Va and Vb is called sub-region As2.

[0105] The aperture ratio of the partition wall 6B in the first region A1 corresponds to the ratio of the area of ​​the openings included in the sub-region As1 to the area of ​​the sub-region As1. For example, when the first region A1 has the configuration shown in FIG. 9A or 9B, the openings 91, 92, and 93 and the slit SLa included in the sub-region As1 correspond to the openings.

[0106] The aperture ratio of the partition 6B in the second region A2 corresponds to the ratio of the area of ​​the openings included in the sub-region As2 to the area of ​​the sub-region As2. For example, if the second region A2 has the configuration shown in FIG. 10B, the openings 101, slits SLx, and SLy included in the sub-region As2 correspond to the openings.

[0107] For example, the aperture ratio of the partition 6B in the first region A1 is 50% or more. The aperture ratio of the partition 6B in the second region A2 is 25% or more and less than 50%. When the display region DA, the dummy pixel region DMY, and the first region A1 have the configurations shown in FIGS. 7, 8, and 9A, respectively, the aperture ratios of these regions are the same.

[0108] 11 illustrates an example in which the aperture ratios of the partition wall 6B in the first region A1 and the second region A2 are defined using the virtual lines Va and Vb of the signal line S1. Alternatively, these aperture ratios may be defined using virtual lines extending the signal line S2 or the signal line S3. For example, if the aperture ratio of the first region A1 calculated based on the virtual lines Va and Vb of the signal line S1, the aperture ratio of the first region A1 calculated based on the virtual line of the signal line S2, and the aperture ratio of the first region A1 calculated based on the virtual line of the signal line S3 are different, the average of these may be used as the aperture ratio of the first region A1. A similar method can be applied to the aperture ratio of the second region A2.

[0109] Next, an example of a method for manufacturing the display device DSP will be described. When manufacturing the display device DSP, a large mother substrate is fabricated on which a plurality of regions (panel portions) each including a portion corresponding to the display device DSP is formed.

[0110] 12 is a schematic plan view of the mother substrate MB (mother substrate for a display device) according to this embodiment. The mother substrate MB has a rectangular shape as shown in the figure, but may have another shape such as a circle.

[0111] The mother substrate MB has a plurality of panel portions PP arranged in a matrix and blank areas BA surrounding the panel portions PP. In the example of Fig. 12, the panel portions PP are lined up in the X and Y directions with blank areas BA between them. However, the arrangement of the plurality of panel portions PP on the mother substrate MB is not limited to this example. As another example, some panel portions PP may be lined up without blank areas BA between them.

[0112] 13 is a schematic plan view of the panel portion PP. The outer shape of the panel portion PP corresponds to the cutting lines CL1 for cutting out each panel portion PP from the motherboard MB.

[0113] The panel unit PP has the above-mentioned display area DA and peripheral area SA. The peripheral area SA in the panel unit PP corresponds to the area between the display area DA and the cut line CL1.

[0114] The peripheral area SA further has a cut line CL2 that defines the outline of the substrate 10 of the display device DSP. When manufacturing the display device DSP, the panel portion PP is cut out from the mother substrate MB along the cut line CL1. Furthermore, the display device DSP is cut out from the panel portion PP along the cut line CL2.

[0115] The panel portion PP includes a dam structure DS2 in addition to the dam structure DS1 described above. The dam structure DS2 serves to block the resin layer RS2 before curing. For example, the dam structure DS2 includes multiple dam portions formed of the organic insulating layers 12 and 34, similar to the dam portions DM1, DM2, and DM3.

[0116] Dam structure DS1 is located between cut line CL2 and display area DA and surrounds display area DA. Dam structure DS2 is located between cut lines CL1 and CL2 and surrounds cut line CL2. In the example of Fig. 13, dam structures DS1 and DS2 join near terminal portion T, and this joined portion passes between terminal portion T and display area DA.

[0117] The majority of the cut line CL2 is located between the dam structures DS1 and DS2. However, in the example of Fig. 13, the cut line CL2 is located outside the dam structures DS1 and DS2 near the terminal portion T. In other words, the cut line CL2 crosses the dam structure DS2 near the terminal portion T.

[0118] Fig. 14 is a flowchart showing an example of a manufacturing method of the display device DSP. Fig. 15A to Fig. 15G are schematic cross-sectional views showing the manufacturing process of the display device DSP. Fig. 15A to Fig. 15G mainly focus on the display area DA, and omit elements below the organic insulating layer 12.

[0119] In forming the panel portion PP, first, a circuit layer 11 including the inorganic insulating layers 31, 32, and 33, the organic insulating layer 34, and the metal layers 41, 42, and 43 described above is formed above the substrate 10 of the motherboard MB (step PR1 in FIG. 14). Further, an organic insulating layer 12 covering the circuit layer 11 is formed (step PR2 in FIG. 14). At this time, dam structures DS1 and DS2 are also formed.

[0120] After step PR2, as shown in FIG. 15A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 (step PR3 in FIG. 14). Furthermore, as shown in FIG. 15A, a rib layer 5 covering the lower electrodes LE1, LE2, and LE3 is formed over the entire mother substrate MB (step PR4 in FIG. 14). At this point, pixel openings AP1, AP2, and AP3 are not provided in the rib layer 5. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0121] After the rib layer 5 is formed, as shown in FIG. 15B, the partition walls 6A are formed on the rib layer 5 (step PR5 in FIG. 14). The partition walls 6B in the peripheral region SA are also formed together with the partition walls 6A. For example, when forming the partition walls 6A and 6B, layers of material for the bottom layer 63, the axis layer 64, the first top layer 65, and the second top layer 66 are formed over the entire mother substrate MB. Furthermore, a resist in the shape of the partition walls 6A and 6B is disposed on these layers. The partition walls 6A and 6B can be formed by etching each layer using this resist as a mask.

[0122] 15C, pixel openings AP1, AP2, and AP3 are formed in the rib layer 5 (step PR6 in FIG. 14). The pixel openings AP1, AP2, and AP3 may be formed before the partition walls 6A and 6B.

[0123] After step PR6, a step for forming display element DE1 is performed (step PR7 in FIG. 14). To form display element DE1, first, as shown in FIG. 15D, a stacked film FL1 and a sealing layer SE11 are formed. As shown in FIG. 3, the stacked film FL1 includes an organic layer OR1 in contact with the lower electrode LE1 through the pixel opening AP1, an upper electrode UE1 covering the organic layer OR1, and a cap layer CP1 covering the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed by, for example, vapor deposition. The sealing layer SE11 can be formed by, for example, CVD.

[0124] The laminated film FL1 and sealing layer SE11 are formed over the entire mother substrate MB, including the display area DA of each panel unit PP, the peripheral area SA, and the margin area BA. The laminated film FL1 is divided by overhanging partition walls 6A and 6B. The sealing layer SE11 continuously covers the divided portions of the laminated film FL1 and the partition walls 6A and 6B.

[0125] Next, the stacked film FL1 and the sealing layer SE11 are patterned. In this patterning, a resist RT is disposed on the sealing layer SE11, as shown in Fig. 15D. The resist RT covers the subpixel SP1 and part of the partition wall 6A around it.

[0126] Then, an etching process is performed using the resist RT as a mask. As a result, as shown in FIG. 15E, the portions of the stacked film FL1 and the sealing layer SE11 exposed by the resist RT are removed. In other words, the portions of the stacked film FL1 and the sealing layer SE11 that overlap the lower electrode LE1 are left, and the other portions are removed. This forms a display element DE1 in the subpixel SP1. For example, in the peripheral region SA and the marginal region BA, the stacked film FL1 and the sealing layer SE11 are removed by this etching process. This etching process may include wet etching or dry etching, which is performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etching processes, the resist RT is removed (peeled off).

[0127] After step PR7, a step for forming display element DE2 is performed (step PR8 in FIG. 14). Display element DE2 can be formed using the same procedure as display element DE1. That is, when forming display element DE2, a stacked film FL2 and a sealing layer SE12 are formed over the entire mother substrate MB. As shown in FIG. 3, stacked film FL2 includes an organic layer OR2 in contact with the lower electrode LE2 through the pixel opening AP2, an upper electrode UE2 covering the organic layer OR2, and a cap layer CP2 covering the upper electrode UE2.

[0128] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 can be formed by, for example, vapor deposition. The sealing layer SE12 can be formed by, for example, CVD. By patterning the stacked film FL2 and the sealing layer SE2, a display element DE2 is formed in the subpixel SP2, as shown in FIG. 15F. For example, in the peripheral region SA and the marginal region BA, the stacked film FL2 and the sealing layer SE12 are removed by etching during the patterning process.

[0129] After step PR8, a step for forming display element DE3 is performed (step PR9 in FIG. 14). Display element DE3 can be formed using the same procedure as display elements DE1 and DE2. That is, when forming display element DE3, a stacked film FL3 and a sealing layer SE13 are formed over the entire mother substrate MB. As shown in FIG. 3, stacked film FL3 includes an organic layer OR3 in contact with the lower electrode LE3 through the pixel opening AP3, an upper electrode UE3 covering the organic layer OR3, and a cap layer CP3 covering the upper electrode UE3.

[0130] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 can be formed by, for example, vapor deposition. The sealing layer SE13 can be formed by, for example, CVD. By patterning the stacked film FL3 and the sealing layer SE13, a display element DE3 is formed in the subpixel SP3, as shown in FIG. 15G.

[0131] For example, in most of the peripheral area SA and the marginal area BA, the stacked film FL3 and the sealing layer SE13 are removed by etching during the patterning. However, portions of the stacked film FL3 and the sealing layer SE13 that cover the partition wall 6B are left. These remaining portions correspond to the stacked film FLx and the sealing layer SE1x described above.

[0132] Although it is assumed here that the display elements DE1, DE2, and DE3 are formed in this order, the display elements DE1, DE2, and DE3 may be formed in a different order.

[0133] After step PR9, a resin layer RS1 is formed, for example, by an inkjet method (step PR10 in FIG. 14). FIGS. 16A and 16B are schematic views illustrating step PR10 for forming the resin layer RS1. In step PR10, a frame-shaped outer resin layer RSa is first formed, as shown in FIG. 16A. The outer resin layer RSa has a circular shape that surrounds the display area DA and is located near the outer periphery of the area where the resin layer RS1 is to be formed. A cross section of the outer resin layer RSa is also shown at the bottom of FIG. 16A.

[0134] The outer resin layer RSa is formed by applying the resin material of the resin layer RS1 in a ring shape using an inkjet device and temporarily curing the resin material by irradiating it with ultraviolet light. For example, during this temporary curing, the viscosity of the resin material is increased to a degree that prevents it from completely curing.

[0135] 16B, an inner resin layer RSb is formed to entirely cover the inner region of the outer resin layer RSa. The inner resin layer RSb is formed by applying a resin material using an inkjet device so as to fill in the inner region of the outer resin layer RSa.

[0136] Such application may be performed in multiple steps. The cross section shown at the bottom of Fig. 16B shows the inner resin layer RSb applied in three steps, that is, inner resin layers RSb1, RSb2, and RSb3. The inner resin layers RSb1, RSb2, and RSb3 have, for example, the same thickness.

[0137] Immediately after application, the inner resin layer RSb spreads outward. The outer resin layer RSa serves to suppress this spreading of the inner resin layer RSb. After the outer resin layer RSa is formed, the outer resin layer RSa and the inner resin layer RSb are fully cured. The outer resin layer RSa and the inner resin layer RSb thus fully cured correspond to the resin layer RS1.

[0138] 17 is a schematic plan view showing an example of an area (hereinafter referred to as application area J) into which droplets of resin material are ejected when forming the outer resin layer RSa. The application area J overlaps with the second area A2 but does not overlap with the first area A1. In the example of FIG. 17, a portion of the second area A2 does not overlap with the application area J near the boundary between the first area A1 and the second area A2. For example, the application area J slightly overlaps with the area between the second area A2 and the dam portion DM1.

[0139] The application area J corresponds to an area where the resin material adheres immediately after being ejected from the inkjet device. The adhered resin material spreads over time and may reach the dam portions DM1 and DM2.

[0140] After forming the resin layer RS1 in step PR10, the sealing layer SE2 is formed by, for example, CVD (step PR11 in FIG. 14). Furthermore, etching is performed to remove the rib layer 5 and the sealing layer SE2 that cover the terminal portions T (step PR12 in FIG. 14). The etching is, for example, dry etching.

[0141] After step PR12, touch panel electrodes TP and touch panel wiring TPL are formed on the sealing layer SE2 (step PR13 in FIG. 14). Furthermore, a resin layer RS2 is formed (step PR14 in FIG. 14). The resin layer RS2 can be formed inside the dam structure DS2 by, for example, an inkjet method. The dam structure DS2 serves to block the resin layer RS2 before it hardens.

[0142] After step PR14, the mother substrate MB is cut along the cut lines CL1 (step PR15 in FIG. 14). Furthermore, the panel portion PP is cut along the cut lines CL2 (step PR16 in FIG. 14). This completes the display device DSP. For cutting in steps PR15 and PR16, for example, laser cutting, in which an infrared laser is irradiated along the cut lines CL1 and CL2, can be used. However, cutting in steps PR15 and PR16 may also be performed by other methods, such as scribe cutting.

[0143] According to the above-described embodiment, it is possible to improve the yield of the display device DSP. That is, the laminated films FL1, FL2, and FL3 formed by vapor deposition may have poor adhesion to the base. Therefore, there is a possibility that the laminated films FL1, FL2, and FL3 and the sealing layers SE11, SE12, and SE13 covering them may peel off from the base during the manufacturing of the display device DSP.

[0144] The peeling is likely to occur when the stacked films FL1, FL2, and FL3 are formed continuously over a wide area. In the display area DA, the stacked films FL1, FL2, and FL3 are divided into small pieces by the partition walls 6A. This prevents the peeling.

[0145] In this embodiment, the partition wall 6B having a plurality of openings is disposed in the peripheral area SA, whereby the stacked films FL1, FL2, FL3 are finely divided in the peripheral area SA as well, thereby suppressing the peeling.

[0146] Furthermore, with the configuration of the display device DSP according to this embodiment, it is possible to obtain the effects described below, for example. 18 is a schematic plan view of a partition wall 6B according to a comparative example of the present embodiment. The partition wall 6B shown in this figure has a plurality of openings 101, similar to the opening patterns shown in FIGS. 10A and 10B. However, the partition wall 6B does not have slits SLx, SLy. Therefore, the openings 101 are independent of each other.

[0147] The diagonally shaded circles represent droplets D of resin material that are ejected toward the mother substrate MB when forming the outer resin layer RSa and inner resin layer RSb of the resin layer RS1. The droplets D are ejected from multiple nozzles of an inkjet device. These nozzles are arranged at regular intervals. Therefore, the droplets D also adhere to the mother substrate MB at regular intervals.

[0148] 19A, 19B, and 19C are schematic cross-sectional views showing how the droplet D shown in FIG. 18 adheres to the mother substrate MB and spreads. The partition wall 6B is covered with a stacked film FLx and a sealing layer SE1x. A recess RP resulting from the opening 101 is formed on the upper surface of the sealing layer SE1x.

[0149] As shown in Fig. 19A, the droplets D are discharged toward the sealing layer SE1x. In Fig. 19B, the droplets D are attached to the sealing layer SE1x. Thereafter, the droplets D wet and spread as shown in Fig. 19C.

[0150] When the droplet D adheres to a position overlapping with the recess RP, the inside of the recess RP is filled with the droplet D. Furthermore, the droplet D also spreads into the recess RP that does not overlap with the droplet D immediately after adhesion. However, as shown in the recess RP in the center of FIG. 19C, a recess RP (a coating void) into which the droplet D does not flow may also occur due to the surface tension of the step portion of the sealing layer SE1x. Such a coating void may lead to a defect in the shape or disconnection of the touch panel wiring TPL formed above the resin layer RS1. Furthermore, the coating void may cause unevenness in the appearance of the display device DSP.

[0151] 10A, 10B, and 10C, if two openings 101 are connected by a slit SLx, when a droplet D flows into one of these openings 101, the droplet D also flows into the other opening 101 through a recess (groove) in the sealing layer SE1x created by the slit SLx. This makes it possible to prevent the occurrence of coating voids as shown in FIG. 19C, and to form a resin layer RS1 with a good shape.

[0152] Note that the higher the opening ratio of the partition wall 6B, the more easily the droplets D adhere to the recesses RP of the sealing layer SE1x formed by the openings, thereby enhancing the effect of suppressing missing portions. However, increasing the opening ratio of the partition wall 6B tends to make the droplets D more likely to wet and spread.

[0153] If the droplets D become too wet and spread, other problems may arise. That is, there may be areas where the outer resin layer RSa shown in FIG. 16A spreads locally toward the display area DA, and even if the inner resin layer RSb is applied thereon, unevenness corresponding to the shape of the outer resin layer RSa may ultimately appear on the upper surface of the resin layer RS1. As described above, such unevenness may cause the touch panel wiring TPL to be deformed or broken, and may even cause unevenness in the appearance of the display device DSP.

[0154] In this regard, in this embodiment, the opening pattern of the partition wall 6B is different between the first region A1 and the second region A2 outside it. Furthermore, the application region J of the outer resin layer RSa overlaps the second region A2 but not the first region A1. Since the aperture ratio of the second region A2 is lower than that of the first region A1, the droplets D are less likely to wet and spread. Therefore, when the outer resin layer RSa is formed, the droplets D are prevented from spreading toward the first region A1 and the dummy pixel region DMY and display region DA therein. This makes it possible to reduce unevenness on the upper surface of the resin layer RS1.

[0155] Furthermore, by suppressing the unevenness of the upper surface of the resin layer RS1, it is possible to suppress poor application of liquid resins such as various resists that are applied after the formation of the resin layer RS1. Examples of such liquid resins include resists for processing the rib layer 5 and the sealing layer SE2 in step PR12, and resists for processing the touch panel electrodes TP and the touch panel wiring TPL in step PR13.

[0156] The display device DSP may include a plurality of color filters corresponding to the colors of the subpixels SP1, SP2, and SP3, and a black matrix located at the boundaries of the subpixels SP1, SP2, and SP3. For example, these color filters and black matrix may be disposed above the sealing layer SE2. By suppressing the unevenness of the upper surface of the resin layer RS1, it is possible to suppress poor application of the resin that is the material for these color filters and black matrix.

[0157] In each of the above embodiments, the term "partition wall" includes various overhanging structures. Even if the overhanging structure has a shape different from the partition wall disclosed in each embodiment, the part that protrudes to the side corresponds to the "upper part," and the part that recedes below the part that protrudes to the side corresponds to the "lower part."

[0158] All display devices that can be implemented by a person skilled in the art by appropriately modifying the design based on the display devices disclosed in each embodiment also fall within the scope of the present invention as long as they include the gist of the present invention.

[0159] Within the scope of the concept of the present invention, a person skilled in the art may conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, even if a person skilled in the art appropriately adds or deletes components or modifies the design of the above-described embodiment, or adds or omits steps or modifies conditions, these modifications are also included within the scope of the present invention as long as they maintain the gist of the present invention.

[0160] Furthermore, with regard to other effects brought about by the aspects described in the above embodiments, those that are clear from the description in this specification or that can be appropriately thought of by a person skilled in the art are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0161] DSP...display device, DA...display area, SA...peripheral area, PX...pixel, SP1, SP2, SP3...subpixel, LE1, LE2, LE3...lower electrode, OR1, OR2, OR3...organic layer, UE1, UE2, UE3...upper electrode, SE11, SE12, SE13, SE1x, SE2...sealing layer, RS1, RS2...resin layer, MB...motherboard, PP...panel portion, 5...rib layer, 6A, 6B...partition wall, 61...lower part, 62...upper part, 63...bottom layer, 64...axis layer, 65...first top layer, 66...second top layer.

Claims

1. a substrate having a display area for displaying an image; a plurality of pixels arranged in the display region, each including a lower electrode, an upper electrode located above the lower electrode, and an organic layer located between the lower electrode and the upper electrode and emitting light in response to application of a voltage; a dummy pixel area including a plurality of dummy pixels that do not display an image and surrounding the display area; a first partition wall surrounding each of the plurality of pixels and the plurality of dummy pixels; a second partition wall having a plurality of openings, the second partition wall being disposed in a first region surrounding the dummy pixel region and a second region surrounding the first region; Equipped with the first and second partition walls each include a conductive lower portion and an upper portion having an end portion protruding from a side surface of the lower portion; a first opening pattern of the second partition wall in the first region and a second opening pattern of the second partition wall in the second region are different from each other; Display device.

2. the first opening pattern is the same as the third opening pattern of the first partition in the display region; the second opening pattern is different from the third opening pattern; The display device according to claim 1 .

3. an aperture ratio of the second partition wall in the first region is higher than an aperture ratio of the second partition wall in the second region; The display device according to claim 1 .

4. an aperture ratio of the second partition wall in the first region is 50% or more; The display device according to claim 3 .

5. an aperture ratio of the second partition wall in the second region is equal to or greater than 25% and less than 50%; The display device according to claim 3 .

6. The first opening pattern is a plurality of first openings; a plurality of first slits provided between the first openings adjacent to each other in a first direction and extending in a second direction intersecting the first direction; It has The display device according to claim 1 .

7. The second opening pattern is a plurality of second openings; a plurality of second slits each connecting the second openings adjacent to each other in the first direction and extending in the first direction; It has The display device according to claim 6.

8. the second opening pattern further includes a plurality of third slits intersecting the first slits; The display device according to claim 7 .

9. a sealing layer formed of an inorganic insulating material and covering the second partition wall in the first region and the second region; a resin layer covering the sealing layer; It further comprises: The display device according to claim 1 .

10. the display region, the dummy pixel region, the first region, and the second region are circular; The display device according to any one of claims 1 to 9.

11. forming a first partition wall surrounding each of a plurality of pixels in a display region and a plurality of dummy pixels in a dummy pixel region surrounding the display region; forming a second partition wall having a plurality of openings in a first region surrounding the dummy pixel region and in a second region surrounding the first region; forming a frame-shaped outer resin layer surrounding the display area so as to overlap at least the second area; forming an inner resin layer that covers an inner region of the outer resin layer; This includes: a first opening pattern of the second partition wall in the first region and a second opening pattern of the second partition wall in the second region are different from each other; A method for manufacturing a display device.

12. the outer resin layer and the inner resin layer are formed by an inkjet method, a coating region onto which droplets for forming the outer resin layer are discharged overlaps with the second region but does not overlap with the first region; The method for manufacturing a display device according to claim 11 .

13. the first opening pattern is the same as the third opening pattern of the first partition in the display region; the second opening pattern is different from the third opening pattern; The method for manufacturing a display device according to claim 11 .

14. an aperture ratio of the second partition wall in the first region is higher than an aperture ratio of the second partition wall in the second region; The method for manufacturing a display device according to claim 11 .

15. an aperture ratio of the second partition wall in the first region is 50% or more; The method for manufacturing a display device according to claim 14 .

16. an aperture ratio of the second partition wall in the second region is equal to or greater than 25% and less than 50%; The method for manufacturing a display device according to claim 14 .

17. The first opening pattern is a plurality of first openings; a plurality of first slits provided between the first openings adjacent to each other in a first direction and extending in a second direction intersecting the first direction; It has The method for manufacturing a display device according to claim 11 .

18. The second opening pattern is a plurality of second openings; a plurality of second slits each connecting the second openings adjacent to each other in the first direction and extending in the first direction; It has The method for manufacturing a display device according to claim 17 .

19. the second opening pattern further includes a plurality of third slits intersecting the first slits; The method for manufacturing a display device according to claim 18.

20. the display region, the dummy pixel region, the first region, and the second region are circular; A method for manufacturing a display device according to any one of claims 11 to 19.

Images