Semiconductor device and communication system

Abstract

To provide a semiconductor device capable of effectively constructing a communication system together with a device of a communication system different from that of itself.SOLUTION: In the semiconductor device (1), the first receiver (11) and the first transmitter (12) are configured to through-output the data for the first device (100) included in the reception data from the first output terminal (1C) to the second bus when the bridge selection data (BR) included in the reception data (RX) indicates that the through-output between the first bus (BS1) and the second bus (BS2) is on, the clock signal output unit (16) is configured to output a clock signal (SCL) synchronized with the data to be through-output, and the second reception unit (13) is configured to receive, via the first input terminal, an acknowledgement (ACK) transmitted from the first device as a response to reception of the through-output data.SELECTED DRAWING: Figure 11A

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Semiconductor devices having a serial communication function are used in a variety of applications.

[0003] An example of circuit technology relating to serial communication is disclosed in Patent Document 1. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2017-224946

[0005] [overview] In some applications, a communication system may be constructed using a semiconductor device (device) that performs serial communication using a communication method different from that of the semiconductor device itself.

[0006] A semiconductor device according to one aspect of the present disclosure includes: A semiconductor device connectable to an external transmitting device via a first bus and connectable to an external first device via a second bus, a first receiving unit configured to be able to receive reception data, which is serial data, from the transmitting device via the first bus using a first serial communication method; a first transmission unit configured to be connectable to the first device via the second bus; a second receiving unit configured to be connectable to the first device via the second bus; a second transmission unit configured to be connectable to the transmission device via the first bus; a clock signal output unit configured to output a clock signal to the first device; a first output terminal configured to be connectable to a data terminal of the first device; a first input terminal configured to be connectable to the data terminal; the first receiving unit and the first transmitting unit are configured to, when bridge selection data included in the received data indicates on of a through output for outputting bit data as is between the first bus and the second bus, through-output the data for the first device included in the received data to the second bus from the first output terminal; the clock signal output unit is configured to output a clock signal synchronized with the data to be through-output when the bridge selection data indicates that the through-output is on and when communication in a predetermined second serial communication method for the first device is set in the semiconductor device; The second receiving unit is configured to receive, via the first input terminal, an acknowledgement transmitted from the first device in response to receiving the through-output data. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a diagram showing a configuration of a communication system according to a first comparative example. [Figure 2] FIG. 2 is a diagram illustrating a configuration of a communication system according to a second comparative example. [Figure 3] FIG. 3 is a diagram illustrating a configuration of a communication system according to an exemplary embodiment of the present disclosure. [Figure 4] FIG. 4 is a block diagram of a semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 5] FIG. 5 is a block diagram of a semiconductor device according to an exemplary embodiment of the present disclosure. [Figure 6] FIG. 6 is a diagram showing the data structure of received data RX when writing or reading is performed with the semiconductor device 1 as the target device. [Figure 7] FIG. 7 is a diagram illustrating a configuration example of a communication system according to an embodiment of the present disclosure. [Figure 8]FIG. 8 is a diagram showing the data structure of received data RX when writing or reading is performed with the device 10 as the target device. [Figure 9] FIG. 9 is a timing chart showing communication control when writing to the device 10. In FIG. [Figure 10] FIG. 10 is a timing chart showing communication control when reading from the device 10. In FIG. [Figure 11A] FIG. 11A is a diagram illustrating a configuration example of a communication system according to an embodiment of the present disclosure. [Figure 11B] FIG. 11B is a diagram illustrating a configuration example of a communication system according to a modified example of the embodiment of the present disclosure. [Figure 12] FIG. 12 is a diagram showing a transmission / reception configuration between the semiconductor device 1 and the I2C device 100. [Figure 13] FIG. 13 is a diagram showing the configuration of a signal output unit having a push-pull configuration. [Figure 14] FIG. 14 is a diagram showing the configuration of a signal output section having an open-drain configuration. [Figure 15] FIG. 15 is a table showing the communication method setting information BRIFSEL. [Figure 16] FIG. 16 is a table showing the bridge mode information BRMODE. [Figure 17] FIG. 17 is a timing chart showing an example of an operation when writing to an I2C device. [Figure 18] FIG. 18 is a diagram showing the data structure of receive data RX when writing or reading is performed with an I2C device as the target device. [Figure 19] FIG. 19 is a timing chart showing an example of an operation when reading from an I2C device. [Figure 20] FIG. 20 is a diagram illustrating an example of the configuration of a motor driver. [Figure 21] FIG. 21 is an external view showing an example of a vehicle.

[0008] [Detailed explanation] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the drawings.

[0009] <1. Communication Systems> 1 is a diagram showing the configuration of a communication system 501 according to a first comparative example for comparison with an embodiment of the present disclosure. The communication system 501 includes an MCU (Micro Controller Unit) 20, a CAN (Controller Area Network) transceiver 30, a CAN transceiver 40, a semiconductor device 1, and n devices 10 (n is an integer equal to or greater than 1). Note that the CAN transceiver may not be provided between the MCU 20 and the semiconductor device 1. The communication system 501 is, as an example, for use in a vehicle, and the same applies to the other communication systems described below.

[0010] Communication between the MCU 20 and the CAN transceiver 30 is performed using UART (Universal Asynchronous Receiver / Transmitter). UART is a format for exchanging serial data between two devices. With UART, bidirectional communication is performed between the sender and receiver using two lines.

[0011] Communication is performed between the CAN transceivers 30 and 40 via a CAN bus 35. CAN is a serial communication protocol standardized by international standards such as ISO11898. Communication is performed between the CAN transceiver 40 and the semiconductor device 1 and the n devices 10 via UART.

[0012] The CAN transceiver 30 has a TXD (transmit data input) terminal 30A and an RXD (receive data output) terminal 30B. The CAN transceiver 30 outputs data input to the TXD terminal 30A to the CAN bus 35, and outputs data input from the CAN bus 35 from the RXD terminal 30B.

[0013] The CAN transceiver 40 has an RXD terminal 40A and a TXD terminal 40B. The CAN transceiver 40 outputs data input to the TXD terminal 40B to the CAN bus 35, and outputs data input from the CAN bus 35 from the RXD terminal 40A.

[0014] The semiconductor device 1 is an IC (integrated circuit) in which circuits with predetermined functions are integrated, and is configured as, for example, an LED (light emitting diode) driver IC. The n devices 10 are ICs in which circuits with predetermined functions are integrated, and are configured as, for example, matrix switch ICs.

[0015] The semiconductor device 1 has an RX (receive data input) terminal 1A and a TX (transmit data output) terminal 1B. The device 10 has an RX terminal 10A and a TX terminal 10B. The RX terminal 1A and the n RX terminals 10A are commonly connected to an RXD terminal 40A. The TX terminal 1B and the n TX terminals 10B are commonly connected to a TXD terminal 40B.

[0016] 1, the semiconductor device 1 and the n devices 10 support the same protocol, so the semiconductor device 1 and the n devices 10 can be commonly connected to the same CAN transceiver 40. Received data RX output from the RXD terminal 40A is input to the RX terminal 1A and the n RX terminals 10A. The received data RX specifies the device address of one of the semiconductor device 1 and the n devices 10. Transmitted data TX output from the TX terminal 1B and the n TX terminals 10B is input to the TXD terminal 40B.

[0017] However, if the protocols supported by the semiconductor device 1 and the n devices 10 are different, it becomes difficult to deal with the configuration of the first comparative example shown in Fig. 1. In such a case, the configuration of the second comparative example shown in Fig. 2 can be adopted.

[0018] 2 differs from the first comparative example in that CAN transceivers 301 and 302 are used instead of CAN transceiver 30, and CAN transceivers 401 and 402 are used instead of CAN transceiver 40. A semiconductor device 1 is connected to MCU 20 via CAN transceiver 301 and CAN transceiver 401, and n devices 10 are connected to MCU 20 via CAN transceiver 302 and CAN transceiver 402. CAN transceivers 401 and 402 perform CAN communication with CAN transceivers 301 and 302, respectively.

[0019] In this way, by grouping devices with different protocols (a group of semiconductor device 1 and a group of n devices 10), communication control can be performed using devices with different protocols. However, an increase in the number of CAN transceivers, such as CAN transceivers 301, 302, 401, and 402, and an increase in the amount of wiring pose a problem of increased costs.

[0020] Therefore, in order to solve such problems, the embodiment of the present disclosure is implemented as described below. Figure 3 is a diagram showing the configuration of a communication system 50 according to an exemplary embodiment of the present disclosure.

[0021] In the configuration shown in FIG. 3, UART communication is performed between the CAN transceiver 40, the semiconductor device 1, and n devices 10. In addition to an RX terminal 1A and a TX terminal 1B, the semiconductor device 1 has an RXD (receive data output) terminal 1C and a TXD (transmit data input) terminal 1D. The RX terminal 1A is connected to the RXD terminal 40A of the CAN transceiver 40. The TX terminal 1B is connected to the TXD terminal 40B of the CAN transceiver 40. In other words, the RX terminal 1A and the TX terminal 1B are connected to the RXD terminal 40A and the TXD terminal 40B by a bus BS1. Communication of receive data RX and transmit data TX is possible via the bus BS1. The receive data RX and transmit data TX are serial data.

[0022] The RXD terminal 1C is connected to the RX terminals 10A of the n devices 10. The TXD terminal 1D is connected to the TX terminals 10B of the n devices 10. That is, the RXD terminal 1C and the TXD terminal 1D are connected to the RX terminals 10A and TX terminals 10B by a bus (local bus) BS2. Communication of receive data BRX and transmit data BTX is possible via the bus BS2. The receive data BRX and transmit data BTX are serial data.

[0023] The semiconductor device 1 also has an SCL terminal (clock terminal) 1E. As will be described later, the SCL terminal 1E is a terminal for outputting a clock signal. The terminal 1E is used when a device that supports I2C (Inter Integrated Circuit) as a communication method is used, as will be described later. However, as shown in FIG. 3, the terminal 1E is not used when a device 10 that supports UART is used.

[0024] In the configuration according to the embodiment of the present disclosure shown in FIG. 3, the semiconductor device 1 and the n devices 10 support different protocols. When the CAN transceiver 40 writes or reads to the semiconductor device 1, the received data RX output from the RXD terminal 40A to the RX terminal 1A consists only of data that supports the protocol of the semiconductor device 1. Note that "write" refers to the process of writing data to the target device, and "read" refers to the process of reading data from the target device. In the case of a read, the semiconductor device 1 receives the received data RX and then outputs the transmitted data TX from the TX terminal 1B to the TXD terminal 40B.

[0025] On the other hand, when the CAN transceiver 40 writes to or reads from the device 10, the receive data RX output from the RXD terminal 40A to the RX terminal 1A includes data corresponding to the protocol of the device 10. At this time, the semiconductor device 1 turns on the bridge function and through-outputs the data included in the receive data RX and corresponding to the protocol of the device 10 as receive data BRX from the RXD terminal 1C. Through-output means outputting bit data as is. The device address of the device 10 is specified in the receive data BRX.

[0026] In the case of a read, the device 10, which is the target device (the device specified by the device address), outputs transmission data BTX from the TX terminal 10B to the TXD terminal 1D. Since the bridge function of the semiconductor device 1 is on, the transmission data BTX is output as transmission data TX from the TX terminal 1B.

[0027] As described above, according to the embodiment of the present disclosure, even if the protocols of the semiconductor device 1 and the device 10 are different, the CAN transceiver 40 can write to and read from each of the semiconductor device 1 and the device 10. Compared to the second comparative example (FIG. 2), the number of CAN transceivers can be reduced, and the amount of wiring can be reduced, thereby reducing costs.

[0028] <2. Configuration of semiconductor device> 4 is a block diagram of a semiconductor device 1 according to an embodiment of the present disclosure. The semiconductor device 1 includes functional blocks including a first receiving unit 11, a first transmitting unit 12, a second receiving unit 13, a second transmitting unit 14, and a control unit 15. Note that FIG. 4 illustrates only functional blocks related to communication functions, and other functional blocks may also be included. For example, if the semiconductor device 1 is an LED driver, it includes a block function related to LED driving.

[0029] The first receiver 11 receives reception data RX via an RX terminal 1A. The first transmitter 12 outputs reception data BRX via an RXD terminal 1C. The second receiver 13 receives transmission data BTX via a TXD terminal 1D. The second transmitter 14 outputs transmission data TX via a TX terminal 1B.

[0030] The control unit 15 controls the first receiving unit 11, the first transmitting unit 12, the second receiving unit 13, and the second transmitting unit 14. The control unit 15 includes a register 151.

[0031] The semiconductor device 1 also includes a clock signal output unit 16, as shown in FIG. 4. FIG. 4 is a diagram showing the state of the semiconductor device 1 when a UART-compatible device 10 is used, as shown in FIG. 3. The clock signal output unit 16 is not used in the state shown in FIG. 4. On the other hand, FIG. 5 is a diagram showing the state of the semiconductor device 1 when an I2C-compatible device is used, as will be described later. As shown in FIG. 5, the clock signal output unit 16 outputs a clock signal SCL via an SCL terminal 1E. The clock signal SCL is a signal necessary for communication according to I2C, and is used together with received data BRX and transmitted data BTX.

[0032] <3. Structure of received data> 6 is a diagram showing the data structure of received data RX when writing or reading is performed using the semiconductor device 1 as the target device. The received data RX shown in FIG.

[0033] In UART, communication is carried out in data units called frames. As shown in Figure 6, a frame FR is made up of bit data from a start bit S to a stop bit P. The start bit S is at low level, and the stop bit P is at high level. A predetermined number of bits of bit data are placed between the start bit S and the stop bit P. In the example of Figure 6, 8 bits of bit data are placed. In other words, the frame FR is made up of 10 bits of bit data.

[0034] As shown in FIG. 6, the received data RX includes, from the beginning, a synchronization frame SYN, a read / write etc. frame RWD, a data number frame ND, a register address frame AD, a data frame DT, and CRC (Cyclic Redundancy Check) frames CR1 and CR2.

[0035] The synchronization frame SYN is bit data for setting the baud rate in the semiconductor device 1 .

[0036] The Read / Write etc. frame RWD includes a device address DA, a bridge bit BR, a broadcast / parity bit B / PA, and a Read / Write bit RW. The device address DA is bit data indicating the address of the target device (semiconductor device 1) (5-bit data in the example of Figure 6). The bridge bit BR is bit data indicating the on / off of the bridge function of the semiconductor device 1. The broadcast / parity bit B / PA is bit data indicating the on / off of the broadcast of the semiconductor device 1 or the parity of the data address DA. The Read / Write bit RW is bit data indicating Read or Write.

[0037] Here, the bridge bit BR=0 indicates that the bridge function is off, i.e., normal mode (the bridge function is off in the received data RX shown in Figure 6). In this case, the broadcast / parity bit B / PA indicates whether broadcast is on or off. When the broadcast / parity bit B / PA=0, it indicates that broadcast is off, and when the broadcast / parity bit B / PA=1, it indicates that broadcast is on.

[0038] When broadcasting the semiconductor device 1, multiple semiconductor devices 1 are connected to the CAN transceiver 40 as shown in Fig. 7. A device 10 is connected to each semiconductor device 1. When broadcasting is on, all of the multiple semiconductor devices 1 become target devices.

[0039] The bridge bit BR=1 indicates that the bridge function is on (the bridge function is on in the received data RX shown in FIG. 8, which will be described later). In this case, the broadcast / parity bit B / PA becomes the parity of the device address DA. This makes it possible to detect errors in the device address DA. In the configuration shown in FIG. 7, if the protocols differ for each group of devices 10 connected to each of the multiple semiconductor devices 1, turning on the broadcast of the semiconductor device 1 will result in the same received data RX being sent as received data BRX to devices 10 with different protocols, making the protocols incompatible with some of the devices 10. Therefore, when the bridge function is turned on, broadcasting is not performed.

[0040] The data number frame ND is bit data that indicates the number of frames in the data frame DT. In FIG. 6, the number of frames in the data frame DT is 1 as an example, but it may be 2 or more.

[0041] The register address frame AD is bit data indicating an address in the register 151. The data frame DT is bit data indicating the data body to be transmitted by the receive data RX. In the case of a read, the data frame DT is not included in the receive data RX.

[0042] The CRC frames CR1 and CR2 are bit data indicating error detection codes added to the frames RWD, ND, AD, and DT for error detection. While the data frame DT is one frame in the example of FIG. 6, two or more frames may be included in the received data RX. In this case, the CRC frames CR1 and CR2 follow two or more data frames DT.

[0043] 8 is a diagram showing the data structure of received data RX when writing or reading is performed with the device 10 as the target device. The synchronization frame SYN and the read / write etc. frame RWD in the received data RX shown in FIG. 8 are as described above.

[0044] 8, a read / write etc. frame RWD is followed by a first data number frame ND1 and a second data number frame ND2. The first data number frame ND1 is bit data indicating the total number of frames. The second data number frame ND2 is bit data indicating the number of frames of write data for the target device (device 10 when the bridge function is used). In the case of a write process for the target device, the number of frames indicated by the second data number frame ND2 matches the number of frames indicated by the first data number frame ND1. In the case of a read process for the target device, the number of frames obtained by subtracting the number of frames indicated by the second data number frame ND2 from the number of frames indicated by the first data number frame ND1 is the number of frames of data (read data) returned from the target device to the semiconductor device 1.

[0045] In the received data RX shown in Figure 8, the second data number frame ND2 is followed by device data DDT. The device data DDT is data that complies with the protocol of the device 10 and is the target to be output as received data BRX. The device data DDT includes a device address BDA. The device address BDA indicates the address of the device 10, which is the target device. The device address BDA is placed in the device data DDT at a position that corresponds to the protocol of the device 10.

[0046] <4. Through output control> Here, the through output control by the semiconductor device 1, that is, the control when the bridge function is on, will be described.

[0047] 9 is a timing chart showing communication control when writing to the device 10. From the top to bottom of FIG. 9, receive data RX, receive data output selection signal (RX output select), transmit data output selection signal (TX output select), receive data BRX, transmit data BTX, and transmit data TX are shown (similar to FIG. 10). The receive data RX has the configuration shown in FIG. 8.

[0048] The received data RX is received by the first receiving unit 11 (FIG. 4). Upon receiving the start bit S1 (low level) at the beginning of the received data RX, the control unit 15 recognizes the start of reception of the received data RX. Thereafter, the control unit 15 recognizes that the bridge function is on from the bridge bit BR included in the received data RX, and also recognizes that it is a write from the read / write bit RW.

[0049] Thereafter, when the second data number frame ND2 is received, the control unit 15 changes the received data output selection signal in the register 151 from low to high at the stop bit P1 of the second data number frame ND2 (timing t1). This starts the through output of the received data RX, and the first receiving unit 11 and the first transmitting unit 12 output the received data RX as is as received data BRX. That is, the device data DDT (FIG. 8) is through output.

[0050] When the received data output selection signal goes high, the control unit 15 starts counting the number of frames of the received data RX (i.e., the number of frames of the device data DDT). When the counted number of frames reaches the number of frames indicated by the received second data number frame ND2, the control unit 15 switches the received data output selection signal to low and stops the through output (timing t2). Thereafter, the received data BRX is fixed at high. In this case, the number of frames indicated by the second data number frame ND2 and the number of frames indicated by the first data number frame ND1 match.

[0051] 10 is a timing chart showing communication control when performing a read from the device 10. In this case, the received data RX has the structure shown in FIG.

[0052] After receiving the start bit S1 (low level) at the beginning of the received data RX, the control unit 15 recognizes that the bridge function is on from the bridge bit BR included in the received data RX, and also recognizes that it is a read from the read / write bit RW.

[0053] Thereafter, when the second data number frame ND2 is received, the control unit 15 changes both the receive data output selection signal and the transmit data output selection signal in the register 151 from low to high at the stop bit P1 of the second data number frame ND2 (timing t1). This initiates through-output of the receive data RX and the transmit data BTX. The first receive unit 11 and the first transmit unit 12 output the receive data RX as it is as receive data BRX, i.e., through-output of the device data DDT (FIG. 8) is performed. After completing output of the receive data BRX, the second receive unit 13 and the second transmit unit 14 through-output the transmit data BTX sent from the device 10 as transmit data TX.

[0054] When the reception data output selection signal and the transmission data output selection signal go high, the control unit 15 starts counting the number of frames of the reception data RX that are received. When the sum of the number of counted frames of the reception data RX and the number of counted frames of the transmission data BTX that are received thereafter reaches the number of frames indicated by the first data number frame ND1, the control unit 15 switches both the reception data output selection signal and the transmission data output selection signal to low, stopping the through output (timing t2). Thereafter, the transmission data TX is fixed to Hi-z (high impedance).

[0055] As described above, in this embodiment, the condition for ending the through output can be determined based on the number of frames received by the semiconductor device 1. In particular, with this embodiment, even if transmission of the received data RX from the MCU 20 is interrupted due to interrupt processing in the MCU 20, the frame count does not advance during the interruption, so it is possible to avoid erroneously interrupting the through output. In other words, because interruption of the through output can be avoided regardless of the interrupt time, it is less subject to restrictions imposed by the specifications of the MCU 20.

[0056] <5.Conversion between UART and I2C> An external device compatible with I2C communication can be connected to the semiconductor device 1 of this embodiment. Fig. 11A is a diagram showing a communication system 55 configured from the semiconductor device 1 and an I2C device 100 compatible with I2C. The I2C device 100 is configured as a semiconductor device having various functions, such as a motor driver as described below.

[0057] The I2C device 100 has an SDA terminal (data terminal) 100A and an SCL terminal (clock terminal) 100B.

[0058] The RXD terminal 1C and TXD terminal 1D of the semiconductor device 1 are commonly connected to the SDA terminal 100A. The RXD terminal 1C and TXD terminal 1D are not limited to being separate terminals, and may be the same input / output terminal 1C' as shown in the configuration of FIG. 11B. Received data BRX output from the RXD terminal 1C is input to the SDA terminal 100A. Transmitted data BTX output from the SDA terminal 100A is input to the TXD terminal 1D.

[0059] The SCL terminal 1E of the semiconductor device 1 is connected to the SCL terminal 100B. The clock signal SCL output from the SCL terminal 1E is input to the SCL terminal 100B. That is, communication is performed between the semiconductor device 1 and the I2C device 100 using the signals BRX, BTX, and SCL via the second bus BS2.

[0060] The semiconductor device 1 operates as a master, and the I2C device 100 operates as a slave. When transmitting receive data BRX from the semiconductor device 1 to the I2C device 100, the semiconductor device 1 transmits a clock signal SCL to the I2C device 100. The semiconductor device 1 transmits the receive data BRX in synchronization with the clock signal SCL. The I2C device 100 receives the receive data BRX in synchronization with the clock signal SCL.

[0061] When transmitting data from the I2C device 100 to the semiconductor device 1, the semiconductor device 1 also transmits a clock signal SCL to the I2C device 100. The I2C device 100 transmits the clock signal SCL and transmission data BTX in synchronization with each other. The semiconductor device 1 receives the clock signal SCL and transmission data BTX in synchronization with each other.

[0062] 12 is a diagram showing a transmission / reception configuration between the semiconductor device 1 and the I2C device 100. The wiring connecting the RXD terminal 1C of the semiconductor layer 1 and the SDA terminal 100A of the I2C device 100 is pulled up by a pull-up resistor 105.

[0063] The first transmission unit 12 of the semiconductor device 1 has signal output units 121 and 122. As will be described later, it is possible to switch between the signal output units 121 and 122 to be enabled.

[0064] The signal output unit 121 has a push-pull configuration as shown in Fig. 13. Specifically, the push-pull configuration is configured by connecting a PMOS transistor (P-channel MOSFET) 121A and an NMOS transistor (N-channel MOSFET) 121B in series between an application terminal of a power supply voltage VCC and an application terminal of a ground potential. The source of the PMOS transistor 121A is connected to the application terminal of the power supply voltage VCC, and the drain of the PMOS transistor 121A is connected to the drain of the NMOS transistor 121B at a node Nd. The source of the NMOS transistor 121B is connected to the application terminal of the ground potential. An RXD terminal 1C is connected to the node Nd. By turning on and off the PMOS transistor 121A and the NMOS transistor 121B, high-level or low-level reception data BRX is output from the RXD terminal 1C.

[0065] 14, the signal output unit 122 has an open-drain configuration using an NMOS transistor 122A. The drain of the NMOS transistor 122A is connected to the RXD terminal 1C, and the source of the NMOS transistor 122A is connected to an application terminal of ground potential. When the NMOS transistor 122A is driven to the on state, the RXD terminal 1C is set to low level, and when the NMOS transistor 122A is driven to the off state, the RXD terminal 1C is set to Hi-z.

[0066] The I2C device 100 has a receiver 101 and a transmitter 102, each connected to an SDA terminal 100A. The receiver 101 receives receive data BRX output from an RXD terminal 1C via the SDA terminal 100A. The transmitter 102 transmits transmit data BTX to a second receiver 13 via the SDA terminal 100A.

[0067] 12, when the semiconductor device 1 is connected to the I2C device 100, the signal output unit 122 having an open-drain configuration is enabled. When reception data BRX is transmitted from the signal output unit 122, the SDA terminal 100A is set to Hi-Z by a signal output unit (open-drain configuration) not shown in the transmission unit 102. On the other hand, when transmission data BTX is transmitted from the transmission unit 102, the RXD terminal 1C is set to Hi-Z by the signal output unit 122.

[0068] Next, the operation of the communication system 55 (FIG. 11A) configured as described above will be described in more detail. Here, communication method setting information BRIFSEL as shown in FIG. 15 can be set in the register 151 of the semiconductor device 1. The communication method setting information BRIFSEL indicates a communication method supported by a device connected to the semiconductor device 1. In the example of FIG. 15, communication method setting information BRIFSEL=0 indicates UART, and BRIFSEL=1 indicates I2C. For example, when a device 10 (FIG. 3) compatible with UART is connected, BRIFSEL=0 is set, and when an I2C device 100 (FIG. 11A) is connected, BRIFSEL=1 is set. Operation is switched depending on the setting of BRIFSEL. In particular, as shown in FIG. 15, when BRIFSEL=0, the signal output unit 121 (push-pull configuration) described above is enabled for transmitting the reception data BRX, and when BRIFSEL=1, the signal output unit 122 (open-drain configuration) described above is enabled.

[0069] Note that various settings using the communication method setting information BRIFSEL and the like are not limited to settings in registers, but can also be made using, for example, resistors connected to the outside of the semiconductor device.

[0070] The operation when writing to the I2C device 100 will be described with reference to the timing chart shown in Fig. 17. Fig. 17 (and Fig. 19, described later) shows, from top to bottom, example waveforms of receive data RX, transmit data TX, receive data BRX, transmit data BTX, and clock signal SCL. Note that, although the receive data BRX and transmit data BTX actually have the same waveform, the receive data BRX is illustrated as a signal from the semiconductor device 1 to the I2C device 100, and the transmit data BTX is illustrated as a signal from the I2C device 100 to the semiconductor device 1.

[0071] As shown in Fig. 18, the received data RX includes a synchronization frame SYN, a read / write etc. frame RWD, a first data number frame ND1, and a second data number frame ND2, similar to Fig. 8. The received data RX shown in Fig. 18 includes data I2CDT for the I2C device 100 after the second data number frame ND2.

[0072] After receiving the start bit (low level) at the beginning of the received data RX, the control unit 15 recognizes that the bridge function is on from the bridge bit BR included in the received data RX, and also recognizes that it is Write from the Read / Write bit RW.

[0073] Thereafter, when the second data number frame ND2 is received, the control unit 15 starts through-output of the received data RX at the stop bit ST of the second data number frame ND2 (timing t1). As a result, the data I2CDT is through-output to the I2C device 100 as received data BRX.

[0074] After timing t1, at timing t2, the receive data BRX falls, and since the clock signal SCL is at high level at this time, a start condition STA is transmitted to the I2C device 100. That is, the start condition is generated in the first frame F1 of the data I2CST that is output through the receive data RX.

[0075] Thereafter, the clock signal SCL is output (for example, at timing t3) so that the rising edge coincides with the center of each bit (bit sandwiched between the start bit and stop bit) of the transmission data BRX that has been through-output as the data I2CDT.

[0076] In the example of FIG. 17, the number of data bits between the start bit S and the stop bit ST in one frame of the data I2CDT is 9 bits. In this embodiment, the number of data bits between the start bit S and the stop bit ST in one frame of the data I2CDT can be set in the register 151 of the semiconductor device 1. FIG. 16 shows bridge mode information BRMODE, which is information for setting such a corresponding number of bits. The bridge mode information BRMODE is used to detect the length of one frame of the data I2CDT. In the example of FIG. 16, the bridge mode information BRMODE is 2-bit data, and the number of data bits is set according to the value of BRMODE. In the example of FIG. 16, when BRMODE=0, the number of bits is set to 8 bits, when BRMODE=1, the number of bits is set to 9 bits, and when BRMODE=2 or 3, the number of bits is set to 10 bits.

[0077] 17, the data I2CDT includes three frames F1, F2, and F3. Here, the number of frames indicated by the second data number frame ND2 is "3," so three frames F1, F2, and F3 are included. Note that in the case of Write, the number of frames indicated by the second data number frame ND2 matches the number of frames indicated by the first data number frame ND1.

[0078] The first frame F1 is a frame for communicating the slave address (the address of the I2C device). In frame F1, the last bit R / W of the first 8 data bits indicates Read or Write. In the case of FIG. 17, the bit R / W indicates Write. Frames F2 and F3 following frame F1 are frames for data communication.

[0079] The last bit of the data bits in each of frames F1, F2, and F3 is set to "1." This causes the transmission data BRX from the signal output unit 122 (open drain configuration) to be set to Hi-Z. This is to enable reception of an acknowledgement ACK by the transmission data BTX transmitted from the transmission unit 102. The acknowledgement ACK is data transmitted from the transmission unit 102 in response to reception of a predetermined number of bits (8 bits in FIG. 17) of data in the transmission data BRX, and is transmitted as a low-level signal. If the second reception unit 13 can receive the acknowledgement ACK, it is in a normal state, but if it cannot receive it, it is in an abnormal state, and therefore the control unit 15 stores data indicating the abnormal state in the register 151.

[0080] When the number of frames of the received data RX to be through-output reaches the number of frames indicated by the second data number frame ND2 ("3" in the example of FIG. 17), the control unit 15 stops the through-output (timing t4). At this time, the transmission data BRX is set to low level and then raised (timing t5). At this time, the clock signal SCL is at high level, so a stop condition STP is transmitted to the I2C device 100. That is, a stop condition is generated after the final frame F3.

[0081] Next, the operation when performing a read from the I2C device 100 will be described with reference to the timing chart shown in FIG.

[0082] As with Write, a start condition STA is generated in the first frame F1, and frames F1, F2, and F3 are output as transmit data BRX. The bit R / W in the first frame F1 indicates Read. Furthermore, in the frame indicated by the second data number frame ND2 (frame F3 in FIG. 19), the transmit data BRX falls and the clock signal SCL is at a high level, so a start condition STA2 is generated.

[0083] When the number of frames of the received data RX to be through-output reaches the number of frames indicated by the second data number frame ND2 ("3" in the example of FIG. 19), the control unit 15 stops the through-output (timing t11).

[0084] Here, the receive data BRX is set to Hi-Z, and a start bit S is generated in the transmit data TX. After that, a clock signal SCL is generated so that the transmit data BTX can be output at the falling edge. Eight bits of transmit data BTX are output (the value of the first bit is determined at the falling edge of the last clock SCL in frame F3), and the ninth bit of the transmit data BTX is set to Hi-Z. This is to output an acknowledgement ACK by the receive data BRX.

[0085] Nine bits of the transmission data BTX are output as transmission data TX, and then a stop bit P is added to the transmission data TX. As a result, a frame F10 including 8 bits of read data RD is transmitted as transmission data TX. When the number of frames obtained by subtracting the number of frames NumofData2 indicated by the second data number frame ND2 from the number of frames NumofData1 indicated by the first data number frame ND1 (in the example of FIG. 19, 4-3=1) is read out as transmission data TX, the processing is completed. Note that in the final frame of the subtracted number of frames, the clock signal SCL is at a high level at the rising edge of the transmission data BRX, so a stop condition STP is generated.

[0086] As described above, the semiconductor device 1 of this embodiment enables conversion between the UART format and the I2C format, and the MCU 20 can write to or read from the I2C device 100 via the semiconductor device 1. Furthermore, there is no need to provide a separate master device for I2C communication with the I2C device 100.

[0087] <6. Application Examples> Next, a motor driver will be described as a specific example of the I2C device 100 according to this embodiment.

[0088] The motor driver 1001 is configured to drive a two-phase excitation stepping motor 60 (hereinafter simply referred to as motor 60). The motor 60 has an excitation coil 61 of a first excitation phase, an excitation coil 62 of a second excitation phase, and a rotor 63. When the motor 60 is driven to rotate, the motor driver 1001 supplies drive currents I1 and I2 to the excitation coils 61 and 62, respectively.

[0089] The motor driver 1001 includes an integrated I2C communication unit 1001A, a control logic unit 1001B, a pre-driver 1001C, a half-bridge 1001D, and a half-bridge 1001E. The motor driver 1001 also includes an SDA terminal 100A and an SCL terminal 100B as external terminals for establishing electrical connection with the outside. The motor driver 1001 also includes output terminals OUT1A, OUT1B, OUT2A, and OUT2B as external terminals.

[0090] The I2C communication unit 1001A communicates with the semiconductor device 1 using I2C. That is, as shown in FIG. 20, communication is performed using receive data BRX, transmit data BTX, and a clock signal SCL. As described above, the semiconductor device 1 converts between UART and I2C, so the I2C communication unit 1001A can communicate with an MCU (not shown) via the semiconductor device 1. The provision of the I2C communication unit 1001A makes it possible to perform various settings for the motor driver 1001 and output the state of the motor driver 1001 to the outside.

[0091] The control logic unit 1001B controls the entire motor driver 1001. The pre-driver 1001C drives the half bridges 1001D and 1001E under the control of the control logic unit 1001B. The half bridge 1001D controls the drive current I1 by generating a voltage signal across the output terminals OUT1A and OUT1B. The half bridge 1001E controls the drive current I2 by generating a voltage signal across the output terminals OUT2A and OUT2B.

[0092] <7. Vehicles> 21 is an external view showing an example of the configuration of a vehicle X. The vehicle X of this example is equipped with various electronic devices X11 to X18 that operate by receiving power supply from a battery (not shown). Note that the installation positions of the electronic devices X11 to X18 in FIG. 21 may differ from the actual positions for convenience of illustration.

[0093] The electronic device X11 is an engine control unit that performs engine-related controls (injection control, electronic throttle control, idling control, oxygen sensor heater control, auto-cruise control, etc.).

[0094] The electronic device X12 is a lamp control unit that controls the turning on and off of HID (high intensity discharged lamp) and DRL (daytime running lamp).

[0095] The electronic device X13 is a transmission control unit that controls transmission-related functions.

[0096] The electronic device X14 is a body control unit that performs control related to the movement of the vehicle X (ABS [anti-lock brake system] control, EPS [electric power steering] control, electronic suspension control, etc.).

[0097] The electronic device X15 is a security control unit that controls the operation of door locks, burglar alarms, and other devices.

[0098] The electronic device X16 is an electronic device that is installed in the vehicle X at the time of shipment from the factory as a standard equipment or a manufacturer option, such as a wiper, an electric door mirror, a power window, a damper (shock absorber), an electric sunroof, and an electric seat.

[0099] The electronic device X17 is an electronic device that is optionally installed in the vehicle X as a user option, such as an in-vehicle A / V (audio / visual) device, a car navigation system, and an ETC (electronic toll collection system).

[0100] The electronic device X18 is an electronic device equipped with a high-voltage motor, such as an in-vehicle blower, oil pump, water pump, or battery cooling fan.

[0101] The communication system including the semiconductor device 1 and the motor driver 1001 (I2C device) and the motor 60 may be used to drive any of the electronic devices X11 to X18. If the vehicle X is an electric vehicle or a hybrid vehicle, the motor driver 1001 may be used as a means for controlling a motor for driving the wheels.

[0102] <8.Other> In addition to the above-described embodiments, various modifications can be made to the various technical features disclosed in this specification without departing from the spirit of the technical creation. In other words, the above-described embodiments should be considered to be illustrative and not restrictive in all respects, and the technical scope of the present disclosure should not be limited to the above-described embodiments, but should be understood to include all modifications that fall within the meaning and scope equivalent to the claims.

[0103] <9. Notes> As described above, the semiconductor device (1) according to one embodiment of the present disclosure is A semiconductor device connectable to an external transmitting device (20) via a first bus (BS1) and connectable to an external first device (100) via a second bus (BS2), a first receiving unit (11) configured to be able to receive received data (RX), which is serial data, from the transmitting device via the first bus using a first serial communication method; a first transmission unit (12) configured to be connectable to the first device via the second bus; a second receiving unit (13) configured to be connectable to the first device via the second bus; a second transmission unit (14) configured to be connectable to the transmission device via the first bus; a clock signal output unit (16) configured to output a clock signal (SCL) to the first device; a first output terminal (1C) configured to be connectable to a data terminal (SDA) of the first device; a first input terminal (1D) configured to be connectable to the data terminal; the first receiving unit and the first transmitting unit are configured to, when bridge selection data (BR) included in the received data indicates on of a through output for outputting bit data as is between the first bus and the second bus, through-output the data for the first device (I2CDT) included in the received data to the second bus from the first output terminal; the clock signal output unit is configured to output a clock signal synchronized with the data to be through-output when the bridge selection data indicates that the through-output is on and when communication in a predetermined second serial communication method for the first device is set in the semiconductor device; The second receiving unit is configured to receive, via the first input terminal, an acknowledgement (ACK) transmitted from the first device in response to reception of the through-output data (first configuration).

[0104] According to this configuration, it is possible to provide a semiconductor device that can effectively build a communication system together with a device that uses a communication method different from that of the semiconductor device itself.

[0105] In the first configuration, the first output terminal and the first input terminal may be separate terminals (second configuration).

[0106] In addition, in the first or second configuration, the first transmitting unit may be configured to set the first output terminal to high impedance in response to the last bit of data bits included in the frame of received data, and to enable the first input terminal to receive the acknowledgment from the first device (third configuration).

[0107] Furthermore, in the third configuration, the number of the data bits provided between the start bit (S) and the stop bit (ST) in the frame may be settable (fourth configuration).

[0108] Furthermore, any one of the first to fourth configurations may be configured to include a register (151) in which data indicating an abnormal state is stored when the acknowledgement cannot be received (fifth configuration).

[0109] Furthermore, in any of the first to fifth configurations, a start condition (STA) may be generated by the falling edge of the data output from the first output terminal and the high level of the clock signal in the first frame of the received data that is output through (sixth configuration).

[0110] Furthermore, in any of the first to sixth configurations, a stop condition (STP) may be generated by the rising edge of the data output from the first output terminal and the high level of the clock signal after the last frame of the received data that is output through (seventh configuration).

[0111] In any of the first to seventh configurations, the clock signal may be output so that its rising edge occurs at the center of each bit of data that is output through from the first output terminal (eighth configuration).

[0112] Furthermore, in any of the first to eighth configurations above, if the bit data indicating Read or Write contained in the received data indicates Read, after the through output of the received data, the transmission data (BTX) read from the first device may be through output to the first bus via the second receiving unit and the second transmitting unit (ninth configuration).

[0113] In addition, in the above ninth configuration, a start condition (STA2) may be generated by the falling edge of the data output from the first output terminal and the high level of the clock signal in the last frame of the received data that is output through (tenth configuration).

[0114] In the ninth or tenth configuration, a start bit and a stop bit may be added to the beginning and end of the transmission data that is output through, and then output to the first bus (eleventh configuration).

[0115] In addition, in any of the ninth to eleventh configurations, the data terminal may be set to high impedance at the last bit of the transmission data, and the acknowledge signal may be output from the first output terminal (twelfth configuration).

[0116] Furthermore, in any of the above ninth to twelfth configurations, a stop condition (STP) may be generated in the last frame of a frame including the transmission data that is output through by the rising edge of the data output from the first output terminal and the high level of the clock signal (thirteenth configuration).

[0117] In any one of the first to thirteenth configurations, the first serial communication method may be UART, and the second serial communication method may be I2C (fourteenth configuration).

[0118] Another aspect of the present disclosure is a communication system (55) including a semiconductor device having any one of the first to fourteenth configurations, the transmitting device, and the first device (fifteenth configuration).

[0119] In the fifteenth configuration, the first device may be configured as a motor driver (1001) (sixteenth configuration).

[0120] In addition, the sixteenth configuration may be mountable on a vehicle (seventeenth configuration). [Industrial Applicability]

[0121] The present disclosure can be used, for example, in communication systems for various applications. [Explanation of symbols]

[0122] 1. Semiconductor device 1A RX terminal 1B TX terminal 1C RXD terminal 1C' input / output terminal 1D TXD terminal 1E SCL terminal 10 devices 10A RX terminal 10B TX terminal 11 First receiving unit 12 First transmission unit 13 Second receiving unit 14 Second transmission unit 15 Control Unit 16 Clock signal output section 30,40 CAN transceiver 30A TXD terminal 30B RXD terminal 35 CAN bus 40A RXD terminal 40B TXD terminal 50 Communication Systems 55 Communication Systems 60 Stepping motor 61, 62 Excitation coil 63 Rotor 100 I2C devices 100A SDA terminal 100B SCL terminal 1001 Motor Driver 1001A I2C communication section 1001B Control logic section 1001C Pre-driver 1001D, 1001E Half Bridge 51 registers 301,302 CAN transceiver 401,402 CAN transceiver 501,502 Communication Systems BS1 Bus BS2 2nd bus OUT1A, OUT1B, OUT2A, OUT2B output terminals X vehicle X11~X18 Electronic equipment

Claims

1. A semiconductor device connectable to an external transmitting device via a first bus and connectable to an external first device via a second bus, a first receiving unit configured to receive reception data, which is serial data, from the transmitting device via the first bus in accordance with a first serial communication method; a first transmission unit configured to be connectable to the first device via the second bus; a second receiving unit configured to be connectable to the first device via the second bus; a second transmission unit configured to be connectable to the transmission device via the first bus; a clock signal output unit configured to output a clock signal to the first device; a first output terminal configured to be connectable to a data terminal of the first device; a first input terminal configured to be connectable to the data terminal; the first receiving unit and the first transmitting unit are configured to, when bridge selection data included in the received data indicates on of a through output for outputting bit data as is between the first bus and the second bus, through-output the data for the first device included in the received data to the second bus from the first output terminal; the clock signal output unit is configured to output a clock signal synchronized with the data to be through-output when the bridge selection data indicates that the through-output is on and when communication in a predetermined second serial communication method for the first device is set in the semiconductor device; the second receiving unit is configured to receive, via the first input terminal, an acknowledgement transmitted from the first device in response to reception of the through-output data. Semiconductor device.

2. The semiconductor device according to claim 1 , wherein said first output terminal and said first input terminal are separate terminals.

3. 2. The semiconductor device according to claim 1, wherein, in response to a last bit of data bits included in a frame of received data, the first transmitting unit sets the first output terminal to high impedance and enables the first input terminal to receive the acknowledgement from the first device.

4. 4. The semiconductor device according to claim 3, wherein the number of said data bits provided between a start bit and a stop bit in said frame is configurable.

5. 2. The semiconductor device according to claim 1, further comprising a register for storing data indicating an abnormal state when said acknowledgement cannot be received.

6. 2. The semiconductor device according to claim 1, wherein a start condition is generated by a falling edge of the data output from said first output terminal and a high level of said clock signal in a first frame of said received data that is output through said first output terminal.

7. 2. The semiconductor device according to claim 1, wherein after the last frame of said received data is outputted through, a stop condition is generated by a rising edge of data outputted from said first output terminal and a high level of said clock signal.

8. 2. The semiconductor device according to claim 1, wherein said clock signal is output so that a rising edge occurs at the center of each bit of data output from said first output terminal.

9. 2. The semiconductor device according to claim 1, wherein, when bit data indicating Read or Write included in the received data indicates Read, after the through output of the received data, transmission data read from the first device is through output to the first bus via the second receiving unit and the second transmitting unit.

10. 10. The semiconductor device according to claim 9, wherein a start condition is generated by a falling edge of the data output from said first output terminal and a high level of said clock signal in the last frame of said received data that is output through said first output terminal.

11. 10. The semiconductor device according to claim 9, wherein a start bit and a stop bit are added to the beginning and end of the transmission data that is outputted through to the first bus.

12. 10. The semiconductor device according to claim 9, wherein said data terminal is set to high impedance at the last bit of said transmission data, and said acknowledge is output from said first output terminal.

13. 10. The semiconductor device according to claim 9, wherein a stop condition is generated by a rising edge of the data output from said first output terminal and a high level of said clock signal in a last frame including said transmission data that is output through.

14. 2. The semiconductor device according to claim 1, wherein the first serial communication method is UART, and the second serial communication method is I2C.

15. 15. A communication system comprising: the semiconductor device according to claim 1; the transmitting device; and the first device.

16. The communication system of claim 15 , wherein the first device is configured as a motor driver.

17. 17. The communication system of claim 16, which is mountable in a vehicle.

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