Display device

Abstract

To provide a display device which can be driven at high speed.SOLUTION: A first transistor whose switching is controlled using a first control signal and which is electrically connected between an image data signal line and a first node, a third transistor whose switching is controlled using a second control signal and which is electrically connected between the first node and a second node, a second transistor which has a gate electrode electrically connected to the second node and which is electrically connected between a power supply line and a third node, a fourth transistor whose switching is controlled using a third control signal and which is electrically connected between a reference voltage power supply line and the second node, and a fifth transistor whose switching is controlled using a fourth control signal and which is electrically connected between an initialization voltage power supply line and the third node; And a sixth transistor whose switching is controlled using the second control signal and which is electrically connected to the third node.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a display device. [Background technology]

[0002] In recent years, display devices equipped with light-emitting elements that emit light in a self-luminous manner (self-luminous display devices) have become widespread. For example, the light-emitting elements are light-emitting diodes (LEDs), tiny light-emitting diodes (micro LEDs), or organic electroluminescence (EL) elements. The self-luminous display device includes a plurality of pixels and a control circuit for driving the plurality of pixels. When the control circuit supplies a voltage to each of the plurality of pixels, a current corresponding to the supplied voltage value flows through the light-emitting element included in each of the plurality of pixels. Each of the light-emitting elements emits light at a brightness corresponding to the current flowing through the light-emitting element, and the pixel including the light-emitting element can display an image with a gradation corresponding to the brightness.

[0003] For example, Patent Document 1 discloses an organic light-emitting diode display device that drives a light-emitting element. The display device described in Patent Document 1 detects the threshold voltage of a drive transistor included in a pixel and includes a program period in which a voltage corresponding to a data voltage compensated for the threshold voltage is stored in a storage capacitor. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-242767 Summary of the Invention [Problem to be solved by the invention]

[0005] In recent years, display devices including light-emitting elements have been required to operate at higher speeds in order to accommodate higher resolutions, larger screens, or higher frequencies. For example, when a display device stores a voltage corresponding to a data voltage whose threshold voltage is compensated in a storage capacitor, both the threshold voltage compensation and the writing of the data voltage are performed within a programming period, which may slow down the writing of the data voltage.

[0006] In view of the above problems, one object of an embodiment of the present invention is to provide a display device that can be driven at high speed. [Means for solving the problem]

[0007] A display device according to one embodiment of the present invention includes a first transistor whose switching is controlled using a first control signal and electrically connected between an image data signal line to which a data voltage is supplied and a first node; a third transistor whose switching is controlled using a second control signal having a timing different from that of the first control signal and electrically connected between the first node and a second node; a second transistor whose gate electrode is electrically connected to the second node and electrically connected between a power supply line to which a constant voltage is supplied and the third node; and a third transistor whose switching is controlled using a third control signal having a timing different from that of the first control signal and the second control signal. a fourth transistor whose switching is controlled using a fourth control signal having a timing different from that of the first control signal, the second control signal, and the third control signal, and electrically connected between a reference voltage power supply line to which a reference voltage is supplied and the second node; a fifth transistor whose switching is controlled using a fourth control signal having a timing different from that of the first control signal, the second control signal, and the third control signal, and electrically connected between an initialization voltage power supply line to which an initialization voltage is supplied and the third node; a sixth transistor whose switching is controlled using the second control signal, and has a first electrode, and is electrically connected to the third node; a light-emitting element electrically connected to the first electrode; and a capacitive element electrically connected between the first node and the third node. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a schematic diagram illustrating a configuration of a display device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a schematic diagram showing input signals to a pixel circuit according to the first embodiment of the present invention. [Figure 3] 1 is a circuit diagram showing a configuration of a pixel circuit according to a first embodiment of the present invention. [Figure 4] 3 is a timing chart of the display device according to the first embodiment of the present invention. [Figure 5] 3 is a timing chart of the display device according to the first embodiment of the present invention. [Figure 6] 3 is a timing chart of the display device according to the first embodiment of the present invention. [Figure 7] 3 is a timing chart of the display device according to the first embodiment of the present invention. [Figure 8] 3 is a timing chart of the display device according to the first embodiment of the present invention. [Figure 9] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 10] FIG. 10 is an end view showing an end surface cut along A1-A2 in the layout shown in FIG. 9. [Figure 11] FIG. 3 is a sequence diagram showing a manufacturing method of the display device according to the first embodiment of the present invention. [Figure 12] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 13] FIG. 2 is a layout diagram of a pixel according to the first embodiment of the present invention. [Figure 14] FIG. 10 is a schematic diagram showing input signals to a pixel circuit according to a second embodiment of the present invention. [Figure 15] FIG. 4 is a circuit diagram showing a configuration of a pixel circuit according to a second embodiment of the present invention. [Figure 16] 10 is a timing chart of a display device according to a second embodiment of the present invention. [Figure 17] 10 is a timing chart of a display device according to a second embodiment of the present invention. [Figure 18]10 is a timing chart of a display device according to a second embodiment of the present invention. [Figure 19] 10 is a timing chart of a display device according to a second embodiment of the present invention. [Figure 20] 10 is a timing chart of a display device according to a second embodiment of the present invention. [Figure 21] FIG. 10 is a schematic diagram showing input signals to a pixel circuit according to a third embodiment of the present invention. [Figure 22] FIG. 10 is a circuit diagram showing a configuration of a pixel circuit according to a third embodiment of the present invention. [Figure 23] 10 is a timing chart of a display device according to a third embodiment of the present invention. [Figure 24] 10 is a timing chart of a display device according to a third embodiment of the present invention. [Figure 25] 10 is a timing chart of a display device according to a third embodiment of the present invention. [Figure 26] 10 is a timing chart of a display device according to a third embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different forms, and should not be construed as being limited to the description of the embodiments exemplified below. Furthermore, in order to clarify the explanation, the drawings may show the width, thickness, shape, configuration, etc. of each part schematically compared to the actual form, but these are merely examples and do not limit the interpretation of the present invention. Furthermore, the letters "first" and "second" attached to each element are convenient labels used to distinguish each element, and have no other meaning unless otherwise specified.

[0010] Furthermore, in this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude cases where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude cases where α includes other elements.

[0011] In one embodiment of the present invention, when the expressions "same," "identical," and "match" are used, the expressions "same," "identical," and "match" may include a tolerance within the design range. In addition, in one embodiment of the present invention, when a tolerance within the design range is included, the expressions "approximately identical" and "approximately match" may be used.

[0012] For example, a display device according to one embodiment of the present invention is a display device that uses EL elements as light-emitting elements that emit light in a self-luminous manner. For example, a display device that uses EL elements may be called a self-luminous display device, an EL display device, or the like.

[0013] 1. First Embodiment <1-1. Overview of the display device 10> An overview of a display device 10 according to a first embodiment will be described with reference to Fig. 1. Fig. 1 is a schematic diagram showing the configuration of the display device 10. The configuration of the display device 10 shown in Fig. 1 is an example, and the configuration of the display device 10 is not limited to the configuration shown in Fig. 1.

[0014] The display device 10 includes an array substrate 100, a flexible printed circuit board 200 (FPC 200), and an IC chip 110. The display device 10 also includes a display area 22 provided on the array substrate 100, a peripheral area 24 surrounding the display area 22, and a terminal area 26.

[0015] In the display region 22, a plurality of pixels 180 are arranged in a matrix along a first direction D1 (column direction) and a second direction D2 (row direction) intersecting the first direction D1. The pixel 180 is the smallest unit that constitutes part of an image displayed in the display region 22. For example, each of the plurality of pixels 180 may correspond to a sub-pixel R, a sub-pixel G, and a sub-pixel B. One pixel may also be formed by three sub-pixels. There are no limitations on the arrangement of the pixels 180, and the arrangement of the plurality of pixels 180 may be, for example, a stripe arrangement. The arrangement of the display device 10 may be a delta arrangement, a pentile arrangement, or the like.

[0016] The subpixels R, G, and B are configured to display images of different colors. For example, each of the subpixels R, G, and B includes a light-emitting element including a light-emitting layer that emits red, green, and blue, respectively. When any voltage or current is supplied to each of the three subpixels, the display device 10 can display an image.

[0017] The peripheral region 24 is provided with an IC chip 110 and two control circuits 120. The two control circuits 120 are provided on the left and right sides of the display region 22. The IC chip 110 is connected to the terminal portion 150 using a connection wiring 341. Each of the two control circuits 120 is connected to the IC chip 110 using a connection wiring 342. The peripheral region 24 is sometimes referred to as a frame region. The connection wiring 341 may be referred to individually as the connection wiring 341, and a bundle of multiple connection wirings 341 may be referred to as the connection wiring 341. Like the connection wiring 341, the connection wiring 342 may be referred to individually as the connection wiring 342, and a bundle of multiple connection wirings 342 may be referred to as the connection wiring 342.

[0018] The terminal region 26 is provided with the terminal portion 150 and the FPC 200 electrically connected to the terminal portion 150. The terminal region 26 is on the opposite side of the peripheral region 24 in the first direction D1 from the region in which the display region 22 is provided.

[0019] The FPC 200 is connected to an external device (not shown) outside the display device 10. The display device 10 is connected to the external device via the FPC 200 and a terminal unit 150 connected to the FPC. Control signals and voltages are transmitted from the external device to the display device 10 via the FPC 200 and the terminal unit 150 connected to the FPC. The display device 10 drives each pixel 180 provided on the display device 10 using the control signals and voltages received from the external device. As a result, the display device 10 can display an image in the display area 22.

[0020] The IC chip 110 supplies signals, voltages, and the like for driving each pixel 180 to the two control circuits 120 and each pixel 180 (pixel circuit 181) via the FPC 200, the terminal section 150, and the connection wiring 341.

[0021] In this specification and drawings, IC chip 110, each of the two control circuits 120, and each of IC chip 110 may be referred to individually as a control circuit, and a group of circuits including IC chip 110, each of the two control circuits 120, and part or all of IC chip 110 may be referred to as a control circuit.

[0022] <1-2. Configuration of IC chip 110> 1, an overview of the IC chip 110 will be described. The IC chip 110 is provided at a position adjacent to the display area 22 in the first direction D1. Image data signal lines 321, 322, and 323 extend from the IC chip 110 in the first direction D1 and are connected to a plurality of pixels 180 arranged in the first direction D1.

[0023] For example, the IC chip 110 includes a plurality of selection circuits (not shown). For example, each of the plurality of selection circuits is a switch controlled based on an on signal and an off signal supplied to a selection signal line. The selection circuit is selected by an on signal supplied to the selection signal line, and supplies an image data signal SL(m) including a data signal VDATA to the image data signal line 321 and the pixels 180 electrically connected to the image data signal line 321. The selection signal and the image data signal SL(m) are transmitted from an external device to the IC chip 110 via the FPC 200 and the terminal unit 150 connected to the FPC 200. For example, the data signal VDATA (image data signal SL(m)) includes a data voltage equal to or higher than a voltage VSIGL (see FIG. 5) and equal to or lower than a voltage VSIGH (see FIG. 5).

[0024] For example, an on signal is a signal including a voltage that turns on a selection circuit (switch), and an off signal is a signal including a voltage that turns off the selection circuit (switch). In the present invention, the on signal may be a high-level voltage (potential) (high, High, HI) and the off signal may be a low-level voltage (potential) (low, Low, LO), or the on signal may be a low-level voltage (potential) (low, Low, LO) and the off signal may be a high-level voltage (potential) (high, High, HI). A high-level voltage is greater (higher) than a low-level voltage. In addition, in a display device according to one embodiment of this specification, as an example, the on signal is a high-level voltage and the off signal is a low-level voltage.

[0025] <1-3. Configuration of Control Circuit 120> An overview of the control circuit 120 will be described with reference to FIG. 1. Two control circuits 120 are provided adjacent to each other on both sides of the display area 22 in the second direction D2 of the display area 22. Scan signal lines 330, 331, 332, and 333 extend from the control circuit 120 in the second direction D2 and are connected to a plurality of pixels 180 arranged in the second direction D2. As an example, each scan signal line of the display device 10 shown in FIG. 1 is connected to both of the two control circuits 120. Each scan signal line may be connected to one of the control circuits 120. That is, the nth scan signal line may be electrically connected to the control circuit 120 on the right side of the display area 22 in the second direction D2, and the (n+1)th scan signal line may be electrically connected to the control circuit 120 on the left side of the display area 22 in the second direction D2. The number n is a positive integer.

[0026] The control circuit 120 includes a shift register circuit 130 and a scan driver circuit 160. For example, the control circuit 120 is a gate driver, and receives control signals including a clock signal, a start pulse, and a plurality of enable signals, as well as voltages such as a drive voltage VDDEL (see FIG. 2) and a reference voltage VSSEL (see FIG. 2). The control circuit 120 can sequentially select scan lines based on the input of the control signals and power supply.

[0027] The shift register circuit 130 is electrically connected to the scan driver circuit 160. The shift register circuit 130 includes a plurality of shift registers (not shown). The shift register circuit 130 is also supplied with the above-mentioned control signals via a plurality of connection wirings 342, a drive voltage VDDEL via a drive power supply line PVDD (see FIG. 2), and a reference voltage VSSEL via a reference voltage line PVSS (see FIG. 2). The shift register circuit 130 has a role of generating a plurality of output signals (not shown) shifted at different timings based on the above-mentioned control signals, and sequentially outputting the output signals to the scan driver circuit 160.

[0028] The scan driver circuit 160 includes multiple scan drivers. For example, the multiple scan drivers receive multiple output signals from the shift register circuit 130, the multiple enable signals from the IC chip 110 via multiple connection lines 342, the drive voltage VDDEL via a drive power supply line PVDD, and the reference voltage VSSEL via a reference voltage line PVSS. Based on the multiple output signals and the multiple enable signals, the multiple scan drivers sequentially supply scan signals (e.g., a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), and a fourth scan signal SC4(n)) with different timings to each scan signal line, and drive the pixels 180 (pixel circuits 181) electrically connected to each scan signal line. For example, the fourth scan signal SC4(n) and the scan signal line 333 to which the fourth scan signal SC4(n) is supplied are so-called scan signals and scan signal lines.

[0029] <1-4. Configuration of pixel 180> An overview of the pixel 180 and the pixel circuit 181 will be described with reference to FIGS. 1 to 3. FIG. 2 is a schematic diagram showing input signals to the pixel circuit 181 included in the pixel 180. FIG. 3 is a circuit diagram showing the configuration of the pixel circuit 181. FIGS. 2 and 3 show, as an example, the configuration of the pixel circuit 181 of the pixel 180 shown in FIG. 1. The configurations of the pixel 180 and the pixel circuit 181 are not limited to those shown in FIGS. 1 to 3. Configurations that are the same as or similar to those in FIG. 1 will be described as necessary.

[0030] The pixel circuit 181 is a circuit for driving the pixel 180. The pixel circuits of the sub-pixels R, G, and B included in the pixel 180 are similar to the pixel circuit 181, but the colors emitted by the light-emitting element OLED are different. In the following description, a light-emitting element OLED that emits red light will be described as an example.

[0031] 2, the pixel circuit 181 is supplied with an image data signal SL(m), a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), a reference voltage VREF, and an initialization voltage VINI. Furthermore, the pixel circuit 181 is supplied with a driving voltage VDDEL and a reference voltage VSSEL as power supplies for driving the pixel 180. For example, the reference voltage VREF, the initialization voltage VINI, the driving voltage VDDEL, and the reference voltage VSSEL may be constant voltages, or may be variable voltages that fluctuate according to the timing of each signal.

[0032] A first scan signal SC2(n) is supplied to a scan signal line 330, a second scan signal SC2(n) is supplied to a scan signal line 331, a third scan signal SC3(n) is supplied to a scan signal line 332, a fourth scan signal SC4(n) is supplied to a scan signal line 333, a reference voltage VREF is supplied to a reference voltage power line SVR, an initialization voltage VINI is supplied to an initialization voltage power line SVI, a drive voltage VDDEL is supplied to a drive power line PVDD, and a reference voltage VSSEL is supplied to a base voltage line PVSS. For example, the reference voltage power line SVR, the initialization voltage power line SVI, the drive power line PVDD, and the base voltage line PVSS are each electrically connected to a different connection wiring 342. Also, for example, the reference voltage power line SVR, the initialization voltage power line SVI, the drive power line PVDD, and the base voltage line PVSS may each be connected to a different connection wiring 342.

[0033] For example, the reference voltage VREF, the initialization voltage VINI, the drive voltage VDDEL, and the reference voltage VSSEL are supplied from an external device to the IC chip 110 via the FPC 200, the terminal unit 150, and the connection wiring 341. Also, for example, the reference voltage VREF, the initialization voltage VINI, the drive voltage VDDEL, and the reference voltage VSSEL are supplied from the IC chip 110 to the plurality of pixels 180 (pixel circuits 181) via the connection wiring 342, the precharge voltage power line SVP, the reference voltage power line SVR, the initialization voltage power line SVI, the drive power line PVDD, and the reference voltage line PVSS. Although not shown, the reference voltage VREF, the initialization voltage VINI, the drive voltage VDDEL, and the standard voltage VSSEL may be connected to the reference voltage power line SVR, the initialization voltage power line SVI, the drive power line PVDD, and the standard voltage line PVSS from an external device via the FPC 200, the terminal unit 150, and the connection wiring 341, without passing through the IC chip 110 and the connection wiring 342, and may be supplied to the plurality of pixels 180 (pixel circuits 181). For example, the reference voltage VREF, the initialization voltage VINI, and the standard voltage VSSEL are smaller than the drive voltage VDDEL.

[0034] 3, the pixel circuit 181 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a capacitance element CS, and a light-emitting element OLED. Each of these transistors includes a gate electrode and a pair of electrodes (a source electrode and a drain electrode) consisting of a first electrode and a second electrode. Each of the capacitance element CS and the light-emitting element OLED includes a pair of electrodes consisting of a first electrode and a second electrode.

[0035] For example, the first transistor T1 is a selection transistor. The first transistor T1 has a function of supplying an image data signal SL(m) to the first node N1.

[0036] For example, the second transistor T2 is a drive transistor. A gate voltage in which variations in the threshold voltage VTH are corrected based on the reference voltage VREF and the initialization voltage VINI is applied between the gate electrode 622 and the first electrode 624 of the second transistor T2. The second transistor T2 controls the amount of current flowing from the drive power line PVDD to the light-emitting element OLED based on the gate voltage in which variations in the threshold voltage VTH are corrected and the input image data signal SL(m). That is, the second transistor T2 has the function of flowing a current corresponding to the display gradation (brightness) from the drive voltage VDDEL to the light-emitting element OLED, causing the light-emitting element OLED to emit light. The first electrode 624 is a source electrode, and the gate voltage is a potential difference Vgs between the voltage applied to the gate electrode 622 (second node N2) and the voltage applied to the first electrode 624 (third node N3).

[0037] The third transistor T3 has a function of connecting the first node N1 and the second node N2 and supplying the image data signal SL(m) to the second node N2.

[0038] The fourth transistor T4 has a function of connecting the second node N2 and the reference voltage power supply line SVR to each other, supplying the reference voltage VREF to the second node N2, and initializing the second node N2.

[0039] The fifth transistor T5 has a function of connecting the third node N3 and the initialization voltage power supply line SVI to each other, supplying the initialization voltage VINI to the third node N3, and initializing the third node N3.

[0040] The sixth transistor T6 is electrically connected between the third node N3 and the light-emitting element OLED, and has a function of controlling conduction and non-conduction between the third node N3 and the light-emitting element OLED.

[0041] The capacitance element CS has a function of holding a charge equivalent to the threshold voltage VTH of the second transistor T2, and a function of holding a charge equivalent to the data voltage (a voltage equal to or greater than the voltage VSIGL (see Figure 5) and equal to or less than the voltage VSIGH (see Figure 5)) included in the image data signal SL(m) supplied to the first node N1.

[0042] The light-emitting element OLED has diode characteristics and emits light based on the current flowing through the light-emitting element OLED, which is the drain current (current Ion) of the second transistor T2.

[0043] The first transistor T1 includes a gate electrode 612, a first electrode 614, and a second electrode 616. The gate electrode 612 is electrically connected to the scan signal line 333. The first electrode 614 is electrically connected to the image data signal line 321. The second electrode 616 is electrically connected to the first node N1, the first electrode 634 of the third transistor T3, and the second electrode 694 of the capacitive element CS. As described above, a fourth scan signal SC4(n) is supplied to the scan signal line 333. The switching of the first transistor T1 is controlled using the fourth scan signal SC4(n). In other words, the conductive state (ON state) and non-conductive state (OFF state) of the first transistor T1 are controlled by the fourth scan signal SC4(n). When the signal supplied to the fourth scan signal SC4(n) is LO, the first transistor T1 is in a non-conductive state. When the signal supplied to the fourth scan signal SC4(n) is HI, the first transistor T1 is in a conductive state.

[0044] The second transistor T2 includes a gate electrode 622, a first electrode 624, and a second electrode 626. The gate electrode 622 is electrically connected to the second node N2, a second electrode 636 of the third transistor T3, and a second electrode 646 of the fourth transistor T4. The first electrode 624 is electrically connected to the third node N3, a second electrode 656 of the fifth transistor T5, a first electrode 692 of the capacitor CS, and a second electrode 666 of the sixth transistor T6. The second electrode 626 is electrically connected to the driving power line PVDD. The threshold voltage of the second transistor T2 is a threshold voltage VTH. The second transistor T2 controls the amount of current flowing to the light-emitting element OLED in accordance with the potential difference Vgs between the voltage supplied to the second node N2 and the voltage supplied to the first electrode 624, the potential difference Vds between the voltage supplied to the second electrode 626 and the voltage supplied to the first electrode 624, and the threshold voltage VTH. For example, when the potential difference Vgs is smaller than the threshold voltage VTH, the second transistor T2 is in a non-conductive state, and no current flows through the light-emitting element OLED, resulting in black display. For example, when the potential difference Vgs is equal to or greater than the threshold voltage VTH and the potential difference Vds is greater than 0 V, the second transistor T2 is in a conductive state, allowing a current Ion to flow and causing the light-emitting element OLED to emit light with a brightness corresponding to the amount of current.

[0045] The third transistor T3 includes a gate electrode 632, a first electrode 634, and a second electrode 636. The gate electrode 632 is electrically connected to the gate electrode 662 of the sixth transistor T6 and the scan signal line 330. As described above, the first scan signal SC1(n) is supplied to the scan signal line 330. The switching of the third transistor T3 is controlled using the first scan signal SC1(n). In other words, the conductive state (on state) and non-conductive state (off state) of the third transistor T3 are controlled by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is HI, the third transistor T3 is in the conductive state. When the signal supplied to the first scan signal SC1(n) is LO, the third transistor T3 is in the non-conductive state.

[0046] The fourth transistor T4 includes a gate electrode 642, a first electrode 644, and a second electrode 646. The gate electrode 642 is electrically connected to the scan signal line 331. The first electrode 644 is electrically connected to the reference voltage power supply line SVR. As described above, the second scan signal SC2(n) is supplied to the scan signal line 331. The switching of the fourth transistor T4 is controlled using the second scan signal SC2(n). In other words, the conductive state (ON state) and non-conductive state (OFF state) of the fourth transistor T4 are controlled by the second scan signal SC2(n). When the signal supplied to the second scan signal SC2(n) is LO, the fourth transistor T4 is non-conductive, and when the signal supplied to the scan signal line 330 is HI, the fourth transistor T4 is conductive.

[0047] The fifth transistor T5 includes a gate electrode 652, a first electrode 654, and a second electrode 656. The gate electrode 652 is electrically connected to the scan signal line 332. The first electrode 654 is electrically connected to the initialization voltage power supply line SVI. As described above, the third scan signal SC3(n) is supplied to the scan signal line 332. The switching of the fifth transistor T5 is controlled using the third scan signal SC3(n). In other words, the fifth transistor T5 is controlled between a conductive state (ON state) and a non-conductive state (OFF state) by the third scan signal SC3(n). When the signal supplied to the third scan signal SC3(n) is LO, the fifth transistor T5 is in a non-conductive state, and when the signal supplied to the third scan signal SC3(n) is HI, the fifth transistor T5 is in a conductive state.

[0048] The sixth transistor T6 includes a gate electrode 662, a first electrode 664, and a second electrode 666. The gate electrode 662 is electrically connected to the scan signal line 330. The first electrode 664 is electrically connected to the second electrode 684 of the light-emitting element OLED. As described above, the first scan signal SC1(n) is supplied to the scan signal line 330. The sixth transistor T6 has its switching controlled using the first scan signal SC1(n). In other words, the sixth transistor T6 has its conductive state (ON state) and non-conductive state (OFF state) controlled by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is LO, the sixth transistor T6 is in a non-conductive state, and when the signal supplied to the first scan signal SC1(n) is HI, the sixth transistor T6 is in a conductive state.

[0049] The first electrode 682 of the light-emitting element OLED is electrically connected to the reference voltage line PVSS. As described above, the reference voltage VSSEL is supplied to the reference voltage line PVSS. The first electrode 682 of the light-emitting element OLED is, for example, a cathode electrode, and the second electrode 684 of the light-emitting element OLED is, for example, an anode electrode.

[0050] For example, the conductive state of a transistor in the display device 10 means that the source electrode and drain electrode of the transistor are conductive and the transistor is in an on (ON) state, and the non-conductive state of a transistor in the display device 10 means that the source electrode and drain electrode of the transistor are non-conductive and the transistor is in an off (OFF) state. Note that in each transistor, the source electrode and drain electrode may be interchanged depending on the voltage or potential supplied to each electrode. Furthermore, it is easily understood by those skilled in the art that even when a transistor is in an off state, a small amount of current, such as leakage current, still flows.

[0051] Each transistor shown in FIG. 3 is an n-channel field-effect transistor, and its channel region contains a Group 14 element such as silicon or germanium, or an oxide exhibiting semiconducting properties. For example, crystalline silicon can be used as the channel region containing a Group 14 element. The crystalline silicon may be low-temperature polysilicon (LTPS) or single-crystal silicon. Furthermore, for example, a metal oxide having semiconducting properties can be used as the oxide exhibiting semiconducting properties. As an example, the metal oxide having semiconducting properties is an oxide semiconductor containing two or more metals including indium (In). The metal oxide having semiconducting properties may be gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), or a lanthanide, in addition to indium. Furthermore, the metal oxide having semiconducting properties may be amorphous, crystalline, or a mixed phase of amorphous and crystalline.

[0052] For example, each transistor in the display device 10 is formed using a thin film transistor (TFT). The channel region of each transistor may be formed using single crystal silicon, such as a silicon wafer or an SOI substrate. Furthermore, when the display device 10 includes both a transistor containing a Group 14 element in its channel region and a transistor containing an oxide exhibiting semiconducting properties in its channel region, the manufacturing method for the display device 10 includes forming a semiconductor layer containing a Group 14 element and forming a semiconductor layer containing an oxide exhibiting semiconducting properties (e.g., an oxide semiconductor layer). The transistor configuration, storage capacitor connection, power supply voltage, etc. of the display device 10 may be appropriately adapted depending on the application and specifications.

[0053] For example, the leakage current of a transistor having a metal oxide with semiconducting properties is extremely small. Therefore, when a transistor having a metal oxide with semiconducting properties is used, the charge corresponding to the voltage (potential) written to a capacitor element is unlikely to escape from the capacitor element. As a result, the use of a transistor having a metal oxide with semiconducting properties enables the charge written to the capacitor element to be retained for a long period of time. Furthermore, under conditions where the potential difference between the gate electrode and the source electrode (gate-source voltage) is the same as the potential difference between the source electrode and the drain electrode (source-drain voltage), the drain current of a transistor having a metal oxide with semiconducting properties may be larger than the drain current of a transistor having crystalline silicon (e.g., low-temperature polysilicon (LTPS)). As a result, under conditions where the drain current is the same, the gate-source voltage and source-drain voltage of a transistor having a metal oxide with semiconducting properties can be smaller than those of a transistor having crystalline silicon. Therefore, the use of a transistor having a metal oxide with semiconducting properties can reduce the power consumption of the display device 10.

[0054] <1-5. Driving method of the display device 10> A method for driving the display device 10 will be described with reference to Figures 4 to 8. Figures 4 to 8 are schematic diagrams showing timing charts of the display device 10. Configurations that are the same as or similar to those in Figures 1 to 3 will be explained as necessary.

[0055] Note that the horizontal axis of the timing chart in each embodiment represents time (TIME). Furthermore, in the image data signal SL(m) including the data signal VDATA in each embodiment, as an example, the data signal VDATA supplied to a selected pixel (pixel circuit) is indicated by diagonal lines as a data voltage (analog data voltage) equal to or greater than the voltage VSIGL and equal to or less than the voltage VSIGH, and the data signal VDATA supplied to pixels (pixel circuits) other than the selected pixel (pixel circuit) is omitted and indicated by solid lines. In reality, in the image data signal SL(m) including the data signal VDATA in each embodiment, the voltage of the data signal VDATA supplied to pixels (pixel circuits) other than the selected pixel (pixel circuit) is also supplied continuously or intermittently.

[0056] For example, the display device 10 is driven at a frequency of 60 Hz, and one frame (1 FRAME) is driven at 60 Hz. For example, FIG. 4 shows the current frame (Kth FRAME), a portion of the frame immediately before the current frame (K-1st FRAME), and a portion of the frame immediately after the current frame (K+1st FRAME). Also, FIGS. 5 to 8 show the light emission period PEM of the frame immediately before the current frame (K-1st FRAME), and the periods PIN, PWR, and PVH of the current frame (Kth FRAME). Also, FIGS. 5 to 8 show one horizontal period (horizontal period HRP) for one pixel 180 (pixel circuit 181).

[0057] First, an overview of a method for driving the display device 10 will be described with reference to Fig. 4. As shown in Fig. 4, the method for driving the display device 10 includes, in one frame, at least an initialization period PIN (period PIN), a write period PWR (period PWR), and a threshold acquisition and retention period PVH (period PVH). In the pixel 180 (pixel circuit 181) included in the display device 10, the period PVH is executed after the period PIN, and after the start of the period PIN, the period PWR is executed in parallel with the periods PIN and PVH. Furthermore, the period PIN, period PWR, and period PVH of the current frame are executed after the light emission period PEM of the frame immediately before the current frame, and the period PIN, period PWR, and period PVH of the frame immediately after the current frame are executed after the light emission period PEM of the current frame.

[0058] The period PIN is a period during which the second node N2, the third node N3, and the fourth node N4 are initialized. The period PWR is a period during which the data signal VDATA is written to the pixel 180 (pixel circuit 181). The period PVH is a period during which the threshold voltage of the second transistor T2 is acquired by performing an operation to make the potential difference Vgs of the second transistor T2 equal to the threshold voltage, and a charge corresponding to the threshold voltage is held at the third node N3 (the first electrode 692 of the capacitor CS). Furthermore, the light-emitting period PEM is a period during which the pixel 180 emits light based on the written (supplied) data signal VDATA and the acquired threshold voltage (corrected threshold voltage) of the second transistor T2 (based on threshold voltage correction). As an example, the period PWR shown in FIG. 4 overlaps with the period PIN and the period PVH, as described above, and is executed during the period PVH.

[0059] Next, a specific method for driving the pixel 180 (pixel circuit 181) of the display device 10 will be described with reference to FIGS.

[0060] The pixel 180 (pixel circuit 181) receives input of a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), a fourth scan signal SC4(n), an image data signal SL(m) including a data signal VDATA, an initialization voltage VINI, and a reference voltage VREF. For example, the pixel 180 (pixel circuit 181) is selected in accordance with the timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n). The image data signal SL(m) is input to the selected pixel 180 (pixel circuit 181) in accordance with the timing of each signal. A similar operation is performed for all pixels 180 (pixel circuits 181), and an image of the current frame corresponding to one frame is displayed in the display area 22 of the display device 10 based on the image data signal SL(m) input to all pixels 180 (pixel circuits 181).

[0061] For example, Table 1 shows the voltages (potentials) supplied to the signals and nodes in each period of each frame in the timing charts shown in FIGS.

[0062] [Table 1]

[0063] <1-5-1. First Example of Driving Method of Display Device 10> A first example of a method for driving the display device 10 will be described with reference to FIG. 5 and Table 1. The driving method shown in the first example involves the pixel 180 (pixel circuit 181) displaying a white image based on the voltage VSIGH of the data signal VDATA in the frame (K-1stFRAME) immediately before the current frame (KthFRAME), and then the pixel 180 (pixel circuit 181) displaying a black image based on the voltage VSIGL of the data signal VDATA in the KthFRAME. In other words, the driving method shown in the first example involves displaying images of different colors in successive frames.

[0064] The image data signal SL(m) is input to each pixel 180 (pixel circuit 181) in accordance with each period (period PIN, period PWR (horizontal period HRP), and period PVH). As shown in Table 1, for example, the voltage VSIGL is 0.2V, and the pixel 180 to which the voltage VSIGL is supplied does not emit light and becomes black. Also, for example, the voltage VSIGH is 4V, and the pixel 180 to which the voltage VSIGH is supplied emits light and produces a white color. For example, the voltage VH(HI) is 10V, the voltage VL(LO) is −3V, the initialization voltage VINI is −2V, the reference voltage VREF is 1.4V, the voltage VM is 5V, and the voltage VN is −5V.

[0065] The light emitting period PEM of the K-1st FRAME is a period during which the pixel 180 (pixel circuit 181) emits light in accordance with the potential difference Vgs of the second transistor T2. For example, the pixel 180 (pixel circuit 181) emits red light, and three pixels, a pixel 180 that emits red light, a pixel 180 that emits blue light, and a pixel 180 that emits green light, emit white light.

[0066] For example, during the light emission period PEM of the (K-1st) FRAME, the image data signal SL(m) is supplied with the voltage of the data signal VDATA supplied to pixels other than the selected pixel 180 (pixel circuit 181), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) are supplied with LO, and the first scan signal SC1(n) is supplied with HI. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are in the OFF state, and the third transistor T3 and the sixth transistor T6 are in the ON state. Furthermore, for example, the voltage Vna supplied to the first node N1 and the second node N2 is 6.1 V, the voltage Vnb supplied to the third node N3 is 2.5 V, and the potential difference Vgs is 3.6 V. Therefore, the second transistor T2 can pass a current Ion based on the potential difference Vgs and the potential difference Vds according to the voltage VSIGH input during the horizontal period HRP of the (K-1st) frame. Also, the second transistor T2 and the sixth transistor T6 are in the on state, and the current Ion flows from the driving power supply line PVDD to the light-emitting element OLED and the reference voltage line PVSS, causing the light-emitting element OLED to emit light.

[0067] During the period between the light-emitting period PEM of the K-1st FRAME and the period PIN of the Kth FRAME (hereinafter, referred to as the period PPIN, for example), the image data signal SL(m) is supplied with the voltage of the data signal VDATA supplied to pixels other than the selected pixel 180 (pixel circuit 181), and the second scan signal SC2(n) changes from a state in which LO is supplied to a state in which HI is supplied. When the second scan signal SC2(n) changes to a state in which HI is supplied, the first scan signal SC1(n) changes from a state in which HI is supplied to a state in which LO is supplied. The third scan signal SC3(n) and the fourth scan signal SC4(n) are in a state in which LO is supplied. Therefore, the fourth transistor T4 changes from an off state to an on state, and the third transistor T3 and the sixth transistor T6 change from an on state to an off state. The first transistor T1 and the fifth transistor T5 maintain their off states. As a result, the voltage supplied to the first node N1 and the voltage supplied to the third node N3 maintain the voltage Vna, and the voltage supplied to the second node N2 gradually drops from the voltage Vna toward the voltage Vnc (reference voltage VREF, 1.4 V) and reaches the voltage Vnc. The second transistor T2 is in either an on state or an off state depending on the potential difference Vgs, but because the sixth transistor T6 is in an off state, no current Ion flows through the light-emitting element OLED, and the light-emitting element OLED does not emit light.

[0068] During the initial period of the period PIN of the Kth FRAME, which follows the light-emitting period PEM of the K-1st FRAME, the image data signal SL(m) is supplied with the voltage of the data signal VDATA supplied to pixels other than the selected pixel 180 (pixel circuit 181). The third scan signal SC3 changes from a state in which LO is supplied to a state in which HI is supplied. The first scan signal SC1(n) and the fourth scan signal SC4(n) are in a state in which LO is supplied, and the second scan signal SC2(n) is in a state in which HI is supplied. Therefore, the fifth transistor T5 changes from an OFF state to an ON state, the fourth transistor T4 remains ON, and the first transistor T1, the third transistor T3, and the sixth transistor T6 remain OFF. As a result, the voltage supplied to the first node N1 remains at voltage Vna, the voltage supplied to the second node N2 remains at voltage Vnc, and the voltage supplied to the third node N3 gradually drops from voltage Vnb to voltage Vnd (initialization voltage VINI, −2V). The second transistor T2 is in either the on state or the off state depending on the potential difference Vgs, as in the PPIN period. However, since the sixth transistor T6 is in the off state, the current Ion does not flow to the light-emitting element OLED, and the light-emitting element OLED does not emit light.

[0069] During the period PIN of the KthFRAME following the beginning of the period PIN, and during the period PWR that runs in parallel (overlapping) with the period PIN, the image data signal SL(m) is supplied with the voltage VSIGL (0.2 V), and the fourth scan signal SC4(n) changes from a state in which LO is supplied to a state in which HI is supplied. The second scan signal SC2(n) and the third scan signal SC3(n) maintain their states in which HI is supplied, and the first scan signal SC1(n) maintains their state in which LO is supplied. Therefore, the first transistor T1 changes from an off state to an on state, the fourth transistor T4 and the fifth transistor T5 maintain their on states, and the third transistor T3 and the sixth transistor T6 maintain their off states.

[0070] As a result, the voltage supplied to the first node N1 gradually drops from voltage Vna toward voltage Vne (voltage VSIGL (0.2V)), the voltage supplied to the second node N2 maintains voltage Vnc, and the voltage supplied to the third node N3 gradually drops from voltage Vnb toward voltage Vnd and reaches voltage Vnd. The potential difference Vgs becomes 3.4V (1.4V-(-2V)), and the potential difference Vds becomes 10V (8V-(-2V)). Therefore, although the second transistor T2 is in the on state, the sixth transistor T6 is in the off state, so that no current Ion flows through the light-emitting element OLED and the light-emitting element OLED does not emit light.

[0071] As described above, during the period PIN, the second node N2 is initialized by the reference voltage VREF (1.4 V), and the third node N3 is initialized by the initialization voltage VINI (−2 V). Furthermore, during the period PWR that is executed in parallel with the period PIN, the data signal VDATA is written to the pixel 180 (pixel circuit 181).

[0072] During the period PVH of the KthFRAME following the period PIN of the KthFRAME, and during the period PWR executed in parallel (overlapping) with the period PVH, the image data signal SL(m) is supplied with the voltage VSIGL (0.2 V), and the third scan signal SC3(n) changes from a HI state to a LO state. The second scan signal SC2(n) and the fourth scan signal SC4(n) maintain their HI states, and the first scan signal SC1(n) maintains their LO state. Therefore, the fifth transistor T5 changes from an ON state to an OFF state, the first transistor T1, the second transistor T2, and the fourth transistor T4 maintain their ON states, and the third transistor T3 and the sixth transistor T6 maintain their OFF states.

[0073] As a result, the voltage supplied to the first node N1 remains at voltage Vne, and the voltage supplied to the second node N2 remains at voltage Vnc. Because the fifth transistor T5 is turned off, the initialization voltage VINI is not supplied to the third node N3, and the third node N3 is released. Furthermore, because the second transistor T2 is turned on, the third node N3 is charged by current Ion. The voltage supplied to the third node N3 gradually increases from voltage Vnd. When the potential difference Vgs becomes equal to the threshold voltage VTH (1 V) of the second transistor T2, the charging of the third node N3 stops. At this time, the voltage supplied to the third node N3 increases from voltage Vnd toward voltage Vnf and reaches voltage Vnf (0.4 V). That is, voltage Vnf is the voltage at which the potential difference Vgs becomes equal to the threshold voltage VTH (1 V) of the second transistor T2. At this time, the second transistor T2 is turned off.

[0074] At the end of the period PVH of the KthFRAME, the image data signal SL(m) is supplied with the voltage VSIGL (0.2V), and the fourth scan signal SC4(n) changes from a HI state to a LO state. When the fourth scan signal SC4(n) changes to a LO state, the second scan signal SC2(n) changes from a HI state to a LO state. The first scan signal SC1(n) and the third scan signal SC3(n) maintain their LO states. Therefore, the first transistor T1 and the fourth transistor T4 change from an ON state to an OFF state, and the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 maintain their OFF states.

[0075] As a result, the voltage supplied to the first node N1 maintains the voltage Vne, the voltage supplied to the second node N2 maintains the voltage Vnc, and the voltage supplied to the third node N3 maintains the voltage Vnf.

[0076] As described above, during the period PWR, which is executed in parallel with the period PVH, the data signal VDATA is written to the pixel 180 (pixel circuit 181). Also, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by an operation that makes the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS).

[0077] During the light emission period PEM of KthFRAME following the period PVH of KthFRAME, the voltage VSIGL supplied to the first node N1 is supplied to the second node N2, and the pixel 180 emits light based on the voltage (VREF-VTH) based on the threshold voltage VTH supplied to the third node, and the potential difference Vgs (=VSIGL-(VREF-VTH)).

[0078] For example, during the light emission period PEM of the KthFRAME, the image data signal SL(m) is supplied with the voltage of the data signal VDATA supplied to pixels other than the selected pixel 180 (pixel circuit 181). Furthermore, the first scan signal SC1(n) changes from a state in which LO is supplied to a state in which HI is supplied, and the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) maintain their states in which LO is supplied. Therefore, the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 maintain their OFF states, and the third transistor T3 and the sixth transistor T6 change from their OFF states to their ON states.

[0079] As a result, the first node N1 becomes conductive with the second node N2, the voltage supplied to the second node N2 gradually drops from voltage Vnc toward voltage Vne (0.2 V) and reaches voltage Vne, the voltage supplied to the first node N1 maintains voltage Vne (0.2 V), and the voltage supplied to the third node N3 maintains voltage Vnf (0.4 V). At this time, the potential difference Vgs becomes 0.2 V (0.2 V - 0.4 V), and the potential difference Vds becomes 7.6 V (8 V - 0.4 V). That is, the second transistor T2 is in an off state, and no current Ion flows through the light-emitting element OLED, so the light-emitting element OLED does not emit light. As a result, for example, the pixel 180 (pixel circuit 181) that emits red light becomes black. Furthermore, like the pixel 180 that emits red light, the pixel 180 that emits blue light and the pixel 180 that emits green light also do not emit light, so the three pixels using the pixel 180 that emits red light, the pixel 180 that emits blue light, and the pixel 180 that emits green light are black.

[0080] The display device 10 includes a capacitive element CS electrically connected between a first node N1 and a third node N3, a fourth transistor T4 for supplying a reference voltage VREF to a second node N2, a fifth transistor T5 for supplying an initialization voltage VINI to the third node N3, a second transistor T2 electrically connected to the second node N2, the third node N3, and a drive power supply line PVDD, and capable of supplying to the third node N3 a current Ion corresponding to a potential difference Vgs between the voltage of the second node N2 and the voltage of the third node N3, a sixth transistor T6 electrically connected between the third node N3 and a second electrode 684 of the light-emitting element OLED, and a first transistor T1 for supplying to the first node N1 a data signal VDATA having a voltage greater than or equal to VSIGL and less than or equal to VSIGH. The driving method of the display device 10 also includes a configuration that can independently control the following: supplying a reference voltage VREF to the second node N2 by the fourth transistor T4; supplying an initialization voltage VINI to the third node N3 by the fifth transistor T5; supplying a current Ion to the third node N3 by the second transistor T2 according to a potential difference Vgs between the voltage of the second node N2 and the voltage of the third node N3; controlling conduction and non-conduction between the third node N3 and the second electrode 684 of the light-emitting element OLED by the sixth transistor T6; and supplying a data signal VDATA that is equal to or greater than the voltage VSIGL and equal to or less than the voltage VSIGH to the first node N1 by the first transistor T1.

[0081] The display device 10 includes the configuration described above, and is capable of: making the third node N3 and the second electrode 684 of the light-emitting element OLED non-conductive by the sixth transistor T6; supplying a reference voltage VREF to the second node N2 (the gate electrode 622 of the second transistor T2) by the fourth transistor T4; and supplying an initialization voltage VINI to the third node N3 (the first electrode 624 of the second transistor T2) by the fifth transistor T5; and then acquiring the threshold voltage VTH of the second transistor T2 and storing a charge equivalent to the threshold voltage VTH at the third node N3 (the first electrode 692 of the capacitive element CS).

[0082] Therefore, the display device 10 can disconnect the parasitic capacitance caused by the light-emitting element OLED from the third node N3 by using the sixth transistor T6 to make the third node N3 and the second electrode 684 of the light-emitting element OLED non-conductive. Furthermore, the display device 10 can supply the reference voltage VREF to the second node N2 (the gate electrode 622 of the second transistor T2) and the initialization voltage VINI to the third node N3 (the first electrode 624 of the second transistor T2), and then acquire the threshold voltage VTH of the second transistor T2 based on the current supplied from the drive voltage VDDEL supplied to the drive power line PVDD, thereby making it possible to reduce the change in potential (voltage) required to acquire the threshold voltage VTH.

[0083] As a result, the display device 10 can reduce the time required for charging and discharging the capacitance by suppressing the parasitic capacitance, and can acquire the threshold voltage VTH by reducing the change in potential (voltage), so that the period VTH can be made shorter than that of a display device that does not include the above-described configuration. Therefore, the display device 10 can be driven at a higher speed.

[0084] Furthermore, the display device 10 can write the data signal VDATA to the first node N1 using the first transistor T1, and supply a voltage based on the data signal VDATA and the corrected threshold voltage VTH to the second node N2 (the gate electrode 622 of the second transistor T2). Thus, the pixel 180 (pixel circuit 181) can display an image in accordance with the data signal VDATA and the voltage based on the corrected threshold voltage VTH acquired over a short period of VTH.

[0085] <1-5-2. Second Example of the Method for Driving the Display Device 10> A second example of a method for driving the display device 10 will be described with reference to FIG. 6. The driving method shown in the second example involves the pixel 180 (pixel circuit 181) displaying a white image based on the voltage VSIGH included in the data signal VDATA in the frame (K-1st FRAME) immediately preceding the current frame (Kth FRAME), and then the pixel 180 (pixel circuit 181) displaying a white image based on the voltage VSIGH included in the data signal VDATA in the Kth FRAME as well. In other words, the driving method shown in the second example involves displaying images of the same color (white) in consecutive frames. Configurations that are the same as or similar to those in FIGS. 1 to 5 will be described as necessary.

[0086] The configurations of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) are the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." The voltage (potential) of the first node N1 during the light-emitting period PEM of the K-1st FRAME, the period between the light-emitting period PEM of the K-1st FRAME following the light-emitting period PEM of the K-1st FRAME and the period PIN of the Kth FRAME (period PPIN), and the initial period of the period PIN of the Kth FRAME are the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." The voltage (potential) of the second node N2 and the third node N3 during periods other than the light-emitting period PEM of the Kth FRAME are the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." Furthermore, the operation of each transistor in each period is the same as the configuration described in "1-5-1. First Example of Method for Driving Display Device 10." Therefore, configurations similar to those described in "1-5-1. First Example of Method for Driving Display Device 10" will be explained as necessary. Note that, as for the image data signal SL(m), a data signal VDATA of VSIGH corresponding to white is supplied during the period PWR of the Kth FRAME (horizontal period HRP), and a data signal VDATA similar to the configuration described in "1-5-1. First Example of Method for Driving Display Device 10" is supplied during periods other than the period PWR of the Kth FRAME.

[0087] During the light emission period PEM of the K-1st FRAME, similar to the configuration described in "1-5-1. First example of the method for driving the display device 10", a current Ion flows from the driving power supply line PVDD to the light emitting element OLED and the reference voltage line PVSS, causing the light emitting element OLED to emit light.

[0088] Furthermore, in the period PPIN following the light-emitting period PEM of the K-1st FRAME, during the initial period and period PIN of the Kth FRAME, the voltage supplied to the first node N1 and the voltage supplied to the third node N3 remain at voltage Vna, and the voltage supplied to the second node N2 becomes voltage Vnc, similar to the configuration described in "1-5-1. First example of the method for driving the display device 10." Also, no current Ion flows through the light-emitting element OLED, and the light-emitting element OLED does not emit light.

[0089] During the initial period of the period PIN of the KthFRAME following the light-emitting period PEM of the K-1stFRAME, the voltage supplied to the first node N1 maintains the voltage Vna, the voltage supplied to the second node N2 maintains the voltage Vnc, and the voltage supplied to the third node N3 gradually drops from the voltage Vnb toward the voltage Vnd (initialization voltage VINI, −2 V). Also, no current Ion flows through the light-emitting element OLED, and the light-emitting element OLED does not emit light.

[0090] During the period PIN of the KthFRAME following the beginning of the period PIN, and during the period PWR that runs in parallel (overlapping) with the period PIN, the image data signal SL(m) is supplied with a voltage VSIGH (Vnh, 4V). The voltage supplied to the first node N1 gradually drops from voltage Vna to voltage Vnh (voltage VSIGH (4V)). Similar to the configuration described in "1-5-1. First Example of the Method for Driving the Display Device 10," the voltage supplied to the second node N2 remains at voltage Vnc, the voltage supplied to the third node N3 gradually drops from voltage Vnb to voltage Vnd, and reaches voltage Vnd. The potential difference Vgs becomes 3.4V, the potential difference Vds becomes 10V, and a current Ion flows through the second transistor T2. However, because the sixth transistor T6 is off, no current Ion flows through the light-emitting element OLED, and the light-emitting element OLED does not emit light.

[0091] As a result, during the period PIN, the second node N2 is initialized by the reference voltage VREF (1.4 V), and the third node N3 is initialized by the initialization voltage VINI (−2 V). Furthermore, during the period PWR that is executed in parallel with the period PIN, the data signal VDATA is written to the pixel 180 (pixel circuit 181).

[0092] During the period PVH of the KthFRAME following the period PIN of the KthFRAME and the period PWR that runs in parallel (overlapping) with the period PVH, the image data signal SL(m) maintains the voltage VSIGH (Vnh, 4V), and the voltage supplied to the first node N1 maintains the voltage Vnh. Also, similar to the configuration described in "1-5-1. First Example of the Method for Driving the Display Device 10," the voltage supplied to the second node N2 maintains the voltage Vnc, the voltage supplied to the third node N3 gradually rises from the voltage Vnd to the voltage Vnf, the potential difference Vgs becomes the threshold voltage VTH (1V) of the second transistor T2, and the second transistor T2 is in the off state.

[0093] At the end of the period PVH of the KthFRAME, the image data signal SL(m) is changed from the state in which the voltage VSIGH was supplied to the pixel data signal SL(m) to the voltage of the data signal VDATA supplied to pixels other than the selected pixel. The voltage supplied to the first node N1 is maintained at voltage Vnh, the voltage supplied to the second node N2 is maintained at voltage Vnc, and the voltage supplied to the third node N3 is maintained at voltage Vnf.

[0094] As described above, during the period PWR, which is executed in parallel with the period PVH, the data signal VDATA is written to the pixel 180 (pixel circuit 181). Also, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by an operation that makes the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS).

[0095] During the light emission period PEM of KthFRAME following the period PVH of KthFRAME, pixel 180 emits light based on the voltage VSIGH supplied to the first node N1 and the potential difference Vsg between the voltage supplied to the second node N2 and the voltage supplied to the third node N3.

[0096] For example, during the light emission period PEM of the Kth FRAME, the image data signal SL(m) is supplied with the voltage of the data signal VDATA supplied to pixels other than the selected pixel. The third transistor T3 is conductive, the first node N1 is conductive with the second node N2, and the voltage of the second node N2 gradually rises from voltage Vnc to voltage Vnh (4V). Furthermore, because the second transistor T2 is conductive and the sixth transistor is conductive, a current Ion flows from the driving power supply line PVDD to the light-emitting element OLED and the reference voltage line PVSS, and the voltage of the third node N3 rises to follow the rise in the voltage of the second node N2. Due to the rise in the voltage of the third node N3, the voltage of the second node N2 and the voltage of the first node N1 connected to the second node N2 further rise.

[0097] As a result, the voltages supplied to the first node N1 and the second node N2 become voltage Vna, and the voltage supplied to the third node N3 becomes voltage Vnb. At this time, the potential difference Vgs becomes 3.6V (6.1V-2.5V), and the potential difference Vds becomes 5.5V (8V-2.5V). That is, the potential difference Vgs is greater than the threshold voltage VTH (1V). Therefore, the second transistor T2 is in an on state, and a current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS, causing the light-emitting element OLED to emit light. For example, the pixel 180 (pixel circuit 181) emits red, and three pixels, one using a pixel 180 that emits blue and one using a pixel 180 that emits green, emit white.

[0098] <1-5-3. Third Example of the Method for Driving the Display Device 10> A third example of a method for driving the display device 10 will be described with reference to FIG. 7. The driving method shown in the third example involves the pixel 180 (pixel circuit 181) displaying a black image based on the voltage VSIGL included in the data signal VDATA in the frame (K-1st FRAME) immediately before the current frame (Kth FRAME), and then the pixel 180 (pixel circuit 181) displaying a black image based on the voltage VSIGH included in the data signal VDATA in the Kth FRAME. In other words, the driving method shown in the third example involves displaying images of the same color (black) in consecutive frames. Configurations that are the same as or similar to those in FIGS. 1 to 6 will be described as necessary.

[0099] The configurations of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) are the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." The voltage (potential) of the first node N1, the voltage (potential) of the second node, and the voltage (potential) of the third node during the period PVH of the KthFRAME following the period PIN of the KthFRAME, the period PWR executed in parallel (overlapping) with the period PVH, the final period of the period PVH of the KthFRAME, and the light-emitting period PEM of the KthFRAME following the period PVH of the KthFRAME are the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." The operation of each transistor during each period is the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." Therefore, configurations similar to those described in "1-5-1. First example of method for driving display device 10" will be described as necessary. Note that, as for the image data signal SL(m), the data signal VDATA of VSIGL corresponding to black is supplied during the period PWR of the Kth FRAME (horizontal period HRP), and the data signal VDATA similar to the configuration described in "1-5-1. First example of method for driving display device 10" is supplied during periods other than the period PWR of the Kth FRAME.

[0100] During the light emission period PEM of the K-1st FRAME, the voltage supplied to the first node N1 and the voltage supplied to the second node N2 are voltage Vne (0.2 V), the voltage supplied to the third node N3 is voltage Vnf (0.4 V), and the potential difference Vgs is −0.2 V. Therefore, the second transistor T2 is in an off state, and the current Ion does not flow from the drive power supply line PVDD to the light-emitting element OLED and the reference voltage line PVSS, so the pixel 180 (pixel circuit 181) that emits red light is black. Similarly to the pixel 180 that emits red light, the pixel 180 that emits blue light and the pixel 180 that emits green light also do not emit light, so the three pixels that use the pixel 180 that emits red light, the pixel 180 that emits blue light, and the pixel 180 that emits green light are black.

[0101] During the period PPIN of the KthFRAME following the light-emitting period PEM of the (K-1stFRAME), the voltage supplied to the first node N1 maintains the voltage Vne, and the voltage supplied to the third node N3 maintains the voltage Vnf. The fourth transistor T4 turns on, and the voltage supplied to the second node N2 gradually increases toward the voltage Vnc (reference voltage VREF, 1.4V) and reaches the voltage Vnc. Because the potential difference Vgs is 1V (1.4V-0.4V) and is equal to or less than the threshold voltage VTH, the second transistor T2 is off, and the sixth transistor T6 is off, no current Ion flows through the light-emitting element OLED, and the light-emitting element OLED does not emit light.

[0102] During the initial period of the period PIN of the KthFRAME following the period PPIN of the KthFRAME, the voltage supplied to the first node N1 maintains the voltage Vne, the voltage supplied to the second node N2 maintains the voltage Vnc, and the voltage supplied to the third node N3 gradually drops from the voltage Vnf toward the voltage Vnd (initialization voltage VINI, -2V) and reaches the voltage Vnd. The potential difference Vgs is 3.4V (1.4V - (-2V)) and is equal to or greater than the threshold voltage VTH, and the second transistor T2 is in a conductive state. However, because the sixth transistor T6 is in an off state, no current Ion flows through the light-emitting element OLED, and the light-emitting element OLED does not emit light.

[0103] During the period PIN of KthFRAME, which follows the beginning of the period PIN of KthFRAME, and during the period PWR, which runs in parallel (overlapping) with the period PIN, the image data signal SL(m) is supplied with the voltage VSIGL (voltage Vne, 0.2V). The voltage VSIGL (0.2V) is supplied to the first node N1, and the voltage supplied to the first node N1 is maintained at voltage Vne. The voltage supplied to the second node N2 is maintained at voltage Vnc, and the voltage supplied to the third node N3 is maintained at voltage Vnd. As in the beginning of the period PIN of KthFRAME, the potential difference Vgs is 3.4V, and the second transistor T2 is on. However, because the sixth transistor T6 is off, no current Ion flows through the light-emitting element OLED, and the light-emitting element OLED does not emit light.

[0104] As described above, during the period PIN, the second node N2 is initialized by the reference voltage VREF (1.4 V), and the third node N3 is initialized by the initialization voltage VINI (−2 V). Furthermore, during the period PWR that is executed in parallel with the period PIN, the data signal VDATA is written to the pixel 180 (pixel circuit 181).

[0105] During the period PVH of KthFRAME following the period PIN of KthFRAME, and the period PWR that runs in parallel (overlapping) with the period PVH, similar to the configuration described in "1-5-1. First example of the driving method of the display device 10", the voltage supplied to the first node N1 remains at voltage Vne, the voltage supplied to the second node N2 remains at voltage Vnc, the voltage supplied to the third node N3 rises from voltage Vnd towards voltage Vnf to become voltage Vnf (0.4V), and the second transistor T2 is in the off state.

[0106] At the end of the period PVH of KthFRAME, similar to the configuration described in "1-5-1. First example of the method for driving the display device 10", the voltage supplied to the first node N1 is maintained at voltage Vne, the voltage supplied to the second node N2 is maintained at voltage Vnc, and the voltage supplied to the third node N3 is maintained at voltage Vnf.

[0107] Therefore, during the period PWR, which is executed in parallel with the period PVH, the data signal VDATA is written to the pixel 180 (pixel circuit 181). Also, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by an operation in which the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS).

[0108] During the light emission period PEM of the KthFRAME following the period PVH of the KthFRAME, similar to the configuration described in "1-5-1. First Example of the Method for Driving the Display Device 10," the voltage supplied to the second node N2 becomes voltage Vne, the voltage supplied to the first node N1 maintains voltage Vne, and the voltage supplied to the third node N3 maintains voltage Vnf. The second transistor T2 is in an off state, and no current Ion flows through the light-emitting element OLED, so the light-emitting element OLED does not emit light. As a result, three pixels, each using a pixel 180 that emits red, a pixel 180 that emits blue, and a pixel 180 that emits green, are black.

[0109] <1-5-4. Fourth Example of the Method for Driving the Display Device 10> A fourth example of a method for driving the display device 10 will be described with reference to FIG. 8. The driving method shown in the fourth example involves the pixel 180 (pixel circuit 181) displaying a black image based on the voltage VSIGL of the data signal VDATA in the frame (K-1st FRAME) immediately before the current frame (Kth FRAME), and then the pixel 180 (pixel circuit 181) displaying a white image based on the voltage VSIGH of the data signal VDATA in the Kth FRAME. In other words, the driving method shown in the fourth example involves displaying images of different colors in successive frames. Configurations that are the same as or similar to those in FIGS. 1 to 11 will be described as necessary.

[0110] The configurations of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the fourth scan signal SC4(n) are the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." The voltage (potential) of the first node N1 during the period PIN of KthFRAME following the beginning of the period PIN of KthFRAME and the period PWR executed in parallel (overlapping) with the period PIN are the same as those described in "1-5-3. Third Example of the Method for Driving the Display Device 10" or "1-5-1. First Example of the Method for Driving the Display Device 10." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the light emission period PEM of KthFRAME are the same as those described in "1-5-2. Second Example of the Method for Driving the Display Device 10." Furthermore, the voltages (potentials) of the second node N2 and the third node N3 during periods other than the light emission period PEM of KthFRAME are the same as those described in "1-5-3. Third example of the method for driving the display device 10." Furthermore, the operation of each transistor during each period is the same as those described in "1-5-1. First example of the method for driving the display device 10." Therefore, configurations similar to those described in "1-5-1. First example of the method for driving the display device 10" to "1-5-3. Third example of the method for driving the display device 10" will be explained as necessary.

[0111] In the light emission period PEM of the (K-1st) frame, the pixel 180 (pixel circuit 181) turns black, similar to the configuration described in "1-5-3. Third example of the method for driving the display device 10."

[0112] During the period PPIN of the KthFRAME following the light-emitting period PEM of the K-1stFRAME, similar to the configuration described in "1-5-3. Third Example of the Method of Driving the Display Device 10," the voltage supplied to the first node N1 remains at voltage Vne, the voltage supplied to the second node N2 becomes voltage Vnc (reference voltage VREF, 1.4 V), and the voltage supplied to the third node N3 remains at voltage Vnf. Because the second transistor T2 is in the off state and the sixth transistor T6 is in the off state, no current Ion flows through the light-emitting element OLED, and the light-emitting element OLED does not emit light.

[0113] During the initial period of the period PIN of the KthFRAME following the period PPIN of the KthFRAME, the voltage supplied to the first node N1 remains at the voltage Vne, the voltage supplied to the second node N2 remains at the voltage Vnc, and the voltage supplied to the third node N3 becomes the voltage Vnd, as in "1-5-3. Third Example of the Method of Driving the Display Device 10." Although the second transistor T2 is in a conductive state, the sixth transistor T6 is in an off state, so that the current Ion does not flow through the light-emitting element OLED, and the light-emitting element OLED does not emit light.

[0114] During the period PIN of the KthFRAME that follows the beginning of the period PIN, and during the period PWR that runs in parallel (overlapping) with the period PIN, the image data signal SL(m) is supplied with the voltage VSIGH (Vnh, 4V). The voltage supplied to the first node N1 gradually increases from voltage Vne toward voltage Vnh (voltage VSIGH (4V)) and reaches voltage Vnh. Similar to the configuration described in "1-5-2. Second Example of the Method for Driving the Display Device 10," the voltage supplied to the second node N2 remains at voltage Vnc, the voltage supplied to the third node N3 changes from voltage Vnb to voltage Vnd, the potential difference Vgs becomes 3.4V, the potential difference Vds becomes 10V, and the second transistor T2 is on. However, because the sixth transistor T6 is off, no current Ion flows through the light-emitting element OLED, and the light-emitting element OLED does not emit light.

[0115] As a result, during the period PIN, the second node N2 is initialized by the reference voltage VREF (1.4 V), and the third node N3 is initialized by the initialization voltage VINI (−2 V). Furthermore, during the period PWR that is executed in parallel with the period PIN, the data signal VDATA is written to the pixel 180 (pixel circuit 181).

[0116] During the period PVH of KthFRAME following the period PIN of KthFRAME and the period PWR which runs in parallel (overlapping) with the period PVH, similar to the configuration described in "1-5-2. Second example of the driving method of the display device 10", the voltage supplied to the first node N1 maintains the voltage Vnh, the voltage supplied to the second node N2 maintains the voltage Vnc, the voltage supplied to the third node N3 gradually rises from the voltage Vnd to the voltage Vnf, the potential difference Vgs becomes the threshold voltage VTH (1V) of the second transistor T2, and the second transistor T2 is in the off state.

[0117] At the end of the period PVH of KthFRAME, similar to the configuration described in "1-5-2. Second example of the method for driving the display device 10", the voltage supplied to the first node N1 remains at voltage Vnh, the voltage supplied to the second node N2 remains at voltage Vnc, and the voltage supplied to the third node N3 remains at voltage Vnf.

[0118] As described above, during the period PWR, which is executed in parallel with the period PVH, the data signal VDATA is written to the pixel 180 (pixel circuit 181). Also, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by an operation that makes the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS).

[0119] During the light-emitting period PEM of the KthFRAME following the period PVH of the KthFRAME, the voltages supplied to the first node N1 and the second node N2 are voltage Vna, and the voltage supplied to the third node N3 is voltage Vnb, similar to the configuration described in "1-5-2. Second Example of the Driving Method of the Display Device 10." The potential difference Vgs is greater than the threshold voltage VTH, the second transistor T2 is on, and a current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS, causing the light-emitting element OLED to emit light. For example, the pixel 180 (pixel circuit 181) emits red, and three pixels, one using a pixel 180 that emits blue and one using a pixel 180 that emits green, emit white.

[0120] <1-6. Edge structure of pixel 180> The end face structure of pixel 180 will be described with reference to FIGS. 9 and 10. FIGS. 9, 12, and 13 are layout diagrams of pixel 180. FIG. 10 is an end face diagram showing an end face cut along A1-A2 in the layout shown in FIG. 9. The layout of pixel 180 shown in FIG. 9 and the end face of pixel 180 shown in FIG. 10 are examples, and the planar layout and end face of pixel 180 are not limited to the examples shown in FIGS. 9 and 10. Configurations that are the same as or similar to those in FIGS. 1 to 8 will be described as necessary.

[0121] The end surface of pixel 180 shown in FIG. 10 is an example of an end surface of pixel 180, and is an end surface along the second wiring 140A, gate wiring 127A, first wiring 132C, organic insulating film opening 138A for capacitance element CS, first wiring 132G, first contact hole opening 135E, second wiring 140B, second contact hole opening 138G, first contact hole opening 135F, semiconductor layer 122B of third transistor T3, gate wiring 127B, first wiring 132C, first contact hole opening 135G, semiconductor layer 122C of sixth transistor T6, first contact hole opening 135K, second contact hole opening 138F, second wiring 140E, contact hole opening 147 for the anode electrode, and first wiring 132A.

[0122] The substrate 101 includes a first surface 101A and a second surface 101B opposite to the first surface 101A. A semiconductor layer 122 is provided on the first surface 101A of the substrate 101 via an underlayer 121. The semiconductor layer 122 includes a semiconductor layer 122A, which includes a channel region 123 and an impurity region 124A (see FIG. 12 ). For example, the impurity region is called a source region or a drain region. Also, for example, the second transistor T2 includes the semiconductor layer 122A, and the first electrode 624 and the second electrode 626 include the impurity region 124A. In other words, the semiconductor layer 122A includes the channel region of the second transistor T2. Similar to the semiconductor layer 122A, for example, the third transistor T3 includes a semiconductor layer 122B, and the first electrode 634 and the second electrode 636 include impurity regions, and the sixth transistor T6 includes a semiconductor layer 122C, and the first electrode 664 and the second electrode 666 include impurity regions. In other words, the semiconductor layer 122B includes the channel region of the third transistor T3, and the semiconductor layer 122C includes the channel region of the sixth transistor T6.

[0123] A gate insulating layer 125, a conductive layer 126, an insulating layer 128, and a conductive layer 132 are provided on the semiconductor layer 122 in this order. The conductive layer 126 includes a gate wiring 127A (gate electrode 622) and a gate wiring 127B (gate electrode 632). The conductive layer 132 includes a first wiring 132C (second electrode 694 of the capacitor CS), a first wiring 132G, a first wiring 132F, and a first wiring 132A (driving power supply line PVDD). The region where the conductive layer 126 and the semiconductor layer 122 overlap is a channel region. In other words, the region where the gate electrode and the semiconductor layer of each transistor overlap is a channel region.

[0124] Each of the transistors of the pixel 180 is formed using a semiconductor layer 122 (channel region 123 and impurity region 124A), a gate insulating layer 125, and a conductive layer 126 (for example, gate wiring 127A).

[0125] A first contact hole opening 135E reaching the conductive layer 126 (here, gate wiring 127A) is provided in the insulating layer 128. Furthermore, first contact hole openings 135F, 135G, and 135K reaching the semiconductor layer 122 are provided in the gate insulating layer 125 and the insulating layer 128. The first contact hole opening 135E exposes the conductive layer 126. The first contact hole openings 135F and 135G expose the semiconductor layer 122B. For example, the first wiring 132G electrically connects the semiconductor layer 122B and the gate wiring 127A via the first contact hole openings 135F and 135E. The first wiring 132C is electrically connected to the semiconductor layer 122B via the first contact hole opening 135G. That is, an opening (not shown) reaching the conductive layer 126 or the semiconductor layer 122 may be provided in the insulating layer 128 .

[0126] The insulating layer 131 is provided to cover the conductive layer 132 and the insulating layer 131 that is not exposed from the conductive layer 132. The insulating layer 136 is provided to cover the insulating layer 131.

[0127] Second contact hole openings are provided in the insulating layer 131 and the insulating layer 136. For example, the second contact hole openings include second contact hole openings 138G and 138F. An organic insulating film opening 138A for the capacitor element CS is provided in the insulating layer 136. A conductive layer 139 is provided on the insulating layer 136, in the organic insulating film opening 138A for the capacitor element CS and the second contact hole openings 138G and 138F. The conductive layer 139 includes a second wiring 140A (the first electrode 692 of the capacitor element CS), a second wiring 140B, and a second wiring 140E (the second electrode 684 of the light-emitting element OLED and the first electrode 664 of the sixth transistor T6). The second contact hole opening 138F exposes the conductive layer 132 (for example, the first wiring 132G). The second contact hole opening 138G electrically connects the second wiring 140B to the first wiring 132G, and the second contact hole opening 138F electrically connects the second wiring 140E to the first wiring 132F. The organic insulating film opening 138A for the capacitance element exposes the insulating layer 131. For example, the capacitance element CS is formed using the first wiring 132C (second electrode 694) and the second wiring 140A (first electrode 692) with the insulating layer 131 as a dielectric. For example, the second wiring 140A also serves as a pixel electrode. Although not shown in the figure, for example, the second contact hole opening 138 exposes some of the multiple terminals (not shown) included in the terminal section 150. Some of the exposed terminals are electrically connected to the FPC 200 using a conductive film such as an anisotropic conductive film (not shown). Furthermore, a pixel electrode is provided independently for each pixel.

[0128] An insulating layer 141 is provided over the conductive layer 139 .

[0129] The base layer 121 , the semiconductor layer 122 , the gate insulating layer 125 , the conductive layer 126 , the insulating layer 128 , the conductive layer 132 , the insulating layer 131 , the insulating layer 136 , the conductive layer 139 , and the insulating layer 141 are collectively referred to as an array section 170 .

[0130] Next, a description will be given of layers above the insulating layer 141. An anode electrode contact hole opening 147 is provided in the insulating layer 141. The anode electrode contact hole opening 147 exposes the conductive layer 139 (for example, the second wiring 140A).

[0131] An anode electrode 143 is provided to cover the exposed conductive layer 139, the anode electrode contact hole opening 147, and the insulating layer 141. A functional layer 148 is provided on the anode electrode 143. A common electrode 149 is provided on the functional layer 148 to cover the functional layer 148. The common electrode 149 is electrically connected to the cathode electrode (first electrode 32 of the light-emitting element OLED). Here, the light-emitting element OLED is composed of the anode electrode 143, the functional layer 148, and the common electrode 149 (cathode electrode).

[0132] The configuration of the functional layer 148 can be selected appropriately. For example, the functional layer 148 can be configured by combining a carrier injection layer, a carrier transport layer, an emitting layer, a carrier blocking layer, an exciton blocking layer, and the like. For example, the functional layer 148 shown in FIG. 10 includes a first layer 144, a second layer 145, and a third layer 146. For example, the first layer 144 is a carrier (hole) injection and transport layer, the second layer 145 is an emitting layer, and the third layer 146 is a carrier (electron) injection and transport layer. For example, the functional layer 148 is provided independently for each pixel, similar to a pixel electrode.

[0133] A sealing film 165 is provided on the common electrode 149. For example, the sealing film 165 includes a first inorganic insulating layer 152, an organic insulating layer 154, and a second inorganic insulating layer 156. The first inorganic insulating layer 152 and the second inorganic insulating layer 156 are formed so as to cover at least the display region 22. A cover film 158 is disposed on the second inorganic insulating layer 156.

[0134] For example, the first layer 144, the second layer 145 (light-emitting layer), and the third layer 146 included in the functional layer 148, as well as the common electrode 149, are not disposed on the IC chip 110 and the control circuit 120. A sealing film 165 and a cover film 158 are disposed on the IC chip 110 and the control circuit 120. The sealing film 165 and the cover film 158 prevent impurities (water, oxygen, etc.) from entering the light-emitting element OLED, the transistors, etc. from the outside of the display device 10.

[0135] Common metal materials are used for the conductive layer 126, the conductive layer 132, the conductive layer 139, and the common electrode 149. For example, common metal materials include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof.

[0136] For example, the semiconductor layer 122 may include crystalline silicon or a metal oxide. The semiconductor layer 122 in the display device 10 includes a metal oxide.

[0137] A general insulating material can be used as the material for forming the base layer 121, the gate insulating layer 125, the insulating layer 131, the first inorganic insulating layer 152, and the second inorganic insulating layer 156. For example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y ) or other inorganic insulating layers are used.

[0138] For example, an organic compound material with excellent surface flatness can be used as the material for forming the insulating layer 128, the insulating layer 136, the insulating layer 141, and the organic insulating layer 154. The insulating layer 128, the insulating layer 136, and the insulating layer 141 may be referred to as organic insulating layers.

[0139] <1-7. Manufacturing method of display device 10> A manufacturing method of the display device 10 (pixel 180) will be described with reference to Figs. 9 to 13. Fig. 11 is a sequence diagram showing a manufacturing method of the display device 10. Configurations that are the same as or similar to those in Figs. 1 to 12 will be explained as necessary. The manufacturing method shown in Fig. 13 includes, as an example, an oxide semiconductor layer formed using an oxide semiconductor.

[0140] As shown in FIG. 10, when the manufacturing of the display device 10 (pixel 180) starts, the underlayer 121 is formed on the first surface 101A of the substrate 101.

[0141] As shown in FIG. 9, FIG. 10, or FIG. 12, a semiconductor layer 122 is formed on the base layer 121 (step 10 (S10) of FIG. 11). The semiconductor layer 122 includes semiconductor layers 122A, 122B, 122C, 122D, and 122E. The semiconductor layer 122A is a semiconductor layer of the second transistor T2. The semiconductor layer 122B serves as a semiconductor layer of the first transistor T1 and a semiconductor layer of the third transistor T3. The semiconductor layer 122C is a semiconductor layer of the fourth transistor T4. The semiconductor layer 122D is a semiconductor layer of the fifth transistor T5. The semiconductor layer 122E is a semiconductor layer of the sixth transistor T6. In other words, the semiconductor layer 122B includes the channel region of the first transistor T1 and the channel region of the third transistor T3, the semiconductor layer 122C includes the channel region of the fourth transistor T4, the semiconductor layer 122D includes the channel region of the fifth transistor T5, and the semiconductor layer 122E includes the channel region of the sixth transistor T6.

[0142] A gate insulating layer 125 (FIGS. 9, 10, 12, and 13) is formed on the semiconductor layer 122 and on the base layer 121 where the semiconductor layer 122 is not formed (step 11 (S11) in FIG. 11).

[0143] A conductive layer 126 (FIGS. 9, 10, 12, and 13) is formed on the gate insulating layer 125 (step 12 (S12) of FIG. 11). As shown in FIG. 9, 10, 12, or 13, the conductive layer 126 includes a gate wiring 127A (gate electrode 622), a gate wiring 127B (scan signal line 330), a gate wiring 127C (scan signal line 331), a gate wiring 127D (scan signal line 332), a gate wiring 127E (scan signal line 333), a gate wiring 127H (reference voltage power supply line SVR), and a gate wiring 127G (initialization voltage power supply line SVI). Gate wiring 127B (scan signal line 333) includes gate electrodes 632 and 662, gate wiring 127C (scan signal line 331) includes gate electrode 642, gate wiring 127D (scan signal line 332) includes gate electrode 652, and gate wiring 127E (scan signal line 333) includes gate electrode 612.

[0144] The region where the gate electrode 622 and the semiconductor layer 122A of the second transistor T2 overlap is the channel region 123, and the channel region 123 corresponds to the channel length of the second transistor T2. Similar to the second transistor T2, the region where the gate electrode 612 and the semiconductor layer 122B of the first transistor T1 overlap is the channel region and also corresponds to the channel length of the first transistor T1. Similar to the second transistor T2, the region where the gate electrode and the semiconductor layer overlap is the channel region and also corresponds to the channel length of the transistor for transistors other than the second transistor T2 and the first transistor T1.

[0145] As shown in FIG. 12, in a plan view, the channel region 123 of the second transistor T2 is larger (longer) than the channel region of the first transistor T1, the channel region of the third transistor T3, the channel region of the fourth transistor T4, the channel region of the fifth transistor T5, and the channel region of the sixth transistor T6.

[0146] The second transistor T2 operates in the saturation region. Therefore, the kink effect in the second transistor T2 needs to be suppressed, and the hot carrier resistance of the second transistor T2 needs to be higher than the hot carrier resistance of the other transistors in the pixel 180. To suppress the kink effect and ensure reliability (hot carrier resistance), the channel length of the second transistor T2 is longer than the channel lengths of the other transistors in the pixel 180. That is, the channel length of the second transistor T2 is longer than the channel lengths of the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6.

[0147] An insulating layer 128 (FIGS. 9, 10, 12, and 13) is formed on the conductive layer 126 and on the gate insulating layer 125 where the conductive layer 126 is not formed (step 13 (S13) in FIG. 11).

[0148] As shown in FIG. 12, first contact hole openings 135, 135A, 135B, 135C, 135D, 135E, 135F, 135G, 135H, 135J, 135K, 135L, 135M, and 135N are opened (step 14 (S14) of FIG. 11). Each opening opens gate insulating layer 125, or gate insulating layer 125 and insulating layer 128, and exposes a corresponding wiring, semiconductor layer, or electrode. For example, first contact hole opening 135 exposes semiconductor layer 122A, and first contact hole opening 135A exposes gate wiring 127G. The other openings also expose corresponding wiring, semiconductor layers, or electrodes.

[0149] A conductive layer 132 (FIGS. 9, 10, 12, and 13) is formed on the insulating layer 128 (step 15 (S15) of FIG. 11). As shown in FIG. 9 or 13, the conductive layer 132 includes a first wiring 132A (driving power supply line PVDD), a first wiring 132B, a first wiring 132C (second electrode 694), a first wiring 132D, a first wiring 132E, a first wiring 132F, a first wiring 132G, a first wiring 132J, and a first wiring 132H (image data signal line 321).

[0150] 13, in a plan view, for example, first wiring 132A is electrically connected to second transistor T2 through first contact hole opening 135D, and first wiring 132B is electrically connected to fourth transistor T4 through first contact hole opening 135C. First wiring 132E is electrically connected to fourth transistor T4 through first contact hole opening 135B and electrically connected to gate wiring 127H through first contact hole opening 135N. The other first wirings are also electrically connected to gate wirings or transistors through their corresponding openings.

[0151] 13, the second electrode 694, the gate electrode 622, and the semiconductor layer 122A (channel region 123) overlap with each other. That is, the second transistor T2 (its channel region and gate electrode 622) overlaps with the second electrode 694 of the capacitance element CS.

[0152] An insulating layer 131 (FIGS. 9, 10, 12, and 13) is formed on the conductive layer 132 and on the insulating layer 128 where the conductive layer 132 is not formed (step 16 (S16) in FIG. 11).

[0153] As shown in FIG. 9 or FIG. 13, second contact hole openings 138B, 138C, 138E, 138F, 138G, and 138H are opened (step 17 (S17) of FIG. 11). Each opening opens the insulating layer 131 and exposes the corresponding wiring, semiconductor layer, or electrode. For example, second contact hole opening 138B exposes the first wiring 132D.

[0154] An insulating layer 136 (organic insulating layer) (FIGS. 9, 10, 12, and 13) is formed on the insulating layer 131 (step 18 (S18) in FIG. 11).

[0155] As shown in FIG. 9 or FIG. 13, holes are opened in the insulating layer 136 (organic insulating layer) (step 19 (S19) in FIG. 11). In the opening of S19, an organic insulating film opening 138A for a capacitor element is opened. In addition, in the opening of S19, second contact hole openings 138B, 138C, 138C, 138E, 138F, 138G, and 138H are opened, similar to the opening of S18. That is, the second contact hole openings 138B, 138C, 138C, 138E, 138F, 138G, and 138H are opened twice. Each opening opens the insulating layer 136, exposing the corresponding insulating layer, wiring, or electrode. For example, organic insulating film opening 138A for the capacitor element removes only the insulating layer 136 on first wiring 132C (second electrode 694), exposing insulating layer 131. On the other hand, for example, second contact hole opening 138F removes only the insulating layer 136 on first wiring 132F, exposing first wiring 132F. Other openings also expose the corresponding insulating layer, wiring, or electrode.

[0156] A conductive layer 139 (FIGS. 9, 10, 12, and 13) is formed on the insulating layer 136 and on the insulating layer 131 exposed in the organic insulating film opening 138A for the capacitor element (step 20 (S20) in FIG. 11). As shown in FIG. 9 or 10, the conductive layer 139 includes a second wiring 140A (first electrode 692 of the capacitor element CS), a second wiring 140B, a second wiring 140C, a second wiring 140D, and a second wiring 140E.

[0157] 9, for example, in a plan view, the second wiring 140A (first electrode 692 of the capacitance element CS) is electrically connected to the first wiring 132F and the sixth transistor T6 through the second contact hole opening 138F and the first contact hole opening 135K. The other wirings are also electrically connected to wirings or electrodes through their corresponding contact hole openings.

[0158] 9, the second wiring 140D is connected to and overlaps with the gate wiring 127G (initialization voltage power line SVI), and extends parallel to the gate wiring 127G in the second direction D2. Since the initializing voltage power line SVI is formed using two layers of metal wiring, it has a lower wiring resistance than a voltage line formed using a single layer of metal wiring. As a result, the initializing voltage power line SVI has a high current supply capability and can supply a stable voltage to each transistor. The second wiring 140C is connected to and overlaps with the gate wiring 127H (reference voltage power line SVR), and extends parallel to the gate wiring 127G in the second direction D2. Since the pre-charge voltage power line SVR is formed using two layers of metal wiring, similar to the initializing voltage power line SVI, it provides the same effects as the initializing voltage power line SVI.

[0159] 13, the second wiring 140A (first electrode 692 of the capacitor CS), the first wiring 132C (second electrode 694), the gate electrode 622, and the semiconductor layer 122A (channel region 123) overlap with each other. That is, the second transistor T2 overlaps with the capacitor CS.

[0160] An insulating layer 141 (organic insulating layer) (FIG. 10) is formed on the conductive layer 139 and on the insulating layer 136 where the conductive layer 139 is not formed (step 21 (S21) in FIG. 11).

[0161] As shown in FIG. 9 or 10, an opening is made in the insulating layer 141 (organic insulating layer) (step 22 (S22) in FIG. 11). In the opening of S22, a contact hole opening 147 for the anode electrode is made. The contact hole opening 147 for the anode electrode removes the insulating layer 141 above the second wiring 140A, exposing the second wiring 140A. The contact hole opening 147 for the anode electrode is sometimes called an organic insulating layer opening. Note that, as shown in FIG. 9, the contact hole opening 147 for the anode electrode overlaps the second wiring 140E in plan view.

[0162] An anode electrode 143 is provided on the exposed second wiring 140E, on the anode electrode contact hole opening 147, and on the insulating layer 141. A functional layer 148 is provided on the anode electrode 143 (FIG. 10). A common electrode 149 is provided on the functional layer 148 (step 23 (S23) in FIG. 11). Note that, for example, the anode electrode 143 and the functional layer 148 are provided for each pixel, and the common electrode 149 is provided so as to overlap the display region 22.

[0163] After S23, the sealing film 165 and the cover film 158 are provided in this order on the common electrode 149 (FIG. 10).

[0164] As shown in FIG. 9, the manufacturing of the display device 10 (pixel 180) is completed in this manner.

[0165] 2. Second Embodiment An overview of the display device according to the second embodiment will be described with reference to Fig. 14 to Fig. 20. Fig. 14 is a schematic diagram showing an input signal to a pixel 180A (pixel circuit 181A) according to the second embodiment, Fig. 15 is a circuit diagram showing the configuration of the pixel circuit 181A, and Figs. 16 to 20 are timing charts of the display device according to the second embodiment.

[0166] The display device according to the second embodiment includes a pixel 180A and a pixel circuit 181A. Specifically, the pixel 180A and the pixel circuit 181A include the configurations shown in (1) and (2) below. The configurations shown in (1) and (2) are mainly different from the configurations of the pixel 180 and the pixel circuit 181 of the display device 10 according to the first embodiment.

[0167] (1) The second scan signal SC2(n) serves as both the second scan signal SC2(n) and the fourth scan signal SC4(n) in the display device 10 according to the first embodiment. Therefore, the pixel 180A and the pixel circuit 181A do not include the fourth scan signal SC4(n). (2) The second scan signal SC2(n) serves as both the second scan signal SC2(n) and the fourth scan signal SC4(n) in the display device 10 according to the second embodiment, and therefore the timing of each signal is different. For example, after the period PWR is executed, the period PIN is executed in parallel with the period PWR.

[0168] The configurations of the pixel 180A and the pixel circuit 181A shown in (1) and (2), and the configurations other than those related to the configurations of the pixel 180A and the pixel circuit 181A shown in (1) and (2), are the same as those of the display device 10 according to the first embodiment. Therefore, differences from the display device 10 according to the first embodiment will be mainly described here. In describing the configuration and functions of the display device according to the second embodiment, configurations and functions that are the same as those of the display device 10 according to the first embodiment will be described as necessary. Furthermore, configurations that are the same as or similar to those in FIGS. 1 to 13 will be described as necessary.

[0169] <2-1. Configuration of pixel 180A> The pixel 180A and the pixel circuit 181A will be outlined with reference to FIGS.

[0170] In the pixel circuit 181A, the gate electrode 612 of the first transistor T1 and the gate electrode 642 of the fourth transistor T4 are electrically connected to a scan signal line 331 to which a second scan signal SC2(n) is supplied. That is, the first transistor T1 and the fourth transistor T4 operate at the same timing in response to the second scan signal SC2(n). The first transistor T1 and the fourth transistor T4 are controlled to be in a conductive state (ON state) or a non-conductive state (OFF state) by the second scan signal SC2(n). When the signal supplied to the second scan signal SC2(n) is LO, the first transistor T1 and the fourth transistor T4 are in a non-conductive state, and when the signal supplied to the scan signal line 330 is HI, the first transistor T1 and the fourth transistor T4 are in a conductive state.

[0171] The configuration and functions of the pixel circuit 181A other than those described in "2-1. Configuration of the pixel 180A" are the same as those of the pixel circuit 181.

[0172] <2-2. Driving Method of Pixel Circuit 181A> A method for driving a display device according to a second embodiment will be described with reference to FIGS. 17 to 20. Configurations identical to or similar to those in FIGS. 1 to 15 will be described as necessary. As in the first embodiment, the horizontal axis of the timing chart represents time, and the data signal VDATA supplied to a selected pixel (pixel circuit) is indicated by diagonal lines as a data voltage (analog data voltage) between voltages VSIGL and VSIGH. Data signals VDATA supplied to pixels (pixel circuits) other than the selected pixel (pixel circuit) are omitted and indicated by solid lines. Furthermore, in each embodiment, the image data signal SL(m) including the data signal VDATA also includes the voltage of the data signal VDATA supplied to pixels (pixel circuits) other than the selected pixel (pixel circuit), either continuously or intermittently. As in the first embodiment, the display device according to the second embodiment is driven at a frequency of 60 Hz, and one frame (1 FRAME) is driven at 60 Hz.

[0173] The method for driving the display device according to the second embodiment differs from the method for driving the display device 10 according to the first embodiment in the configurations related to the configurations shown in (1) and (2) described in "2-1. Configuration of pixel 180A." The configurations and functions other than the configurations related to (1) and (2) described in "2-1. Configuration of pixel 180A" are the same as those of the method for driving the display device 10 according to the first embodiment. For example, as shown in (2) above and FIG. 16, in the method for driving the display device according to the second embodiment, after the period PWR is executed, the period PIN is executed in parallel with the period PWR. The configurations other than (2) in the method for driving the display device according to the second embodiment are the same as those of the method for driving the display device 10 according to the first embodiment shown in FIG.

[0174] During one horizontal period (horizontal period HRP) in the driving method of the display device according to the second embodiment, the pixel 180A (pixel circuit 181A) receives a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), an image data signal SL(m), an initialization voltage VINI, and a reference voltage VREF. For example, the pixel 180 (pixel circuit 181) is selected according to the timing of the first scan signal SC1(n), the second scan signal SC2(n), and the third scan signal SC3(n). The image data signal SL(m) is input to the selected pixel 180A (pixel circuit 181A) according to the timing of each signal. Similar operations are performed for all pixels 180A (pixel circuits 181A), and an image of the current frame corresponding to one frame is displayed in the display area 22 of the display device 10 based on the image data signal SL(m) input to all pixels 180A (pixel circuits 181A).

[0175] For example, the voltages (potentials) supplied to the signals in each frame in the timing charts shown in FIGS.

[0176] <2-2-1. First Example of Method for Driving Pixel Circuit 181A> A first example of a method for driving the pixel circuit 181A will be described with reference to Fig. 17. The first example of the method for driving the pixel circuit 181A includes displaying images of different colors in successive frames, similar to the first example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 15 will be described as necessary.

[0177] The configurations of the first scan signal SC1(n) to the third scan signal SC3(n) are the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." Furthermore, the conduction and non-conduction of the second transistor T2 to the sixth transistor T6 other than the first transistor T1 are the same as those described in "1-5-1. First Example of the Method for Driving the Display Device 10." Configurations similar to those described in "1-5-1. First Example of the Method for Driving the Display Device 10" will be described as necessary.

[0178] For example, during the light emission period PEM of the (K-1st) frame, the image data signal SL(m) is supplied with the voltage of the data signal VDATA supplied to pixels other than the selected pixel 180 (pixel circuit 181). The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are in an off state, and the third transistor T3 and the sixth transistor T6 are in an on state. For example, the voltage Vna supplied to the first node N1 and the second node N2 is 6.1 V, the voltage Vnb supplied to the third node N3 is 2.5 V, and the potential difference Vgs is 3.6 V. Therefore, the second transistor T2 can pass a current Ion based on the potential difference Vgs and the potential difference Vds corresponding to the voltage VSIGH input during the horizontal period HRP of the (K-1st) frame. Furthermore, the second transistor T2 and the sixth transistor T6 are in an on state, and the current Ion flows from the drive power supply line PVDD to the light-emitting element OLED and the reference voltage line PVSS, causing the light-emitting element OLED to emit light.

[0179] During the period between the period PWR of the Kth FRAME and the period PIN of the Kth FRAME (hereinafter, for example, referred to as the period BWRAIN), which follows the light emission period PEM of the K-1st FRAME, the image data signal SL(m) is supplied with the voltage of the data signal VDATA supplied to pixels other than the selected pixel 180 (pixel circuit 181). The second scan signal SC2(n) changes from a state in which LO is supplied to a state in which HI is supplied. When the second scan signal SC2(n) changes to a state in which HI is supplied, the first scan signal SC1(n) changes from a state in which HI is supplied to a state in which LO is supplied. The third scan signal SC3(n) maintains a state in which LO is supplied. As a result, the first transistor T1 and the fourth transistor T4 change from an off state to an on state. The third transistor T3, the fifth transistor T5, and the sixth transistor T6 maintain their off states. Furthermore, the voltage supplied to the first node N1 gradually drops from voltage Vna toward voltage VSIGL (voltage Vne, 0.2 V), the voltage supplied to the second node N2 gradually drops from voltage Vna toward voltage Vnc (reference voltage VREF, 1.4 V) and becomes voltage Vnc, and the voltage supplied to the third node N3 maintains voltage Vnb. The second transistor T2 is in either an on state or an off state depending on the potential difference Vgs, but because the sixth transistor T6 is in an off state, no current Ion flows through the light-emitting element OLED, and the light-emitting element OLED does not emit light.

[0180] During the period PWR of the KthFRAME following the period BWRAIN of the KthFRAME, and during the period PIN executed in parallel (overlapping) with the period PWR, the image data signal SL(m) is supplied with a voltage VSIGL (0.2 V). The image data signal SL(m) is supplied with the voltage of the data signal VDATA supplied to pixels other than the selected pixel 180 (pixel circuit 181). The third scan signal SC3 changes from a state in which LO is supplied to a state in which HI is supplied. The first scan signal SC1(n) is in a state in which LO is supplied, and the second scan signal SC2(n) is in a state in which HI is supplied. Therefore, the fifth transistor T5 changes from an off state to an on state, the first transistor T1 and the fourth transistor T4 remain on, and the third transistor T3 and the sixth transistor T6 remain off.

[0181] As a result, the voltage supplied to the first node N1 gradually drops toward voltage VSIGL (voltage Vne, 0.2 V) and becomes voltage Vne, the voltage supplied to the second node N2 maintains voltage Vnc, and the voltage supplied to the third node N3 gradually drops from voltage Vnb toward voltage Vnd (initialization voltage VINI, -2 V) and becomes voltage Vnd. The potential difference Vgs becomes 3.4 V (1.4 V - (-2 V)), and the potential difference Vds becomes 10 V (8 V - (-2 V)). Therefore, although the second transistor T2 is in an on state, the sixth transistor T6 is in an off state, so that no current Ion flows through the light-emitting element OLED and the light-emitting element OLED does not emit light.

[0182] As described above, during the period PIN, the second node N2 is initialized by the reference voltage VREF (1.4 V), and the third node N3 is initialized by the initialization voltage VINI (−2 V). Furthermore, during the period PWR that is executed in parallel with the period PIN, the data signal VDATA is written to the pixel 180A (pixel circuit 181A).

[0183] During the period PVH, which runs in parallel (overlapping) with the period PWR of the KthFRAME following the period PIN of the KthFRAME, the operations of the signals, the transistors, and the voltages (potentials) supplied to the nodes are the same as those in the period PVH of the KthFRAME following the period PIN of the KthFRAME and the period PWR, which runs in parallel (overlapping) with the period PVH, as described in "1-5-1. First Example of the Driving Method of the Display Device 10." That is, the voltage supplied to the first node N1 remains at voltage Vne, the voltage supplied to the second node N2 remains at voltage Vnc, and the voltage supplied to the third node N3 rises from voltage Vnd to voltage Vnf (0.4 V). At this time, voltage Vnf is the voltage at which the potential difference Vgs becomes the threshold voltage VTH (1 V) of the second transistor T2, and the second transistor T2 is in the off state.

[0184] At the end of the period PVH of the KthFRAME, the image data signal SL(m) is supplied with the voltage VSIGL (0.2V). The second scan signal SC2(n) changes from a HI state to a LO state. The first scan signal SC1(n) and the third scan signal SC3(n) are both in a LO state. Therefore, the first transistor T1 and the fourth transistor T4 change from an ON state to an OFF state, and the second transistor T2, the third transistor T3, the fifth transistor T5, and the sixth transistor T6 remain in an OFF state.

[0185] As a result, the voltage supplied to the first node N1 maintains the voltage Vne, the voltage supplied to the second node N2 maintains the voltage Vnc, and the voltage supplied to the third node N3 maintains the voltage Vnf.

[0186] As described above, during the period PVH executed in parallel with the period PWR, the data signal VDATA is written to the pixel 180 (pixel circuit 181). Also, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by an operation that makes the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS).

[0187] During the light-emitting period PEM of the KthFRAME following the period PVH of the KthFRAME, the signals, the operation of the transistors, and the voltages (potentials) supplied to the nodes are the same as those in the light-emitting period PEM of the KthFRAME following the period PVH of the KthFRAME described in "1-5-1. First Example of the Driving Method of the Display Device 10." That is, the voltage supplied to the first node N1 is maintained at voltage Vne (0.2 V), the voltage supplied to the second node N2 gradually drops from voltage Vnc to voltage Vne, and the voltage supplied to the third node N3 is maintained at voltage Vnf (0.4 V). At this time, the potential difference Vgs is 0.2 V, the potential difference Vds is 7.6 V, the second transistor T2 is in the off state, and no current Ion flows through the light-emitting element OLED. As a result, the three pixels using the red-emitting pixel 180A, the blue-emitting pixel 180A, and the green-emitting pixel 180A are black.

[0188] The first example of the method for driving the pixel circuit 181A including the configuration described above has the same effects as the method for driving the display device 10 according to the first embodiment.

[0189] Furthermore, pixel circuit 181A includes a configuration that also serves as the second scan signal SC2(n) and the fourth scan signal SC4(n) in pixel circuit 181. Thus, pixel circuit 181A has a configuration that allows the number of signals and the number of signal lines to be reduced. As a result, a display device including pixel circuit 181A can reduce the number of signal lines within a pixel, thereby enabling the pixel size to be reduced. Therefore, a display device including pixel circuit 181A can increase the number of pixels, and also enable higher definition and larger screens.

[0190] <2-2-2. Second Example of Method for Driving Pixel Circuit 181A> A second example of a method for driving the pixel circuit 181A will be described with reference to Fig. 18. The driving method shown in the second example of the pixel circuit 181A includes displaying images of the same color (white) in consecutive frames, similar to the second example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 17 will be described as necessary.

[0191] The configuration of the first scan signal SC1(n) to the third scan signal SC3(n) is the same as the configuration described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A." Furthermore, the voltage (potential) of the first node N1 during the light-emitting period PEM of the K-1st FRAME is the same as the configuration described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A." Furthermore, the voltage (potential) of the second node N2 and the third node N3 during periods other than the light-emitting period PEM of the Kth FRAME is the same as the configuration described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A." Furthermore, the operation of each transistor during each period is the same as the configuration described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A." Therefore, configurations similar to those described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A" will be described as necessary. In addition, as for the image data signal SL(m), during the period PWR of the KthFRAME (horizontal period HRP), a data signal VDATA of VSIGH corresponding to white is supplied, and during periods other than the period PWR of the KthFRAME, a data signal VDATA similar to the configuration described in "2-2-1. First example of the driving method of the pixel circuit 181A" is supplied.

[0192] The second example of the driving method for the pixel circuit 181A in the light emission period PEM of the K-1st FRAME is the same as the driving method described in "2-2-1. First example of the driving method for the pixel circuit 181A."

[0193] During the period BWRAIN following the light-emitting period PEM of the (K-1st) FRAME, the voltage supplied to the first node N1 gradually drops from voltage Vna toward voltage VSIGH (voltage Vnh, 4 V). Similar to the configuration described in "2-2-1. First Example of the Method of Driving the Pixel Circuit 181A," the voltage supplied to the second node N2 gradually drops from voltage Vna toward voltage Vnc (reference voltage VREF, 1.4 V) and reaches voltage Vnc, and the voltage supplied to the third node N3 maintains voltage Vna. The second transistor T2 is in either an on state or an off state depending on the potential difference Vgs. However, because the sixth transistor T6 is in an off state, no current Ion flows through the light-emitting element OLED, and the light-emitting element OLED does not emit light.

[0194] During the period PWR of the KthFRAME following the period BWRAIN of the KthFRAME, and during the period PIN executed in parallel (overlapping) with the period PWR, the voltage supplied to the first node N1 gradually drops toward the voltage VSIGH (voltage Vnh, 4 V) and becomes voltage Vnh. Similarly to the configuration described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A," the voltage supplied to the second node N2 remains at voltage Vnc, and the voltage supplied to the third node N3 gradually drops from voltage Vnb toward voltage Vnd (initialization voltage VINI, −2 V) and becomes voltage Vnd. The potential difference Vgs becomes 3.4 V, the potential difference Vds becomes 10 V, and the second transistor T2 is in the on state. However, because the sixth transistor T6 is in the off state, no current Ion flows through the light-emitting element OLED, and the light-emitting element OLED does not emit light.

[0195] As described above, during the period PIN, the second node N2 is initialized by the reference voltage VREF (1.4 V), and the third node N3 is initialized by the initialization voltage VINI (−2 V). Furthermore, during the period PWR that is executed in parallel with the period PIN, the data signal VDATA is written to the pixel 180A (pixel circuit 181A).

[0196] During the period PVH that runs in parallel (overlaps) with the period PWR of the KthFRAME that follows the period PIN of the KthFRAME, the voltage supplied to the first node N1 maintains the voltage Vnh. Also, similar to the configuration described in "2-2-1. First Example of the Method of Driving the Pixel Circuit 181A," the voltage supplied to the second node N2 maintains the voltage Vnc, the voltage supplied to the third node N3 rises from the voltage Vnd toward the voltage Vnf and reaches the voltage Vnf (0.4 V), and the second transistor T2 is in the off state.

[0197] At the end of the period PVH of the KthFRAME, the image data signal SL(m) is supplied with the voltage VSIGL (4V), and the second scan signal SC2(n) changes from a HI state to a LO state. The voltage supplied to the first node N1 remains at the voltage Vnh, the voltage supplied to the second node N2 remains at the voltage Vnc, and the voltage supplied to the third node N3 remains at the voltage Vnf.

[0198] As described above, during the period PVH executed in parallel with the period PWR, the data signal VDATA is written to the pixel 180 (pixel circuit 181). Also, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by an operation that makes the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS).

[0199] During the light-emitting period PEM of the KthFRAME following the period PVH of the KthFRAME, the signals, the operation of the transistors, and the voltages (potentials) supplied to the nodes are the same as those in the light-emitting period PEM of the KthFRAME described in "1-5-2. Second Example of the Driving Method of the Display Device 10." That is, the voltages supplied to the first node N1 and the second node N2 are voltage Vna, the voltage supplied to the third node N3 is voltage Vnb, the potential difference Vgs is 3.6 V, and the potential difference Vds is 5.5 V. The second transistor T2 is in the on state, and the light-emitting element OLED emits light. White light is emitted by three pixels: pixel 180A (pixel circuit 181A) that emits red light, pixel 180 that emits blue light, and pixel 180 that emits green light.

[0200] <2-2-3. Third Example of Method for Driving Pixel Circuit 181A> A third example of a method for driving the pixel circuit 181A will be described with reference to Fig. 19. The third example of the method for driving the pixel circuit 181A includes displaying images of the same color (black) in consecutive frames, similar to the third example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 18 will be described as necessary.

[0201] The configurations of the first scan signal SC1(n) to the third scan signal SC3(n) are the same as those described in "2-2-1. First Example of the Method for Driving the Pixel Circuit 181A." The third example of the method for driving the pixel circuit 181A also includes controlling the first transistor T1 and the fourth transistor T4 by the second scan signal SC2(n). When the first transistor T1 is in a conductive state, the voltage supplied to the first node N1 is voltage VSIGL (voltage Vne, 0.2 V), and when the fourth transistor T4 is in a conductive state, the voltage supplied to the second node N2 is voltage Vnc (reference voltage VREF, 1.4 V). Therefore, the configuration and operation in "2-2-3. Third Example of the Method for Driving the Pixel Circuit 181A" are the same as those described in "1-5-3. Third Example of the Method for Driving the Display Device 10," except for the above (1) and (2). Therefore, detailed description thereof will be omitted here.

[0202] <2-2-4. Fourth Example of Method for Driving Pixel Circuit 181A> A fourth example of a method for driving the pixel circuit 181A will be described with reference to Fig. 20. The fourth example of the method for driving the pixel circuit 181A includes displaying images of different colors in successive frames, similar to the fourth example of the method for driving the display device 10 according to the first embodiment. Configurations that are the same as or similar to those in Figs. 1 to 19 will be described as necessary.

[0203] The configurations of the first scan signal SC1(n) to the third scan signal SC3(n) are the same as those described in "2-2-1. First Example of Method for Driving Pixel Circuit 181A." Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the light emission period PEM of the K-1st FRAME are the same as those described in "2-2-3. Third Example of Method for Driving Pixel Circuit 181A." Furthermore, the voltages (potentials) of the second node N2 and the third node N3 and the operation of each transistor during the period BWRAIN following the light-emitting period PEM of the K-1st FRAME, the period PWR of the Kth FRAME following the period BWRAIN of the Kth FRAME, the period PIN executed in parallel (overlapping) with the period PWR, the period PVH executed in parallel (overlapping) with the period PWR of the Kth FRAME following the period PIN of the Kth FRAME, and the final period of the period PVH of the Kth FRAME are the same as the configurations and operations described in "2-2-3. Third Example of the Method for Driving the Pixel Circuit 181A." Furthermore, the voltages (potentials) of the first node N1, the second node N2 and the third node N3 and the operation of each transistor during the light-emitting period PEM of the Kth FRAME are the same as the configurations and operations described in "2-2-2. Second Example of the Method for Driving the Pixel Circuit 181A." Configurations similar to those described in "2-2-1. First Example of Method for Driving Pixel Circuit 181A" to "2-2-3. Third Example of Method for Driving Pixel Circuit 181A" will be described as necessary. Note that, as for the image data signal SL(m), a data signal VDATA including a voltage VSIGH corresponding to white is supplied during the period between the light emission period PEM of the K-1st FRAME and the light emission period PEM of the Kth FRAME.

[0204] During the light emission period PEM of the K-1st FRAME, the pixel 180 (pixel circuit 181) becomes black, as in "2-2-3. Third example of the method for driving the pixel circuit 181A" ("1-5-3. Third example of the method for driving the display device 10").

[0205] During the period BWRAIN following the light-emitting period PEM of the (K-1st) FRAME, the voltage supplied to the first node N1 gradually increases from voltage Vnf toward voltage VSIGH (Vnh, 4V). The voltage supplied to the second node N2 gradually increases from voltage Vnf toward the reference voltage VREF (voltage Vnc, 1.4V) and becomes voltage Vnc, and the voltage supplied to the third node N3 maintains voltage Vne. The potential difference Vgs is 1.2, and the second transistor T2 is on, but the sixth transistor T6 is off, so the light-emitting element OLED does not emit light.

[0206] During the period PWR of the KthFRAME following the period BWRAIN of the KthFRAME, and during the period PIN executed in parallel (overlapping) with the period PWR, the voltage supplied to the first node N1 gradually increases from voltage Vnf toward voltage VSIGH (Vnh, 4V) and reaches voltage Vnh. Similarly to "2-2-3. Third Example of the Method for Driving the Pixel Circuit 181A" or "2-2-2. Second Example of the Method for Driving the Pixel Circuit 181A," the voltage supplied to the second node N2 remains at voltage Vnc, and the voltage supplied to the third node N3 gradually decreases from voltage Vnb toward voltage Vnd (initialization voltage VINI, −2V) and reaches voltage Vnd. The potential difference Vgs becomes 3.4V, the potential difference Vds becomes 10V, and the second transistor T2 is in the on state. However, because the sixth transistor T6 is in the off state, no current Ion flows through the light-emitting element OLED, and the light-emitting element OLED does not emit light.

[0207] As described above, during the period PIN, the second node N2 is initialized by the reference voltage VREF (1.4 V), and the third node N3 is initialized by the initialization voltage VINI (−2 V). Furthermore, during the period PWR that is executed in parallel with the period PIN, the data signal VDATA is written to the pixel 180A (pixel circuit 181A).

[0208] During the period PVH that runs in parallel (overlaps) with the period PWR of KthFRAME that follows the period PIN of KthFRAME, similar to the configuration described in "2-2-2. Second example of the driving method of pixel circuit 181A", the voltage supplied to the first node N1 maintains the voltage Vnh, the voltage supplied to the second node N2 maintains the voltage Vnc, the voltage supplied to the third node N3 rises from the voltage Vnd towards the voltage Vnf and becomes the voltage Vnf (0.4V), and the second transistor T2 is in the off state.

[0209] At the end of the period PVH of KthFRAME, similar to the configuration described in "2-2-2. Second example of the driving method for pixel circuit 181A", the voltage supplied to the first node N1 remains at voltage Vnh, the voltage supplied to the second node N2 remains at voltage Vnc, and the voltage supplied to the third node N3 remains at voltage Vnf.

[0210] As described above, during the period PVH executed in parallel with the period PWR, the data signal VDATA is written to the pixel 180 (pixel circuit 181). Also, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by an operation that makes the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS).

[0211] During the light emission period PEM of the KthFRAME following the period PVH of the KthFRAME, similar to the configuration described in "2-2-2. Second Example of Driving Method of Pixel Circuit 181A," the voltage supplied to the first node N1 and the second node N2 becomes voltage Vna, the voltage supplied to the third node N3 becomes voltage Vnb, the potential difference Vgs becomes 3.6 V, and the potential difference Vds becomes 5.5 V. The second transistor T2 is in the on state, and the light-emitting element OLED emits light. White light is emitted by three pixels: pixel 180A (pixel circuit 181A) that emits red, pixel 180 that emits blue, and pixel 180 that emits green.

[0212] 3. Third Embodiment An overview of the display device according to the third embodiment will be described with reference to Fig. 21 to Fig. 26. Fig. 21 is a schematic diagram showing input signals to a pixel 180B (pixel circuit 181B) according to the third embodiment, Fig. 22 is a circuit diagram showing the configuration of the pixel circuit 181B, and Figs. 23 to 26 are timing charts of the display device according to the third embodiment.

[0213] The display device according to the third embodiment includes a pixel 180B and a pixel circuit 181B. Specifically, the pixel 180B and the pixel circuit 181B include the configurations shown in the following (1) to (3). The configurations shown in (1) to (3) are mainly different from the configurations of the pixel 180A and the pixel circuit 181A of the display device according to the second embodiment.

[0214] (1) The scan voltage power supply line SVIR to which the scan voltage power supply SIR(n) is supplied is included. (2) The scan voltage power supply line SVIR is a common signal line that serves as both the reference voltage power supply line SVR to which the reference voltage power supply VREF is supplied and the initialization voltage power supply line SVI to which the initialization voltage VINI is supplied. That is, the scan voltage power supply line SVIR has a configuration that serves as both the reference voltage power supply line SVR and the initialization voltage power supply line SVI. (3) The scan voltage power supply SIR(n) includes a voltage that alternates with time, which is an initialization voltage VINI2 and an initialization voltage VINI1.

[0215] The configurations of the pixel 180B and the pixel circuit 181B shown in (1) to (3), and the configurations other than those related to the configurations of the pixel 180B and the pixel circuit 181B shown in (1) to (3), are the same as those of the pixel 180A and the pixel circuit 181A of the display device according to the second embodiment. Therefore, differences from the pixel 180A and the pixel circuit 181A of the display device according to the second embodiment will be mainly described here. In describing the configuration and functions of the display device according to the third embodiment, configurations and functions that are the same as those of the display device 10 according to the first embodiment will be described as necessary. Furthermore, configurations that are the same as or similar to those in FIGS. 1 to 20 will be described as necessary.

[0216] <3-1. Configuration of pixel 180B> The pixel 180B and pixel circuit 181B will be outlined with reference to FIGS.

[0217] The pixel circuit 181B is connected to a scan voltage power supply line SVIR. The scan voltage power supply line SVIR functions as a power supply line that supplies voltage to the pixel 180B and the pixel circuit 181B, and also functions as a signal line whose voltage (potential) changes over time.

[0218] In the pixel circuit 181B, a first electrode 644 of the fourth transistor T4 and a first electrode 654 of the fifth transistor T5 are electrically connected to the scan voltage power supply line SVIR. The first electrode 644 of the fourth transistor T4 and the first electrode 654 of the fifth transistor T5 are supplied with the initialization voltage VINI2 or the initialization voltage VINI1 depending on time.

[0219] For example, the scan voltage power supply line SVIR is electrically connected to a connection wiring 342 that is different from the precharge voltage power supply line SVP, the drive power supply line PVDD, and the reference voltage line PVSS among the connection wirings 342. Also, for example, the scan voltage power supply line SVIR may be one of the connection wirings 342.

[0220] For example, the scan voltage power supply SIR(n) may be supplied from an external device to the IC chip 110, similar to the initialization voltage VINI, or may be supplied from the IC chip 110 to the plurality of pixels 180A (pixel circuits 181A) via the connection wiring 342 and the scan voltage power supply line SVIR. Although not shown, the scan voltage power supply SIR(n) may be connected from an external device to the scan voltage power supply line SVIR via the FPC 200, the terminal unit 150, and the connection wiring 341, similar to the initialization voltage VINI, without going through the IC chip 110 and the connection wiring 342.

[0221] The fourth transistor T4 has a function of connecting the second node N2 and the scan voltage power supply line SVIR and supplying the initialization voltage VINI1 or VINI2 to the second node N2, thereby initializing the second node N2. For example, the initialization voltages VINI1 and VINI2 are constant voltages.

[0222] The fifth transistor T5 has a function of connecting the third node N3 and the scan voltage power supply line SVIR to each other, supplying the initialization voltage VINI1 to the third node N3, and initializing the third node N3.

[0223] The configuration and functions of the pixel circuit 181B other than those described in "3-1. Configuration of the pixel 180B" are the same as those of the pixel circuit 181A.

[0224] <3-2. Driving method of pixel circuit 181B> A method for driving a display device according to the third embodiment will be described with reference to Fig. 4 and Fig. 23 to Fig. 26. Configurations that are the same as or similar to those in Fig. 1 to Fig. 22 will be described as necessary. As in the second embodiment, the horizontal axis of the timing chart represents time.

[0225] The method for driving the display device according to the third embodiment differs from the method for driving the display device according to the second embodiment in the configuration related to the configurations shown in (1) to (3) described in "3-1. Configuration of pixel 180B." The configurations and functions other than the configurations related to (1) to (3) described in "3-1. Configuration of pixel 180B" are the same as those of the method for driving the display device according to the second embodiment.

[0226] The method for driving the display device according to the third embodiment includes the same period as the method for driving the display device 10 according to the first embodiment shown in FIG.

[0227] In one horizontal period (horizontal period HRP) in the driving method of the display device according to the third embodiment, the pixel 180B (pixel circuit 181B) receives a first scan signal SC1(n), a second scan signal SC2(n), a third scan signal SC3(n), an image data signal SL(m), and a scan voltage power supply SIR(n). For example, the pixel 180B (pixel circuit 181B) is selected according to the timing of the first scan signal SC1(n), the second scan signal SC2(n), the third scan signal SC3(n), and the scan voltage power supply SIR(n). The image data signal SL(m) and the scan voltage power supply SIR(n) are input to the selected pixel 180B (pixel circuit 181B) according to the timing of each signal. A similar operation is performed for all pixels 180B (pixel circuits 181B), and based on the image data signals SL(m) input to all pixels 180B (pixel circuits 181B), an image of the frame corresponding to one frame is displayed in the display area 22 of the display device 10.

[0228] For example, the voltages (potentials) supplied to the signals in each frame in the timing charts shown in FIGS.

[0229] [Table 2]

[0230] For example, as shown in Table 2, the initialization voltage VINI2 is 1.4 V and the initialization voltage VINI1 is −2 V. The initialization voltage VINI2 is the same as the reference voltage VREF, and the initialization voltage VINI1 is the same as the initialization voltage VINI. The setting values ​​of the other voltages are the setting values ​​shown in Table 1 described in “1-5. Method of driving the display device 10.”

[0231] <3-2-1. First Example of Method for Driving Pixel Circuit 181B> A first example of a method for driving the pixel circuit 181B will be described with reference to Fig. 23. The first example of the method for driving the pixel circuit 181B includes displaying images of different colors in successive frames, similar to the first example of the method for driving the pixel circuit 181A according to the second embodiment. Configurations that are the same as or similar to those in Figs. 1 to 22 will be described as necessary.

[0232] The scan voltage power supply SIR(n) supplies an initialization voltage VINI2 during the light emission period PEM of the K-1stFRAME and the period BWRAIN following the light emission period PEM of the K-1stFRAME, supplies an initialization voltage VINI1 during the period PWR of the KthFRAME following the period BWRAIN of the KthFRAME and the period PIN which runs in parallel (overlapping) with the period PWR, and supplies an initialization voltage VINI2 during the period PVH which runs in parallel (overlapping) with the period PWR of the KthFRAME following the period PIN of the KthFRAME and the light emission period PEM of the KthFRAME which follows the period PVH of the KthFRAME.

[0233] The configurations of the first scan signal SC1(n) to the fifth scan signal SC3(n) are the same as those described in "2-2-1. First Example of Method for Driving Pixel Circuit 181A." Furthermore, the operation of each transistor in each period is the same as that described in "2-2-1. First Example of Method for Driving Pixel Circuit 181A." Therefore, configurations similar to those described in "2-2-1. First Example of Method for Driving Pixel Circuit 181A" will be described as necessary.

[0234] In the light emitting period PEM of the K-1st FRAME, the light emitting element OLED emits light in the same manner as in the configuration described in "2-2-1. First example of the method for driving the pixel circuit 181A."

[0235] In the period BWRAIN following the light-emitting period PEM of the (K-1st) FRAME, the voltage supplied to the first node N1 gradually drops from voltage Vna toward voltage VSIGL (voltage Vne, 0.2 V), the voltage supplied to the second node N2 gradually drops from voltage Vna toward voltage Vnd (initialization voltage VINI1, -2 V), and the voltage supplied to the third node N3 maintains voltage Vnb. The second transistor T2 is in either an on state or an off state depending on the potential difference Vgs, but because the sixth transistor T6 is in an off state, no current Ion flows through the light-emitting element OLED, and the light-emitting element OLED does not emit light.

[0236] During the period PWR of KthFRAME following the period BWRAIN of KthFRAME, and during the period PIN executed in parallel (overlapping) with the period PWR, the voltage supplied to the first node N1 gradually drops toward voltage VSIGL (voltage Vne, 0.2V) and becomes voltage Vne, the voltage supplied to the second node N2 gradually drops toward voltage Vnd and becomes voltage Vnd, and the voltage supplied to the third node N3 also gradually drops toward voltage Vnd (initialization voltage VINI1, -2V) and becomes voltage Vnd. The potential difference Vgs becomes 0V (-2V - -2V), and the potential difference Vds becomes 10V (8V - -2V). Therefore, the second transistor T2 is in an off state, and the sixth transistor T6 is also in an off state, so that no current Ion flows through the light-emitting element OLED, and the light-emitting element OLED does not emit light.

[0237] As described above, during the period PIN, the second node N2 and the third node N3 are initialized by the initialization voltage VINI (-2 V). Furthermore, during the period PWR that is executed in parallel with the period PIN, the data signal VDATA is written to the pixel 180B (pixel circuit 181B).

[0238] During the period PVH that runs in parallel (overlaps) with the KthFRAME period PWR following the KthFRAME period PIN, the voltage supplied to the first node N1 remains at voltage Vne, the voltage supplied to the second node N2 rises from voltage Vnd toward the initialization voltage VINI2 (voltage Vnc, 1.4 V) to become voltage Vnc (1.4 V), and the voltage supplied to the third node N3 rises from voltage Vnd toward voltage Vnf to become voltage Vnf (0.4 V). At this time, voltage Vnf is the voltage at which the potential difference Vgs becomes the threshold voltage VTH (1 V) of the second transistor T2, and the second transistor T2 is in the off state.

[0239] At the end of the period PVH of KthFRAME, the voltage supplied to the first node N1 maintains the voltage Vne, the voltage supplied to the second node N2 maintains the voltage Vnc, and the voltage supplied to the third node N3 maintains the voltage Vnf.

[0240] As described above, during the period PVH executed in parallel with the period PWR, the data signal VDATA is written to the pixel 180 (pixel circuit 181). Also, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by an operation that makes the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS).

[0241] During the light-emitting period PEM of the KthFRAME following the period PVH of the KthFRAME, the voltage supplied to the first node N1 remains at voltage Vne (0.2 V), the voltage supplied to the second node N2 gradually drops from voltage Vnc toward voltage Vne (0.2 V) and reaches voltage Vne, and the voltage supplied to the third node N3 remains at voltage Vnf (0.4 V). At this time, the potential difference Vgs becomes 0.2 V, the potential difference Vds becomes 7.6 V, the second transistor T2 is in the off state, and no current Ion flows through the light-emitting element OLED. As a result, the three pixels using the red-emitting pixel 180B, the blue-emitting pixel 180B, and the green-emitting pixel 180B are black.

[0242] The first example of the method for driving the pixel circuit 181B including the configuration described above has the same effects as the method for driving the display device 10 according to the first embodiment.

[0243] Furthermore, pixel circuit 181B includes a scan voltage power supply line SVIR that is a common line that serves as the reference voltage power supply line SVR and the initialization voltage power supply line SVI in pixel circuit 181A. Thus, pixel circuit 181B has a configuration that can further reduce the number of signals and signal lines. As a result, a display device including pixel circuit 181B can further reduce the number of signal lines within a pixel, thereby enabling further reduction in pixel size. Therefore, a display device including pixel circuit 181B can achieve higher definition and a larger screen.

[0244] <3-2-2. Second Example of Method for Driving Pixel Circuit 181B> A second example of a method for driving the pixel circuit 181B will be described with reference to Fig. 23. The method for driving the pixel circuit 181B shown in the second example includes displaying images of the same color (white) in consecutive frames, similar to the second example of the method for driving the pixel circuit 181A according to the second embodiment. Configurations that are the same as or similar to those in Figs. 1 to 22 will be described as necessary.

[0245] The configuration of the first scan signal SC1(n) to the third scan signal SC3(n) is the same as the configuration described in "3-2-1. First Example of a Method for Driving a Pixel Circuit 181B." Furthermore, the voltage (potential) of the first node N1 during the light-emitting period PEM of the K-1st FRAME is the same as the configuration described in "3-2-1. First Example of a Method for Driving a Pixel Circuit 181B." Furthermore, the voltage (potential) of the second node N2 and the third node N3 during periods other than the light-emitting period PEM of the Kth FRAME is the same as the configuration described in "3-2-1. First Example of a Method for Driving a Pixel Circuit 181B." Furthermore, the operation of each transistor during each period is the same as the configuration described in "3-2-1. First Example of a Method for Driving a Pixel Circuit 181B." Therefore, configurations similar to those described in "3-2-1. First Example of a Method for Driving a Pixel Circuit 181B" will be described as necessary. In addition, as for the image data signal SL(m), during the period PWR of the KthFRAME (horizontal period HRP), a data signal VDATA of VSIGH corresponding to white is supplied, and during periods other than the period PWR of the KthFRAME, a data signal VDATA similar to the configuration described in "3-2-1. First example of the driving method of the pixel circuit 181B" is supplied.

[0246] The second example of the driving method for the pixel circuit 181B in the light emission period PEM of the K-1st FRAME is the same as the driving method described in "3-2-1. First example of the driving method for the pixel circuit 181B".

[0247] During the period BWRAIN following the light-emitting period PEM of the (K-1st) FRAME, the voltage supplied to the first node N1 gradually drops from voltage Vna toward voltage VSIGH (voltage Vnh, 4 V). Similarly to the configuration described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B," the voltage supplied to the second node N2 gradually drops from voltage Vna toward voltage Vnd (initialization voltage VINI2, -2 V), and the voltage supplied to the third node N3 gradually drops from voltage Vnb toward voltage Vnd. Because the sixth transistor T6 is in the off state, no current Ion flows through the light-emitting element OLED, and the light-emitting element OLED does not emit light.

[0248] During the period PWR of the KthFRAME following the period BWRAIN of the KthFRAME, and during the period PIN that runs in parallel (overlapping) with the period PWR, the voltage supplied to the first node N1 gradually drops toward the voltage VSIGH (voltage Vnh, 4 V) and becomes voltage Vnh. Similarly to the configuration described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B," the voltage supplied to the second node N2 and the voltage supplied to the third node N3 become voltage Vnd. The potential difference Vgs is 0 V, the potential difference Vds is 10 V, the second transistor T2 is in the off state, and the sixth transistor T6 is in the off state. Therefore, no current Ion flows through the light-emitting element OLED, and the light-emitting element OLED does not emit light.

[0249] As described above, during the period PIN, the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (-2 V). Furthermore, during the period PWR that is executed in parallel with the period PIN, the data signal VDATA is written to the pixel 180A (pixel circuit 181A).

[0250] During the period PVH that runs in parallel (overlaps) with the period PWR of the KthFRAME that follows the period PIN of the KthFRAME, the voltage supplied to the first node N1 maintains the voltage Vnh. Also, similar to the configuration described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B," the voltage supplied to the second node N2 rises to voltage Vnc, the voltage supplied to the third node N3 becomes voltage Vnf, and the second transistor T2 is in the off state.

[0251] At the end of the period PVH of KthFRAME, the voltage supplied to the first node N1 maintains the voltage Vnh, the voltage supplied to the second node N2 maintains the voltage Vnc, and the voltage supplied to the third node N3 maintains the voltage Vnf.

[0252] As described above, during the period PVH executed in parallel with the period PWR, the data signal VDATA is written to the pixel 180 (pixel circuit 181). Also, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by an operation that makes the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS).

[0253] During the light emission period PEM of the KthFRAME following the period PVH of the KthFRAME, the voltages supplied to the first node N1 and the second node N2 become voltage Vna, the voltage supplied to the third node N3 becomes voltage Vnb, the potential difference Vgs becomes 3.6 V, and the potential difference Vds becomes 5.5 V. The second transistor T2 is in the on state, and the light-emitting element OLED emits light. Three pixels, including a pixel 180A (pixel circuit 181A) that emits red, a pixel 180 that emits blue, and a pixel 180 that emits green, emit white light.

[0254] <3-2-3. Third Example of Method for Driving Pixel Circuit 181B> A third example of a method for driving the pixel circuit 181B will be described with reference to Fig. 25. The driving method shown in the third example of the method for driving the pixel circuit 181B includes displaying images of the same color (black) in consecutive frames, similar to the third example of the method for driving the pixel circuit 181A according to the second embodiment. Configurations that are the same as or similar to those in Figs. 1 to 24 will be described as necessary.

[0255] The configurations of the first scan signal SC1(n) to the third scan signal SC3(n) are the same as those described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B." Furthermore, the voltage (potential) of the first node N1, the voltage (potential) of the second node, and the voltage (potential) of the third node during the period PVH executed in parallel (overlapping) with the period PWR of the KthFRAME following the period PIN of the KthFRAME, the final period of the period PVH of the KthFRAME, and the light-emitting period PEM of the KthFRAME following the period PVH of the KthFRAME are the same as those described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B." Therefore, configurations similar to those described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B" will be described as necessary. In addition, during the KthFRAME period PWR (horizontal period HRP), the image data signal SL(m) is supplied with the data signal VDATA of VSIGL corresponding to black, and during periods other than the KthFRAME period PWR, the image data signal SL(m) is supplied with the data signal VDATA similar to the configuration described in "3-2-1. First example of the driving method for pixel circuit 181B".

[0256] During the light emission period PEM of the K-1st FRAME, the voltage supplied to the first node N1 and the voltage supplied to the second node N2 are voltage Vne (0.2 V), the voltage supplied to the third node N3 is voltage Vnf (0.4 V), and the potential difference Vgs is −0.2 V. Therefore, the second transistor T2 is in an off state, and current Ion does not flow from the drive power supply line PVDD to the light-emitting element OLED and the reference voltage line PVSS, so the pixel 180B (pixel circuit 181B) that emits red light is black. Similarly to the pixel 180B that emits red light, the pixel 180B that emits blue light and the pixel 180B that emits green light also do not emit light, so the three pixels that use the pixel 180B that emits red light, the pixel 180B that emits blue light, and the pixel 180B that emits green light are black.

[0257] During the period BWRAIN of the KthFRAME following the light-emitting period PEM of the (K-1stFRAME), the voltage supplied to the first node N1 maintains the voltage Vne, and the voltage supplied to the third node N3 maintains the voltage Vnf. The fourth transistor T4 turns on, and the voltage supplied to the second node N2 gradually drops toward the voltage Vnd (initialization voltage VINI1, −2V) and reaches the voltage Vnd. Because the potential difference Vgs is −2.2V (−2V−0.2V), the second transistor T2 is off, and the sixth transistor T6 is also off, no current Ion flows through the light-emitting element OLED, and the light-emitting element OLED does not emit light.

[0258] During the period PWR of KthFRAME following the period BWRAIN of KthFRAME, and during the period PIN that runs in parallel (overlapping) with the period PWR, the voltage supplied to the first node N1 maintains the voltage Vnf, the voltage supplied to the second node N2 maintains the voltage Vnd, and the voltage supplied to the third node N3 gradually drops from the voltage Vnf toward the voltage Vnd (initialization voltage VINI1, −2 V) and reaches the voltage Vnd. Because the potential difference Vgs is 0 V, the second transistor T2 is in the off state, and the sixth transistor T6 is also in the off state, no current Ion flows through the light-emitting element OLED, and the light-emitting element OLED does not emit light.

[0259] During the period PVH, which runs in parallel (overlaps) with the period PWR of the KthFRAME following the period PIN of the KthFRAME, the voltage supplied to the first node N1 remains at voltage Vne, and the voltage supplied to the second node N2 rises to voltage Vnc (initialization voltage VINI2, 1.4 V), similar to the configuration described in "3-2-1. First Example of the Driving Method of the Pixel Circuit 181B." When the third scan signal SC3(n) is set to LO, the fifth transistor T5 is turned off, and the third node N3 is released, turning on the second transistor T2. The third node N3 is charged, the potential at the third node N3 rises, and the voltage supplied to the third node N3 stops at voltage Vnf (initialization voltage VINI2 - threshold voltage VTH). The potential difference Vgs is equal to the threshold voltage VTH (1.0 V), and the second transistor T2 is turned off. During the charging period until the voltage supplied to the third node N3 reaches the voltage Vnf, the second transistor T2 is in the ON state, but the sixth transistor T6 is in the OFF state, so that the current Ion does not flow to the light-emitting element OLED and the light-emitting element OLED does not emit light.

[0260] As described above, during the period PIN, the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (-2 V). Furthermore, during the period PWR that is executed in parallel with the period PIN, the data signal VDATA is written to the pixel 180 (pixel circuit 181).

[0261] During the final period of the KthFRAME period PVH following the KthFRAME period PVH, similar to the configuration described in "3-2-1. First example of the driving method for pixel circuit 181B", the voltage supplied to the first node N1 remains at voltage Vne, the voltage supplied to the second node N2 remains at voltage Vnc, and the voltage supplied to the third node N3 remains at voltage Vnf.

[0262] Therefore, during the period PWR, which is executed in parallel with the period PVH, the data signal VDATA is written to the pixel 180 (pixel circuit 181). Also, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by an operation in which the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS).

[0263] During the light emission period PEM of the KthFRAME following the period PVH of the KthFRAME, similar to the configuration described in "3-2-1. First Example of the Method for Driving the Pixel Circuit 181B," the voltage supplied to the second node N2 becomes voltage Vne, the voltage supplied to the first node N1 maintains voltage Vne, and the voltage supplied to the third node N3 maintains voltage Vnf. The second transistor T2 is in an off state, and no current Ion flows through the light-emitting element OLED, so the light-emitting element OLED does not emit light. As a result, the three pixels, which use the pixel 180B that emits red, the pixel 180B that emits blue, and the pixel 180B that emits green, are black.

[0264] <3-2-4. Fourth Example of Method for Driving Pixel Circuit 181B> A fourth example of a method for driving the pixel circuit 181B will be described with reference to Fig. 26. The fourth example of the method for driving the pixel circuit 181B includes displaying images of different colors in successive frames, similar to the fourth example of the method for driving the display device according to the second embodiment. Configurations that are the same as or similar to those in Figs. 1 to 25 will be described as necessary.

[0265] The configurations of the first scan signal SC1(n) to the third scan signal SC3(n) are the same as those described in "3-2-1. First example of the method for driving the pixel circuit 181B." In addition, the voltages (potentials) of the first node N1, the second node N2, and the third node N3, and the operation of each transistor during the light emission period PEM of the K-1st FRAME are the same as those described in "3-2-3. Third example of the method for driving the pixel circuit 181B." Furthermore, the voltages (potentials) of the second node N2 and the third node N3 and the operation of each transistor during the period BWRAIN following the light-emitting period PEM of the K-1st FRAME, the period PWR of the Kth FRAME following the period BWRAIN of the Kth FRAME, the period PIN executed in parallel (overlapping) with the period PWR, the period PVH executed in parallel (overlapping) with the period PWR of the Kth FRAME following the period PIN of the Kth FRAME, and the final period of the period PVH of the Kth FRAME are the same as the configurations and operations described in "3-2-3. Third Example of the Method for Driving the Pixel Circuit 181B." Furthermore, the voltages (potentials) of the first node N1, the second node N2 and the third node N3 and the operation of each transistor during the light-emitting period PEM of the Kth FRAME are the same as the configurations and operations described in "3-2-2. Second Example of the Method for Driving the Pixel Circuit 181B." Configurations similar to those described in "3-2-1. First Example of Method for Driving Pixel Circuit 181B" to "3-2-3. Third Example of Method for Driving Pixel Circuit 181B" will be described as necessary. Note that, as for the image data signal SL(m), a data signal VDATA including a voltage VSIGH corresponding to white is supplied during the period between the light emission period PEM of the K-1st FRAME and the light emission period PEM of the Kth FRAME.

[0266] During the light emission period PEM of the K-1st FRAME, the pixel 180B (pixel circuit 181B) becomes black, as in "3-2-3. Third example of the method for driving the pixel circuit 181B" ("1-5-3. Third example of the method for driving the display device 10").

[0267] During the period BWRAIN following the light-emitting period PEM of the (K-1st) FRAME, the voltage supplied to the first node N1 gradually increases from voltage Vnf toward voltage VSIGH (Vnh, 4V). The voltage supplied to the second node N2 gradually decreases from voltage Vnf toward the initialization voltage VINI1 (voltage Vnd, -2V) and reaches voltage Vnd, and the voltage supplied to the third node N3 maintains voltage Vne (0.2V). Since the potential difference Vgs (-2V - 0.2V) is -2.2V, the second transistor T2 is in the off state, and the sixth transistor T6 is also in the off state, the light-emitting element OLED does not emit light.

[0268] During the period PWR of the KthFRAME following the period BWRAIN of the KthFRAME, and during the period PIN that runs in parallel (overlapping) with the period PWR, the voltage supplied to the first node N1 gradually rises from voltage Vnf toward voltage VSIGH (Vnh, 4V) and reaches voltage Vnh. Similarly to "3-2-3. Third Example of the Method for Driving the Pixel Circuit 181B" or "3-2-2. Second Example of the Method for Driving the Pixel Circuit 181B," the voltage supplied to the second node N2 and the voltage supplied to the third node N3 reach voltage Vnd. Because the potential difference Vgs is 0V, the second transistor T2 is in an off state, and the sixth transistor T6 is also in an off state, no current Ion flows through the light-emitting element OLED, and the light-emitting element OLED does not emit light.

[0269] As described above, during the period PIN, the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (-2 V). Furthermore, during the period PWR that is executed in parallel with the period PIN, the data signal VDATA is written to the pixel 180A (pixel circuit 181A).

[0270] During the period PVH that runs in parallel (overlaps) with the period PWR of KthFRAME that follows the period PIN of KthFRAME, similar to the configuration described in "3-2-2. Second example of the driving method of pixel circuit 181B", the voltage supplied to the first node N1 remains at voltage Vnh, the voltage supplied to the second node N2 rises to voltage Vnc and becomes voltage Vnc, the voltage supplied to the third node N3 rises to voltage Vnf and becomes voltage Vnf, and the second transistor T2 is in the off state.

[0271] At the end of the period PVH of KthFRAME, similar to the configuration described in "3-2-2. Second example of the driving method for pixel circuit 181B", the voltage supplied to the first node N1 remains at voltage Vnh, the voltage supplied to the second node N2 remains at voltage Vnc, and the voltage supplied to the third node N3 remains at voltage Vnf.

[0272] As described above, during the period PVH executed in parallel with the period PWR, the data signal VDATA is written to the pixel 180 (pixel circuit 181). Also, during the period PVH, the threshold voltage VTH of the second transistor T2 is acquired by an operation that makes the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH, and a charge equivalent to the threshold voltage VTH is held at the third node N3 (the first electrode 692 of the capacitance element CS).

[0273] During the light emission period PEM of the KthFRAME following the period PVH of the KthFRAME, similar to the configuration described in "3-2-2. Second Example of Driving Method of Pixel Circuit 181B," the voltage supplied to the first node N1 and the second node N2 becomes voltage Vna, the voltage supplied to the third node N3 becomes voltage Vnb, the potential difference Vgs becomes 3.6 V, and the potential difference Vds becomes 5.5 V. The second transistor T2 is in the on state, and the light-emitting element OLED emits light. White light is emitted by three pixels: pixel 180A (pixel circuit 181A) that emits red, pixel 180 that emits blue, and pixel 180 that emits green.

[0274] The above-described embodiments of the present invention or parts of the embodiments can be combined as appropriate as long as they are not mutually inconsistent.

[0275] Even if there are other effects and advantages different from those brought about by the aspects of each of the above-mentioned embodiments, if they are clear from the description in this specification or can be easily predicted by a person skilled in the art, they are naturally understood to be brought about by the present invention. [Explanation of symbols]

[0276] 10: display device, 22: display region, 24: peripheral region, 26: terminal region, 32: first electrode, 100: array substrate, 101: substrate, 101A: first surface, 101B: second surface, 110: IC chip, 120: control circuit, 121: underlayer, 122: semiconductor layer, 122A: semiconductor layer, 122B: semiconductor layer, 122C: semiconductor layer, 122D: semiconductor layer, 122E: semiconductor layer, 123: channel region, 124A: impurity region, 125: gate insulating layer, 126: conductive layer, 127A: gate wiring, 127B: gate wiring, 127C: gate wiring, 127D: gate wiring, 1 27E: gate wiring, 127G: gate wiring, 127H: gate wiring, 128: insulating layer, 130: shift register circuit, 131: insulating layer, 132: conductive layer, 132A: first wiring, 132B: first wiring, 132C: first wiring, 132D: first wiring, 132E: first wiring, 132F: first wiring, 132G: first wiring, 132H: first wiring, 132J: first wiring, 135: first contact hole opening, 135A: first contact hole opening, 135B: first contact hole opening, 135C: first contact hole opening, 13 5D: first contact hole opening, 135E: first contact hole opening, 135F: first contact hole opening, 135G: first contact hole opening, 135H: first contact hole opening, 135J: first contact hole opening, 135K: first contact hole opening, 135L: first contact hole opening, 135M: first contact hole opening, 135N: first contact hole opening, 136: insulating layer, 138: second contact hole opening, 138A: organic insulating film opening, 138B: second contact contact hole opening, 138C: second contact hole opening, 138E: second contact hole opening, 138F: second contact hole opening, 138G: second contact hole opening, 138H: second contact hole opening, 139: conductive layer, 140A: second wiring, 140B: second wiring, 140C: second wiring, 140D: second wiring, 140E: second wiring, 141: insulating layer, 143: anode electrode, 144: first layer, 145: second layer, 146: third layer, 147: contact hole opening, 148: functional layer, 149: common electrode,150: terminal section, 152: first inorganic insulating layer, 154: organic insulating layer, 156: second inorganic insulating layer, 158: cover film, 160: scan driver circuit, 165: sealing film, 170: array section, 180: pixel, 180A: pixel, 180B: pixel, 181: pixel circuit, 181A: pixel circuit, 181B: pixel circuit, 200: flexible printed circuit board, 321: image data signal line, 322: image data signal line, 323: image data signal line, 330: scan signal line, 331: scan signal line, 332: scan signal line, 333: scan Signal line, 341: connecting wiring, 342: connecting wiring, 612: gate electrode, 614: first electrode, 616: second electrode, 622: gate electrode, 624: first electrode, 626: second electrode, 632: gate electrode, 634: first electrode, 636: second electrode, 642: gate electrode, 644: first electrode, 646: second electrode, 652: gate electrode, 654: first electrode, 656: second electrode, 662: gate electrode, 664: first electrode, 666: second electrode, 682: first electrode, 684: second electrode, 692: first electrode, 694: second electrode,

Claims

1. a first transistor whose switching is controlled using a first control signal and electrically connected between an image data signal line to which a data voltage is supplied and a first node; a third transistor whose switching is controlled by a second control signal having a timing different from that of the first control signal, the third transistor being electrically connected between the first node and the second node; a second transistor having a gate electrode electrically connected to the second node, the second transistor being electrically connected between a power supply line to which a constant voltage is supplied and a third node; a fourth transistor whose switching is controlled using a third control signal having a timing different from that of the first control signal and the second control signal, the fourth transistor being electrically connected between a reference voltage power supply line to which a reference voltage is supplied and the second node; a fifth transistor whose switching is controlled using a fourth control signal having a timing different from that of the first control signal, the second control signal, and the third control signal, and which is electrically connected between an initialization voltage power supply line to which an initialization voltage is supplied and the third node; a sixth transistor whose switching is controlled using the second control signal, the sixth transistor having a first electrode and electrically connected to the third node; a light-emitting element electrically connected to the first electrode; a capacitance element electrically connected between the first node and the third node; Including, Display device.

2. a sixth control signal line; a sixth control signal that serves as both the first control signal and the third control signal is supplied to the sixth control signal line; The display device according to claim 1 .

3. a reference voltage signal line; the reference voltage signal line serves as both the reference voltage power supply line and the initialization voltage power supply line; The display device according to claim 1 .

4. a control circuit that outputs the first control signal, the second control signal, the third control signal, and the fourth control signal; The control circuit a control is performed such that a low-level voltage is supplied to the second control signal, the third transistor and the sixth transistor are turned off, a high-level voltage is supplied to the third control signal, the fourth transistor is turned on, the reference voltage is supplied to the second node, a high-level voltage is supplied to the fourth control signal, the fifth transistor is turned on, and the initialization voltage is supplied to the third node, and then a high-level voltage is supplied to the first control signal, the first transistor is turned on, and the data voltage is supplied to the first node; The display device according to claim 1 .

5. a control circuit that outputs the first control signal, the second control signal, the third control signal, and the fourth control signal; The control circuit a control is performed such that a low-level voltage is supplied to the second control signal, the third transistor and the sixth transistor are turned off, a high-level voltage is supplied to the sixth control signal, the first transistor is turned on, the data voltage is supplied to the first node, the fourth transistor is turned on, the reference voltage is supplied to the second node, and then a high-level voltage is supplied to the fourth control signal, the fifth transistor is turned on, and the initialization voltage is supplied to the third node; The display device according to claim 2 .

6. the first to sixth transistors are n-channel field effect transistors; The display device according to claim 1 .

7. a channel length of the second transistor is longer than a channel length of the first transistor, a channel length of the third transistor, a channel length of the fourth transistor, a channel length of the fifth transistor, and a channel length of the sixth transistor; The display device according to claim 1 .

8. a channel region of each of the first to sixth transistors includes an oxide semiconductor; The display device according to claim 1 .

9. a first conductive layer and a second conductive layer different from the first conductive layer; the initialization voltage power supply line and the reference voltage power supply line include the first conductive layer and the second conductive layer which are different from each other; In a plan view, the first conductive layer and the second conductive layer included in the initialization voltage power supply line overlap each other, and the first conductive layer and the second conductive layer included in the reference voltage power supply line overlap each other. The display device according to claim 1 .

10. In a plan view, the gate electrode overlaps with the capacitance element. The display device according to claim 1 .

Images