Photoelectric conversion device

Abstract

To provide a photoelectric conversion device capable of reducing the influence of noise caused by a global electronic shutter operation.SOLUTION: A solid-state imaging device includes a pixel array in which a plurality of pixels are arranged in a plurality of rows and a plurality of columns, and a scanning circuit that performs scanning for sequentially selecting a row from the plurality of rows in which the pixels output signals, wherein a first pixel arranged in a first region of the pixel array outputs a signal based on incident light, and a second pixel arranged in a second region of the pixel array does not output a signal based on incident light. A reset operation starts or ends in a period in which pixels in one row of the pixel array output signals, and the number of times of the reset operation performed in the second pixel is larger than the number of times of the reset operation performed in the first pixel in a period from the start of one scanning to the start of the next scanning.SELECTED DRAWING: Figure 6

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device. [Background technology]

[0002] Patent Document 1 discloses a photoelectric conversion device including a plurality of pixels. In the photoelectric conversion device of Patent Document 1, resetting of the photoelectric conversion units of the pixels and reading of charges from the photoelectric conversion units are performed simultaneously for a plurality of pixels. Such an operation of the photoelectric conversion device is called a global electronic shutter operation. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-177349 Summary of the Invention [Problem to be solved by the invention]

[0004] In a photoelectric conversion device in which a global electronic shutter operation is performed, a change in the potential of a control line that propagates a control signal for the global electronic shutter operation may propagate to other wiring or other elements via parasitic capacitance. Also, a transient fluctuation in the potential of a reference potential line that occurs with the global electronic shutter operation may propagate to other wiring or other elements. In this way, noise may occur due to the global electronic shutter operation. An object of the present invention is to provide a photoelectric conversion device that can reduce the influence of noise caused by the global electronic shutter operation. [Means for solving the problem]

[0005] According to one disclosure of the present specification, there is provided a pixel array in which a plurality of pixels are arranged in a plurality of rows and a plurality of columns, each pixel having a charge accumulation unit that accumulates charge, a drain transistor that performs a reset operation to drain the charge accumulated in the charge accumulation unit, a holding unit that holds the transferred charge, an amplifier unit that outputs a signal based on the transferred charge, a first transfer transistor that transfers charge from the charge accumulation unit to the holding unit, and a second transfer transistor that transfers the charge transferred by the first transfer transistor to the amplifier unit; and a scanning operation that sequentially selects rows from which the pixels output signals from the plurality of rows. a scanning circuit configured to output a signal based on incident light from a first pixel arranged in a first region of the pixel array, and a second pixel arranged in a second region of the pixel array not to output a signal based on incident light, wherein the reset operation by the discharge transistor starts or ends during a period in which pixels in one row of the pixel array output signals, and the number of times the reset operation is performed in the second pixel during a period from the start of one scan to the start of the next scan is greater than the number of times the reset operation is performed in the first pixel. [Effects of the Invention]

[0006] According to the present invention, a photoelectric conversion device capable of reducing the influence of noise caused by a global electronic shutter operation is provided. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a diagram illustrating a configuration of a photoelectric conversion device according to a first embodiment. [Figure 2] FIG. 2 is a diagram showing an equivalent circuit of a pixel according to the first embodiment. [Figure 3] FIG. 2 is a diagram showing an equivalent circuit of a column circuit according to the first embodiment. [Figure 4] FIG. 6 is a diagram showing drive timings of a photoelectric conversion device according to a comparative example of the first embodiment. [Figure 5] FIG. 2 is a diagram showing regions within a pixel array according to the first embodiment. [Figure 6]FIG. 3 is a diagram showing drive timings of the photoelectric conversion device according to the first embodiment. [Figure 7] FIG. 10 is a diagram showing a modified example of an equivalent circuit of the column circuit according to the first embodiment. [Figure 8] FIG. 2 is a diagram illustrating driving of pixels and holding of data in a memory according to the first embodiment. [Figure 9] FIG. 10 is a diagram showing an equivalent circuit of a pixel according to a second embodiment. [Figure 10] FIG. 10 is a diagram showing drive timings of a photoelectric conversion device according to a second embodiment. [Figure 11] FIG. 10 is a diagram showing a modified example of the drive timing of the photoelectric conversion device according to the second embodiment. [Figure 12] FIG. 10 is a diagram showing an equivalent circuit of a column circuit according to a second embodiment. [Figure 13] FIG. 10 is a diagram illustrating pixel driving and data storage in a memory according to the second embodiment. [Figure 14] 10A and 10B are diagrams illustrating a modified example of driving pixels and storing data in a memory according to the second embodiment. [Figure 15] 10A and 10B are diagrams illustrating a modified example of driving pixels and storing data in a memory according to the second embodiment. [Figure 16] FIG. 11 is a diagram showing an equivalent circuit of a column circuit according to a third embodiment. [Figure 17] FIG. 10 is a diagram showing drive timings of a photoelectric conversion device according to a fourth embodiment. [Figure 18] FIG. 10 is a diagram showing regions within a pixel array according to a fourth embodiment. [Figure 19] FIG. 10 is a diagram showing a procedure of signal processing according to the fourth embodiment. [Figure 20] FIG. 10 is a diagram showing a modified example of the procedure of signal processing according to the fourth embodiment. [Figure 21] FIG. 10 is a diagram showing a modified example of an area in a pixel array according to the fourth embodiment. [Figure 22] FIG. 10 is a diagram illustrating a photoelectric conversion device and a signal processing device according to a fifth embodiment. [Figure 23] FIG. 11 is a diagram showing a procedure of signal processing according to the fifth embodiment. [Figure 24]FIG. 13 is a block diagram of a device according to a sixth embodiment. [Figure 25] FIG. 13 is a block diagram of a device according to a seventh embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The same or corresponding elements in multiple drawings are designated by common reference numerals, and their description may be omitted or simplified.

[0009] In the first to fifth embodiments described below, an imaging device will be mainly described as an example of a photoelectric conversion device. However, the photoelectric conversion device in each embodiment is not limited to an imaging device, and can also be applied to other photodetection devices based on photoelectric conversion. Examples of other photodetection devices include a range finder and a photometer. The range finder may be, for example, a focus detection device or a distance measurement device using TOF (Time-Of-Flight). The photometer may be a device that measures the amount of light incident on the device.

[0010] In the following description, transistors are assumed to be N-type transistors unless otherwise specified. However, the transistors that can be used in the following embodiments are not limited to N-type transistors, and P-type transistors may also be used. In such cases, the potentials of the gate, source, and drain of the transistor may be changed as appropriate. For example, in a transistor operated as a switch, the level (low level or high level) of the potential supplied to the gate may be reversed compared to that described in the embodiments.

[0011] [First embodiment] 1 is a diagram showing the configuration of a photoelectric conversion device according to this embodiment. The photoelectric conversion device includes a pixel array 10, a timing generation unit 21, a vertical scanning circuit 22, a ramp signal output circuit 23, a counter circuit 24, a plurality of current sources 25, a plurality of column circuits 26, a horizontal scanning circuit 27, and a signal processing circuit 28. The timing generation unit 21 supplies control signals to the vertical scanning circuit 22, the ramp signal output circuit 23, the counter circuit 24, the plurality of column circuits 26, the horizontal scanning circuit 27, and the signal processing circuit 28.

[0012] As shown in Fig. 1, a pixel array 10 includes a plurality of pixels 11 arranged in a plurality of rows and a plurality of columns. For simplicity, Fig. 1 shows an example in which 16 pixels 11 are arranged in 4 rows and 4 columns, but in an actual photoelectric conversion device, tens of millions of pixels 11 may be arranged in the pixel array 10. The photoelectric conversion device in Fig. 1 is a so-called CMOS image sensor.

[0013] The photoelectric conversion device is provided with vertical output lines 31 corresponding to each column of the plurality of pixels 11. Each of the plurality of pixels 11 may include a photoelectric conversion unit that generates electric charges through photoelectric conversion. Signals output from the pixels 11 in each column are output to the corresponding vertical output line 31. A detailed configuration of the pixels 11 will be described later. A current source 25 is electrically connected to the corresponding vertical output line 31. The current source 25 supplies current to the vertical output line 31. Note that, although the vertical output line 31 is connected to the plurality of pixels 11 in one column in FIG. 1 , the connection between the vertical output line 31 and the pixels 11 is not limited to this. For example, instead of the vertical output line 31, an output line connected to the plurality of pixels 11 in one row may be provided.

[0014] The vertical scanning circuit 22 outputs control signals via control lines to control the pixels 11 for each row. The vertical scanning circuit 22 sequentially selects the pixels 11 in each row and performs scanning to cause the selected pixels 11 to output signals to vertical output lines 31.

[0015] The column circuits 26 are arranged corresponding to each column of pixels 11. Signals output from the pixels 11 of each column are input to the column circuits 26 of the corresponding column via the vertical output lines 31 of the corresponding column. The column circuits 26 amplify the signals output from the pixels 11 and perform analog-to-digital conversion (AD conversion).

[0016] The ramp signal output circuit 23 outputs a ramp signal VRAMP, which is used as a reference signal in AD conversion, to the column circuit 26. The ramp signal VRAMP is a signal whose voltage changes over time. In this embodiment, the ramp signal VRAMP has a constant slope (amount of voltage change per unit time), but the slope of the ramp signal VRAMP may change during the voltage change. A ramp signal VRAMP whose slope changes during the voltage change includes a ramp signal VRAMP whose voltage changes in a step-like manner. The ramp signal output circuit 23 may output multiple types of ramp signals VRAMP with different slopes. Note that the ramp signal VRAMP may be generated by the ramp signal output circuit 23 itself, or a circuit (not shown) different from the ramp signal output circuit 23 may generate the ramp signal VRAMP.

[0017] The counter circuit 24 outputs a count signal CNT used for AD conversion to the column circuit 26. The count signal CNT indicates the elapsed time from the point when the ramp signal VRAMP started to change with time. The count signal CNT is a signal obtained by counting clock pulse signals supplied from a clock pulse supply unit (not shown). Note that, although one counter circuit 24 is provided in common for the plurality of column circuits 26 in FIG. 1, a plurality of counter circuits 24 may be provided corresponding to each of the column circuits 26.

[0018] The horizontal scanning circuit 27 sequentially selects the plurality of column circuits 26. The column circuits 26 output signals after AD conversion to the signal processing circuit 28 via horizontal output lines 32. The signal processing circuit 28 processes the signals input from the column circuits 26 and outputs them to the outside of the photoelectric conversion device.

[0019] 2 is a diagram showing an equivalent circuit of a pixel 11 according to this embodiment. The pixel 11 has a photoelectric conversion unit PD, a holding unit CM1, a first transfer transistor M1, a second transfer transistor M2, a reset transistor M3, an amplification transistor M4, a selection transistor M5, and a discharge transistor M6. The first transfer transistor M1, the second transfer transistor M2, the reset transistor M3, the amplification transistor M4, the selection transistor M5, and the discharge transistor M6 may typically be MOS transistors.

[0020] The photoelectric conversion unit PD is a photoelectric conversion element that generates and accumulates electric charges based on incident light through photoelectric conversion. The photoelectric conversion unit PD is typically a photodiode. Another example of the photoelectric conversion unit PD is a photoelectric conversion film. In the following description, the photoelectric conversion unit PD is assumed to be a photodiode having an anode and a cathode.

[0021] The anode of the photoelectric conversion unit PD is connected to a ground line having a ground potential GND. The cathode of the photoelectric conversion unit PD is connected to the source of the first transfer transistor M1 and the source of the discharge transistor M6. The drain of the discharge transistor M6 is connected to a power supply line having a power supply potential VDD. The drain of the first transfer transistor M1 is connected to the source of the second transfer transistor M2 and the holding unit CM1. The holding unit CM1 has a capacitance that holds the charge transferred from the photoelectric conversion unit PD.

[0022] The drain of the second transfer transistor M2 is connected to the source of the reset transistor M3 and the gate of the amplification transistor M4. The connection node between the drain of the second transfer transistor M2, the source of the reset transistor M3, and the gate of the amplification transistor M4 is a floating diffusion FD. The floating diffusion FD has parasitic capacitance that is parasitic on the impurity diffusion layers, wiring, gate electrodes, etc. that make up these transistors, and the holding unit CM1 holds the charges transferred from the photoelectric conversion unit PD.

[0023] The drain of the reset transistor M3 and the drain of the amplification transistor M4 are connected to a power supply line having a power supply potential VDD. The source of the amplification transistor M4 is connected to the drain of the selection transistor M5. The drain of the selection transistor M5 is connected to the vertical output line 31.

[0024] A plurality of control lines are arranged in each row of the pixel array 10, extending in the row direction. A vertical scanning circuit 22 supplies control signals to the gates of a plurality of transistors in the pixels 11 via the plurality of control lines. A control signal TX1 is supplied to the gate of the first transfer transistor M1. A control signal TX2 is supplied to the gate of the second transfer transistor M2. A control signal RES is supplied to the gate of the reset transistor M3. A control signal SEL is supplied to the gate of the selection transistor M5. A control signal OFD is supplied to the gate of the discharge transistor M6.

[0025] When the first transfer transistor M1 is turned on by a control signal TX1, the charge generated and accumulated in the photoelectric conversion unit PD is transferred to the holding unit CM1. The holding unit CM1 holds the charge transferred from the photoelectric conversion unit PD. When the second transfer transistor M2 is turned on by a control signal TX2, the charge held in the holding unit CM1 is transferred to the floating diffusion FD. When the reset transistor M3 is turned on by a control signal RES, the potential of the floating diffusion FD is reset. When the selection transistor M5 is turned on by a control signal SEL, a signal is output from the amplification transistor M4 of the corresponding row to the vertical output line 31. At this time, the amplification transistor M4 and the current source 25 connected to the vertical output line 31 form a source follower circuit that outputs a signal corresponding to the charge transferred to the floating diffusion FD, thereby functioning as an amplifier. When the discharge transistor M6 is turned on by a control signal OFD, the charge accumulated in the photoelectric conversion unit PD is discharged, and the potential of the cathode of the photoelectric conversion unit PD is reset.

[0026] These configurations realize a configuration in which charges are generated in the photoelectric conversion unit PD while charges are held in the holding unit CM1 and accumulated in the photoelectric conversion unit PD. This allows the photoelectric conversion device to operate using a global electronic shutter method, which synchronizes the start and end times of charge accumulation in multiple photoelectric conversion units PD in the pixel array 10. Charge accumulation using the global electronic shutter method can be started, for example, by simultaneously controlling multiple discharge transistors M6 in the pixel array 10 from on to off to end charge discharge. Furthermore, charge accumulation using the global electronic shutter method can be ended, for example, by simultaneously controlling multiple first transfer transistors M1 in the pixel array 10 from off to on and then back to off to complete charge transfer.

[0027] 3 is a diagram showing an equivalent circuit of the column circuit 26 according to this embodiment. The column circuit 26 includes a column amplifier 261, a comparator 262, and memories N0 and S0. The column amplifier 261 includes an amplifier AMP, an input capacitance C0, feedback capacitances Cf1, Cf2, Cf3, and Cf4, and switches SW1, SW2, SW3, SW4, and SW5. Each of the switches SW1, SW2, SW3, SW4, and SW5 can be turned on or off by a control signal output from the timing generation unit 21.

[0028] The vertical output line 31 is connected to a first terminal of the input capacitor. A second terminal of the input capacitor is connected to an input terminal of the amplifier AMP, first terminals of the feedback capacitors Cf1, Cf2, Cf3, and Cf4, and a first terminal of the switch SW5. Second terminals of the feedback capacitors Cf1, Cf2, Cf3, and Cf4 are connected to first terminals of the switches SW1, SW2, SW3, and SW4, respectively. Second terminals of the switches SW1, SW2, SW3, SW4, and SW5 are connected to an output terminal of the amplifier AMP and a first input terminal of the comparator 262. A ramp signal VRAMP is input from the ramp signal output circuit 23 to a second input terminal of the comparator 262.

[0029] The output terminal of the comparator 262 is connected to first input terminals of memories N0 and S0. A count signal CNT is input from the counter circuit 24 to second input terminals of memories N0 and S0. The output terminals of memories N0 and S0 are connected to the signal processing circuit 28 via a horizontal output line 32. The horizontal output line 32 is composed of two wires, and the digital signals output from memories N0 and S0 are input to the signal processing circuit 28 via separate wires.

[0030] Signals output from the pixels 11 are input to the column amplifier 261 via the vertical output line 31. The column amplifier 261 is an amplifier circuit with variable gain. If the combined capacitance of enabled feedback capacitances Cf1, Cf2, Cf3, and Cf4 on the feedback path of the amplifier AMP is Cf, the gain of the column amplifier 261 is determined by C0 / Cf, which is the ratio of the capacitance value of the input capacitance C0 to the combined capacitance Cf. The combined capacitance Cf of the feedback capacitances is controlled by switches SW1, SW2, SW3, and SW4. The switch SW5 resets the column amplifier 261 to a predetermined state by shorting the input terminal and output terminal of the amplifier AMP. The gain of the column amplifier 261 may be either amplification or attenuation. For example, some of the multiple gains that can be set in the column amplifier 261 may be amplification and others may be attenuation. In this case, the column amplifier 261 may still be referred to as an amplification circuit.

[0031] The output signal of the column amplifier 261 is input to a first input terminal of the comparator 262, and the ramp signal VRAMP is input to a second input terminal of the comparator 262. The comparator 262 is a comparison circuit that compares the potential of the output signal of the column amplifier 261 with the potential of the ramp signal VRAMP and outputs a comparison result signal. More specifically, the comparator 262 outputs a low-level comparison result signal when the potential of the ramp signal VRAMP is lower than the potential of the output signal of the column amplifier 261. Furthermore, the comparator 262 outputs a high-level comparison result signal when the potential of the ramp signal VRAMP is equal to or higher than the potential of the output signal of the column amplifier 261. When it is higher, the comparator 262 outputs a high level. Note that the magnitude relationship between the input signals to the comparator 262 and the level of the comparison result signal described above is an example, and the relationship may be reversed.

[0032] The comparison result signal is input to first input terminals of memories N0 and S0. A count signal CNT indicating the elapsed time from the point in time when the ramp signal VRAMP began to change over time is input to second input terminals of memories N0 and S0. Memories N0 and S0 hold the count signal CNT supplied from the counter circuit 24 at the timing when the comparison result signal changes from low level to high level.

[0033] The memory N0 holds a digital signal (N signal) of the reset level of the floating diffusion FD. This digital signal also contains components of characteristic variations among the column circuits 26. The memory S0 holds a digital signal (S signal) of the level after the charge is transferred from the holding unit CM1 to the floating diffusion FD.

[0034] The digital signals held in memories N0 and S0 are output to signal processing circuit 28 via horizontal output line 32 in response to a control signal from horizontal scanning circuit 27. Signal processing circuit 28 performs correlated double sampling to subtract the digital signal held in memory N0 from the digital signal held in memory S0. This allows signal processing circuit 28 to generate a signal in which noise components generated when the floating diffusion FD is reset have been reduced.

[0035] 4 is a diagram showing the drive timing of a photoelectric conversion pixel according to a comparative example of this embodiment. Prior to describing the drive timing of the photoelectric conversion device of this embodiment, a comparative example of this embodiment will be described with reference to FIG.

[0036] FIG. 4 shows the timing of potential changes of the control signals OFD, TX1, SEL, RES, and TX2 during one frame period. Furthermore, "Row 1" to "Row N" in FIG. 4 show the timing of readout performed sequentially for each row of the pixel array 10. Each transistor is turned on during a period when the level of the signal shown in FIG. 4 is high, and turned off during a period when the level is low. For the control signals OFD and TX1, a common pulse is input to all pixels 11 in the pixel array 10. For the control signals SEL, RES, and TX2, the pulses shown in FIG. 4 are input sequentially for each row in the pixel array 10.

[0037] At time t1, the control signal OFD changes from low level to high level. This turns on the discharge transistor M6, discharging the charge in the photoelectric conversion unit PD and resetting the photoelectric conversion unit PD to a potential corresponding to the power supply potential VDD. In other words, time t1 is the start time of the reset operation. At time t2, the control signal OFD changes from high level to low level. This turns off the discharge transistor M6. In other words, time t1 is the end time of the reset operation. In this way, the period T1 from time t1 to time t2 is the period during which the reset operation of the photoelectric conversion unit PD is performed.

[0038] During a period T2 after time t2, charge accumulation in the photoelectric conversion unit PD due to incident light is performed. That is, time t2 is the start time of the charge accumulation operation, and period T2 is the charge accumulation period in the photoelectric conversion unit PD.

[0039] At time t3 in the next frame period, the control signal TX1 changes from low to high. This turns on the first transfer transistor M1, and the charges accumulated in the photoelectric conversion unit PD during period T2 are transferred to the holding unit CM1. That is, time t3 is the start time of the transfer operation. At time t1, the control signal TX1 changes from high to low. This turns off the first transfer transistor M1. That is, time t1 is the end time of the transfer operation. Time t1 is also the end time of charge accumulation in the photoelectric conversion unit PD. Thus, the period T3 from time t3 to time t1 is the period during which the transfer operation from the photoelectric conversion unit PD to the holding unit CM1 is performed. Furthermore, the period T2 from time t2 to time t1 in the next frame period is the charge accumulation period in the photoelectric conversion unit PD. Charges generated in the photoelectric conversion unit PD during periods after period T3 are discharged via the discharge transistor M6 and do not contribute to the output signal of the photoelectric conversion device.

[0040] 4, period T3 is set at the beginning of one frame period, but this is not limited to this. Period T3 may be set between before the completion of readout of each row and before the start of the next readout. For example, period T3 may be set at the end of one frame period.

[0041] As described above, the control signals OFD and TX1 collectively control the multiple pixels 11. Therefore, the start time of the charge accumulation period in the photoelectric conversion unit PD is simultaneous for each of the multiple pixels 11. Furthermore, the end time of the charge accumulation period in the photoelectric conversion unit PD is also simultaneous for each of the multiple pixels 11. In other words, the photoelectric conversion device of this embodiment can perform a global electronic shutter operation in which the charge accumulation periods of the multiple pixels 11 are consistent.

[0042] Next, the readout timing for each row of the pixel array 10 will be described. Figure 4 shows the details of period T4, which is the readout period for the Nth row. The operations for the 1st row to the (N-1)th row are the same as for the Nth row.

[0043] At time t4, the control signal SEL changes from low to high, turning on the selection transistor M5 of the pixel 11 in the row to be read out and outputting a signal from the amplification transistor M4 of the pixel 11 in the row to be read out to the vertical output line 31.

[0044] At time t4, the control signal RES changes from low to high, turning on the reset transistor M3 of the pixel 11 in the row being read, and resetting the potential of the floating diffusion FD to a potential corresponding to the power supply potential VDD.

[0045] Then, at time t5, the control signal RES changes from high to low. This turns off the reset transistor M3 of the pixel 11 in the row being read, and the floating diffusion FD is released from reset. Therefore, the period from time t4 to time t5 is the reset period of the floating diffusion FD. After the reset is released at time t5, a signal (noise signal) based on the potential of the reset level of the floating diffusion FD can be read out. This noise signal can be used in correlated double sampling processing.

[0046] At time t6, the control signal TX2 changes from low to high, turning on the second transfer transistor M2 of the pixel 11 in the row to be read, and transferring the charge held in the holding unit CM1 to the floating diffusion FD.

[0047] At time t7, the control signal TX2 changes from high to low. This turns off the second transfer transistor M2 of the pixel 11 in the row being read, and the charge transfer from the holding unit CM1 to the floating diffusion FD ends. After the charge transfer from time t6 to time t7 ends, a signal based on the potential of the floating diffusion FD after the charge transfer is read out.

[0048] At time t8, the control signal SEL changes from high to low, turning off the selection transistors M5 of the pixels 11 in the row to be read out and stopping the signal output from the amplification transistors M4 of the pixels 11 in the row to be read out to the vertical output line 31.

[0049] After time t8, signal processing such as AD conversion is performed in the column circuit 26, and the digital signals are stored in memories N0 and S0. Thereafter, horizontal transfer is performed to transfer the digital signals from the column circuit 26 to the signal processing circuit 28.

[0050] At the start of the reset operation at time t1, the control signal OFD changes from low to high in all pixels 11, turning on the drain transistor M6. The potential change during this operation can propagate to other wires or other transistors via parasitic capacitance between wires and between elements. At the end of the reset operation at time t2, the control signal OFD changes from high to low in all pixels 11, turning off the drain transistor M6. The potential change during these operations can propagate to other wires or other transistors via parasitic capacitance between wires and between elements. At times t1 and t2, these factors can cause transient fluctuations in, for example, the potential of the ground line, the potential of the power supply line, and the potential of the vertical output line 31.

[0051] The above-mentioned potential fluctuations cause, for example, fluctuations in the potentials of the drain, source, and back gate of the amplifier transistor M4. The potential fluctuations at each terminal of the amplifier transistor M4 are superimposed as noise on the output signal when the signal is output from the amplifier transistor M4 to the vertical output line 31. In this way, the potential fluctuations of the control signal for the global electronic shutter operation may become a source of noise in the output signal.

[0052] At least one of the start of the reset operation at time t1 and the end of the reset operation at time t2 may overlap with the period of signal readout from the pixels 11 of a certain row. In the example of FIG. 4, the start of the reset operation at time t1 overlaps with the readout of the first row, and the end of the reset operation at time t2 overlaps with the readout of the (M+1)th row. Therefore, when the first row and the (M+1)th row are readout, noise generated by the start and end of the reset operation may be superimposed on the output signal. If the signal output from the photoelectric conversion device is used to generate an image, horizontal stripes may appear in the generated image, degrading image quality. Because horizontal stripes are easily visible, it may be necessary to reduce such noise.

[0053] To solve this problem, it is possible to prevent the start of the reset operation at time t1 and the end of the reset operation at time t2 from overlapping with the readout period. However, applying this method may result in a decrease in the frame rate due to the readout operation including a waiting time to account for the reset operation. Furthermore, it may be necessary to ensure time for the transient fluctuations in the potential of the ground line, the power supply line, and the vertical output line 31 to converge, which may further decrease the frame rate.

[0054] Furthermore, the above-described technique places greater constraints on the setting of the period T2 during which the charge accumulation operation is performed in the photoelectric conversion unit PD. For example, the length of the period during which the charge accumulation operation is performed in the photoelectric conversion unit PD may become shorter. In this case, the continuity of the subject between multiple consecutive frames may decrease. For example, when the output signal of the photoelectric conversion device is used to generate a moving image, the movement of the subject in the moving image may become discontinuous, and the quality of the moving image may decrease.

[0055] As described above, the inventors have found that it can be an issue to suppress degradation in image quality during the reset operation for the global electronic shutter operation without increasing the constraints on the timing of periods T1 and T2. Below, an example of the configuration and operation of a photoelectric conversion device that can address the above issue will be described.

[0056] FIG. 5 is a diagram illustrating regions within a pixel array 10 according to this embodiment. The pixel array 10 has an effective pixel region R1 (first region) and an optical black (OB) pixel region R2 (second region). The effective pixel region R1 includes pixels 11 (effective pixels) that output signals based on incident light, as shown in FIG. 2. That is, the pixels 11 (first pixels) within the effective pixel region R1 include photoelectric conversion elements that generate charges in response to incident light. The OB pixel region R2 has a circuit configuration similar to that of the pixel 11 in FIG. 2, but the photoelectric conversion units PD are covered with a light-shielding film to prevent light from entering the photoelectric conversion units PD. As a result, the pixels 11 (OB pixels) within the OB pixel region R2 output signals that are not based on incident light. That is, the pixels 11 (second pixels) within the OB pixel region R2 include photoelectric conversion elements with the same device structure as those within the effective pixel region R1, but the photoelectric conversion elements are light-shielded. The output signals from the pixels 11 within the OB pixel region R2 can be used for noise correction.

[0057] The pixel array 10 may include a dummy pixel region in which dummy pixels that do not include photoelectric conversion units PD are arranged. In other words, dummy elements that do not include photoelectric conversion elements are arranged in the dummy pixel region. In the processing described below, the processing performed on the pixels 11 in the OB pixel region R2 can be replaced with processing performed on the dummy pixels.

[0058] The photoelectric conversion elements in the effective pixels have the function of generating and storing charges in response to incident light, while the light-shielded photoelectric conversion elements in the OB pixels and the dummy elements in the dummy pixels have the function of generating and storing charges generated by noise. That is, the photoelectric conversion elements in the effective pixels, the light-shielded photoelectric conversion elements in the OB pixels, and the dummy elements in the dummy pixels all function as charge storage units, and signals can be read out by an operation corresponding to period T4 in Figure 4.

[0059] In FIG. 4, the range from row 1 to row M is the OB pixel region R2, and the range from row (M+1) to row N is the effective pixel region R1. In this case, noise generated by the start and end of the reset operation significantly affects the output signal, especially if it overlaps with the readout of the effective pixel region R1. Therefore, for example, if the start timing of the reset operation at time t1 is set to the period between the readout of row 1 and the readout of row M, the impact of the start of the reset operation on the output signal is reduced. However, the end timing of the reset operation at time t2 must be set to any time between the readout of row 1 and the readout of row N to ensure the length of the charge accumulation period T2. In other words, the end of the reset operation at time t2 may have to overlap with the readout of the effective pixel region R1. In the example readout method of FIG. 4, the end of the reset operation at time t2 overlaps with the readout of row (M+1). Therefore, the output signal of the (M+1)th row may be affected by noise caused by the end of the reset operation, which may cause horizontal stripes to appear in the part of the output image corresponding to the (M+1)th row.

[0060] Fig. 6 is a drive timing diagram of the photoelectric conversion device according to this embodiment. The drive timing diagram of Fig. 6 differs from Fig. 4 in that a period TD, which is a reset period for the OB pixel region R2, is added. In the description of Fig. 6, the description of parts common to Fig. 4 will be omitted as appropriate.

[0061] 6, pulses during a period TD from time t9 to time t10 are input to the pixels 11 in the OB pixel region R2 in the first to Mth rows, but are not input to the pixels 11 in the other rows. A pulse during a period T1 from time t11 to time t2 is input in common to all pixels 11, as in the case of FIG.

[0062] At time t9, the control signal OFD supplied to the pixels 11 in the first to Mth rows changes from low to high. As a result, the discharge transistors M6 in the pixels 11 in the first to Mth rows are turned on, the charges in the photoelectric conversion units PD are discharged, and the photoelectric conversion units PD are reset to a potential corresponding to the power supply potential VDD. In other words, time t9 is the start time of the reset operation for the pixels 11 in the first to Mth rows.

[0063] At time t10, the control signal OFD supplied to the pixels 11 in the first to Mth rows changes from high to low. This causes the discharge transistors M6 in the pixels 11 in the first to Mth rows to be turned off. In other words, time t10 is the end time of the reset operation for the pixels 11 in the first to Mth rows. In this way, the period TD from time t9 to time t10 is the period during which the reset operation of the photoelectric conversion units PD of the pixels 11 in the first to Mth rows included in the OB pixel region R2 is performed.

[0064] Then, at time t11, the control signal OFD supplied to the pixels 11 in all rows changes from low to high. As a result, the discharge transistors M6 in the pixels 11 in all rows are turned on, the charges in the photoelectric conversion units PD are discharged, and the photoelectric conversion units PD are reset to a potential corresponding to the power supply potential VDD. In other words, time t11 is the start time of the reset operation for the pixels 11 in all rows.

[0065] At time t2, the control signal OFD supplied to the pixels 11 in all rows changes from high to low. This turns off the discharge transistors M6 in the pixels 11 in all rows. In other words, time t2 is the end time of the reset operation for the pixels 11 in all rows. Thus, the period T1 from time t11 to time t2 is a period during which the reset operation of the photoelectric conversion units PD of the pixels 11 in all rows is performed, similar to the period T1 in FIG. 4. The operation thereafter is the same as in FIG. 4.

[0066] Because charge accumulation begins at time t2, the reset operation during period TD is a dummy reset operation that does not contribute to the length of charge accumulation period T2. However, in the example of Figure 6, the start of the reset operation at time t9 overlaps with the readout of the first row, and the end of the reset operation at time t10 overlaps with the readout of the second row. Therefore, noise generated by the start of the reset operation is superimposed on the signal read from the OB pixels in the first row, and noise generated by the end of the reset operation is superimposed on the signal read from the OB pixels in the second row. Because noise generated by the end of the reset operation is also superimposed on the signal read from the valid pixels in the (M+1)th row, the signals in the second row and the (M+1)th row are superimposed with equivalent noise.

[0067] The photoelectric conversion device of this embodiment reads out and outputs a signal superimposed with noise generated by the end of the reset operation in period TD from the OB pixels in the second row. Because this signal contains noise components generated by the end of the reset operation, it can be used for correction processing of the output signal of the effective pixels in the (M+1)th row superimposed with noise generated by the end of the reset operation in period T1. This correction processing can reduce the influence of noise contained in the output signal of the effective pixels in the (M+1)th row.

[0068] As described above, in this embodiment, a reset operation is performed on the pixels 11 in rows 1 to M in the OB pixel region R2 during period TD, and signals on which noise generated by the reset operation is superimposed are read out from the OB pixel region R2 and output. Then, a reset operation is performed on the pixels 11 in all rows during period T1, and signals on which noise generated by the reset operation is superimposed are read out from the effective pixel region R1 and output. Therefore, during one frame period, a total of two reset operations are performed on the pixels 11 in rows 1 to M in the OB pixel region R2 during periods TD and T1, and one reset operation is performed on the pixels 11 in rows (M+1) to N in the effective pixel region R1 during period T1. In other words, during one frame period from the start of one scan to the start of the next scan, the reset operation is performed more times on the pixels 11 in rows 1 to M in the OB pixel region R2 than on the pixels 11 in rows (M+1) to N in the effective pixel region R1. This is because a dummy reset operation is added to generate a correction signal for the pixels 11 in the first to Mth rows of the OB pixel region R2.

[0069] 6, it becomes possible to output a signal for correcting noise caused by the reset operation for the global electronic shutter operation. Therefore, according to this embodiment, a photoelectric conversion device capable of reducing the influence of noise caused by the global electronic shutter operation is provided.

[0070] The above-described correction processing may be performed, for example, by the signal processing circuit 28. Specifically, for example, a line memory (not shown) provided in the photoelectric conversion device holds the digital signals of the second row read out during the period TD. Then, the signal processing circuit 28 performs arithmetic processing of the digital signals of the (M+1)th row based on the digital signals of the second row, thereby correcting the digital signals of the (M+1)th row. Note that this line memory may have a storage capacity for storing signals equal to the number of columns of the pixel array 10, for example.

[0071] Alternatively, this correction processing can be performed in, for example, a signal processing device external to the photoelectric conversion device. Specifically, for example, a memory arranged in the signal processing device external to the photoelectric conversion device holds the digital signals of the second row read out during the period TD. Then, the signal processing device performs arithmetic processing on the digital signals of the (M+1)th row based on the digital signals of the second row, thereby correcting the digital signals of the (M+1)th row.

[0072] 6 requires a readout period of at least one row to set the period TD, which may reduce the upper limit of the length of the charge accumulation period T2. However, if the readout period of the effective pixel region R1 and the end time of the reset operation in the period T1 do not overlap, i.e., if the end time of the reset operation in the period T1 is set within the readout period of the OB pixel region R2, the period TD is not necessary. Therefore, the method of this embodiment does not substantially affect the upper limit of the length of the charge accumulation period T2. In other words, the timing, length, etc. of the period TD can be set appropriately depending on the setting of the period T2.

[0073] FIG. 7 is a diagram showing a modified equivalent circuit of the column circuit 26 according to the present embodiment. This modified example is an example in which the column circuit 26 includes a memory that stores the digital signals of the second row read out during the period TD. The column circuit 26 further includes memories N1 and S1 in addition to the configuration shown in FIG. 3. First input terminals of the memories N1 and S1 are connected to the output terminal of the comparator 262. A count signal CNT is input from the counter circuit 24 to second input terminals of the memories N1 and S1. Output terminals of the memories N1 and S1 are connected to the signal processing circuit 28 via a horizontal output line 32. In this modified example, the horizontal output line 32 is composed of four wires.

[0074] 8(a) and 8(b) are diagrams illustrating pixel driving and data storage in memory according to this embodiment. FIG. 8(a) illustrates the levels of the control signals OFD and TX1 during the readout period of the OB pixel region R2, and the memory in which the S and N signals are stored. FIG. 8(b) illustrates the levels of the control signals OFD and TX1 during the readout period of the effective pixel region R1, and the memory in which the S and N signals are stored. Note that FIGS. 8(a) and 8(b) are based on the assumption that the column circuit 26 has the configuration shown in FIG. 7.

[0075] In FIG. 8(a), "1H" to "(M)H" indicate the period from the first row readout period to the Mth row readout period, respectively. In FIG. 8(b), "(M+1)H" to "(N)H" indicate the period from the (M+1)th row readout period to the Nth row readout period, respectively. In FIGS. 8(a) and 8(b), "L" indicates that the control signal is at a low level. In FIGS. 8(a) and 8(b), "L→H" indicates that the control signal transitions from a low level to a high level, and "H→L" indicates that the control signal transitions from a high level to a low level.

[0076] 8(a) and 8(b) correspond to the drive timing diagram of FIG. 6. As shown in FIG. 8(a), at the readout timing (1H) of the first row, the control signal OFD transitions from low to high, and the reset operation begins. At this time, the S signal is held in memory S0, and the N signal is held in memory N0. At the readout timing (2H) of the second row, the control signal OFD transitions from high to low, and the reset operation ends. At this time, the S signal is held in memory S1, and the N signal is held in memory N1. At the readout timing ((M-1)H) of the (M-1)th row, the control signal OFD transitions from low to high, and the reset operation begins. At this time, the S signal is held in memory S0, and the N signal is held in memory N0. As described above, the signals acquired from the OB pixel region R2 at the end of the reset operation are stored in memories N1 and S1 separate from signals acquired at other times, and are maintained without being overwritten until the time when the effective pixel region R1 is read later.

[0077] As shown in FIG. 8(b), at the readout timing ((M+1)H) of the (M+1)th row, the control signal OFD transitions from high to low, and the reset operation ends. At this time, the S signal is stored in memory S0, and the N signal is stored in memory N0. Then, the digital signal of the (M+1)th row stored in memories N0 and S0 and the digital signal of the second row stored in memories N1 and S1 are input to the signal processing circuit 28. The signal processing circuit 28 performs correction processing using these digital signals to reduce the effects of noise generated by the end of the reset operation.

[0078] Here, an example of the correction process performed in the signal processing circuit 28 will be described. The digital signals held in memories N0 and S0 are DN0 and DS0, respectively, and the digital signals held in memories N1 and S1 are DN1 and DS1, respectively. For digital signals of rows (other than the (M+1)th row) where the start or end of the reset operation overlaps with the readout of the effective pixel region R1, the correction process is performed using equation (1). Furthermore, for digital signals of rows (the (M+1)th row) where the start or end of the reset operation overlaps with the readout of the effective pixel region R1, the correction process is performed using equation (2). However, the equations used for the correction process are not limited to equations (1) and (2). DS0-DN0 (1) DS0-DN0-(DS1-DN1) (2)

[0079] The transfer of digital signals from memories N1 and S1 to the signal processing circuit 28 may be performed when reading out each row, or may be performed only when reading out a row that overlaps with the start or end of the reset operation when reading out the effective pixel area R1.

[0080] The memory capacities of the memories N0 and S0 may be different from those of the memories N1 and S1, and the column circuit 26 may be configured to include only one of the memories N1 and S1.

[0081] The digital signals do not have to be stored in the memories N1 and S1 every frame. For example, the operation of storing the digital signals in the memories N1 and S1 may be performed once every several frames. In this case, the signal processing circuit 28 may share the digital signals in the memories N1 and S1 during the processing of several frames.

[0082] The memory N1 and S1 may be configured to switch between a state where digital signals are stored and a state where they are not stored. This switching may be performed based on settings of the imaging device in which the photoelectric conversion device is installed, such as the imaging target and the camera's gain setting. For example, the noise caused by the reset operation is likely to appear as horizontal stripes in situations where the noise level due to factors other than the reset operation is low, such as when photographing in a dark place or when photographing a low-luminance imaging target. Therefore, for example, when the imaging target is brighter than a predetermined value, the memory N1 and S1 may be configured not to store digital signals. Also, for example, when the camera's gain setting is higher than a predetermined value, the memory N1 and S1 may be configured not to store digital signals. Furthermore, whether or not digital signals are stored in the memory N1 and S1 may be configured based on settings other than these.

[0083] One pixel 11 may be composed of multiple sub-pixels. Output signals from each of the multiple sub-pixels may be used for phase-difference focus detection. In this case, memories N1 and S1 may be arranged to hold the output signal of each of the multiple sub-pixels, or memories N1 and S1 may be arranged to hold the output signal of any of the multiple sub-pixels. Alternatively, memories N1 and S1 may be arranged to hold the sum of the signal outputs of the multiple sub-pixels.

[0084] In this embodiment, signals are read out from the plurality of pixels 11 one row at a time, but the number of rows that are simultaneously read out is not limited to one. For example, a plurality of vertical output lines 31 are arranged for one column of pixels 11. Then, while a signal is being output from the pixels 11 in one row to one of the plurality of vertical output lines 31, a signal is being output from the pixels 11 in another row to another of the plurality of vertical output lines 31, thereby making it possible to simultaneously output signals from the pixels 11 in a plurality of rows.

[0085] The photoelectric conversion device of this embodiment includes the pixel array 10 and circuits for processing signals output from the pixel array 10, such as the current source 25 and the column circuit 26, which may be arranged on a single substrate or on multiple substrates. For example, a first substrate on which the pixel array 10 is arranged may be stacked with one or multiple second substrates on which circuits related to signal processing, including the current source 25, the column circuit 26, etc., are arranged. In this case, the current source 25, the column circuit 26, etc. may be arranged for each column of multiple pixels 11, as shown in FIG. 1, or may be arranged corresponding to multiple pixels 11 arranged in a portion of the pixel array 10.

[0086] FIG. 2 illustrates a configuration in which the pixel 11 includes the selection transistor M5, but this is not limiting. As another example, the pixel 11 may not include the selection transistor M5. In this case, the vertical output line 31 is connected to the source of the amplification transistor M4. The row for outputting a signal can be selected by changing the potential supplied to the drain of the reset transistor M3. That is, a potential (off potential) that turns off the amplification transistor M4 is applied to the drain of the reset transistor M3 in a row that does not output a signal. Then, the reset transistor M3 is turned on by control from the vertical scanning circuit 22, and an off potential is applied to the floating diffusion FD. As a result, the amplification transistor M4, whose gate is applied with an off potential, is turned off. Meanwhile, a potential (on potential) that turns on the amplification transistor M4 is applied to the drain of the reset transistor M3 in a row that outputs a signal. Then, the reset transistor M3 is turned on by control from the vertical scanning circuit 22, and an on potential is applied to the floating diffusion FD. As a result, the amplification transistor M4, whose gate is given an ON potential, is turned ON, and a signal can be output to the vertical output line 31.

[0087] In this embodiment, the photoelectric conversion unit PD is reset by the power supply potential VDD, but this is not limiting, and the photoelectric conversion unit PD may be reset by another potential.

[0088] Furthermore, the holding unit CM1 and the floating diffusion FD only need to have a capacitance for holding the transferred charge. That is, the structures of the capacitive elements constituting the holding unit CM1 and the floating diffusion FD are not particularly limited. The holding unit CM1 and the floating diffusion FD may include, for example, a structure utilizing the junction capacitance of a P-type semiconductor region and an N-type semiconductor region, or may include an MIM structure in which a dielectric is sandwiched between metals.

[0089] [Second embodiment] In this embodiment, a modification in which a holding unit and a transfer transistor are added to a pixel in comparison with the first embodiment will be described. In this embodiment, the description of elements common to the first embodiment may be omitted or simplified.

[0090] FIG. 9 is a diagram showing an equivalent circuit of a pixel 11 according to this embodiment. The pixel 11 according to this embodiment further includes a third transfer transistor M7 and a holding unit CM2 in addition to the configuration of the pixel 11 according to the first embodiment shown in FIG. 2. The source of the third transfer transistor M7 is connected to the connection node between the drain of the first transfer transistor M7 and the holding unit CM1. The drain of the third transfer transistor M7 is connected to the source of the second transfer transistor M7 and the holding unit CM2. A control signal TX3 is supplied to the gate of the third transfer transistor M7. When the third transfer transistor M7 is turned on by the control signal TX3, the charge held in the holding unit CM1 is transferred to the holding unit CM2. The holding unit CM2 has a capacitance that holds the charge transferred from the holding unit CM1. When the second transfer transistor M2 is turned on by the control signal TX2, the charge held in the holding unit CM2 is transferred to the floating diffusion FD.

[0091] The configuration of other parts in the pixel 11 is the same as in Fig. 2, and therefore description thereof will be omitted. Also, the overall configuration of the photoelectric conversion device, the configuration of the column circuit 26, the arrangement of the pixel region, and the like are assumed to be the same as in the first embodiment, and description thereof will be omitted.

[0092] Fig. 10 is a drive timing diagram of the photoelectric conversion device according to this embodiment. Fig. 10 shows the timing of potential changes of the control signals OFD, TX1, and TX3 during one frame period, and the timing of readout of each row. The timing of the control signals SEL, RES, and TX2 during readout of each row is the same as that of period T4 in Fig. 4 or 6, and is therefore omitted from Fig. 10.

[0093] At time t11, the control signal OFD changes from low level to high level. This turns on the discharge transistor M6, discharging the charge in the photoelectric conversion unit PD and resetting the photoelectric conversion unit PD to a potential corresponding to the power supply potential VDD. In other words, time t11 is the start time of the reset operation. At time t2, the control signal OFD changes from high level to low level. This turns off the discharge transistor M6. In other words, time t2 is the end time of the reset operation. In this way, the period T1 from time t11 to time t2 is the period during which the reset operation of the photoelectric conversion unit PD is performed.

[0094] During a period T2 after time t2, charge accumulation in the photoelectric conversion unit PD due to incident light is performed. That is, time t2 is the start time of the charge accumulation operation, and period T2 is the charge accumulation operation period in the photoelectric conversion unit PD.

[0095] Thereafter, at time t14, the control signal TX1 changes from low level to high level. This turns on the first transfer transistor M1, and the charges accumulated in the photoelectric conversion unit PD during the period from time t2 to time t14 are transferred to the holding unit CM1. In other words, time t14 is the start time of the transfer operation. At time t15, the control signal TX1 changes from high level to low level. This turns off the first transfer transistor M1. In other words, time t15 is the end time of the transfer operation. In this way, the period T31 from time t14 to time t15 is the period during which the transfer operation from the photoelectric conversion unit PD to the holding unit CM1 is performed.

[0096] Thereafter, in periods T32, T33, and T34, as in period T31, the first transfer transistor M1 transfers the charges accumulated in the photoelectric conversion unit PD to the holding unit CM1. In this manner, in this embodiment, charge transfer from the photoelectric conversion unit PD to the holding unit CM1 is performed multiple times. Time t16, when the fourth charge transfer ends, is the end time of period T2. Charges generated in the photoelectric conversion unit PD during periods after period T2 are discharged via the discharge transistor M6 and do not contribute to the output signal of the photoelectric conversion device.

[0097] The driving method in which charge transfer is performed multiple times, as shown in FIG. 10, is effective in reducing the effects of saturation when, for example, there is a difference between the maximum charge amount (first saturation charge amount) that the photoelectric conversion unit PD can accumulate and the maximum charge amount (second saturation charge amount) that the holding unit CM1 can accumulate. For example, a case in which the second saturation charge amount is greater than the first saturation charge amount will be described. If the photoelectric conversion unit PD reaches the first saturation charge amount before the start of transfer at a predetermined time within period T2, the photoelectric conversion unit PD can no longer accumulate charge. Therefore, by transferring the charge accumulated in the photoelectric conversion unit PD to the holding unit CM1 during period T31 in period T2, the photoelectric conversion unit PD returns to its initial state in which all charge has been discharged. Therefore, even if the first saturation charge amount of the photoelectric conversion unit PD is small, as long as the second saturation charge amount of the holding unit CM1 is sufficiently large, a sufficient amount of saturation charge of the pixel 11 that can be detected in one frame period can be ensured. By designing the photoelectric conversion unit PD and the holding unit CM1 taking into consideration the amount of charge that can be accumulated per unit area of ​​the photoelectric conversion unit PD and the holding unit CM1 and the pixel pitch, the saturated charge amount of pixel 11 and the area of ​​the photoelectric conversion unit PD and the holding unit CM1 can be further optimized.

[0098] After period T34, at time t3 of the next frame period, the control signal TX3 changes from low level to high level. This turns on the third transfer transistor M7, and the charges generated in the photoelectric conversion unit PD and transferred to the holding unit CM1 during period T2 of the previous frame period are transferred to the holding unit CM2. In other words, time t3 is the start time of the transfer operation. At time t9, the control signal TX3 changes from high level to low level. This turns off the third transfer transistor M7. In other words, time t9 is the end time of the transfer operation. Period T5, from time t3 to time t9, is the period during which the transfer operation from the holding unit CM1 to the holding unit CM2 is performed.

[0099] 10, period T5 is set at the beginning of one frame period, but this is not limited thereto. Period T5 may be set between before the completion of readout of each row and before the start of the next readout. For example, period T5 may be set at the end of one frame period.

[0100] The control signals OFD, TX1, and TX3 collectively control the multiple pixels 11. Therefore, the start time of the charge accumulation period in the photoelectric conversion unit PD is simultaneous for the multiple pixels 11. Furthermore, the end time of the charge accumulation period in the photoelectric conversion unit PD is also simultaneous for the multiple pixels 11. In other words, the photoelectric conversion device of this embodiment can perform a global electronic shutter operation in which the charge accumulation periods of the multiple pixels 11 are consistent.

[0101] 6 of the first embodiment, the range from row 1 to row M is the OB pixel region R2, and the range from row (M+1) to row N is the effective pixel region R1. As in the example of FIG. 6 of the first embodiment, in this embodiment too, a dummy reset operation is performed on pixels 11 in the OB pixel region R2 during period TD between time t9 and time t10.

[0102] At time t9, the control signal OFD supplied to the pixels 11 in the first to Mth rows changes from low to high. As a result, the discharge transistors M6 in the pixels 11 in the first to Mth rows are turned on, the charges in the photoelectric conversion units PD are discharged, and the photoelectric conversion units PD are reset to a potential corresponding to the power supply potential VDD. In other words, time t9 is the start time of the reset operation for the pixels 11 in the first to Mth rows.

[0103] At time t10, the control signal OFD supplied to the pixels 11 in the first to Mth rows changes from high to low. This causes the discharge transistors M6 in the pixels 11 in the first to Mth rows to be turned off. In other words, time t10 is the end time of the reset operation for the pixels 11 in the first to Mth rows. In this way, the period TD from time t9 to time t10 is the period during which the reset operation of the photoelectric conversion units PD of the pixels 11 in the first to Mth rows included in the OB pixel region R2 is performed.

[0104] As a result, the photoelectric conversion device of this embodiment, like the photoelectric conversion device of the first embodiment, can read out and output signals superimposed with noise generated by the end of the reset operation during the period TD from the OB pixels in the second row. By performing correction processing using this signal, like the first embodiment, the influence of noise generated by the end of the reset operation and included in the output signals of the effective pixels in the (M+1)th row can be reduced.

[0105] In the driving method of FIG. 10 , the start or end of the transfer operation from period T31 to period T34 may overlap with the readout period of signals from the pixels 11 of a certain row. In FIG. 10 , for example, the start of the transfer operation at time t14 overlaps with the readout of row (M+A). This can cause noise generated by the start of the transfer operation to be superimposed on the output signal when row (M+A) is readout, due to factors similar to those associated with the start or end of the reset operation. The output signal of row (M+A) can be affected by noise resulting from the start of the transfer operation, resulting in horizontal stripes appearing in the portion of the output image corresponding to row (M+A). Similarly, noise generated by the start of the transfer operation during periods T32, T33, and T34 can affect the output signals of rows (M+B), (M+C), and (M+D). The end of the transfer operation can also be a source of noise. For example, when reading out one row between the (M+A)th row and the (M+B)th row (e.g., the (M+A+1)th row), noise caused by the end of the transfer operation at time t15 may be superimposed on the output signal.

[0106] As described above, in this embodiment, in addition to the reset operation, the transfer operation can also be a cause of noise. The noise caused by the transfer operation can be corrected using the same method as for correcting the noise caused by the reset operation. Therefore, in this embodiment, a dummy transfer operation is performed on the pixel 11 in the OB pixel region R2 during the period TG from time t12 to time t13.

[0107] At time t12, the control signal TX1 supplied to the pixels 11 in the first to Mth rows changes from low to high. As a result, the first transfer transistors M1 in the pixels 11 in the first to Mth rows are turned on, and the charges in the photoelectric conversion units PD are transferred to the holding units CM1. In other words, time t12 is the start time of the transfer operation for the pixels 11 in the first to Mth rows.

[0108] At time t13, the control signal TX1 supplied to the pixels 11 in the first to Mth rows changes from high to low. This causes the first transfer transistors M1 in the pixels 11 in the first to Mth rows to be turned off. In other words, time t13 is the end time of the transfer operation for the pixels 11 in the first to Mth rows. In this way, the period TG from time t12 to time t13 is the period during which the transfer operation of the photoelectric conversion units PD of the pixels 11 in the first to Mth rows included in the OB pixel region R2 is performed.

[0109] Because charge accumulation begins at time t2 and ends at time t16, the transfer operation during period TG is a dummy transfer operation that does not contribute to the length of charge accumulation period T2. However, in the example of FIG. 10, the start of the transfer operation at time t12 overlaps with the readout of row 3. Therefore, noise generated by the start of the transfer operation is superimposed on the signals read out from the OB pixels in row 3. Furthermore, noise generated by the start of the reset operation is also superimposed on the signals read out from the valid pixels in rows (M+A), (M+B), (M+C), and (M+D). Therefore, the same amount of noise is superimposed on the signals in row 3 and the signals in rows (M+A), (M+B), (M+C), and (M+D).

[0110] In the photoelectric conversion device of this embodiment, a signal superimposed with noise caused by the start of the transfer operation during period TG is read from the OB pixels in the third row and output. This signal contains noise components caused by the start of the transfer operation. Therefore, this signal can be used for correction processing of output signals from effective pixels in rows (M+A), (M+B), (M+C), and (M+D) on which noise caused by the start of the transfer operation during periods T31, T32, T33, and T34 is superimposed. This correction processing can reduce the influence of noise contained in the output signals from effective pixels in rows (M+A), (M+B), (M+C), and (M+D).

[0111] In this way, the photoelectric conversion device of this embodiment performs a transfer operation on the pixels 11 in the first to Mth rows of the OB pixel region R2 during the period TG, reads out and outputs signals superimposed with noise generated by the transfer operation from the OB pixel region R2, and then performs a transfer operation on the pixels 11 in all rows during periods T31, T32, T33, and T34, reads out and outputs signals superimposed with noise generated by the transfer operation from the effective pixel region R1.

[0112] This makes it possible to output a signal for correcting noise caused by the transfer operation for the global electronic shutter operation. Therefore, according to this embodiment, a photoelectric conversion device capable of reducing the influence of noise caused by the global electronic shutter operation is provided.

[0113] The above-described correction processing may be performed, for example, in the signal processing circuit 28. Specifically, for example, a line memory (not shown) provided in the photoelectric conversion device holds the digital signal of the third row read out during the period TG. Then, the signal processing circuit 28 performs arithmetic processing of the digital signals of the (M+A)th, (M+B)th, (M+C)th, and (M+D)th rows based on the digital signal of the third row, thereby correcting the digital signals of these rows. Note that this line memory may have a storage capacity for storing signals equal to the number of columns of the pixel array 10, for example.

[0114] Alternatively, this correction processing can be performed in, for example, a signal processing device external to the photoelectric conversion device. Specifically, for example, a memory in the signal processing device external to the photoelectric conversion device holds the digital signals of the third row read out during the period TG. Then, the signal processing device performs arithmetic processing of the digital signals of the (M+A)th, (M+B)th, (M+C)th, and (M+D)th rows based on the digital signals of the third row, thereby correcting the digital signals of these rows.

[0115] 11 is a diagram showing a modified example of the drive timing of the photoelectric conversion device according to this embodiment. The difference between FIG. 11 and FIG. 10 is that periods T21, T22, T23, and T24, during which the reset operation of the photoelectric conversion unit PD is performed, have been added. Period T21 occurs before period T31, period T22 occurs between periods T31 and T32, period T23 occurs between periods T32 and T33, and period T24 occurs between periods T33 and T34. That is, in this modified example, the reset operation of the photoelectric conversion unit PD and the transfer operation from the photoelectric conversion unit PD to the holding unit CM1 are alternately repeated during drive.

[0116] The amount of light incident on the photoelectric conversion device may change periodically or over time, such as when the subject is a blinking object or when flash photography is performed. In the driving methods shown in FIGS. 4, 6, and 10, the photoelectric conversion unit PD is in a reset state during period T1, and charge accumulation is not performed. Therefore, if the amount of light changes during period T1, appropriate signal acquisition may not be possible. In response to this, the effect of temporal changes in the amount of light can be reduced by setting a driving method in which the reset operation and transfer operation are alternately repeated multiple times within a predetermined time range within one frame period, as shown in FIG. 11, or by allocating the reset operation and transfer operation evenly within one frame period. Furthermore, by appropriately adjusting the number of times or the interval between repetitions of the reset operation and transfer operation, the photoelectric conversion device can be controlled so that the photoelectric conversion unit PD and the holding unit CM1 do not saturate, even when the subject is highly bright.

[0117] In the driving method of FIG. 11, the start or end of the reset operation from period T21 to period T24 may overlap with the period of signal readout from the pixels 11 of a certain row. In FIG. 11, for example, the end of the reset operation in period T22 and the start of the transfer operation in period T32 overlap with the readout of the (M+B)th row. This may cause the output signal of the (M+B)th row to be affected by noise resulting from the end of the reset operation and the start of the transfer operation. In this modification, since noise resulting from the end of the reset operation and the start of the transfer operation is superimposed during the readout of the second row, the influence of the noise can be reduced by performing a correction process using the signals readout from the OB pixels of the second row.

[0118] 12 is a diagram showing an equivalent circuit of the column circuit 26 according to this embodiment. The column circuit 26 further includes memories N2 and S2 in addition to the configuration shown in FIG. 7. First input terminals of the memories N2 and S2 are connected to the output terminal of the comparator 262. A count signal CNT is input from the counter circuit 24 to second input terminals of the memories N2 and S2. Output terminals of the memories N2 and S2 are connected to the signal processing circuit 28 via a horizontal output line 32. In this modification, the horizontal output line 32 is composed of six wires.

[0119] Memories N1 and S1 store digital signals read out during a period TD, for example. Memories N2 and S2 store digital signals read out during a period TG, for example. Memories N0 and S0 store digital signals read out at times other than the periods TD and TG, for example. However, the allocation of signals stored in each memory is not limited to the above example and can be changed as appropriate depending on the driving method to be applied, etc.

[0120] 13(a) and 13(b) are diagrams showing pixel driving and data storage in memory according to this embodiment. The notation in FIGS. 13(a) and 13(b) is the same as that in FIGS. 8(a) and 8(b). In FIGS. 13(a) and 13(b), it is assumed that the column circuit 26 has the configuration shown in FIG. 12. Note that the examples shown in FIGS. 13(a) and 13(b) do not correspond to the driving methods in FIGS. 10 and 11.

[0121] As shown in FIG. 13(a), at the readout timing (1H) of the first row, the control signal OFD transitions from low to high, starting the reset operation. At this time, the S signal is stored in memory S0, and the N signal is stored in memory N0. At the readout timing (2H) of the second row, the control signal OFD transitions from high to low, ending the reset operation. At this time, the S signal is stored in memory S1, and the N signal is stored in memory N1. At the readout timing (3H) of the third row, the control signal TX1 transitions from low to high, starting the transfer operation. At this time, the S signal is stored in memory S0, and the N signal is stored in memory N0. At the readout timing (4H) of the fourth row, the control signal TX1 transitions from high to low, ending the transfer operation. At this time, the S signal is stored in memory S2, and the N signal is stored in memory N2. As described above, the signals acquired from the OB pixel region R2 at the end of the reset operation are stored in memories N1 and S1, and the signals acquired from the OB pixel region R2 at the end of the transfer operation are stored in memories N2 and S2. The signals stored in memories N1, S1, N2, and S2 are maintained without being overwritten until the next readout from the effective pixel region R1.

[0122] As shown in FIG. 13(b), at the readout timing ((M+2)H) of the (M+2)th row, the control signal OFD transitions from high to low, and the reset operation ends. At this time, the S signal is stored in memory S0, and the N signal is stored in memory N0. At this time, the digital signal of the (M+2)th row stored in memories N0 and S0 and the digital signal of the second row stored in memories N1 and S1 are input to the signal processing circuit 28. The signal processing circuit 28 performs correction processing using these digital signals to reduce the effects of noise generated by the end of the reset operation.

[0123] 13(b), at the readout timing ((N-2)H) of the (N-2)th row, the control signal TX1 transitions from high to low, and the transfer operation ends. At this time, the S signal is stored in memory S0, and the N signal is stored in memory N0. The digital signal of the (N-2)th row stored in memories N0 and S0 and the digital signal of the 4th row stored in memories N2 and S2 are input to the signal processing circuit 28. The signal processing circuit 28 performs correction processing using these digital signals to reduce the effects of noise generated by the end of the transfer operation.

[0124] 13(a) and 13(b) show examples of reducing the influence of noise at the end of the reset operation and the transfer operation, but the driving method may be modified to reduce the influence of noise at the start of the reset operation and the transfer operation. Also, it may be possible to select for each frame whether to reduce noise at the start or end of the reset operation and the transfer operation.

[0125] 14(a) and 14(b) are diagrams showing modified examples of pixel driving and data storage in memory according to this embodiment. Because FIGS. 14(a) and 14(b) are modified examples of FIGS. 13(a) and 13(b), the following description will focus on the differences from FIGS. 13(a) and 13(b). The examples shown in FIGS. 14(a) and 14(b) do not correspond to the driving methods of FIGS. 10 and 11.

[0126] As shown in FIG. 14(a), at the readout timing (2H) of the second row, the control signal OFD transitions from high to low, ending the reset operation. Also, at the readout timing (2H) of the second row, the control signal TX1 transitions from low to high, starting the transfer operation. At this time, the S signal is stored in memory S1, and the N signal is stored in memory N1. At the readout timing (3H) of the third row, the control signal TX1 transitions from high to low, ending the transfer operation. At this time, the S signal is stored in memory S2, and the N signal is stored in memory N2. As described above, the signals acquired from the OB pixel region R2 at the end of the reset operation and the start of the transfer operation are stored in memories S1 and N1, and the signals acquired from the OB pixel region R2 at the end of the transfer operation are stored in memories N2 and S2.

[0127] As shown in FIG. 14(b), at the readout timing ((M+3)H) of the (M+3)th row, the control signal OFD transitions from high to low, ending the reset operation. Also, at the readout timing ((M+3)H) of the (M+3)th row, the control signal TX1 transitions from low to high, starting the transfer operation. At this time, the S signal is stored in memory S0, and the N signal is stored in memory N0. The digital signals of the (M+3)th row stored in memories N0 and S0 and the digital signals of the second row stored in memories N1 and S1 are input to the signal processing circuit 28. The signal processing circuit 28 performs correction processing using these digital signals to reduce the effects of noise generated by the end of the reset operation and the start of the transfer operation. Thus, noise may be generated due to both the reset operation and the transfer operation. This modification allows for correction of such noise.

[0128] 14(b), at the readout timing ((N-2)H) of the (N-2)th row, the control signal TX1 transitions from high to low, and the transfer operation ends. At this time, the S signal is stored in memory S0, and the N signal is stored in memory N0. Then, the digital signal of the (N-2)th row stored in memories N0 and S0 and the digital signal of the third row stored in memories N2 and S2 are input to the signal processing circuit 28. The signal processing circuit 28 performs correction processing using these digital signals to reduce the effects of noise generated by the end of the transfer operation.

[0129] 15(a) and 15(b) are diagrams showing modified examples of pixel driving and data storage in memory according to this embodiment. Because FIGS. 15(a) and 15(b) are modified examples of FIGS. 13(a) and 13(b) or FIGS. 14(a) and 14(b), the following description will focus on the differences from FIGS. 13(a) and 13(b) or FIGS. 14(a) and 14(b). The examples shown in FIGS. 15(a) and 15(b) do not correspond to the driving methods of FIGS. 10 and 11.

[0130] As shown in FIG. 15(a), at the readout timing (2H) of the second row, the control signal OFD transitions from high to low, ending the reset operation. At this time, the S signal is stored in memory S1, and the N signal is stored in memory N1. At the readout timing (3H) of the third row, the control signal TX1 transitions from low to high, and then from high to low, starting and ending the transfer operation. At this time, the S signal is stored in memory S2, and the N signal is stored in memory N2. As described above, the signal acquired from the OB pixel region R2 at the end of the reset operation is stored in memories N1 and S1, and the signals acquired from the OB pixel region R2 at the start and end of the transfer operation are stored in memories N2 and S2.

[0131] As shown in FIG. 15(b), at the readout timing ((M+2)H) of the (M+2)th row, the control signal OFD transitions from high to low, and the reset operation ends. At this time, the S signal is stored in memory S0, and the N signal is stored in memory N0. Then, the digital signal of the (M+2)th row stored in memories N0 and S0 and the digital signal of the second row stored in memories N1 and S1 are input to the signal processing circuit 28. The signal processing circuit 28 performs correction processing using these digital signals to reduce the effects of noise generated by the end of the reset operation.

[0132] 15(b), at the readout timing ((N-3)H) of the (N-3)th row, the control signal TX1 transitions from low to high and then from high to low, thereby starting and ending the transfer operation. At this time, the S signal is stored in memory S0, and the N signal is stored in memory N0. The digital signals of the (N-3)th row stored in memories N0 and S0 and the digital signals of the third row stored in memories N2 and S2 are input to the signal processing circuit 28. The signal processing circuit 28 performs correction processing using these digital signals to reduce the effects of noise caused by the start and end of the transfer operation. In this way, noise may occur due to both the start and end of the transfer operation within one readout period, and this modification can correct such noise. Furthermore, noise may also occur due to both the start and end of the reset operation within one readout period. In such cases, such noise can be corrected using a driving method similar to that of this modification.

[0133] [Third embodiment] In this embodiment, a modification of the first embodiment will be described in which multiple column circuits share memories N1 and S1. In this embodiment, descriptions of elements common to the first embodiment may be omitted or simplified.

[0134] FIG. 16 is a diagram showing an equivalent circuit of the column circuit 26 according to this embodiment. FIG. 16 illustrates column circuits 26-1 and 26-2. Signals are input to the column circuits 26-1 and 26-2 via two adjacent vertical output lines 31-1 and 31-2. The column circuit 26-1 includes a column amplifier 261-1, a comparator 262-1, and memories N0, S0, N1, and S1. The column circuit 26-2 includes a column amplifier 261-2, a comparator 262-2, and memories N0 and S0. The column circuit 26-1 has a circuit configuration similar to that of the column circuit 26 in FIG. 7. The memories N1 and S1 of the column circuit 26-1 are also shared by the column circuit 26-2. That is, the column circuit 26-2 has a circuit configuration in which the memories N1 and S1 are omitted from the column circuit 26 in FIG. 7.

[0135] As described above, in this embodiment, the area occupied by the column circuits can be reduced compared to when memories N1 and S1 are arranged in the column circuits of each column. Furthermore, since the number of memories arranged can be reduced, the power required for memory operations such as data transfer can be reduced. Therefore, according to this embodiment, in addition to obtaining the same effects as the first embodiment, a photoelectric conversion device is provided that can achieve a reduction in element area or power consumption.

[0136] Signals may be transferred from the memories N0, S0, N1, and S1 of the column circuit 26-1 and the memories N0 and S0 of the column circuit 26-2 to the signal processing circuit 28, for example, as follows: When the memories N0 and S0 of the column circuit 26-1 output signals, the memories N1 and S1 of the column circuit 26-1 may also output signals, and when the memories N0 and S0 of the column circuit 26-2 output signals, the memories N1 and S1 of the column circuit 26-1 may also output signals.

[0137] Alternatively, when the memories N0 and S0 of the column circuit 26-1 output signals, the memories N1 and S1 of the column circuit 26-1 output signals, but when the memories N0 and S0 of the column circuit 26-2 output signals, the memories N1 and S1 of the column circuit 26-1 do not output signals. In this case, the signal processing circuit 28 may hold the signals output from the memories N1 and S1 of the column circuit 26-1 and use them to process the output signal from the column circuit 26-2.

[0138] The circuit configuration for sharing memories N1 and S1, the number of column circuits sharing memories N1 and S1, and the signal transfer method between the column circuits and the signal processing circuit are not limited to those described above. For example, only memory N1 may be shared by multiple column circuits, or only some bits of memory N1 may be shared by multiple column circuits. Furthermore, in a configuration such as that shown in FIG. 12 , where the column circuits have memories N1, S1, N2, and S2, either memory N1 or S1 or memory N2 or S2 may be shared by multiple column circuits. The memory sharing method may be appropriately designed taking into account the effect of noise reduction by correction processing, noise distribution within a row, element area, and the like. The signal transfer method between the column circuits and the signal processing circuit may be appropriately designed taking into account the data volume of the transmitted signal, power consumption, and the like.

[0139] [Fourth embodiment] In this embodiment, a modified example in which the driving method and signal processing technique are changed from those in the second embodiment will be described. In this embodiment, the description of elements common to the second embodiment may be omitted or simplified.

[0140] Fig. 17 is a drive timing diagram of the photoelectric conversion device according to this embodiment, showing the timing of potential changes in the control signals OFD, TX1, and TX3 during one frame period and the timing of reading out each row.

[0141] In period T11, during the readout period for four rows (rows 1 to 4), a reset operation corresponding to the reset operation in period TD in FIG. 10 is performed four times. In period T12, during the readout period for four rows (rows 5 to 8), a transfer operation corresponding to the transfer operation in period TG in FIG. 10 is performed four times. In period T13, during the readout period for four rows (rows 9 to 12), no reset operation or transfer operation is performed. In period T14, which corresponds to after time t11 in FIG. 10, a charge accumulation and transfer operation is performed.

[0142] FIG. 18 is a diagram showing regions within a pixel array 10 according to this embodiment. The pixel array 10 has an effective pixel region R3 and OB pixel regions R4, R5, R6, and R7. Effective pixels that output signals based on incident light are arranged in the effective pixel region R3, and OB pixels that are configured to prevent light from entering their photoelectric conversion units PD are arranged in the OB pixel regions R4, R5, R6, and R7. Rows 1 to 4 in FIG. 17 correspond to the OB pixel region R4. Rows 5 to 8 in FIG. 17 correspond to the OB pixel region R5. Rows 9 to 12 in FIG. 17 correspond to the OB pixel region R6. Rows 13 to N in FIG. 17 correspond to the effective pixel region R3.

[0143] Fig. 19 is a diagram showing the procedure of signal processing according to this embodiment. Fig. 19 schematically shows the procedure of four stages of signal processing (signal processing 1 to signal processing 4) for acquiring signals acquired from the effective pixel region R3 based on signals acquired from the OB pixel regions R4, R5, and R6. This signal processing may be performed in the column circuit 26, in the signal processing circuit 28, or in a signal processing device external to the photoelectric conversion device.

[0144] The signals read from the OB pixel regions R4, R5, and R6 are assumed to be stored in advance in memory as data DR4, DR5, and DR6. Data DR4 is read during the reset operation in period T11, and therefore includes information about noise generated by the reset operation. Data DR5 is read during the transfer operation in period T12, and therefore includes information about noise generated by the transfer operation. Data DR6 is read during period T13 without performing the reset operation or transfer operation, and therefore does not include information about noise generated by the reset operation or transfer operation. This memory may be arranged within the column circuit 26, the signal processing circuit 28, or external to the photoelectric conversion device.

[0145] In signal processing 1, data DR4 obtained from multiple pixels in OB pixel region R4 is averaged (averaging processing 1). The averaged data D1 is then stored in memory. In signal processing 2, data DR5 obtained from multiple pixels in OB pixel region R5 is averaged (averaging processing 2). The averaged data D2 is then stored in memory. In signal processing 3, data DR6 obtained from multiple pixels in OB pixel region R6 is averaged (averaging processing 3). The averaged data D3 is then stored in memory. These averaging processes may be performed on multiple pixels in a single column, or on multiple pixels in a block, where a region including multiple columns is treated as one block. Signal processing 1, signal processing 2, and signal processing 3 may be performed sequentially as shown in FIG. 19 or in parallel. Note that although averaging is illustrated as an example of the arithmetic processing performed in signal processing 1, signal processing 2, and signal processing 3, other statistical processing may also be performed. This arithmetic processing may, for example, be a process of integrating data obtained from multiple pixels.

[0146] In signal processing 4, correction processing is performed using data D1 to DR3 on data DR3 obtained from multiple pixels in the effective pixel region R3. For data DR3 obtained from multiple pixels in a row (row 13 in FIG. 17) whose readout timing overlaps with the reset operation in the effective pixel region R3, processing is performed to subtract data D1 from data DR3. For data DR3 obtained from multiple pixels in rows (rows A, B, C, and N in FIG. 17) whose readout timing overlaps with the transfer operation in the effective pixel region R3, processing is performed to subtract data D2 from data DR3. For data DR3 obtained from multiple pixels in rows (rows A, B, C, and N in FIG. 17) whose readout timing does not overlap with either the reset operation or the transfer operation in the effective pixel region R3, processing is performed to subtract data D3 from data DR3. These three types of correction processing may be performed in parallel as shown in FIG. 19 or sequentially. These signal processing operations can effectively reduce noise, such as offset components for each row and each column of the pixel array 10.

[0147] According to this embodiment, a photoelectric conversion device capable of reducing the influence of noise caused by the global electronic shutter operation is provided. In addition, in this embodiment, by performing multiple reset and transfer operations in the OB pixel region, multiple correction data can be generated, thereby more effectively reducing the influence of noise.

[0148] In the above example, the averaging in generating the data D1, D2, and D3 may be performed on multiple pixels in a block, with each block being an area including multiple columns. Figure 20 is a diagram showing a modified example of the signal processing procedure according to this embodiment. Figure 20 shows an example in which the pixel array 10 is divided into blocks of five column ranges and averaging is performed.

[0149] In signal processing 1, averaging similar to that in Fig. 19 is performed on each of the five blocks, and data D1-1 to D1-5 are stored. Similarly, data D2-1 to D2-5 and data D3-1 to D3-5 are stored in signal processing 2 and 3. In signal processing 4, processing is performed for each block to subtract data D1-1 to D1-5, data D2-1 to D2-5, and data D3-1 to D3-5 from data DR3, similar to that in Fig. 19.

[0150] 20 shows an example where there are five blocks, but similar processing is possible if there are two or more blocks. When pixel array 10 has a first block and a second block, processing is performed as follows. For signals from pixels in the first block, data D1-1, D2-1, and D3-1 are stored by signal processing 1, 2, and 3 (first processing). For signals from pixels in the second block, data D1-2, D2-2, and D3-2 are stored by signal processing 1, 2, and 3 (second processing). Then, in signal processing 4, processing is performed for each block to subtract data D1-1, D1-2, D2-1, D2-2, D3-1, and D3-2 from data DR3, as in FIG. 19.

[0151] 20, in which the data for signal processing 1, 2, and 3 are stored for each block, arithmetic processing using a predetermined function may be performed on the data for multiple blocks. An example of this arithmetic processing is interpolation processing.

[0152] A modified example of the method of dividing the OB pixel region will be described. Fig. 21 is a diagram showing a modified example of the regions within the pixel array 10 according to this embodiment. The pixel array 10 has an effective pixel region R3 and OB pixel regions R7, R8, R9, R10, and R11. Each of the OB pixel regions R7, R8, R9, R10, and R11 can be a pixel region that is driven in the same way as any of the OB pixel regions R4, R5, and R6 in Fig. 18.

[0153] The OB pixel regions R4, R5, and R6 in FIG. 18 are arranged so that they are read out continuously. However, the OB pixel regions may be arranged so that they are read out discontinuously, as in the case of the OB pixel regions R8, R10, and R11 in FIG. 21. The OB pixel regions R4, R5, and R6 in FIG. 18 are arranged to include all columns of the pixel array 10. However, the OB pixel regions may be arranged to include only a portion of all columns of the pixel array 10, as in the case of the OB pixel regions R8, R10, and R11 in FIG. 21. The positions, ranges, and the like of these OB pixel regions may be determined according to the output characteristics of each pixel in the pixel array 10. Furthermore, data from multiple OB pixel regions may be combined and used when performing each of signal processing 1, 2, and 3.

[0154] [Fifth embodiment] In this embodiment, a modification in which correction processing is performed outside the photoelectric conversion device of the above embodiment will be described. In this embodiment, the description of elements common to the above embodiment may be omitted or simplified.

[0155] FIG. 22 is a diagram showing a photoelectric conversion device 1 and a signal processing device 2 according to this embodiment. The system shown in FIG. 22 includes a photoelectric conversion device 1 and a signal processing device 2. The photoelectric conversion device 1 corresponds to the photoelectric conversion device shown in the above-described embodiment. However, in the photoelectric conversion device 1 of this embodiment, correction processing is performed outside the photoelectric conversion device 1. The signal processing device 2 processes the digital signal generated by the photoelectric conversion device 1. The signal processing device 2 may be an image signal processor.

[0156] The photoelectric conversion device 1 and the signal processing device 2 are communicatively connected via an output interface IF1 and a control interface IF2. A digital signal output from the photoelectric conversion device 1 is input to the signal processing device 2 via the output interface IF1. The signal processing device 2 processes the digital signal output from the photoelectric conversion device 1. The signal processing device 2 may generate setting data based on the digital signal output from the photoelectric conversion device 1 and output the setting data to the photoelectric conversion device 1. In this case, the photoelectric conversion device 1 may perform processing according to the setting data.

[0157] A specific example of signal processing performed in the photoelectric conversion device 1 and the signal processing device 2 will be described. Fig. 23 is a diagram showing the procedure of signal processing according to this embodiment. In the signal processing of Fig. 23, it is assumed that the pixel regions in the pixel array 10 are set as in Fig. 18 of the fourth embodiment. It is also assumed that the number of rows in the OB pixel regions R4, R5, and R6 is four, as in the fourth embodiment.

[0158] The photoelectric conversion device 1 performs three-stage signal readout (signal readout 1 to signal readout 3). The signal processing device 2 receives the digital signal readout from the photoelectric conversion device 1, performs four-stage signal processing (signal processing 1 to signal processing 4), and outputs the signal to the photoelectric conversion device 1.

[0159] In signal readout 1, the photoelectric conversion device 1 outputs data DR4 obtained from multiple pixels (4 rows × all columns) in the OB pixel region R4 to the signal processing device 2. The data DR4 includes information on noise generated by the reset operation. In signal processing 1, the signal processing device 2 averages the data DR4 for each block of five columns (column averaging process 1).

[0160] In signal readout 2, the photoelectric conversion device 1 outputs data DR5 obtained from multiple pixels (4 rows × all columns) in the OB pixel region R5 to the signal processing device 2. The data DR5 includes information on noise generated by the transfer operation. In signal processing 2, the signal processing device 2 averages the data DR5 for each block of five columns (column averaging process 2).

[0161] In signal readout 3, the photoelectric conversion device 1 outputs data DR6 obtained from multiple pixels (4 rows × all columns) in the OB pixel region R6 to the signal processing device 2. The data DR6 does not include information about noise generated by the reset operation and transfer operation. In signal processing 3, the signal processing device 2 averages the data DR5 for each block of five columns (column averaging process 3).

[0162] In signal processing 4, signal processing device 2 performs arithmetic processing based on the averaged data obtained in signal processing 1, signal processing 2, and signal processing 3 to calculate a correction value. Then, signal processing device 2 outputs the correction value to photoelectric conversion device 1. This arithmetic processing is also performed for each block of five column ranges. This arithmetic processing may include, for example, processing to detect the influence of noise caused by a reset operation or a transfer operation. For example, the influence of noise caused by a reset operation can be detected from the difference between the data obtained by column averaging processing 3 and the data obtained by column averaging processing 1. Furthermore, for example, the influence of noise caused by a transfer operation can be detected from the difference between the data obtained by column averaging processing 3 and the data obtained by column averaging processing 2.

[0163] The photoelectric conversion device 1 can perform arithmetic processing based on the correction value input from the signal processing device 2. For example, the signal processing circuit 28 of the photoelectric conversion device 1 can perform arithmetic processing such as gain processing and offset addition processing on the digital signals read out from the pixels 11 in the effective pixel area based on the correction value, and output the processed digital signals.

[0164] According to this embodiment, a photoelectric conversion device is provided that can reduce the influence of noise caused by the global electronic shutter operation. Furthermore, in this embodiment, correction processing can be performed in a signal processing device external to the photoelectric conversion device. This allows the photoelectric conversion device to have high functionality while maintaining the area occupied by the photoelectric conversion device.

[0165] [Sixth embodiment] The photoelectric conversion device in the above-described embodiment can be applied to various devices, such as digital still cameras, digital camcorders, camera heads, copiers, fax machines, mobile phones, vehicle-mounted cameras, observation satellites, and surveillance cameras. Fig. 24 shows a block diagram of a digital still camera as an example of such a device.

[0166] The device 70 shown in FIG. 24 includes a barrier 706, a lens 702, an aperture 704, and an image pickup device 700 (an example of a photoelectric conversion device). The device 70 also includes a signal processing unit (processing device) 708, a timing generating unit 720, an overall control / calculation unit 718 (control device), a memory unit 710 (storage device), a recording medium control I / F unit 716, a recording medium 714, and an external I / F unit 712. At least one of the barrier 706, the lens 702, and the aperture 704 is an optical device corresponding to the device. The barrier 706 protects the lens 702, and the lens 702 forms an optical image of a subject on the image pickup device 700. The aperture 704 varies the amount of light passing through the lens 702. The image pickup device 700 is configured as in the above-described embodiment, and converts the optical image formed by the lens 702 into image data (image signals). The signal processing unit 708 performs various corrections, data compression, etc. on the image pickup data output from the image pickup device 700. The timing generation unit 720 outputs various timing signals to the imaging device 700 and the signal processing unit 708. The overall control / calculation unit 718 controls the entire digital still camera, and the memory unit 710 temporarily stores image data. The recording medium control I / F unit 716 is an interface for recording or reading image data to or from the recording medium 714, which is a removable recording medium such as a semiconductor memory for recording or reading imaging data. The external I / F unit 712 is an interface for communicating with an external computer, etc. Timing signals may be input from outside the device. The device 70 may also include a display device (monitor, electronic viewfinder, etc.) that displays information obtained by the photoelectric conversion device. The device 70 includes at least a photoelectric conversion device. The device 70 further includes at least one of an optical device, a control device, a processing device, a display device, a storage device, and a mechanical device that operates based on information obtained by the photoelectric conversion device. The mechanical device is a movable part (e.g., a robot arm) that operates in response to a signal from the photoelectric conversion device.

[0167] Each pixel may include a plurality of photoelectric conversion units (a first photoelectric conversion unit and a second photoelectric conversion unit). The signal processing unit 708 may be configured to process a pixel signal based on the charge generated in the first photoelectric conversion unit and a pixel signal based on the charge generated in the second photoelectric conversion unit, and acquire information about the distance from the image capturing device 700 to the subject.

[0168] [Seventh embodiment] 25(a) and 25(b) are block diagrams of devices related to an in-vehicle camera according to this embodiment. The device 80 includes an image capture device 800 (an example of a photoelectric conversion device) according to the above-described embodiment and a signal processing device (processing device) that processes signals from the image capture device 800. The device 80 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the image capture device 800, and a parallax calculation unit 802 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the device 80. The device 80 also includes a distance measurement unit 803 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax calculation unit 802 and the distance measurement unit 803 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information includes information about the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 804 may determine the possibility of a collision using any of this distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0169] The device 80 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The device 80 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The device 80 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high collision possibility, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel. The device 80 functions as a control means for controlling the operation of controlling the vehicle as described above.

[0170] In this embodiment, the device 80 captures images of the surroundings of the vehicle, for example, the front or rear. Fig. 25(b) shows the device when capturing an image of the area in front of the vehicle (image capturing range 850). A vehicle information acquisition device 810, which serves as an image capturing control means, sends an instruction to the device 80 or the image capturing device 800 to perform an image capturing operation. This configuration can further improve the accuracy of distance measurement.

[0171] Although the above describes an example of control to prevent collision with other vehicles, the present invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from a lane, etc. Furthermore, the present invention is not limited to vehicles such as automobiles, but can be applied to moving objects (moving devices) such as ships, aircraft, artificial satellites, industrial robots, and consumer robots. In addition, the present invention can be applied to a wide range of devices that use object recognition or biometric recognition, such as intelligent transport systems (ITS) and surveillance systems, without being limited to moving objects.

[0172] The disclosure of this specification includes the complement of the concepts described in this specification. In other words, if this specification states, for example, that "A is B" (A=B), then this specification is deemed to disclose or suggest that "A is not B" even if the statement that "A is not B" (A≠B) is omitted. This is because when "A is B," it is assumed that the case where "A is not B" is taken into consideration.

[0173] The disclosure of this specification includes the following configurations. (Configuration 1) a pixel array in which a plurality of pixels are arranged in a plurality of rows and a plurality of columns, each pixel having a charge accumulation unit that accumulates charges, a drain transistor that performs a reset operation to drain the charges accumulated in the charge accumulation unit, a holding unit that holds the transferred charges, an amplifier unit that outputs a signal based on the transferred charges, a first transfer transistor that transfers charges from the charge accumulation unit to the holding unit, and a second transfer transistor that transfers the charges transferred by the first transfer transistor to the amplifier unit; a scanning circuit that performs scanning to sequentially select rows from the plurality of rows to which the pixels output signals; and a first pixel arranged in a first region of the pixel array outputs a signal based on incident light; a second pixel arranged in a second region of the pixel array does not output a signal based on incident light; the reset operation by the drain transistor starts or ends during a period in which pixels in one row of the pixel array output signals; During a period from the start of one scan to the start of the next scan, the number of times the reset operation is performed in the second pixel is greater than the number of times the reset operation is performed in the first pixel. A photoelectric conversion device characterized by: (Configuration 2) The charge storage unit of the first pixel includes a photoelectric conversion element that generates and stores charges in response to incident light. 2. The photoelectric conversion device according to configuration 1, (Configuration 3) The charge storage unit of the second pixel includes a light-shielded photoelectric conversion element. 3. The photoelectric conversion device according to configuration 1 or 2. (Configuration 4) The charge storage portion of the second pixel is a dummy element that does not include a photoelectric conversion element. 3. The photoelectric conversion device according to configuration 1 or 2. (Configuration 5) The transfer of the charges by the first transfer transistor starts or ends during a period in which pixels in one row of the pixel array output signals. 5. The photoelectric conversion device according to any one of configurations 1 to 4. (Configuration 6) During a period from the start of one scan to the start of the next scan, the charge is transferred multiple times in each of the first pixel and the second pixel. 6. The photoelectric conversion device according to configuration 5. (Configuration 7) The reset operation is performed multiple times in each of the first pixel and the second pixel during a period from the start of one scan to the start of the next scan. 7. The photoelectric conversion device according to any one of configurations 1 to 6. (Configuration 8) The pixel circuit further includes a column circuit that is arranged corresponding to each of the plurality of columns and processes signals output from pixels in the corresponding column. 8. The photoelectric conversion device according to any one of configurations 1 to 7. (Configuration 9) Further, the image sensor has a memory for storing the signal output from the pixel. 9. The photoelectric conversion device according to any one of configurations 1 to 8. (Configuration 10) The column circuit includes a memory that stores signals output from pixels in a corresponding column. 9. The photoelectric conversion device according to configuration 8, (Configuration 11) The memory holds a signal output from the first pixel in a corresponding column and a signal output from the second pixel in a corresponding column. 11. The photoelectric conversion device according to configuration 10. (Configuration 12) The memory holds a signal output from the first pixel in a corresponding column and signals output from two second pixels in a corresponding column. 11. The photoelectric conversion device according to configuration 10. (Configuration 13) The signal stored in the memory of one column circuit is used to correct the signal stored in the memory of another column circuit. 11. The photoelectric conversion device according to configuration 10. (Configuration 14) Output the signal output from the pixel to an external memory 9. The photoelectric conversion device according to any one of configurations 1 to 8. (Configuration 15) A correction process is performed on the signal output from the first pixel based on the signal output from the second pixel. 15. The photoelectric conversion device according to any one of configurations 1 to 14. (Configuration 16) A correction process is performed on the signal output from the first pixel during the period in which the reset operation is being performed, based on the signal output from the second pixel during the period in which the reset operation is being performed. 16. The photoelectric conversion device according to configuration 15. (Configuration 17) A correction process is performed on the signal output from the first pixel during a period including the timing at which the reset operation starts, based on the signal output from the second pixel during a period including the timing at which the reset operation starts. 17. The photoelectric conversion device according to configuration 16, (Configuration 18) A correction process is performed on the signal output from the first pixel during a period including the timing at which the reset operation ends, based on the signal output from the second pixel during a period including the timing at which the reset operation ends. 18. The photoelectric conversion device according to configuration 16 or 17. (Configuration 19) Based on a signal output from the second pixel during a period in which a transfer operation of transferring the charge is being performed by the first transfer transistor, a correction process is performed on the signal output from the first pixel during the transfer operation. 16. The photoelectric conversion device according to configuration 15. (Configuration 20) Correction processing of the signal output from the first pixel during a period including the timing at which the transfer operation starts is performed based on the signal output from the second pixel during a period including the timing at which the transfer operation starts. 20. The photoelectric conversion device according to claim 19, (Configuration 21) A correction process is performed on the signal output from the first pixel during a period including the timing at which the transfer operation ends, based on the signal output from the second pixel during a period including the timing at which the transfer operation ends. 21. The photoelectric conversion device according to configuration 19 or 20. (Configuration 22) The correction process includes a calculation process of subtracting the signal output from the second pixel from the signal output from the first pixel. 22. The photoelectric conversion device according to any one of configurations 15 to 21, (Configuration 23) The signal processing circuit further includes a signal processing circuit for performing the correction process. 23. The photoelectric conversion device according to any one of configurations 15 to 22. (Configuration 24) The signal output from the first pixel and the signal output from the second pixel are output to a signal processing device that performs the correction processing. 23. The photoelectric conversion device according to any one of configurations 15 to 22. (Configuration 25) The correction value obtained by the correction process is received from the signal processing device, and processing is performed based on the correction value. 25. The photoelectric conversion device according to configuration 24. (Configuration 26) The correction process includes integrating or averaging signals from a plurality of pixels. 26. The photoelectric conversion device according to any one of configurations 15 to 25. (Configuration 27) The correction processing includes a first processing for signals from pixels included in a first block among the plurality of pixels, and a second processing for signals from pixels included in a second block among the plurality of pixels. 27. The photoelectric conversion device according to any one of configurations 15 to 26, (Configuration 28) the pixel array is disposed on a first substrate; The signals output from each of the plurality of pixels are processed in a circuit disposed on a second substrate stacked on the first substrate. 28. The photoelectric conversion device according to any one of configurations 1 to 27, (Configuration 29) The photoelectric conversion device according to any one of configurations 1 to 28, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device. (Configuration 30) 30. The device according to claim 29, wherein the processing device acquires distance information from the photoelectric conversion device to an object.

[0174] The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0175] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0176] 10 pixel array 11 pixels CM1 holding part M1 First transfer transistor M2 Second transfer transistor M4 Amplifying transistor M6 Emission transistor PD photoelectric conversion unit R1 Effective pixel area R2 OB pixel area

Claims

1. a pixel array in which a plurality of pixels are arranged in a plurality of rows and a plurality of columns, each pixel having a charge accumulation unit that accumulates charges, a drain transistor that performs a reset operation to drain the charges accumulated in the charge accumulation unit, a holding unit that holds the transferred charges, an amplifier unit that outputs a signal based on the transferred charges, a first transfer transistor that transfers charges from the charge accumulation unit to the holding unit, and a second transfer transistor that transfers the charges transferred by the first transfer transistor to the amplifier unit; a scanning circuit that performs scanning to sequentially select rows from the plurality of rows to which the pixels output signals; and a first pixel arranged in a first region of the pixel array outputs a signal based on incident light; a second pixel arranged in a second region of the pixel array does not output a signal based on incident light; the reset operation by the drain transistor starts or ends during a period in which pixels in one row of the pixel array output signals; During a period from the start of one scan to the start of the next scan, the number of times the reset operation is performed in the second pixel is greater than the number of times the reset operation is performed in the first pixel. A photoelectric conversion device characterized by:

2. The charge storage unit of the first pixel includes a photoelectric conversion element that generates and stores a charge in response to incident light.

2. The photoelectric conversion device according to claim 1.

3. The charge storage unit of the second pixel includes a light-shielded photoelectric conversion element.

2. The photoelectric conversion device according to claim 1.

4. The charge storage portion of the second pixel is a dummy element that does not include a photoelectric conversion element.

2. The photoelectric conversion device according to claim 1.

5. The transfer of the electric charges by the first transfer transistor starts or ends during a period in which the pixels in one row of the pixel array output a signal.

2. The photoelectric conversion device according to claim 1.

6. During a period from the start of one scan to the start of the next scan, the charge is transferred multiple times in each of the first pixel and the second pixel.

6. The photoelectric conversion device according to claim 5.

7. The reset operation is performed multiple times in each of the first pixel and the second pixel during a period from the start of one scan to the start of the next scan.

2. The photoelectric conversion device according to claim 1.

8. The pixel circuit further includes a column circuit that is arranged corresponding to each of the plurality of columns and processes signals output from pixels in the corresponding column.

2. The photoelectric conversion device according to claim 1.

9. Further, the image sensor has a memory for storing the signal output from the pixel.

2. The photoelectric conversion device according to claim 1.

10. The column circuit includes a memory that stores signals output from pixels in a corresponding column.

9. The photoelectric conversion device according to claim 8.

11. The memory holds a signal output from the first pixel in a corresponding column and a signal output from the second pixel in a corresponding column.

11. The photoelectric conversion device according to claim 10.

12. The memory holds a signal output from the first pixel in a corresponding column and signals output from two second pixels in a corresponding column.

11. The photoelectric conversion device according to claim 10.

13. The signal stored in the memory of one column circuit is used to correct the signal stored in the memory of another column circuit.

11. The photoelectric conversion device according to claim 10.

14. Output the signal output from the pixel to an external memory 2. The photoelectric conversion device according to claim 1.

15. A correction process for the signal output from the first pixel is performed based on the signal output from the second pixel.

2. The photoelectric conversion device according to claim 1.

16. A correction process is performed on the signal output from the first pixel during the period in which the reset operation is being performed, based on the signal output from the second pixel during the period in which the reset operation is being performed.

16. The photoelectric conversion device according to claim 15.

17. A correction process is performed on the signal output from the first pixel during a period including the timing at which the reset operation starts, based on the signal output from the second pixel during a period including the timing at which the reset operation starts.

17. The photoelectric conversion device according to claim 16.

18. A correction process is performed on the signal output from the first pixel during a period including the timing at which the reset operation ends, based on the signal output from the second pixel during a period including the timing at which the reset operation ends.

17. The photoelectric conversion device according to claim 16.

19. Based on the signal output from the second pixel during a period in which the first transfer transistor is performing a transfer operation of transferring the charge, a correction process is performed on the signal output from the first pixel during the transfer operation.

16. The photoelectric conversion device according to claim 15.

20. Correction processing is performed on the signal output from the first pixel during a period including the timing at which the transfer operation starts, based on the signal output from the second pixel during a period including the timing at which the transfer operation starts.

20. The photoelectric conversion device according to claim 19.

21. A correction process is performed on the signal output from the first pixel during a period including the timing at which the transfer operation ends, based on the signal output from the second pixel during a period including the timing at which the transfer operation ends.

20. The photoelectric conversion device according to claim 19.

22. The correction process includes a calculation process of subtracting the signal output from the second pixel from the signal output from the first pixel.

16. The photoelectric conversion device according to claim 15.

23. The signal processing circuit further includes a signal processing circuit for performing the correction process.

16. The photoelectric conversion device according to claim 15.

24. The signal output from the first pixel and the signal output from the second pixel are output to a signal processing device that performs the correction processing.

16. The photoelectric conversion device according to claim 15.

25. The correction value obtained by the correction process is received from the signal processing device, and processing is performed based on the correction value.

25. The photoelectric conversion device according to claim 24.

26. The correction process includes integrating or averaging signals from a plurality of pixels.

16. The photoelectric conversion device according to claim 15.

27. The correction processing includes a first processing for signals from pixels included in a first block among the plurality of pixels, and a second processing for signals from pixels included in a second block among the plurality of pixels.

16. The photoelectric conversion device according to claim 15.

28. the pixel array is disposed on a first substrate; The signals output from the plurality of pixels are processed in a circuit disposed on a second substrate stacked on the first substrate.

2. The photoelectric conversion device according to claim 1.

29. The photoelectric conversion device according to any one of claims 1 to 28, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

30. 30. The device of claim 29, wherein the processing device acquires distance information from the photoelectric conversion device to an object.

Images