Mapping result verification method and mapping result verification apparatus

Abstract

To provide a mapping result verification program, a mapping result verification method and a mapping result verification device for improving the accuracy of mapping to a CGRA.SOLUTION: Acquiring a data flow graph representing a predetermined calculation including a plurality of operations and a mapping result obtained by mapping the data flow graph to a CGRA having a plurality of arithmetic elements, and verifying whether the mapping result and the data flow graph match based on an operation result obtained by executing an operation for each of first arithmetic elements to which the operation is assigned in the mapping result.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a mapping result verification program, a mapping result verification method, and a mapping result verification device. [Background technology]

[0002] In recent years, Coarse-Grained Reconfigurable Architectures (CGRAs) have been attracting attention as a type of data processing device that offers excellent computational performance and energy efficiency in data processing. CGRA is a processor technology with a structure in which processing elements called PEs (Processing Elements), each equipped with an arithmetic unit and registers, are arranged in a two-dimensional array. CGRAs can reconfigure the calculations performed by PEs and the data transfer paths between PEs during operation. A processor with PEs arranged in a two-dimensional array is sometimes called a CGRA.

[0003] A program is executed using a CGRA as follows: The program to be executed is converted into a DFG (Data Flow Graph) using a compiler. The DFG contains nodes that indicate operations and directed edges that indicate data dependencies between operations. A directed edge indicates that output data from a source node is used as input data for a destination node. Next, based on the DFG, the operations to be performed by each PE and the data wiring between PEs are determined according to the configuration of each PE in the CGRA. This determination of the operations and the data wiring between PEs is called mapping. After that, data is input to the CGRA after mapping is complete, and the CGRA performs operations using the input data.

[0004] If this mapping is done manually, there is a risk of mistakes being made and the process is time-consuming due to the complexity when there are a large number of PEs or when the data wiring is complex. Therefore, a device called an automatic mapper is used, which performs mapping automatically based on a predetermined algorithm determined according to the DFG.

[0005] However, automatic mapper programs can also contain bugs, and the mapping results may not be identical to the specified DFG. This makes it difficult to verify the accuracy of the output of an automatic mapper when developing it. For example, when developing an automatic mapper tailored to the characteristics of a target CGRA, mapping is manually tested and constraints on the mapping and optimization algorithms are considered, but it is difficult to guarantee that the execution results are correct. Therefore, it is necessary to verify the accuracy of the mapping results output by the automatic mapper, that is, whether the results calculated according to the DFG are identical to the results executed on the CGRA.

[0006] As a technique for verifying circuit equivalence, a technique has been proposed in which a reference circuit in a hardware description language is compared with a gate circuit in a netlist that has been logically synthesized using the reference circuit as input, before and after the logic synthesis processing step, to verify the logical equivalence of the circuit. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-257003 Summary of the Invention [Problem to be solved by the invention]

[0008] However, it is difficult to prove the correctness of an automatic mapper program from its own information, so it is important to ensure the correctness of the mapping results by other means. Also, just as speed is increased by manually writing some code using inline assembler, manual mapping is also possible, so it is important to manually tune the mapping results of an automatic mapper and to guarantee the correctness of the results of all manual mapping.

[0009] A typical testing method is to compare the results of a CGRA calculation with the results of a DFG calculation when several input values ​​are given. However, it is not realistic to verify all input values. Furthermore, when comparing calculation results, it is difficult to track the flow of calculated values ​​and detect which PEs have incorrect settings, making it difficult to correct the automatic mapper. Therefore, it is difficult to improve the accuracy of mapping to a CGRA by comparing calculation results.

[0010] Furthermore, the technique of verifying the logical equivalence of a circuit by comparing the results before and after the logic synthesis processing step is equivalent to comparing the calculation results of individual parts, and it is difficult to improve the accuracy of mapping to a CGRA.

[0011] The disclosed technology has been made in consideration of the above, and aims to provide a mapping result verification program, a mapping result verification method, and a mapping result verification device that improve the accuracy of mapping for CGRA. [Means for solving the problem]

[0012] In one aspect of the mapping result verification program, mapping result verification method, and mapping result verification device disclosed in the present application, a computer is caused to obtain a data flow graph representing a predetermined calculation including multiple operations and a mapping result obtained by mapping the data flow graph to a CGRA having multiple arithmetic units, and to execute a process of verifying whether the mapping result and the data flow graph match, using the calculation results obtained by executing the calculation for each first arithmetic unit to which the operation is assigned in the mapping result. [Effects of the Invention]

[0013] In one aspect, the present invention can improve the accuracy of mapping to a CGRA. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a block diagram of a mapping result verification device. [Figure 2] FIG. 2 is a diagram showing an example of a method for expressing the mapping of PEs. [Figure 3] FIG. 3 is a diagram showing an example of a DFG and a mapping result. [Figure 4] FIG. 4 is a diagram showing an outline of the mapping result verification process. [Figure 5] FIG. 5 is a diagram illustrating an example of a CGRA to be mapped. [Figure 6] FIG. 6 is a diagram illustrating an example of connections between PEs. [Figure 7] FIG. 7 is a diagram illustrating an example of the verification information list. [Figure 8] FIG. 8 is a diagram showing an example of a DFG and a mapping result used in a detailed description of the mapping result verification process. [Figure 9] FIG. 9 is a diagram showing the verification information list in which the output of the 0th cycle is registered. [Figure 10] FIG. 10 is a diagram showing the verification information list in which the output of the first cycle is registered. [Figure 11] FIG. 11 is a diagram showing the verification information list in which the output of the second cycle is registered. [Figure 12] FIG. 12 is a flowchart of the mapping result verification process according to the first embodiment. [Figure 13] FIG. 13 is a diagram showing an example of mapping in which existing mapping results are partially combined. [Figure 14] FIG. 14 is a diagram for explaining an extension of the mapping expression method. [Figure 15] FIG. 15 is a diagram illustrating an example of a mapping result according to the second embodiment. [Figure 16] FIG. 16 is a diagram illustrating transition of the verification information list in the mapping verification process according to the second embodiment. [Figure 17] FIG. 17 is a diagram illustrating an example of a method for using the mapping result verification device. [Figure 18]FIG. 18 is a diagram showing the hardware configuration of the mapping result verification device. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments of the mapping result verification program, the mapping result verification method, and the mapping result verification device disclosed in the present application will be described in detail with reference to the accompanying drawings. Note that the mapping result verification program, the mapping result verification method, and the mapping result verification device disclosed in the present application are not limited to the following embodiments. [Example]

[0016] 1 is a block diagram of a mapping result verification device 1 according to this embodiment. The mapping result verification device 1 is connected to an automatic mapper 2 and a user terminal device 3.

[0017] The user terminal device 3 is a terminal device of a user who uses an information processing device (not shown) equipped with a CGRA. The CGRA has multiple PEs, which are computing units. The user designs a DFG (data flow graph) to operate the CGRA. A DFG is a diagram showing the flow of data and the operations to be executed in a system that performs calculations. Here, the object performed by the DFG as a whole is called a "calculation," and this "calculation" contains multiple "operations." The user terminal device 3 sends the DFG designed by the user to the automatic mapper 2, which performs mapping to the CGRA. Furthermore, the user terminal device 3 sends the DFG designed by the user to the mapping result verification device 1 to verify the mapping results by the automatic mapper 2.

[0018] The automapper 2 receives a DFG to be mapped to a CGRA from the user terminal device 3. The automapper 2 stores configuration information of the CGRA to be mapped in advance. The automapper 2 then maps the received DFG to the CGRA. Mapping is a process of assigning operations defined in the DFG to one of the PEs in the CGRA, determining the connections between PEs so that each operation is performed according to the data flow defined in the DFG, and configuring the CGRA so that the calculation of the DFG can be performed. The automapper 2 transmits the mapping result to the mapping result verification device 1 to verify the mapping result.

[0019] Next, a description will be given of the mapping result verification device 1. The mapping result verification device 1 includes an information collection unit 11, a verification information generation unit 12, a verification unit 13, an output number confirmation unit 14, and an output unit 15.

[0020] The information collection unit 11 receives a DFG designed by a user from the user terminal device 3. The information collection unit 11 also receives the mapping result of the DFG by the automatic mapper 2. Then, the information collection unit 11 outputs the DFG and the mapping result to the verification information generation unit 12 and the verification unit 13.

[0021] In this way, the information collection unit 11 acquires a data flow graph representing a predetermined calculation including multiple operations and a mapping result obtained by mapping the data flow graph to a CGRA having multiple arithmetic units. A PE to which an operation defined in a DFG is assigned by mapping by the automatic mapper 2 is an example of a "first arithmetic unit." The acquisition process includes a process of acquiring a mapping result in which information output from the first arithmetic unit, including the operation result, is used as information input to another arithmetic unit or as a calculation result of the predetermined calculation.

[0022] The mapping result includes information about where each PE in the mapped CGRA receives its input signal, what calculation it performs, and what signal it outputs to what destination. The input source is either an input node or another PE, which is the source of the initial information. The output destination is either another PE or a result output.

[0023] Fig. 2 is a diagram showing an example of a method for expressing mapping of a PE. Representations 21 and 22 in Fig. 2 respectively show information on different methods for expressing mapping for the PE 100. Abstractly, mapping for each PE 100 can be expressed by the following information:

[0024] The mapping result includes, as the first piece of information, information on the input ports used in each PE 100. The input port information uses identification information of the input ports. In both expressions 21 and 22, p, q, r, and s are the identification information of the input ports, respectively. In the following, for example, an input port whose identification information is p may be referred to as the input port of p.

[0025] The mapping result also includes, as second information, an output value for each output port from each PE 100. Expression 21 indicates that the output value from one output port is p and the output value from the other output port is p*c0. Here, p*c0 is an operation executed by the PE 100, and c0 is a constant stored in the PE 100. In this case, it is indicated that the input values ​​to the input ports of q, r, and s are not used.

[0026] Furthermore, using an arithmetic expression as an output value as is, as in expression 21, can be considered to be complicated. In that case, as in expression 22, it is possible to express the output value by using the identification information of the output port for the output value and separately storing the arithmetic expression corresponding to that identification information. For example, expression 22 has output ports with identification information o1 and o2, and the output values ​​from the respective output ports are o1 and o2. Furthermore, if expression 22 also has the same output value as expression 21, then expression 22 separately stores information such as o1=p and o2=p*c0. In the following, for example, an output port with identification information o1 may be referred to as the output port of o1.

[0027] Furthermore, the mapping result includes, as a third piece of information, the node ID of the node in the DFG mapped to each PE 100. If these three pieces of information are included in the mapping result, it is possible to express the mapping to each PE 100 in the CGRA. In the following description, each PE is assumed to be a PE 100.

[0028] The verification information generation unit 12 receives the DFG and the mapping result as input from the information collection unit 11. Next, the verification information generation unit 12 sets the timing of the output from the input node as cycle 0, and sets the output value from the virtual PE 100 corresponding to the input node as the output value in cycle 0. Then, the verification information generation unit 12 outputs the generated output value to the verification unit 13.

[0029] When the input value is output by the PE 100 as is, the verification information generation unit 12 sets the input value as the output value. Furthermore, in this embodiment, the verification of the operation executed by the PE 100 uses an operation result obtained by symbolic execution, which performs algebraic symbolic calculations using symbols as values. Therefore, when the operation result of the PE 100 using the input value is output, the output value is the operation result using the symbol. However, since the operation in the next PE 100 using the output value is also symbolic execution, the verification information generation unit 12 further abstracts the output value and sets the identification information of the PE 100 that outputs the operation result as the output value. By replacing the operation result with the identification information of the PE 100 that is the output source and outputting it in this way, the verification information generation unit 12 can prevent the output value from becoming a complex value, thereby simplifying the verification of the calculation.

[0030] Thereafter, when the verification information generation unit 12 receives a notification from the verification unit 13 that the validity has been verified for the first cycle, the verification information generation unit 12 generates an output value from each PE 100 in the first cycle. Then, the verification information generation unit 12 outputs the generated output value to the verification unit 13.

[0031] After that, when the verification information generation unit 12 receives a notification from the verification unit 13 that the validity has been verified, the verification information generation unit 12 generates an output value from each PE 100 in the next cycle and outputs it to the verification unit 13 until there is no PE 100 that outputs a signal. Also, when the verification information generation unit 12 receives a notification from the verification unit 13 that verification has been stopped, the verification information generation unit 12 stops generating output values ​​at that point. In this way, the verification information generation unit 12 generates verification information including information on the output values ​​of each PE 100 used in the mapping result.

[0032] The verification unit 13 receives an input of the output value of each PE 100 for each cycle, starting from cycle 0. Then, the verification unit 13 performs the following verification for the PE 100 to which the output value in the previous cycle is input.

[0033] As a first verification, the verification unit 13 confirms that all outputs input to and used by the PE 100 have been obtained in the previous cycle. Here, "output" refers to an output value being sent from a specific PE 100. In other words, "output being obtained" refers to an output being obtained from the PE 100 that is the output source of the output value used in the calculation. Here, the verification unit 13 can acquire signals output from the PE 100 connected to each port of the PE 100 from the architecture of the CGRA. The information on the CGRA architecture includes the number of wires between the PEs 100 and connection information between the PEs 100.

[0034] If there is an output that has not been obtained among the outputs used in the PE 100, the verification unit 13 outputs a notification that the mapping is invalid to the output unit 15. In addition, the verification unit 13 outputs a notification that the verification has been stopped to the verification information generation unit 12.

[0035] As the second verification, the verification unit 13 verifies that the output values ​​obtained in the previous cycle all match the output values ​​from the PE 100 that is the input source in the DFG, and that the operation of the PE 100 matches the operation specified in the DFG. Here, the verification unit 13 verifies the identity of the operation based on the operation result when the operation executed by the PE 100 is symbolically executed. Furthermore, if the operation executed by the PE 100 has a conditional branch, the verification unit 13 verifies this conditional branch as a constraint, and can verify that the branch is not reached if the constraint is contradictory.

[0036] If any of the output values ​​obtained in the previous cycle does not match the output value from the PE 100 that is the input source in the DFG, the verification unit 13 outputs a notification that mapping is invalid to the output unit 15. Also, if the operation of the PE 100 is different from the operation specified in the DFG, the verification unit 13 outputs a notification that mapping is invalid to the output unit 15. Furthermore, the verification unit 13 outputs a notification that verification is stopped to the verification information generation unit 12.

[0037] If the validity of the mapping result in that cycle is confirmed by the first verification and the second verification, the verification unit 13 outputs a notification that the validity has been verified to the verification information generation unit 12. Furthermore, if there is no next PE 100 to which the output value is to be input, the verification unit 13 sets the output value as one of the calculation results output by the CGRA.

[0038] Then, when there is no PE 100 that operates in the next cycle for all the output values, the verification unit 13 outputs all the output values ​​that are the calculation result outputs of the CGRA together with the DFG to the output number confirmation unit 14.

[0039] Here, symbolic execution corresponds to "executing an operation using symbols." That is, the verification unit 13 verifies whether the mapping result and the data flow graph match using the operation result obtained by executing the operation using symbols. The verification process also includes a process of comparing the verification information generated by the verification information generation unit 12 with information on the output value of the operation in the data flow graph. The verification process also includes a process of comparing information that serves as input to the operation assigned to the first computing unit in the data flow graph with information that is input to the first computing unit in the mapping result, to verify whether the mapping result and the data flow graph match. The verification process also compares information that serves as input to the operation assigned to the first computing unit in the data flow graph with information that is input to the first computing unit in the mapping result, based on information indicating the connection relationship between the computing units.

[0040] The output number confirmation unit 14 receives information on the output values ​​that are the calculation result output of the CGRA and the input of the DFG from the verification unit 13. Then, the output number confirmation unit 14 determines whether the number of output values ​​that are the calculation result output of the CGRA matches the number of outputs of the calculation result specified in the DFG.

[0041] If the number of output values ​​set as the calculation result output of the CGRA matches the number of outputs of the calculation result specified in the DFG, and if the output node specified in the DFG matches the output of the CGRA, the output number confirmation unit 14 determines that the verification is successful. Then, the output number confirmation unit 14 outputs a notification that the mapping result is valid to the output unit 15. On the other hand, if the number of output values ​​set as the calculation result output of the CGRA does not match the number of outputs of the calculation result specified in the DFG, the output number confirmation unit 14 outputs a notification that the mapping is invalid to the output unit 15. In this way, the output number confirmation unit 14 compares the number of calculation results indicated in the data flow graph with the number of calculation results obtained from the mapping result.

[0042] When the output unit 15 receives an input of a notification that the mapping is invalid from the verification unit 13, it transmits the notification that the mapping is invalid to the user terminal device 3. Furthermore, when the output unit 15 receives an input of a notification that the mapping result is valid from the output number confirmation unit 14, it transmits a notification that the mapping result is valid to the user terminal device 3.

[0043] Here, the validity of the mapping result will be explained. When a node equivalent to the output of the DFG is confirmed by verification by the mapping result verification device 1, soundness and completeness are guaranteed, and it is guaranteed that the mapping is correct and the calculation results match. As a premise, the mapping targets only a single DFG, and PEs 100 that do not assign operations pass the data through without modification. In other words, when an operation using an intermediate operation result is added to a specific DFG, or when a different operation is added, the DFG becomes a different DFG to which the DFG has been added.

[0044] Soundness means that something that can be proven is correct, and in this case, it indicates that the mapped calculation has a part that corresponds to the DFG. Soundness is guaranteed because the following is guaranteed by verification by the mapping result verification device 1. First, it is guaranteed that the mapped calculation exists in the DFG and does not contain any extra operations along the way. Second, it is guaranteed that the PE 100 will never execute an operation that is not assigned a node in the DFG. Third, it is guaranteed that the input to the PE 100 that is assigned a node in the DFG matches the input specified in the DFG.

[0045] Furthermore, completeness means that the correctness can be proven, and here indicates that the calculation of the DFG is performed by the mapped CGRA. In the verification by the mapping result verification device 1, if all nodes of the DFG are assigned to PEs 100, it is guaranteed that the calculation contents and inputs of each node of the DFG match in the calculations of all assigned PEs 100, and therefore completeness is guaranteed.

[0046] Next, a specific example of mapping result verification will be described. Fig. 3 is a diagram showing an example of a DFG and a mapping result. Fig. 4 is a diagram showing an outline of the mapping result verification process. Here, the outline of the mapping result verification process will be briefly described with reference to Figs. 3 and 4.

[0047] The information collector 11 receives the DFG 31 and the mapping result 32. The nodes 101 to 105 in the DFG 31 are nodes that execute operations given in the DFG, respectively. Furthermore, the information written in each of the nodes 101 to 105 indicates the operation that is executed at each node.

[0048] Node 111 is an input node from outside to CGRA. Node 112 is an input node that provides a fixed value used in the calculation of node 101. Node 113 is an input node that provides a fixed value used in the calculation of node 102. Node 114 is an input node that provides a fixed value used in the calculation of node 104. Here, the output values ​​from nodes 112 to 114 are actually values ​​that nodes 101, 102, and 104 have in advance, but are treated as output values ​​from input nodes in DFG31. Information written in each of nodes 111 to 114 indicates the output value from each.

[0049] 3 and 4, the output values ​​from the nodes 101 to 104 are designated n1 to n4 as output values ​​used in the calculations performed by the nodes 102 to 105. For example, the node 102 performs a calculation to add n1, which is the output value from the node 101, and c1, which is the output value from the node 113.

[0050] The mapping result 32 shows a state in which the nodes 101 to 105 are assigned to the five PEs 100 of the CGRA. Hereinafter, the PEs 100 to which the nodes 101 to 105 are assigned will be referred to as the nodes 101 to 105, respectively. The mapping result 32 includes information on the output values ​​of the nodes 101 to 105 and the names of the input ports to which the output values ​​are input. Here, the mapping result 32 is shown schematically, but in reality it is information describing the inputs and outputs to each PE 100 and the operations executed by the PE 100. The output values ​​output from the nodes 112 to 114 in the mapping result 32 are unique values ​​that the nodes 101, 102, and 104 each have in advance.

[0051] Based on the DFG 31 and the mapping result 32, the mapping result verification process is performed in the procedure shown in Fig. 4. In Fig. 4, the input and output states of signals from cycles 0 to 5 are shown in order.

[0052] The verification information generator 12 sets the output value in1 from the node 111 as the output value in the 0th cycle.

[0053] In the first cycle, the verification unit 13 performs verification on the node 101 that receives the input of the output value in the zeroth cycle. The verification unit 13 confirms that the outputs from the node 111 that are input to the input port p of the node 101 are complete in the mapping result 32. Next, the verification unit 13 confirms that the output value in1 from the node 111, which is the output value used by the node 101, exists. Furthermore, the verification unit 13 confirms from the mapping result 32 that p*c0, which corresponds to in1*c0, is executed in the node 101.

[0054] Next, the verification information generation unit 12 confirms that in1 and the operation result are output from the node 101. Then, the verification information generation unit 12 sets the input value in1 to the node 101 as the output value of the node 101 in the first cycle, and sets n1, which is the identification information of the node 101, as the output value of the operation result of the node 101 in the first cycle.

[0055] In the second cycle, the verification unit 13 performs verification on the node 102 that receives the input of the output value in the first cycle. The verification unit 13 confirms that the outputs from the node 101 that are input to the input ports p and q of the node 102 are all present in the mapping result 32. Next, the verification unit 13 confirms that the output values ​​in1 and n1 from the node 101, which are the output values ​​used by the node 102, exist. Furthermore, the verification unit 13 confirms from the mapping result 32 that the operation q+c1, which corresponds to n1+c1 that is specified in the DFG 31, is executed in the node 102.

[0056] Next, the verification information generation unit 12 confirms that in1 and the operation result are output from the node 102. Then, the verification information generation unit 12 sets the input value in1 to the node 102 as the output value of the node 102 in the second cycle, and sets n2, which is the identification information of the node 102, as the output value of the operation result of the node 102 in the second cycle.

[0057] In the third cycle, the verification unit 13 performs verification on the node 103 that receives the input of the output value in the second cycle. The verification unit 13 confirms that the outputs from the node 102 that are input to the input ports p and q of the node 103 are complete in the mapping result 32. Next, the verification unit 13 confirms that the output values ​​in1 and n2 from the node 102 that are the output values ​​used by the node 103 exist. Furthermore, the verification unit 13 confirms from the mapping result 32 that p*q, which corresponds to the operation in1*n2 specified in the DFG 31, is executed in the node 103.

[0058] Next, the verification information generation unit 12 confirms that in1 and the operation result are output from the node 103. Then, the verification information generation unit 12 sets the input value in1 to the node 103 as the output value of the node 103 in the third cycle, and sets n3, which is the identification information of the node 103, as the output value of the operation result of the node 103 in the third cycle.

[0059] In the fourth cycle, the verification unit 13 performs verification on the node 104 that receives the input of the output value of the third cycle. The verification unit 13 confirms that the outputs from the node 103 that are input to the input ports p and q of the node 104 are all present in the mapping result 32. Next, the verification unit 13 confirms that the output values ​​in1 and n3 from the node 103, which are the output values ​​used by the node 104, exist. Furthermore, the verification unit 13 confirms from the mapping result 32 that the operation q+c2, which corresponds to n3+c2 that is specified in the DFG 31, is executed in the node 104.

[0060] Next, the verification information generation unit 12 confirms that in1 and the operation result are output from the node 104. Then, the verification information generation unit 12 sets the input value in1 to the node 104 as the output value of the node 104 in the fourth cycle, and sets n4, which is the identification information of the node 104, as the output value of the operation result of the node 104 in the fourth cycle.

[0061] In the fifth cycle, the verification unit 13 performs verification on the node 105 that receives the input of the output value in the fourth cycle. The verification unit 13 confirms that the outputs from the node 104 that are input to the input ports p and q of the node 105 are all present in the mapping result 32. Next, the verification unit 13 confirms that the output values ​​in1 and n4 from the node 104, which are the output values ​​used by the node 105, exist. Furthermore, the verification unit 13 confirms from the mapping result 32 that p*q, which corresponds to in1*n4, the operation specified in the DFG 31, is executed in the node 105.

[0062] Next, the verification information generation unit 12 confirms that in1 and the operation result are output from the node 105. Then, the verification information generation unit 12 sets the input value in1 to the node 105 as the output value of the node 105 in the fifth cycle, and sets n5, which is the identification information of the node 105, as the output value of the operation result of the node 105 in the fifth cycle.

[0063] The verification unit 13 confirms that there is no PE 100 to which the output value from the node 105 is input in the fifth cycle. In this case, since there is no PE 100 to which the output value is input, the verification unit 13 takes the output from the node 105 as the calculation result. Here, a description of the confirmation of the number of outputs by the output number confirmation unit 14 will be omitted.

[0064] Furthermore, a specific example of detailed mapping result verification will be described. FIG. 5 is a diagram showing an example of a CGRA to be mapped. In CGRA120, PE100s are arranged in a 3×3 array. In the description here, numbers indicating their respective positions are described for each PE100. Here, each PE100 is represented by the number indicating its position. That is, CGRA120 has PE100s at (0,0), (0,1), (0,2), (1,0), (1,1), (1,2), (2,0), (2,1), and (2,2). Each PE100 has the input ports and output ports shown in FIG. 2. Also, input values are externally input to the p and q ports of each of the PE100s at (0,0), (0,1), and (0,2). The information described for each of the input nodes 121 corresponds to the respective output values from the input nodes 121.

[0065] FIG. 6 is a diagram showing an example of the connection between PEs. Here, as shown in FIG. 6, each of the PE100s is connected to each other. That is, when using the expression 22 in FIG. 3, the o1 output port of the PE100 at (i,j) is connected to the p input port of the PE100 at (i + 1,j). Also, the o2 output port of the PE100 is connected to the q input port of the PE100 at (i + 1,j - 1), the r output port of the PE100 at (i + 1,j), and the s output port of the PE100 at (i + 1,j + 1).

[0066] FIG. 7 is a diagram showing an example of a verification information list. The verification information generation unit 12 obtains the output value of each PE100 for each cycle and registers it in the corresponding cycle column of the verification information list 130. Here, the verification information generation unit 12 uses a set of an output port and an output value from the position of the PE100 as verification information. For example, the verification information generation unit 12 generates information such as <position of PE100, {<identification information of output port, output value>}> as verification information. The output in the first cycle of the verification information list 130 in FIG. 5 indicates that in1 was output as the output value from the o1 output port of the PE100 at the position (0,0). However, since the 0th cycle is the output from the input node, the verification information generation unit 12 uses a set of the identification information of the input node and the output value as verification information.

[0067] Based on the above, the mapping result verification process will be described. Fig. 8 is a diagram showing an example of a DFG and mapping results used in the detailed description of the mapping result verification process. DFG 201 has nodes 211 to 214 and nodes 215 to 217. Here, the identification information of nodes 211 to 214, which are input nodes, is represented as I1 to I4, respectively. Also, the identification information of nodes 215 to 217 is represented as n1 to n3, respectively. The output value of node 215 is represented as its identification information, n1. Also, the output value of node 216 is represented as its identification information, n2.

[0068] Node 215 multiplies the output value of node 211 by the output value of node 212. Node 216 multiplies the output value of node 213 by the output value of node 214. Furthermore, node 217 adds n1, which is the output value of node 215, and n2, which is the output value of node 216.

[0069] Then, node 215 of DFG 201 is mapped to PE 100 at (0,0) in mapping result 202. Also, node 216 of DFG 201 is mapped to PE 100 at (0,1) in mapping result 202. Also, node 217 of DFG 201 is mapped to PE 100 at (1,0) in mapping result 202.

[0070] 9 is a diagram showing a verification information list in which the outputs of the 0th cycle are registered. In the 0th cycle, in1 to in4 are output as output values ​​from the four input nodes, 111 to 114, respectively. Therefore, as shown in FIG. 9, the verification information generation unit 12 registers verification information in the verification information list 130, which is a combination of I1 to I4, which are the identification information of the nodes 111 to 114, and in1 to in4, which are the output values ​​from the input nodes. Then, the verification information generation unit 12 outputs the verification information list 130, in which registration has been completed, to the verification unit 13.

[0071] The verification unit 13 checks the verification information list 130. Then, verification is performed on the PE 100 of (0,0) that uses the output value of the 0th cycle. The input to the PE 100 of (0,0) is the output of the input nodes with identification information I1 and I2, and the verification unit 13 confirms that the output of the input nodes with identification information I1 and I2 exists in the 0th cycle of the verification information list 130.

[0072] Next, the verification unit 13 confirms that the output values ​​are in1 and in2 used in the node assigned to the PE 100 at (0,0) in the DFG 201. Furthermore, the verification unit 13 confirms from the connection information of the CGRA 120 that the output value for the input port p of the PE 100 at (0,0) is the output value of the input node with identification information I1, and the output value for the input port q is the output value of the input node with identification information I2. The verification unit 13 then confirms that the output value of the input node with identification information I1 is in1, and the output value of the input node with identification information I2 is in2. Therefore, the verification unit 13 can confirm that the signal values ​​obtained in the 0th cycle all match the signal values ​​output from the PE 100 that is the input source in the DFG. Furthermore, it can be confirmed that the operation assigned to the PE 100 at (0,0) is in1*in2, which matches the operation specified in the DFG 201.

[0073] The verification unit 13 similarly performs verification on the PE 100 at (0,1) that uses the output value of cycle 0. If the verification is successful for all PEs 100, the verification unit 13 outputs a notification that the validity has been verified to the verification information generation unit 12.

[0074] FIG. 10 is a diagram showing a verification information list in which the output of the first cycle is registered. As shown in FIG. 10, the verification information generation unit 12 generates verification information for the PEs 100 (0,0) and (0,1) that performed the operation in the first cycle. For example, the operation result is output from the output port o1 of the PE 100 (0,0). Therefore, for the PE 100 (0,0), the verification information generation unit 12 registers verification information indicating that the identification information of the PE 100 (0,0) is output from the output port o1 in the verification information list 130 in the first cycle. That is, as shown in FIG. 10, the verification information generation unit 12 registers <(0,0>,<{o1,n1>}> in the verification information list 130. Similarly, as shown in FIG. 10, the verification information generation unit 12 registers <(0,1>,<{o1,n2>}> in the verification information list 130.

[0075] The verification unit 13 checks the verification information list 130. Then, verification is performed on the PE 100 of (1,0) that uses the output value of the first cycle. The input of the PE 100 of (1,0) is the output values ​​of the PE 100 of (0,0) and (0,1), and the verification unit 13 confirms that the output values ​​of the PE 100 of (0,0) and (0,1) exist in the first cycle of the verification information list 130.

[0076] Next, the verification unit 13 confirms that the output values ​​used by the node assigned to the PE100 at (1,0) in the DFG201 are n1 and n2. Furthermore, the verification unit 13 confirms, from the connection information of the CGRA 120, that the output value for the input port p of the PE100 at (1,0) is the output value of the PE100 at (0,0), and the output value for the input port q is the output value of the PE100 at (0,1). The verification unit 13 then confirms that the output value of the PE100 at (0,0) is n1, and the output value of the PE100 at (0,1) is n2. Therefore, the verification unit 13 can confirm that the signal values ​​obtained in the first cycle all match the signal values ​​output from the PE100 that is the input source in the DFG. Furthermore, it can be confirmed that the operation assigned to the PE100 at (1,0) is n1+n2, which matches the operation specified in the DFG201. If the verification of the PE 100 at (1,0) is successful, the verification unit 13 outputs a notification that the validity has been verified to the verification information generation unit 12.

[0077] FIG. 11 is a diagram showing a verification information list in which the output of the second cycle is registered. As shown in FIG. 11, the verification information generation unit 12 generates verification information for the PE 100 of (1,0) that performed the operation in the second cycle. For example, the operation result is output from the output port o1 of the PE 100 of (1,0). Therefore, the verification information generation unit 12 registers verification information indicating that the identification information of the PE 100 of (1,0) has been output from the output port o1 for the PE 100 of (1,0) in the second cycle in the verification information list 130. That is, as shown in FIG. 11, the verification information generation unit 12 registers verification information indicating that the identification information of the PE 100 of (1,0) has been output from the output port o1 for the PE 100 of (1,0).<o1,n3>}> is registered in the verification information list 130.

[0078] Since there is no PE 100 that uses the output value of the second cycle, the verification unit 13 sets the output value of the second cycle as the calculation result output. In this case, the output number confirmation unit 14 determines that the verification is successful because the number of outputs of the calculation result of the DFG 201 is 1, which matches the number of calculation result outputs, and outputs a notification to the output unit 15 that the mapping result is valid.

[0079] 12 is a flowchart of the mapping result verification process according to the embodiment 1. Next, the flow of the mapping result verification process according to the embodiment 1 will be described with reference to FIG.

[0080] The verification information generator 12 registers an output value from an input node in the 0th cycle of the verification information list 130 (step S1).

[0081] Next, the verification information generating unit 12 and the verifying unit 13 initialize n to 1 (step S2).

[0082] Next, the verification unit 13 checks the correspondence with the DFG for the PE 100 that uses the output value of the (n-1)th cycle (step S3).

[0083] Then, the verification unit 13 determines whether or not the mapping result for the PE 100 that uses the output value of the (n-1)th cycle corresponds correctly to the DFG (step S4).

[0084] If the DFG correctly corresponds (step S4: Yes), the verification information generator 12 then additionally registers the nth cycle verification information including the output value of the PE 100 in the nth cycle of the verification information list 130 (step S5).

[0085] Next, the verification unit 13 determines whether or not there is a PE 100 that uses the output value of the nth cycle (step S6).

[0086] If there is a PE 100 that uses the output value of the nth cycle (step S6: Yes), the verification information generating unit 12 and the verifying unit 13 increment n by 1 (step S7). After that, the mapping result verification process returns to step S3.

[0087] On the other hand, if there is no PE 100 that uses the output value of the nth cycle (step S6: No), the output number confirmation unit 14 determines whether all the calculation results specified in the DFG exist as calculation results in the verification information list 130 (step S8).

[0088] If all the calculation results specified in the DFG exist in the verification information list 130 as calculation results (step S8: Yes), the output unit 15 outputs a notification that the mapping result is correct to the user terminal device 3 (step S9).

[0089] On the other hand, if the mapping result does not correspond correctly to the DFG (step S4: No) or if any calculation result specified by the DFG does not exist in the verification information list 130 (step S8: No), the following process is performed: That is, the output unit 15 outputs a notification that the mapping result is invalid to the user terminal device 3 (step S10).

[0090] As described above, the mapping result verification device 1 according to this embodiment uses symbolic execution for the operations performed at each node to verify that the mapping result has the same data flow as the DFG. By performing operations using abstract values ​​rather than execution using test data, verification equivalent to exhaustive verification can be performed at low cost. This makes it possible to improve the accuracy of mapping to the CGRA.

[0091] (Variation 1) In the first embodiment, the mapping result verification device 1 verifies the validity using the output value from each PE 100, but the information used for verification is not limited to this. For example, the validity can also be verified using the input value to each PE 100.

[0092] In this case, the verification information generation unit 12 registers information on inputs for each cycle as verification information in the verification information list 130. For example, the verification information generation unit 12 registers information such as <(PE position), <{input port ID, output value}> in the verification information list 130.

[0093] The verification unit 13 performs verification on inputs to each PE 100. For example, the verification unit 13 uses the verification information list 130 to check whether output values ​​used by the PE 100 for an operation match all values ​​input to the PE 100, and whether the operation specified in the DFG 31 is executed in the PE 100. By checking these, the verification unit 13 can confirm that the mapping in that cycle is valid.

[0094] Here, when an input is used, the verification information generation unit 12 uses the connection relationships of the CGRA when verifying the input value in the verification information list 130, so the verification unit 13 does not need to determine the value input to the port in each PE 100 from the connection relationships of the CGRA. However, when an output value is output from the same output port to multiple ports, the number of elements with the same value increases.

[0095] As described above, even when an input is used, the mapping result verification device 1 can properly verify the mapping result, thereby improving the accuracy of mapping to the CGRA.

[0096] (Variation 2) In the first embodiment, the mapping result verification device 1 verifies the validity of mapping for one calculation execution, but the target of verification may be a process executed by a pipeline. For example, even when the process from input of an output value from an input node to output of a calculation result is continuously and repeatedly executed by a pipeline execution, the validity of the mapping result can be verified.

[0097] In this case, when registering the output values ​​from the input nodes in the verification information list 130, the verification information generating unit 12 assigns consecutive numbers starting from 1 to the output values ​​from the input nodes, and adds information indicating which output value is the corresponding output value. It is possible to distinguish whether the information is used in pipeline processing.

[0098] In this case, the verification unit 13 also verifies the validity of the mapping result by using the verification information, the CGRA architecture, and the DFG information, as in the first embodiment. The verification unit 13 also repeats the verification for the output values ​​from the input nodes equal to the number of pipeline processes. When the number of output values ​​from the input nodes reaches the number of pipeline processes, the verification unit 13 ends the verification of the mapping result at the end of that round of verification.

[0099] As described above, the mapping result verification device 1 can verify the validity of the mapping result for pipeline processing by using abstract values. Therefore, it is possible to improve the accuracy of mapping for CGRA for pipeline processing as well. [Example]

[0100] Next, a second embodiment will be described. For example, a case where a deep neural network is realized by CGRA will be described. The activation function of a DNN may be realized by a composite function of elementary functions such as exponential, sin, cos, and errfn. In this case, the automatic mapper 2 can perform high-speed mapping by combining individual mapping results for parts corresponding to elementary functions and performing overall mapping, rather than mapping the entire DFG. In this way, in mapping by combining mapping results or mapping in which some results are replaced, the mapping result verification device 1 can represent and verify specific parts, such as parts corresponding to elementary functions, in a library-like manner.

[0101] 13 is a diagram showing an example of mapping that partially combines existing mapping results. In this example, the CGRA has a structure in which PEs 100 are arranged in a 4x4 array. In addition, in the mapping to the CGRA shown in FIG. 13, components 300 whose mapping results have been verified and whose validity has been guaranteed are used.

[0102] 14 is a diagram for explaining an extension of the mapping representation method. Here, an extension of the mapping representation method by the automatic mapper 2 for the component 300 will be explained. For example, as shown in input / output state 301, the component 300 has input ports p1, q1, p2, and q2, and output ports o1, o2, o3, and o4. If the port name of each input port is the input value and the port name of the output port is the output value, then o1=p1, o2=f(p1, p2), o3=p2, and o4=q2.

[0103] Then, as shown in the mapping result 302, the part 300 is mapped to the PEs 100 at (1,0), (1,1), and (2,0), where each PE 100 has p and q as input ports.

[0104] When mapping is performed as in mapping result 302, as shown in input / output 303, input p1 of component 300 corresponds to an input to the input port p of PE100 at (1,0). Here, the input value to the input port p of PE100 at (1,0) is represented as p(1,0). Also, input q1 corresponds to an input to the input port q of PE100 at (1,0). Here, the input value to the input port q of PE100 at (1,0) is represented as q(1,0). Also, input p2 corresponds to an input to the input port p of PE100 at (1,1). Here, the input value to the input port p of PE100 at (1,1) is represented as p(1,1). Also, input q2 corresponds to an input to the input port q of PE100 at (1,1). Here, the input value to the input port q of PE100 at (1,1) is represented as q(1,1).

[0105] That is, o1=p(1,0), and o1 is output two cycles after input to component 300. Also, o2=f(p(1,0),p(1,1)), and o2 is output two cycles after input to component 300. Also, o3=p(1,1), and o3 is output one cycle after input to component 300. Also, o4=q(1,1), and o4 is output one cycle after input to component 300.

[0106] Verification of the mapping result obtained by mapping using such a mapping expression method will be described. A mapping result verification device 1 according to this embodiment is also shown in the block diagram of Fig. 1. In the following description, description of the operation of each unit similar to that of the first embodiment will be omitted.

[0107] Here, the existing mapping result in the mapping result of the mapping that combines existing mapping results is an example of a “predetermined mapping result that executes a predetermined operation including one or more operations.” That is, the information collecting unit 11 acquires the mapping result of the mapping that is performed using the predetermined mapping result that executes a predetermined operation including one or more operations.

[0108] The verification information generation unit 12 receives the DFG and the mapping result as input from the information collection unit 11. Next, the verification information generation unit 12 sets the timing of the output from the input node as cycle 0, and sets the output value from the virtual PE 100 corresponding to the input node as the output value in cycle 0. Then, the verification information generation unit 12 outputs the generated output value to the verification unit 13.

[0109] The verification information generation unit 12 sets the input value as the output value when the input value is output as is by the PE 100. In addition, when the operation result becomes the output value, the verification information generation unit 12 sets the identification information of the PE 100 that outputs the operation result as the output value.

[0110] Thereafter, when the verification information generation unit 12 receives a notification from the verification unit 13 that the validity has been verified for each cycle in order from the first cycle, the verification information generation unit 12 generates an output value from each PE 100 for the next cycle. Then, the verification information generation unit 12 outputs the generated output value to the verification unit 13.

[0111] The verification unit 13 receives an input of the output value in the 0th cycle. Then, the verification unit 13 executes a first verification and a second verification for the PE 100 to which the output value is input in the 1st cycle. If the validity of the mapping result in that cycle can be confirmed by the first verification and the second verification, the verification unit 13 outputs a notification that the validity has been verified to the verification information generation unit 12.

[0112] Thereafter, when the verification unit 13 receives verification information from the verification information generation unit 12, it selects the cycle with the smallest number of cycles after the cycle for which the validity verification has already been completed from among the acquired verification information as the verification target. Then, the verification unit 13 performs a first verification and a second verification for the PE 100 to which an output value is input in the cycle to be verified. If the first verification and the second verification confirm the validity of the mapping result in that cycle, the verification unit 13 outputs a notification that the validity verification has been completed to the verification information generation unit 12. Furthermore, if there is no next PE 100 to which an output value is input, the verification unit 13 selects the output value as one of the calculation results output by the CGRA.

[0113] Then, when there is no PE 100 that will operate in the next cycle for all output values, the verification unit 13 collectively outputs the output values ​​that have been set as the calculation result output of the CGRA together with the DFG to the output number confirmation unit 14. In this way, the verification unit 13 verifies whether the mapping result matches the data flow graph by using the calculation result obtained by performing a predetermined calculation using symbols for the predetermined mapping result.

[0114] Fig. 15 is a diagram illustrating an example of a mapping result according to Example 2. Here, a case will be described in which a DFG including a part of the DFG 304 in Fig. 15 is mapped to a CGRA and a mapping result including a part of the mapping result 305 is obtained.

[0115] DFG304 has input nodes 311 and 312, and nodes 321 and 322. Node 311 inputs in1 as an output value to the CGRA. Node 312 inputs in2 as an output value to the CGRA. Node 321 executes an operation expressed by a function f(in1, in2). The operation result of node 321 is an output value output to node 322. Node 322 executes an operation expressed by a function g(n1, in2).

[0116] In the mapping result 305, node 321 of DFG 304 is mapped as component 300. Furthermore, node 322 of DFG 304 is mapped to PE 100 of (3.0). Here, as shown in input / output state 306, PE 100 has two input ports, p and q. Furthermore, PE 100 has two output ports, o1 and o2. Furthermore, component 300 has the input port and output port shown in input / output state 301 in FIG. 14. Furthermore, in the mapping result 305 of FIG. 14, the output value output from each output port in response to the input value is written near each PE 100 and component 300. Here, the input value is shown by the name of the input port.

[0117] Based on the above, a description will be given of the mapping result verification process according to Example 2. Fig. 16 is a diagram showing the transition of the verification information list in the mapping verification process according to Example 2. Here, the identification information of node 311 is I1, and the identification information of node 312 is I2.

[0118] In the 0th cycle, in1 is output from node 311 as an output value, and in2 is output from node 312 as an output value. Therefore, as shown in state 331 in FIG. 16 , the verification information generation unit 12 registers verification information that combines I1 and I2, which are the identification information of nodes 311 and 312, respectively, with in1 and in2, which are the output values ​​from each of them, in the verification information list 130. Then, the verification information generation unit 12 outputs the verification information list 130, for which registration has been completed, to the verification unit 13.

[0119] The verification unit 13 checks the verification information list 130. Then, verification is performed on the PE 100 of (0,0) that uses the output value of the 0th cycle. The input to the PE 100 of (0,0) is the output of the input node with identification information I1, and the verification unit 13 confirms that the output of the input node with identification information I1 exists in the 0th cycle of the verification information list 130.

[0120] Next, the verification unit 13 confirms that the output value used in the node assigned to the PE 100 at (0,0) in the DFG 304 is in1. Furthermore, the verification unit 13 confirms from the connection information of the CGRA that the output value for the input port p of the PE 100 at (0,0) is the output value of the input node with identification information I1. The verification unit 13 then confirms that the output value of the input node with identification information I1 is in1. Therefore, the verification unit 13 can confirm that the values ​​of the signals obtained in the 0th cycle all match the values ​​of the signals output from the PE 100 that is the input source in the DFG 304. Furthermore, the verification unit 13 can confirm that no operation is assigned to the PE 100 at (0,0) and that the input value is passed through.

[0121] The verification unit 13 similarly performs verification on the PE 100 at (0,1) that uses the output value of cycle 0. If the verification is successful for all PEs 100, the verification unit 13 outputs a notification that the validity has been verified to the verification information generation unit 12.

[0122] Next, in the first cycle, the PE 100 at (0,0) and the PE 100 at (0,1) each pass the input value. Therefore, as shown in state 332, the verification information generation unit 12 registers verification information in the verification information list 130, which is a combination of (0,0), which is the identification information of the PE 100 at (0,0), and in1, which is the output value from the output ports of o1 and o2. The verification information generation unit 12 also registers verification information in the verification information list 130, which is a combination of (0,1), which is the identification information of the PE 100 at (0,1), and in1, which is the output value from the output ports of o1 and o2. Then, the verification information generation unit 12 outputs the verification information list 130, for which registration has been completed, to the verification unit 13.

[0123] The verification unit 13 checks the verification information list 130. Then, the verification unit 13 determines the first cycle, which has the smallest number of cycles registered in the rows of the verification information list 130 after the zeroth cycle, for which verification has already been completed, as the verification target.

[0124] The verification unit 13 performs verification on the component 300 that uses the output value of the first cycle. The input to the component 300 is the output of the PE 100 at (0,0) and the output of the PE 100 at (0,1), and the verification unit 13 confirms that the respective identification information exists in the first cycle of the verification information list 130.

[0125] Next, the verification unit 13 confirms that the output values ​​used at the node assigned to the component 300 in the DFG 304 are in1 and in2. Furthermore, the verification unit 13 confirms, from the connection information of the CGRA, that the output value for the input port p1 of the component 300 is the output value for the output port o1 of the PE 100 having identification information (0,0). The verification unit 13 then confirms that the output value for the output port o1 of the PE 100 having identification information (0,0) is in1. Furthermore, the verification unit 13 confirms, from the connection information of the CGRA, that the output value for the input port q1 of the component 300 is the output value for the output port o1 of the PE 100 having identification information (0,1). The verification unit 13 then confirms that the output value for the output port o1 of the PE 100 having identification information (0,1) is in2. Furthermore, the verification unit 13 confirms, from the connection information of the CGRA, that the output value for the input port p2 of the component 300 is the output value for the output port o2 of the PE 100 having identification information (0,0). Then, the verification unit 13 confirms that the output value of the output port o2 of the PE 100 at (0,0) is in1. Furthermore, the verification unit 13 confirms from the connection information of the CGRA that the output value of the input port q2 of the component 300 is the output value of the output port o2 of the PE 100 at (0,1) as identified. Then, the verification unit 13 confirms that the output value of the output port o2 of the PE 100 at (0,1) is in2. Therefore, the verification unit 13 can confirm that the signal values ​​obtained in the first cycle all match the signal values ​​output from the input source PE 100 in the DFG 304.

[0126] The verification unit 13 also confirms that the operation executed by the component 300 matches f(in1, in2), which is the operation executed by the node 321 of the DFG 304. After that, the verification unit 13 outputs a notification that the validity has been verified to the verification information generation unit 12.

[0127] Next, the verification information generator 12 generates verification information regarding the output from the component 300. In the second cycle, the component 300 outputs in1 from the output port o3 and in2 from the output port o4. In the third cycle, the component 300 outputs in1 from the output port o3 and in2 from the output port o4. The verification information generator 12 already knows the number of cycles required from when an input is made to the component 300 until an output is made from each output port of the component 300, and therefore can confirm from which output port of the component 300 an output will be made in each cycle.

[0128] The verification information generation unit 12 identifies that the PE 100 that performs the second cycle output of the component 300 is the PE 100 at (1,1). Next, as shown in state 333, the verification information generation unit 12 registers verification information that combines (1,1), which is the identification information of the PE 100 at (1,1), and in1, which is the output value from the output port o3 of the component 300, in the second cycle of the verification information list 130. In addition, the verification information generation unit 12 registers verification information that combines (1,1), which is the identification information of the PE 100 at (1,1), and in2, which is the output value from the output port o4 of the component 300, in the second cycle of the verification information list 130.

[0129] The verification information generation unit 12 also identifies that the PE 100 performing the third cycle output of the component 300 is the PE 100 at (2,0). Next, as shown in state 333, the verification information generation unit 12 registers verification information that combines (2,0), which is the identification information of the PE 100 at (2,0), with in1, which is the output value from the output port o1 of the component 300, in the third cycle in the verification information list 130. Furthermore, since the output value from the output port o2 of the component 300 is the calculation result, the verification information generation unit 12 sets this output value as the identification information of the component 300. Here, the identification information of the component 300 is set to n1. Therefore, the verification information generation unit 12 registers verification information that combines (2,0), which is the identification information of the PE 100 at (2,0), with n1, which is the output value from the output port o2 of the component 300, in the third cycle in the verification information list 130. Then, the verification information generating unit 12 outputs the verification information list 130 for which registration has been completed to the verifying unit 13.

[0130] The verification unit 13 checks the verification information list 130. Then, the verification unit 13 determines the second cycle, which has the smallest number of cycles registered in the rows of the verification information list 130 after the first cycle for which verification has already been completed, as the verification target.

[0131] The verification unit 13 performs verification on the PE 100 at (2,1) that uses the output value of the second cycle. The input to the PE 100 at (2,1) is the output of the PE 100 at (1,1) in the component 300, and the verification unit 13 confirms that the identification information of the PE 100 at (1,1) exists in the first cycle of the verification information list 130.

[0132] Next, the verification unit 13 confirms that there is no node assigned to the PE 100 at (2,1) in the DFG 304, and confirms that the PE 100 at (2,1) is a node that passes an input value and that the output values ​​that it passes are in1 and in2. Furthermore, the verification unit 13 confirms from the connection information of the CGRA that the value input to the PE 100 at (2,1) is the output value of the output ports o3 and o4 of the component 300. The verification unit 13 then confirms that the output value of the output port o3 of the component 300 is in1. The verification unit 13 also confirms that the output value of the output port o4 of the component 300 is in2. Therefore, the verification unit 13 can confirm that the signal values ​​obtained in the second cycle all match the signal values ​​output from the PE 100 that is the input source in the DFG 304. Furthermore, the verification unit 13 can confirm that no operation is assigned to the PE 100 at (2,1) and that it passes an input value. Thereafter, the verification unit 13 outputs a notification that the validity has been verified to the verification information generation unit 12.

[0133] Next, the verification information generation unit 12 generates verification information regarding the output from the PE 100 at (2,1). The PE 100 at (2,1) outputs in1 from the output port o1 and outputs in2 from the output port o2 in the third cycle. Therefore, as shown in state 334, the verification information generation unit 12 registers verification information that combines (2,1), which is the identification information of the PE 100 at (2,1), and in2, which is the output value from the output port o1 of the PE 100 at (2,1), in the verification information list 130 in the third cycle. Furthermore, the verification information generation unit 12 registers verification information that combines (2,1), which is the identification information of the PE 100 at (2,1), and in2, which is the output value from the output port o2 of the PE 100 at (2,1), in the verification information list 130 in the third cycle.

[0134] The verification unit 13 checks the verification information list 130. Then, the verification unit 13 selects the third cycle, which has the smallest number of cycles registered in the rows of the verification information list 130 from the second cycle onwards for which verification has already been completed, as the verification target.

[0135] The verification unit 13 performs verification on the PE 100 at (3,0) that uses the output value of the third cycle. The input to the PE 100 at (3,0) is the output of the PE 100 at (2,1) and the PE 100 at (2,0) in the component 300, and the verification unit 13 confirms that the identification information of the PE 100 at (2,0) and the PE 100 at (2,1) exists in the third cycle of the verification information list 130.

[0136] Next, the verification unit 13 confirms that the output values ​​used in the node assigned to the PE 100 at (3,0) in the DFG 304 are n1 and in2. Furthermore, the verification unit 13 confirms that the values ​​input to the PE 100 at (3,0) from the connection information of the CGRA are the output value of the output port o1 of the component 300 and the output value of the output port o1 of the PE 100 at (2,1). The verification unit 13 then confirms that the output value of the output port o1 of the component 300 is n1. Furthermore, the verification unit 13 confirms that the output value of o1 of the PE 100 at (2,1) is in2. Therefore, the verification unit 13 can confirm that the signal values ​​obtained in the second cycle all match the signal values ​​output from the PE 100 that is the input source in the DFG 304. Furthermore, the verification unit 13 confirms that the operation assigned to the PE 100 at (3,0) matches g(n1, in2), which is the operation executed at the node 322 in the DFG 304.

[0137] The verification unit 13 similarly performs verification on the PE 100 at (3,1) that uses the output value of the third cycle. If the verification is successful for all PEs 100, the verification unit 13 outputs a notification that the validity has been verified to the verification information generation unit 12.

[0138] Thereafter, the verification information generation unit 12 generates verification information for the output of the fourth cycle and registers the generated verification information in the verification information list 130, as shown in state 335. Thereafter, the verification unit 13 and the verification information generation unit 12 repeat the verification until there is no PE 100 that uses the output value.

[0139] As described above, the mapping result verification device 1 according to the present embodiment can verify the mapping result of a mapping that combines existing mapping results and determine the validity of the mapping result. In this way, even for a mapping result whose validity is partially guaranteed and whose validity does not need to be verified, it is possible to verify that the mapping result has the same data flow as the DFG by using symbolic execution for the operations. Therefore, even in such cases, by performing operations using abstract values, it is possible to perform a verification equivalent to a comprehensive verification at low cost, thereby improving the accuracy of mapping for a CGRA.

[0140] 17 is a diagram showing an example of how to use the mapping result verification device 1. Here, how to use the mapping result verification device 1 described in each of the above embodiments and modifications will be described with reference to FIG.

[0141] Configuration 401 shows how to use the mapping result verification device 1 when the automatic mapper 2 is under development. For example, when the automatic mapper 2 is under development, the automatic mapper 2 is made to generate a mapping result for a specified DFG. The mapping result verification device 1 then verifies the validity of the mapping result using the specified DFG and the mapping result. If the mapping result is incorrect, the verification result can be fed back to the development of the automatic mapper 2 to correct the algorithm of the automatic mapper 2.

[0142] Configuration 402 shows how the mapping result verification device 1 is used when the mapping result generated by the automatic mapper 2 is manually improved. For example, a user modifies a mapping result generated by the automatic mapper 2 based on a predetermined DFG, the validity of which has already been confirmed, to generate a manually improved mapping result. The mapping result verification device 1 then verifies the validity of the manually improved mapping result using the predetermined DFG and the manually improved mapping result. If the mapping result is incorrect, the user can correct the manual improvement based on the verification result.

[0143] Configuration 403 shows how the mapping result verification device 1 is used for manual mapping. For example, it is conceivable that a user manually performs mapping based on a predetermined DFG to generate a mapping result without using the automatic mapper 2. Even in such a case, the mapping result verification device 1 can verify the validity of the mapping result of the manual mapping using the predetermined DFG and the mapping result obtained by the manual mapping. If the mapping result is incorrect, the user can make corrections to the manual mapping based on the verification result.

[0144] (Hardware configuration) 18 is a diagram showing the hardware configuration of the mapping result verification device 1. Next, an example of a hardware configuration for realizing each function of the mapping result verification device 1 will be described with reference to FIG.

[0145] 18, the mapping result verification device 1 includes, for example, a CPU (Central Processing Unit) 91, a memory 92, a hard disk 93, and a network interface 94. The CPU 91 is connected to the memory 92, the hard disk 93, and the network interface 94 via a bus.

[0146] The network interface 94 is an interface for communication between the mapping result verification device 1 and an external device. The network interface 94 relays, for example, communication between the automatic mapper 2 and the user terminal device 3 and the CPU 91. For example, the network interface 94 is used in the information collection unit 11 and the output unit 15 for communication with external devices.

[0147] The hard disk 93 is an auxiliary storage device that stores various programs, including programs for realizing the functions of the information collecting unit 11, the verification information generating unit 12, the verifying unit 13, the output number confirming unit 14, and the output unit 15, as illustrated in FIG.

[0148] The memory 92 is a main storage device and may be, for example, a dynamic random access memory (DRAM).

[0149] The CPU 91 reads various programs from the hard disk 93, expands them into the memory 92, and executes them. As a result, the CPU 91 realizes the functions of the information collection unit 11, the verification information generation unit 12, the verification unit 13, the output number confirmation unit 14, and the output unit 15 illustrated in FIG.

[0150] In addition, in this embodiment, the mapping result verification device 1 is a device different from the automatic mapper 2 and the user terminal device 3, but this is not limited to this, and it is also possible to incorporate the functions of the mapping result verification device 1 into the automatic mapper 2 or the user terminal device 3. [Explanation of symbols]

[0151] 1. Mapping result verification device 2 Automapper 3. User terminal device 11 Information Gathering Department 12 Verification information generation unit 13 Verification Department 14 Output number confirmation section 15 Output section

Claims

1. A data flow graph representing a predetermined calculation including a plurality of operations and a mapping result obtained by mapping the data flow graph onto a CGRA having a plurality of arithmetic units are obtained; For each of the first computing units to which the operations are assigned in the mapping result, it is verified whether or not the mapping result matches the data flow graph based on the operation result obtained by executing the operation. A mapping result verification program that causes a computer to execute a process.

2. causing the computer to further execute a process of generating verification information including information on output values ​​of the arithmetic units used in the mapping result; The verification process includes a process of comparing the verification information with information on the output value of the operation in the data flow graph.

2. The mapping result verification program according to claim 1.

3. the obtaining process includes a process of obtaining the mapping result, which is used as information to be input to another computing unit or as a calculation result of the predetermined calculation, output from the first computing unit and including the calculation result; The verification process includes a process of comparing information to be input to the operation assigned to the first operation unit in the data flow graph with information to be input to the first operation unit in the mapping result, and verifying whether the mapping result and the data flow graph match.

2. The mapping result verification program according to claim 1.

4. 4. The mapping result verification program according to claim 3, wherein the verification process compares, based on information indicating a connection relationship between the computing units, information to be input to the first computing unit in the data flow graph with information to be input to the first computing unit in the mapping result.

5. 4. The mapping result verification program according to claim 3, wherein the verification process includes a process of comparing the number of calculation results indicated by the data flow graph with the number of calculation results obtained from the mapping result.

6. The obtaining process includes obtaining the mapping result of the mapping performed using a predetermined mapping result that performs a predetermined operation including one or more operations; The verification process includes a process of verifying whether the mapping result matches the data flow graph by using an operation result obtained by executing the predetermined operation using symbols for the predetermined mapping result.

2. The mapping result verification program according to claim 1.

7. The information processing device A data flow graph representing a predetermined calculation including a plurality of operations and a mapping result obtained by mapping the data flow graph onto a CGRA having a plurality of arithmetic units are obtained; For each of the first computing units to which an operation is assigned in the mapping result, it is verified whether or not the mapping result matches the data flow graph based on the operation result obtained by executing the operation. A mapping result verification method comprising:

8. an information collection unit that acquires a data flow graph representing a predetermined calculation including a plurality of operations and a mapping result obtained by mapping the data flow graph to a CGRA having a plurality of operation units; a verification unit that verifies whether or not the mapping result matches the data flow graph based on an operation result obtained by executing the operation for each first operation unit to which an operation is assigned in the mapping result; A mapping result verification device comprising:

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