Overvoltage protection device and package including the same

Abstract

To provide an overvoltage protection element which is constituted on the upper surface of one semiconductor substrate and in which a current flows along the main surface of the semiconductor substrate, and to provide a package.SOLUTION: The overvoltage protection element 100 includes a semiconductor substrate 3, first conductivity-type first and third well regions 111 and 211 embedded in the upper surface of the semiconductor substrate 3, and second conductivity-type second and fourth well regions 112 and 212. A first diffusion region 111a of the first conductivity type and a second diffusion region 111b of the second conductivity type, a third diffusion region 112a of the first conductivity type and a fourth diffusion region 112b of the second conductivity type, a fifth diffusion region 211a of the first conductivity type, and a sixth diffusion region 212b of the second conductivity type are embedded in the upper surfaces of the first, second, third, and fourth well regions 111, 112, 211, and 212, respectively. The first and second diffusion regions 111a and 111b are connected to the first electrodes T1, the third, fourth, and sixth diffusion regions 112a, 112b, and 212b are connected to the second electrodes T2, and the fifth diffusion region 211a is connected to the third electrodes T3.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] SUMMARY OF THE DISCLOSURE Embodiments of the present disclosure relate to overvoltage protection devices and packages that include overvoltage protection devices. [Background technology]

[0002] Conventionally, semiconductor devices such as ICs (Integrated Circuits) and LSIs (Large-scale integration) use overvoltage protection elements to protect downstream ICs from unexpected surges caused by static electricity and power supply variations. Overvoltage protection elements include ESD (electrostatic discharge) protection elements. In some cases, overvoltage protection elements are built into ICs and LSIs, while in other cases, overvoltage protection elements manufactured separately from ICs are used in combination with ICs. Overvoltage protection elements enter a low-resistance state only when a surge voltage is applied, allowing the surge current to flow (escape) safely.

[0003] Types of overvoltage protection elements include diodes such as transient voltage suppressors (TVS) diodes, npn or pnp bipolar transistors, and thyristors. Overvoltage protection elements have polarity, and can be unidirectional or bidirectional. Unidirectional overvoltage protection elements are used in single-polarity circuits such as LH (Low-High) circuits. Bidirectional overvoltage protection elements can protect both positive and negative polarities, making them suitable for protecting bipolar signals or data lines such as Controller Area Networks (CAN).

[0004] An example of an overvoltage protection element separated from an IC is as follows: An overvoltage protection element has a first electrode arranged on the main surface of a semiconductor substrate such as silicon, a second electrode arranged on the back surface opposite the main surface of the semiconductor substrate, and a thyristor and a diode arranged in parallel between the first and second electrodes in a direction perpendicular to the main surface of the substrate. This overvoltage protection element has unidirectional polarity and is configured singly on a single semiconductor substrate. For example, when an overvoltage higher than a predetermined voltage is applied to the second electrode relative to the first electrode, current flows from the second electrode to the first electrode in a direction perpendicular to the main surface of the substrate. Based on the direction of the current path, this type of overvoltage protection element will be referred to as a unidirectional vertical overvoltage protection element, and a semiconductor substrate equipped with a unidirectional vertical overvoltage protection element will be referred to as a unidirectional vertical overvoltage protection chip. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Patent Publication No. 2021-190531 [Patent Document 2] Patent Publication No. 2021-057491

[0006] [overview] By connecting two of the above-mentioned unidirectional vertical overvoltage protection chips in series as shown below, an overvoltage protection element with a thyristor and diode connected in series can be configured. Specifically, the first electrode of one chip is connected to the first electrode of the other chip, the second electrode of one chip is connected to the signal line as the first terminal, and the second electrode of the other chip is connected to the ground terminal as the second terminal. When an overvoltage is applied between the first and second terminals, the surge current can be released via the current path formed by the thyristor of one chip and the diode of the other chip connected in series.

[0007] However, when two unidirectional vertical overvoltage protection chips are used to construct an overvoltage protection element in which a thyristor and a diode are connected in series, there are problems in that the volume occupied by the overvoltage protection element increases, and the parasitic capacitance connected to the signal line and manufacturing costs increase.

[0008] In view of the above-mentioned problems, an object of the present disclosure is to provide an overvoltage protection element that is configured on the upper surface of a single semiconductor substrate and includes a thyristor and a diode connected in series, through which a surge current flows along the main surface of the semiconductor substrate, and a package that includes the overvoltage protection element.

[0009] An overvoltage protection element according to one embodiment of the present disclosure includes a semiconductor substrate, a first well region of a first conductivity type embedded in an upper surface of the semiconductor substrate, and a second well region of a second conductivity type embedded in the upper surface of the semiconductor substrate and spaced apart from the first well region. The overvoltage protection element further includes a third well region of the first conductivity type and a fourth well region of the second conductivity type embedded in the upper surface of the semiconductor substrate and spaced apart from the first and second well regions. The third and fourth well regions are embedded and spaced apart from each other.

[0010] A first diffusion region of a first conductivity type and a second diffusion region of a second conductivity type are embedded and spaced apart from each other in a portion of the upper surface of the first well region. A third diffusion region of the first conductivity type and a fourth diffusion region of the second conductivity type are embedded and spaced apart from each other in a portion of the upper surface of the second well region. A fifth diffusion region of the first conductivity type is embedded and spaced apart from each other in a portion of the upper surface of the third well region. A sixth diffusion region of the second conductivity type is embedded and spaced apart from each other in a portion of the upper surface of the fourth well region.

[0011] The overvoltage protection element further includes a first electrode, a second electrode, and a third electrode. The first electrode is electrically connected to the first diffusion region and the second diffusion region. The second electrode is electrically connected to the third diffusion region, the fourth diffusion region, and the sixth diffusion region. The third electrode is electrically connected to the fifth diffusion region. The arrangement of the second diffusion region, the first well region, the second well region, and the third diffusion region forms a first pnpn junction, and the arrangement of the fourth well region and the third well region forms a second pn junction. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a cross-sectional view of an overvoltage protection element according to a first embodiment. [Figure 2] FIG. 2 is a diagram showing a current path of the overvoltage protection element according to the first embodiment. [Figure 3] FIG. 3 is a plan view of a well region and a diffusion region of the overvoltage protection element according to the first embodiment. [Figure 4] FIG. 4 is an enlarged plan view of the well region and diffusion region of the thyristor of the overvoltage protection element according to the first embodiment. [Figure 5] FIG. 5 is a plan view of metal wiring of the overvoltage protection element according to the first embodiment. [Figure 6] FIG. 6 is a perspective view of a thyristor of the overvoltage protection element according to the first embodiment. [Figure 7] FIG. 7 is a plan view of the entire overvoltage protection element according to the first embodiment. [Figure 8] FIG. 8 is a diagram showing an example of connection of the overvoltage protection element according to the first embodiment. [Figure 9A] FIG. 9A is a plan view of a package including the overvoltage protection element according to the first embodiment. [Figure 9B] FIG. 9B is a front view of a package including the overvoltage protection element according to the first embodiment. [Figure 10A] FIG. 10A is a cross-sectional view of an overvoltage protection element according to the second embodiment. [Figure 10B] FIG. 10B is a cross-sectional view of the overvoltage protection element according to the second embodiment. [Figure 11A] FIG. 11A is a diagram showing a current path of the overvoltage protection element according to the second embodiment. [Figure 11B] FIG. 11B is a diagram showing a current path of the overvoltage protection element according to the second embodiment. [Figure 12] FIG. 12 is a plan view of the entire overvoltage protection element according to the second embodiment. [Figure 13] FIG. 13 is a plan view of metal wiring of the overvoltage protection element according to the second embodiment. [Figure 14] FIG. 14 is a diagram showing an example of connection of the overvoltage protection element according to the second embodiment. [Figure 15A] FIG. 15A is a cross-sectional view of an overvoltage protection element according to a third embodiment. [Figure 15B] FIG. 15B is a cross-sectional view of the overvoltage protection element according to the third embodiment. [Figure 16A] FIG. 16A is a diagram showing a current path of the overvoltage protection element according to the third embodiment. [Figure 16B] FIG. 16B is a diagram showing a current path of the overvoltage protection element according to the third embodiment. [Figure 17] FIG. 17 is a plan view of the entire overvoltage protection element according to the third embodiment. [Figure 18] FIG. 18 is a plan view of metal wiring of the overvoltage protection element according to the third embodiment. [Figure 19] FIG. 19 is a diagram illustrating an example of connections of overvoltage protection elements according to the third embodiment. [Figure 20A] FIG. 20A is a cross-sectional view of an overvoltage protection element according to the fourth embodiment. [Figure 20B] FIG. 20B is a cross-sectional view of the overvoltage protection element according to the fourth embodiment. [Figure 21A] FIG. 21A is a diagram showing a current path of the overvoltage protection element according to the fourth embodiment. [Figure 21B] FIG. 21B is a diagram showing a current path of the overvoltage protection element according to the fourth embodiment. [Figure 22] FIG. 22 is a plan view of the entire overvoltage protection element according to the fourth embodiment. [Figure 23] FIG. 23 is a diagram showing an example of connection of the overvoltage protection element according to the fourth embodiment. [Figure 24A] FIG. 24A is a plan view of a package including an overvoltage protection element according to the fourth embodiment. [Figure 24B]FIG. 24B is a front view of a package including an overvoltage protection element according to the fourth embodiment. [Figure 25] FIG. 25 is an enlarged plan view of the well region and diffusion region of the thyristor of the overvoltage protection element according to the fifth embodiment. [Figure 26A] FIG. 26A is a cross-sectional view of an overvoltage protection element according to a fifth embodiment. [Figure 26B] FIG. 26B is a cross-sectional view of the overvoltage protection element according to the fifth embodiment. [Figure 27] FIG. 27 is a plan view of the well region and diffusion region of the thyristor of the overvoltage protection element according to the sixth embodiment. [Figure 28] FIG. 28 is an enlarged plan view of the well region and diffusion region of the thyristor of the overvoltage protection element according to the seventh embodiment. [Figure 29A] FIG. 29A is a plan view of a package including an overvoltage protection element according to the eighth embodiment. [Figure 29B] FIG. 29B is a front view of a package including an overvoltage protection element according to the eighth embodiment.

[0013] [Detailed explanation] The embodiments will be described with reference to the drawings. In the following description of the drawings, identical or similar parts will be denoted by identical or similar reference numerals, and their description will be omitted. The drawings are schematic. The dimensional proportions in the drawings have been exaggerated for the sake of explanation, and may differ from the actual proportions.

[0014] Furthermore, the embodiments shown below are merely examples of devices or methods for embodying the technical ideas, and do not specify the materials, shapes, structures, arrangements, etc. of each component part. Various modifications can be made to these embodiments within the scope of the claims.

[0015] [First embodiment] (Configuration of overvoltage protection element) Fig. 1 is a cross-sectional view of an overvoltage protection device 100 according to a first embodiment. Fig. 1 is a cross-sectional view taken along lines I1-I2 and I3-I4 in the plan views of Figs. 3, 4 and 5, which will be described later.

[0016] In the following description, an XYZ coordinate system, which is an example of a Cartesian coordinate system, is used. That is, a plane parallel to the main surface of the semiconductor substrate 3 constituting the overvoltage protection device 100 is defined as the XY plane, and a normal direction perpendicular to the XY plane is defined as the Z direction. The X axis and Y axis are defined as two orthogonal directions in the XY plane.

[0017] The overvoltage protection element 100 is configured on the upper surface of a semiconductor substrate 3. In the first embodiment, the semiconductor substrate 3 is an intrinsic (i-type) semiconductor. However, the semiconductor substrate 3 may be a p-type semiconductor. The semiconductor substrate 3 may be silicon or a semiconductor other than silicon. On the upper surface of the semiconductor substrate 3, a well region pair 11 is configured in a region along I1-I2, and a diode 2 is configured in a region along I3-I4. The well region pair 11 is included in a thyristor 1, which will be described later with reference to FIG. 3.

[0018] First, the cross-sectional structure of the thyristor 1 taken along line I1-I2 including the well region pair 11 will be described.

[0019] In the well region pair 11, a first well region 111 of a first conductivity type and a second well region 112 of a second conductivity type are embedded in the upper surface of the semiconductor substrate 3 and spaced apart from each other in the X direction, which is a second direction. In the first embodiment, the first conductivity type is n-type and the second conductivity type is p-type. A first diffusion region 111a of the first conductivity type and a second diffusion region 111b of the second conductivity type are embedded in a portion of the upper surface of the first well region 111 and spaced apart from each other in the X direction. Furthermore, a third diffusion region 112a of the first conductivity type and a fourth diffusion region 112b of the second conductivity type are embedded in a portion of the upper surface of the second well region 112 and spaced apart from each other in the X direction.

[0020] A contact 31a is disposed on the upper surface of the first diffusion region 111a, and a contact 31b is disposed on the upper surface of the second diffusion region 111b. An M1 wiring 41, which is a first-layer metal wiring, is disposed above the contacts 31a and 31b so as to connect to the upper surfaces of the contacts 31a and 31b, and the contacts 31a and 31b are connected by the M1 wiring 41. Here, the direction toward the M1 wiring as viewed from the well region is defined as the upward direction, and the direction toward the well region as viewed from the M1 wiring is defined as the downward direction. Similarly, a contact 32a is disposed on the upper surface of the third diffusion region 112a, and a contact 32b is disposed on the upper surface of the fourth diffusion region 112b. An M1 wiring 42 is disposed above the contacts 32a and 32b so as to connect to the upper surfaces of the contacts 32a and 32b, and the contacts 32a and 32b are connected by the M1 wiring 42.

[0021] A contact 51 is arranged on the upper surface of the M1 wiring 41, and a contact 52 is arranged on the upper surface of the M1 wiring 42. In the cross-sectional view along I1-I2, an insulating film 71 is arranged in a region from the main surface of the semiconductor substrate 3 to the height of the upper surfaces of the contacts 51 and 52, where the contacts 31a, 31b, 32a, 32b, 51, 52 and the M1 wirings 41 and 42 are not present.

[0022] Above the contacts 51 and 52, M2 wirings 61 and 62, which are second-layer metal wirings, are respectively arranged so as to connect to the upper surfaces of the contacts 51 and 52. In the cross-sectional view along I1-I2, the insulating film 72 is arranged in a region from the main surface of the insulating film 71 to a height higher than the upper surfaces of the M2 wirings 61 and 62, where the M2 wirings 61 and 62 are not present.

[0023] The insulating film 71 is an interlayer insulating film between the semiconductor substrate 3, the M1 wiring 41, and the M2 wiring 42, and serves to insulate between the wirings in the multilayer wiring structure of the overvoltage protection device 100. The insulating film 72 coats the surface of the overvoltage protection device 100 and serves as a protective film to prevent influence from the external environment and adhesion of contaminants.

[0024] The contacts 31a and 31b, the M1 wiring 41, the contact 51, and the M2 wiring 61 are electrically connected to form a first electrode T1. The first electrode T1 is electrically connected to the first diffusion region 111a and the second diffusion region 111b. Although not shown in FIG. 1, an opening region where the insulating film 72 is not disposed is provided on the upper surface of the M2 wiring 61 at a position different from the cross section taken along I1-I2 in FIG. 1. In the opening region provided on the upper surface of the M2 wiring 61, the first electrode T1 can be electrically connected to a terminal provided outside the overvoltage protection device 100.

[0025] The contacts 32a and 32b, the M1 wiring 42, the contact 52, and the M2 wiring 62 are electrically connected to each other and form a part of the second electrode T2. The second electrode T2 is electrically connected to the third diffusion region 112a and the fourth diffusion region 112b.

[0026] In the cross-sectional structure described above, the arrangement of second diffusion region 111b, first well region 111, second well region 112, and third diffusion region 112a forms a first pnpn junction. In the first embodiment, since semiconductor substrate 3 is an i-type semiconductor, the first pnpn junction includes a pnipn junction. Alternatively, semiconductor substrate 3 may be a p-type semiconductor, in which case the first pnpn junction includes a pnpn junction.

[0027] Next, the cross-sectional structure along I3-I4 including the diode 2 will be described.

[0028] In the diode 2, a third well region 211 of a first conductivity type (n-type) and a fourth well region 212 of a second conductivity type (p-type) are embedded in the upper surface of the semiconductor substrate 3 and spaced apart from each other in the Y direction (first direction). As will be described later in FIG. 3 , the cross section I1-I2 is a cross section viewed from the negative side to the positive side in the Y direction, and the cross section I3-I4 is a cross section viewed from the positive side to the negative side in the X direction, but for convenience, these cross sections are shown on the same page. A fifth diffusion region 211a of the first conductivity type is embedded in a portion of the upper surface of the third well region 211. Furthermore, a sixth diffusion region 212b of the second conductivity type is embedded in a portion of the upper surface of the fourth well region 212.

[0029] Contacts 34a and 34b are disposed on the upper surface of the fifth diffusion region 211a. An M1 wiring 44 is disposed above the contacts 34a and 34b so as to connect to the upper surfaces of the contacts 34a and 34b, and the contacts 34a and 34b are connected by the M1 wiring 44. Similarly, contacts 33a and 33b are disposed on the upper surface of the sixth diffusion region 212b. An M1 wiring 43 is disposed above the contacts 33a and 33b so as to connect to the upper surfaces of the contacts 33a and 33b, and the contacts 33a and 33b are connected by the M1 wiring 43.

[0030] A contact 54 is arranged on the upper surface of the M1 wiring 44, and a contact 53 is arranged on the upper surface of the M1 wiring 43. In the cross-sectional view taken along I3-I4, an insulating film 71 is arranged in a region from the main surface of the semiconductor substrate 3 to the height of the upper surfaces of the contacts 53 and 54, where the contacts 33a, 33b, 34a, 34b, 53, and 54 and the M1 wirings 43 and 44 are not present.

[0031] M2 wirings 63 and 64 are respectively arranged above the contacts 53 and 54 so as to connect to the upper surfaces of the contacts 53 and 54. In the cross-sectional view along I3-I4, an insulating film 72 is arranged in a region from the main surface of the insulating film 71 to a height higher than the upper surfaces of the M2 wirings 63 and 64, where the M2 wirings 63 and 64 are not present.

[0032] In the cross section taken along I1-I2, the insulating film 71 is an interlayer insulating film. The insulating film 72 serves as a protective film for the overvoltage protection element 100.

[0033] The contacts 33a and 33b, the M1 wiring 43, the contact 53, and the M2 wiring 63 are electrically connected to each other and form a part of the second electrode T2. The second electrode T2 is electrically connected to the sixth diffusion region 212b.

[0034] As will be described later with reference to Fig. 5, the M2 wiring 62 and the M2 wiring 63 are electrically connected at positions different from the positions on the I1-I2 cross section and the I3-I4 cross section. For convenience, this electrical connection is shown by connecting them with solid lines in Fig. 1. The second electrode T2 includes the M2 wiring 62 and the M2 wiring 63.

[0035] Furthermore, the contacts 34a and 34b, the M1 wiring 44, the contact 54, and the M2 wiring 64 are electrically connected to form the third electrode T3. The third electrode T3 is electrically connected to the fifth diffusion region 211a. Although not shown in FIG. 1, an opening region in which the insulating film 72 is not disposed is provided on part of the upper surface of the M2 wiring 64. In the opening region provided on the upper surface of the M2 wiring 64, the third electrode T3 can be electrically connected to a terminal provided outside the overvoltage protection element.

[0036] In the cross-sectional structure described above, the first pn junction is formed by the arrangement of the fourth well region 212 and the third well region 211. In the first embodiment, since the semiconductor substrate 3 is an i-type semiconductor, the first pn junction forms a PIN diode. Alternatively, the semiconductor substrate 3 may be a p-type semiconductor, in which case the first pn junction forms a PN diode.

[0037] As described above, the overvoltage protection element 100 according to the first embodiment includes a structure in which a thyristor 1 including a well region pair 11 shown in the region I1-I2 and a diode 2 shown in the region I3-I4 are electrically connected in series via a second electrode T2.

[0038] Next, the voltages and current paths applied to the above-described structure in the overvoltage protection device 100 according to the first embodiment will be described.

[0039] 2 is a diagram showing current paths in the overvoltage protection element 100 according to the first embodiment. The same parts as those in FIG. 1 are denoted by the same reference numerals, and their explanations will be omitted. In addition, for the sake of simply showing the locations where voltages are applied, the insulating film 72 that covers the first to third electrodes T1 to T3 is not shown.

[0040] In the overvoltage protection device 100 of Fig. 2, a first voltage V1 is input to the first electrode T1, and a second voltage V2 is input to the third electrode T3. The overvoltage protection device 100 of Fig. 2 has unidirectional polarity. When the first voltage V1 is lower than the second voltage V2 by a first differential voltage, no current flows between the first electrode T1 and the third electrode T3 of the overvoltage protection device 100.

[0041] Here, the first differential voltage may be, for example, in the range of 5 V or more and 50 kV or less, or, for example, in the range of 8 V or more and 12 V or less.

[0042] Generally, the voltage that turns on a thyristor in an overvoltage protection element and acts to release an overvoltage surge is called a breakdown voltage or a breakover voltage. For simplicity's sake, the terms "breakdown voltage" and "breakover voltage" will not be distinguished from each other in the following description. When the first voltage V1 becomes higher than the second voltage V2 by a first differential voltage or more, a current flows from the first electrode T1 to the third electrode T3 along the path indicated by the arrow in FIG. 2. Specifically, when the first voltage V1 becomes higher than the second voltage V2 by the first differential voltage or more, a voltage equal to or greater than the breakdown voltage is applied to the first pnpn junction in the well region pair 11 of the thyristor 1, and a current flows from the first electrode T1 to the second electrode T2 along the path indicated by the arrow in FIG. 2. Since a forward voltage equal to or greater than the voltage at which the first pn junction turns on is applied to the first pn junction in diode 2, the current that flows from the first electrode T1 through the first pnpn junction in thyristor 1 to the second electrode T2 passes through the first pn junction in diode 2 and flows to the third electrode T3.

[0043] On the other hand, when the second voltage V2 becomes higher than the first voltage V1 by the first differential voltage or more, a reverse voltage is applied to the diode 2, and no current flows between the third electrode T3 and the first electrode T1.

[0044] As described above, when the first voltage V1 input to the first electrode T1 becomes higher than the second voltage V2 input to the third electrode by at least the first differential voltage, the overvoltage protection element 100 passes a current from the first electrode T1 to the third electrode T3 and releases the overvoltage input to the first electrode T1 to the third electrode T3. By releasing the overvoltage input to the first electrode T1, the overvoltage protection element 100 protects the input terminal of an IC or LSI connected downstream of the overvoltage protection element 100 from the overvoltage.

[0045] The current that releases the overvoltage flows along the main surface of the semiconductor substrate 3 of the overvoltage protection element 100. Because the current flows along the main surface of the semiconductor substrate 3, an overvoltage protection element with the required characteristics can be configured on a single semiconductor substrate 3 by arranging and interconnecting multiple overvoltage protection elements with unidirectional polarity, such as thyristors and diodes, on the upper surface of a single semiconductor substrate 3. Compared to configuring an overvoltage protection element using two unidirectional vertical overvoltage protection chips in which a thyristor and a diode are connected in series, the volume occupied by the overvoltage protection element can be reduced, and the parasitic capacitance connected to the signal line and manufacturing costs can be reduced.

[0046] The cross-sectional view and current paths of the overvoltage protection device 100 according to the first embodiment have been described above. Next, a plan view and a perspective view of the overvoltage protection device 100 will be described.

[0047] 3 is a plan view of the well region and diffusion region of the overvoltage protection device 100 according to the first embodiment. Also, FIG. 4 is an enlarged plan view of the well region and diffusion region of a portion 1a of FIG. 3. Compared to the cross-sectional view of FIG. 1, FIGS. 3 and 4 show only the semiconductor substrate 3, well regions such as the well region pair 11, and diffusion regions such as the first diffusion region 111a. A plan view of metal wiring such as M2 wiring 61 will be described later with reference to FIG. 5.

[0048] Referring to FIG. 3, in the overvoltage protection device 100, a thyristor 1 and a diode 2 are arranged along the Y direction, which is a first direction.

[0049] The thyristor 1 includes a pair of well regions 11, 12, and 13. The well region pair 11 includes a first well region 111 of a first conductivity type, which is n-type, and a second well region 112 of a second conductivity type, which is p-type. The first well region 111 and the second well region 112 extend in the Y direction and are arranged adjacent to each other in the X direction, which is a second direction intersecting the first direction. Similarly, the well region pair 12 includes a well region 121 of a first conductivity type and a well region 122 of a second conductivity type. The well regions 121 and 122 extend in the Y direction and are arranged adjacent to each other in the X direction. The well region pair 12 is arranged in the same direction as the well region pair 11, at a position shifted toward the negative side of the X direction from the well region pair 11. The well region pair 13 is arranged in the same manner as the well region pair 12.

[0050] Referring to the enlarged plan view of region 1a shown in FIG. 4, the first well region 111 includes a first diffusion region 111a of a first conductivity type and a second diffusion region 111b of a second conductivity type. The second well region 112 includes a third diffusion region 112a of a first conductivity type and a fourth diffusion region 112b of a second conductivity type. The first diffusion region 111a, the second diffusion region 111b, the third diffusion region 112a, and the fourth diffusion region 112b are arranged extending in the Y direction. The cross-sectional views of the semiconductor substrate 3, well region, and diffusion region in the cross-sectional views taken along line I1-I2 in FIGS. 1 and 2 are cross-sectional views taken along line I1-I2 in FIG. 4.

[0051] 3, the diode 2 includes a third well region 211 of a first conductivity type and a fourth well region 212 of a second conductivity type. The third well region 211 includes a fifth diffusion region 211a of a first conductivity type. The fourth well region 212 includes a sixth diffusion region 212b of a second conductivity type. The third well region 211, the fourth well region 212, the fifth diffusion region 211a, and the sixth diffusion region 212b are arranged to extend in the X direction. The cross-sectional views of the semiconductor substrate 3, well region, and diffusion region in the cross-sectional views I3-I4 in FIGS. 1 and 2 are cross-sectional views taken along the line I3-I4 in FIG. 3.

[0052] FIG. 5 is a plan view of the metal wiring of the overvoltage protection device 100 according to the first embodiment. FIG. 5 shows a plan view of the M2 wiring, the contact between the M2 wiring and the M1 wiring, the M1 wiring, and the semiconductor substrate 3, which are arranged above the well region and the diffusion region shown in FIG. 3, as viewed from the normal direction of the main surface of the semiconductor substrate 3. However, the drawing is schematic, and the dimensional ratio in FIG. 5 is exaggerated for the sake of explanation, and therefore differs from that in FIG. 3. It should also be noted that the contact between the M1 wiring and the diffusion region is not shown in FIG. 5 for the sake of explanation. The contact between the M1 wiring and the diffusion region will be described later with reference to the perspective view in FIG. 6.

[0053] Referring to FIG. 5, similarly to FIG. 3, in the overvoltage protection device 100, the thyristor 1 and the diode 2 are arranged along the Y direction.

[0054] First, we will explain the metal wiring of thyristor 1. As shown in Figures 3 and 4, M1 wirings 41 and 42 are respectively arranged above first well region 111 and second well region 112 included in well region pair 11 of thyristor 1, as shown in Figure 5. Similarly, M1 wirings 45 and 46 are respectively arranged above well regions 121 and 122 included in well region pair 12, and M1 wirings 47 and 48 are respectively arranged above well regions 131 and 132 included in well region pair 13.

[0055] Furthermore, M2 wiring 61 is disposed above M1 wirings 41, 45, and 47. M2 wiring 61 extends from positions above M1 wirings 41, 45, and 47 toward the positive side in the Y direction and is connected to M2 wirings disposed along the X direction. That is, M2 wiring 61 has a comb-like shape with the M2 wiring portions disposed above M1 wirings 41, 45, and 47 as teeth and the M2 wiring portion disposed along the X direction as a body. In FIG. 5, the width of the teeth of M2 wiring 61 in the X direction is shown narrower than the width of M1 wirings 41, 45, and 47 in the X direction, but the width of the teeth of M2 wiring 61 in the X direction may be wider than the width of M1 wirings 41, 45, and 47 in the X direction.

[0056] 5, as will be described later with reference to Fig. 7, the M2 wiring 61 is connected to a pad portion for electrically connecting to the outside of the overvoltage protection device 100. Note that the M2 wiring 61 may not have an M2 wiring arranged along the X direction, and wiring arranged above the M1 wirings 41, 45, and 47 and extending in the Y direction may be connected to the pad portion.

[0057] Similarly, the M2 wiring 62 is disposed above the M1 wirings 42, 46, and 48. The M2 wiring 62 extends from positions above the M1 wirings 42, 46, and 48 to the negative side in the Y direction and is connected to the M2 wirings disposed along the X direction. That is, the M2 wiring 62 has a comb-like shape with the M2 wiring portions disposed above the M1 wirings 42, 46, and 48 as teeth and the M2 wiring portion disposed along the X direction as a body. In FIG. 5, the width in the X direction of the teeth of the M2 wiring 62 is shown narrower than the width in the X direction of the M1 wirings 42, 46, and 48, but the width in the X direction of the teeth of the M2 wiring 62 may be wider than the width in the X direction of the M1 wirings 42, 46, and 48.

[0058] A contact 51 is disposed between the M2 wiring 61 and the M1 wiring 41, and the M2 wiring 61 and the M1 wiring 41 are electrically connected via the contact 51. A contact is similarly disposed between the M2 wiring 61 and the M1 wirings 45 and 47. A contact 52 is disposed between the M2 wiring 62 and the M1 wiring 42, and the M2 wiring 62 and the M1 wiring 42 are electrically connected via the contact 52. A contact is similarly disposed between the M2 wiring 62 and the M1 wirings 46 and 48.

[0059] 1 and 2 are cross-sectional views taken along the line I1-I2 in Fig. 5. Although not shown in Fig. 5, an insulating film 71 is disposed between the M1 wiring and the M2 wiring, and the contacts 51 and 52 are disposed with openings in the insulating film 71.

[0060] Next, we will explain the metal wiring of the diode 2. As shown in Fig. 3, an M1 wiring 44 is arranged along the X direction above the third well region 211 included in the diode 2 as shown in Fig. 5, and an M1 wiring 43 is arranged along the X direction above the fourth well region 212 as shown in Fig. 3.

[0061] Moreover, M2 wires 63 and 64 are respectively arranged along the X direction above the M1 wires 43 and 44. The M2 wire 63 is arranged in contact with and electrically connected to the M2 wire 62 included in the thyristor 1. Although not shown in FIG. 5, as will be described later with reference to FIG. 7, the M2 wire 64 is connected to a pad portion for electrically connecting the overvoltage protection device 100 to the outside.

[0062] A contact 53 is disposed between the M2 wiring 63 and the M1 wiring 43, and the M2 wiring 63 and the M1 wiring 43 are electrically connected via the contact 53. In addition, a contact 54 is disposed between the M2 wiring 64 and the M1 wiring 44, and the M2 wiring 64 and the M1 wiring 44 are electrically connected via the contact 54.

[0063] The cross-sectional views of the metal wiring in the cross-sectional views taken along the line I3-I4 in FIGS. 1 and 2 are cross-sectional views taken along the line I3-I4 in FIG.

[0064] FIG. 6 is a perspective view of the thyristor 1 of the overvoltage protection device 100 according to the first embodiment. FIG. 6 shows a perspective view of region 1b in FIG. 5. The same or similar reference numerals are used for parts that are the same as or similar to those in FIGS. 1 to 5. Here, the well region embedded in the upper surface of the semiconductor substrate 3 and the diffusion region embedded in part of the upper surface of the well region are not shown. In the description of FIG. 6, the semiconductor substrate 3 will be referred to as the semiconductor substrate 3 without distinction between the well region and the diffusion region.

[0065] As shown in FIG. 6, contacts 31a and 31b are arranged between the M1 wiring 41 and the semiconductor substrate 3. Although not shown in FIG. 6, the contacts 31a and 31b are arranged on the upper surfaces of the first diffusion region 111a and the second diffusion region 111b, respectively. The contact 31a electrically connects the M1 wiring 41 to the first diffusion region 111a, and the contact 31b electrically connects the M1 wiring 41 to the second diffusion region 111b. Similarly, contacts 32a and 32b are arranged between the M1 wiring 42 and the semiconductor substrate 3. Although not shown in FIG. 6, the contacts 32a and 32b are arranged on the upper surfaces of the third diffusion region 112a and the fourth diffusion region 112b, respectively. The contact 32a electrically connects the M1 wiring 42 to the third diffusion region 112a, and the contact 32b electrically connects the M1 wiring 42 to the fourth diffusion region 112b.

[0066] In FIG. 6, the arrangement and connections of the M1 wirings 41 and 42, the contacts 51 and 52, and the M2 wirings 61 and 62 are the same as those in FIGS. 1, 2, and 5, and therefore will not be described.

[0067] Fig. 7 is a plan view of the entire overvoltage protection device 100 according to the first embodiment. For convenience of explanation, Fig. 7 shows only the M2 wiring, the well region, and the semiconductor substrate, and other layers are omitted from the illustration.

[0068] The thyristor 1 described with reference to Figures 1 to 6 and the diode 2 described with reference to Figures 1 to 3 and Figure 5 are arranged along the Y direction and are electrically connected via the second electrode T2.

[0069] The pad portion 4t is disposed on the positive side of the thyristor 1 in the Y direction. The pad portion 4t includes an M2 wiring. In FIG. 7, the portion where the pad portion 4t and the M2 wiring 61 shown in FIG. 5 are connected is connected without an M2 wiring disposed along the X direction. However, the M2 wiring 61 may have an M2 wiring disposed along the X direction, and the pad portion 4t and the M2 wiring 61 may be connected via the M2 wiring disposed along the X direction. The first electrode T1 includes a structure in which the pad portion 4t and the M2 wiring 61 are electrically connected.

[0070] Similar to the pad portion 4t, the pad portion 4b is arranged on the negative side of the diode 2 in the Y direction. The pad portion 4b includes an M2 wiring. The third electrode T3 has a structure in which the pad portion 4b and the M2 wiring 64 shown in FIG. 5 are electrically connected. Note that, although the pad portion 4b is arranged on the negative side of the diode 2 in the Y direction in FIG. 5, the pad portion 4b may also be arranged on the positive or negative side of the diode 2 in the X direction.

[0071] As described above, the overvoltage protection device 100 includes the first electrode T1, the thyristor 1, the second electrode T2, the diode 2, and the third electrode T3, and the first electrode T1 and the third electrode T3 include the pad portions 4t and 4b, respectively. The pad portions 4t and 4b are configured so as to be connectable to input signal wiring provided outside the overvoltage protection device 100.

[0072] (Example of connection of an overvoltage protection element) Fig. 8 is a diagram showing a connection example when the overvoltage protection element 100 according to the first embodiment is used in combination with an IC 300. Fig. 8 shows an example in which the overvoltage protection element 100 and the IC 300 are separated onto different semiconductor substrates, but the overvoltage protection element 100 and the IC 300 may be configured on the same semiconductor substrate.

[0073] IC300 has an input terminal TS1, to which an input signal S1 is input. Inside IC300, the input signal S1 is input to circuit block block1. If an overvoltage protection element is not connected to input terminal TS1 of IC300, an overvoltage surge on the input signal S1 will damage the input circuit of circuit block block1 to which the input signal S1 is input. To prevent this, an overvoltage protection element 100 is used in combination with IC300.

[0074] 2, the overvoltage protection element 100 has unidirectional polarity. The first electrode T1 of the overvoltage protection element 100 is connected to a signal line through which an input signal S1 propagates, and the third electrode T3 is set to a ground potential GND. If the voltage of the input signal S1 is a first voltage V1, the overvoltage protection element 100 is in a state in which the first voltage V1 is applied to the first electrode T1 and the ground potential GND is applied to the third electrode T3.

[0075] When the input signal S1 has a voltage value within the normal voltage range defined in the specifications, the overvoltage protection element 100 does not allow current to flow between the first electrode T1 and the third electrode T3. When an overvoltage surge is superimposed on the input signal S1 and the first voltage V1 becomes higher than the ground potential GND by a first differential voltage, the overvoltage protection element 100 operates to release the voltage of the first electrode T1 to the third electrode T3. This operation pulls down the voltage of the input signal S1 toward the ground potential GND, thereby protecting the input circuit of circuit block block 1 of the IC300.

[0076] (Package configuration including overvoltage protection element) 9A and 9B are a plan view and a front view, respectively, of a package 200 including the overvoltage protection device 100 according to the first embodiment.

[0077] The package 200 includes a first terminal 81 and a second terminal 82, each of which includes a conductor. In the package 200, the semiconductor substrate 3 of the overvoltage protection element 100 is disposed so as to overlap both a portion of the first terminal 81 and a portion of the second terminal 82 when viewed in the normal direction of the main surface of the semiconductor substrate 3. The first electrode T1 and the third electrode T3 of the overvoltage protection element 100 are electrically connected to the first terminal 81 and the second terminal 82 of the package 200 by bonding wires 91 and 92, respectively.

[0078] 9A shows the semiconductor substrate 3 of the overvoltage protection element 100 rotated 90° counterclockwise with respect to the plan view of the overvoltage protection element 100 in FIG. By rotating it 90°, the distance between the first electrode T1 and the first terminal 81 and the distance between the third electrode T3 and the second terminal 82 are shortened, and the lengths of the bonding wires 91 and 92 are shortened. However, the orientation of the semiconductor substrate 3 may remain as in the plan view of FIG. 7, and may be determined taking into consideration the ease of arranging the semiconductor substrate 3, the ease of connecting the electrodes and terminals, the characteristics, etc.

[0079] The package 200 including the overvoltage protection element 100 can reduce the volume occupied by the overvoltage protection element, as well as the parasitic capacitance connected to the signal line and manufacturing costs, compared to using two vertical overvoltage protection chips to mount an overvoltage protection element in which a thyristor and a diode are connected in series.

[0080] (Effects of the first embodiment) The overvoltage protection device 100 can provide an overvoltage protection device that includes a thyristor 1 and a diode 2 that are connected in series and configured on the upper surface of a single semiconductor substrate 3, and through which a surge current flows along the main surface of the semiconductor substrate 3. Compared to configuring an overvoltage protection device in which two unidirectional vertical overvoltage protection chips are used to connect a thyristor and a diode in series, the volume occupied by the overvoltage protection device can be reduced, and the parasitic capacitance connected to the signal line and manufacturing costs can be reduced.

[0081] [Second embodiment] (Configuration of overvoltage protection element) 10A and 10B are cross-sectional views of an overvoltage protection element 101 according to a second embodiment. FIG. 10A is a cross-sectional view taken along lines X1-X2 and X3-X4 in the plan view of FIG. 13 (described later). FIG. 10B is a cross-sectional view taken along lines X5-X6 and X7-X8 in the plan view of FIG. 13 (described later). The overvoltage protection element 101 is configured by arranging two overvoltage protection elements 100 according to the first embodiment of FIG. 1 on the same semiconductor substrate 3 and connecting their electrodes. Although FIGS. 10A and 10B are shown separately due to space limitations, they are actually arranged on the same semiconductor substrate 3 and connected at connection points A and B. In addition, in the subsequent cross-sectional views, the insulating film 72 is omitted to make it easier to understand the connections between electrodes and connection points.

[0082] FIG. 10A is the same as FIG. 1 except that "l" (lowercase L) is added to the reference numerals of constituent elements to indicate symmetry with FIG. 10B, and the substantial configuration is the same as FIG. 1. In the overvoltage protection device 101 according to the second embodiment, the configuration of FIG. 10B is added to the configuration of FIG. 10A. FIG. 10B differs from FIG. 10A in the following respects. In FIG. 10B, the cross-sectional view of FIG. 10A is inverted with respect to a line passing through X1 and perpendicular to the line connecting X1 and X2 as the axis of symmetry, and "r" is added to the reference numerals of constituent elements. Furthermore, the electrode that is the second electrode T2 in FIG. 10A is the fourth electrode T4 in FIG. 10B. The substantial configuration of FIG. 10B is also the same as FIG. 1.

[0083] As described above, since the substantial configurations of Figures 10A and 10B are the same as those of Figure 1, the explanation of the similarities between them will be omitted, and the explanation will focus on the points not included in Figure 1, such as the names defined to distinguish the components constituting Figure 10B and the connections between them.

[0084] In a portion of the overvoltage protection element 101 shown in FIG. 10A, a well region pair 11l of a thyristor 1l is formed on the upper surface of a semiconductor substrate 3 in a region along X1-X2, similar to FIG. 1. In the well region pair 11l, a first pnpn junction is formed by the arrangement of a second diffusion region 111bl, a first well region 111l, a second well region 112l, and a third diffusion region 112al. Here, the second embodiment also shows a case where the semiconductor substrate 3 is an i-type semiconductor. Therefore, the first pnpn junction includes a pnipn junction. Alternatively, the semiconductor substrate 3 may be a p-type semiconductor, in which case the first pnpn junction includes a pnpn junction.

[0085] 10A, a diode 2l is formed on the upper surface of the semiconductor substrate 3 in a region along X3-X4, similar to FIG. 1. In the diode 2l, a first pn junction is formed by the arrangement of the fourth well region 212l and the third well region 211l. Here, since the second embodiment shows a case where the semiconductor substrate 3 is an i-type semiconductor, the first pn junction includes a p-i-n junction and forms a p-i-n diode. Alternatively, the semiconductor substrate 3 may be a p-type semiconductor, in which case the first pn junction forms a p-n diode.

[0086] In a part of the overvoltage protection element 101 shown in FIG. 10B, a well region pair 11r of the thyristor 1r is formed on the upper surface of the semiconductor substrate 3 in the region along X5-X6, similar to FIG.

[0087] In the well region pair 11r, a fifth well region 111r of a first conductivity type and a sixth well region 112r of a second conductivity type are embedded in the upper surface of the semiconductor substrate 3 and spaced apart from each other in the X direction, which is the second direction. In the second embodiment, the first conductivity type is n-type and the second conductivity type is p-type. A seventh diffusion region 111ar of a first conductivity type and an eighth diffusion region 111br of a second conductivity type are embedded in a portion of the upper surface of the fifth well region 111r and spaced apart from each other in the X direction. A ninth diffusion region 112ar of a first conductivity type and a tenth diffusion region 112br of a second conductivity type are embedded in a portion of the upper surface of the sixth well region 112r and spaced apart from each other in the X direction.

[0088] In the well region pair 11r, the arrangement of the eighth diffusion region 111br, the fifth well region 111r, the sixth well region 112r, and the ninth diffusion region 112ar forms a second pnpn junction. In the second embodiment, the semiconductor substrate 3 is an i-type semiconductor, so the second pnpn junction includes a pnipn junction. Alternatively, the semiconductor substrate 3 may be a p-type semiconductor, in which case the second pnpn junction includes a pnpn junction.

[0089] The components arranged above the well region pair 11r of the thyristor 1r, i.e., contacts 31ar, 31br, 32ar, 32br, 51r, and 52r, M1 wirings 41r and 42r, and M2 wirings 61r and 62r, are arranged as follows: The components arranged above the well region pair 11r are arranged inverted with respect to Figure 1, with a line that passes through I1 in Figure 1 and is perpendicular to the line connecting I1 and I2 as the axis of symmetry, and the components are the same except that "r" is added to the reference numerals of the components, so explanations will be omitted.

[0090] 10B, a diode 2r is formed on the upper surface of the semiconductor substrate 3 in a region along X7-X8, similar to FIG.

[0091] In the diode 2r, a seventh well region 211r of a first conductivity type (n-type) and an eighth well region 212r of a second conductivity type (p-type) are embedded in the upper surface of the semiconductor substrate 3 and spaced apart from each other in the Y direction (first direction). An eleventh diffusion region 211ar of the first conductivity type is embedded in a portion of the upper surface of the seventh well region 211r. A twelfth diffusion region 212br of the second conductivity type is embedded in a portion of the upper surface of the eighth well region 212r.

[0092] In diode 2r, the arrangement of eighth well region 212r and seventh well region 211r forms a second pn junction. In the second embodiment, the semiconductor substrate 3 is an i-type semiconductor, so the second pn junction includes a pin junction and forms a PIN diode. Alternatively, semiconductor substrate 3 may be a p-type semiconductor, in which case the second pn junction forms a PN diode.

[0093] The components arranged above the diode 2r, i.e., the contacts 33ar, 33br, 34ar, 34br, 53r, 54r, the M1 wirings 43r, 44r, and the M2 wirings 63r, 64r, are arranged as follows: The components arranged above the diode 2r are arranged inverted with respect to Figure 1, with the axis of symmetry being a line that passes through I1 in Figure 1 and is perpendicular to the line connecting I1 and I2, and the components are the same except that "r" is added to the reference numerals of the components, so explanations will be omitted.

[0094] The M2 wiring 64l in FIG. 10A and the M2 wiring 61r in FIG. 10B are connected by the M2 wiring via connection point B in a cross section not shown in FIGS. 10A and 10B. Therefore, the M2 wiring 61r in FIG. 10B is electrically connected to the third electrode T3. Furthermore, the M2 wiring 61l in FIG. 10A and the M2 wiring 64r in FIG. 10B are connected by the M2 wiring via connection point A in a cross section not shown in FIGS. 10A and 10B. Therefore, the M2 wiring 64r in FIG. 10B is electrically connected to the first electrode T1. That is, the overvoltage protection element 101 according to the second embodiment is configured as follows: Two overvoltage protection elements 100 having unidirectional polarity are arranged on one semiconductor substrate 3, and the first electrode T1 of one element is connected to the third electrode T3 of the other element to newly define a first electrode T1. Furthermore, the third electrode T3 of one element is connected to the first electrode T1 of the other element to define a new third electrode T3.

[0095] 11A and 11B are diagrams showing current paths in the overvoltage protection device 101 according to the second embodiment. The same parts as those in FIGS. 10A and 10B are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0096] 11A and 11B, a first voltage V1 is input to the first electrode T1, and a second voltage V2 is input to the third electrode T3. Each of the overvoltage protection elements 101 shown in FIGS. 11A and 11B has unidirectional polarity, but as described above, bidirectional polarity can be achieved by connecting the first electrode T1 and the third electrode T3 of each element.

[0097] When the first voltage V1 is lower than the first differential voltage with respect to the second voltage V2, and the second voltage V2 is lower than the second differential voltage with respect to the first voltage V1, no current flows between the first electrode T1 and the third electrode T3 of the overvoltage protection element 101.

[0098] Here, the first differential voltage and the second differential voltage may be, for example, in the range of 5 V or more and 50 kV or less, or may be in the range of 8 V or more and 12 V or less.

[0099] When the first voltage V1 becomes higher than the second voltage V2 by at least the first differential voltage, a current flows from the first electrode T1 to the third electrode T3 along the path indicated by the solid arrow in Fig. 11A. Specifically, when the first voltage V1 becomes higher than the second voltage V2 by at least the first differential voltage, a voltage equal to or greater than the breakdown voltage is applied to the first pnpn junction in the well region pair 11l of the thyristor 1l, and a current flows from the first electrode T1 to the second electrode T2 along the path indicated by the solid arrow in Fig. 11A. Because a forward voltage equal to or greater than the voltage at which the first pn junction turns on is applied to the first pn junction in the diode 2l, the current that flows from the first electrode T1 through the first pnpn junction in the thyristor 1l to the second electrode T2 flows through the first pn junction in the diode 2l to the third electrode T3.

[0100] On the other hand, when the second voltage V2 becomes higher than the first voltage V1 by at least the second differential voltage, a current flows from the third electrode T3 to the first electrode T1 along the path indicated by the dashed arrow in Fig. 11B. Specifically, when the second voltage V2 becomes higher than the first voltage V1 by at least the second differential voltage, a voltage equal to or greater than the breakdown voltage is applied to the second pnpn junction in the well region pair 11r of the thyristor 1r, and a current flows from the third electrode T3 to the fourth electrode T4 along the path indicated by the dashed arrow in Fig. 11B. Because a forward voltage equal to or greater than the voltage at which the second pn junction turns on is applied to the second pn junction in the diode 2r, the current that flows from the third electrode T3 through the second pnpn junction in the thyristor 1r to the fourth electrode T4 then flows through the second pn junction in the diode 2r to the first electrode T1.

[0101] In this manner, when the first voltage V1 input to the first electrode T1 is higher than the second voltage V2 input to the third electrode T1 by at least the first differential voltage, the overvoltage protection element 101 passes a current from the first electrode T1 to the third electrode T3, thereby dissipating the overvoltage input to the first electrode T1 to the third electrode T3. Furthermore, when the second voltage V2 input to the third electrode T3 is higher than the first voltage V1 input to the first electrode T1 by at least the second differential voltage, the overvoltage protection element 101 passes a current from the third electrode T3 to the first electrode T1, thereby dissipating the overvoltage input to the third electrode T3 to the first electrode T1. In this manner, the overvoltage protection element 101 protects the input terminal of an IC or LSI connected downstream of the overvoltage protection element 101 from overvoltage.

[0102] The current that releases the overvoltage flows along the main surface of the semiconductor substrate 3 of the overvoltage protection element 101. Because the current flows along the main surface of the semiconductor substrate 3, an overvoltage protection element with bidirectional polarity can be configured on one semiconductor substrate 3 by arranging and interconnecting multiple overvoltage protection elements with unidirectional polarity on the upper surface of one semiconductor substrate 3. Compared to configuring an overvoltage protection element with bidirectional polarity using two unidirectional vertical overvoltage protection chips, the volume occupied by the overvoltage protection element can be reduced, and the parasitic capacitance connected to the signal line and manufacturing costs can be reduced.

[0103] The cross-sectional view and current paths of the overvoltage protection element 101 according to the second embodiment have been described above. Next, a plan view of the overvoltage protection element 101 will be described.

[0104] Fig. 12 is a plan view of the entire overvoltage protection device 101 according to the second embodiment. For convenience of explanation, Fig. 12 shows only the M2 wiring, the well region, and the semiconductor substrate, and other layers are omitted from the illustration.

[0105] The overvoltage protection element 101 includes a first electrode T1, a thyristor 1l, a second electrode T2, a diode 2l, a third electrode T3, a thyristor 1r, a fourth electrode T4, and a diode 2r. The first electrode T1 and the third electrode T3 include circular pads 4l and 4r, respectively, which are configured to be connectable to input signal wiring provided outside the overvoltage protection element 101. The arrangement of the first electrode T1, the thyristor 1l, the second electrode T2, and the diode 2l in the overvoltage protection element 101 is similar to the arrangement of the first electrode T1, the thyristor 1l, the second electrode T2, and the diode 2l in the overvoltage protection element 100 according to the first embodiment shown in FIG. 7. The overvoltage protection element 100 shown in FIG. 12 differs from the overvoltage protection element 100 shown in FIG. 7 in that the pad 4b is not located on the negative side of the diode 2l in the Y direction.

[0106] 12, the first electrode T1 including the pad portion 4l, the thyristor 1l, the second electrode T2, the diode 2l, and the M2 wiring 64l constitute one set 101l. Also, the third electrode T3 including the pad portion 4r, the thyristor 1r, the fourth electrode T4, the diode 2r, and the M2 wiring 64r constitute one set 101r. The arrangement of the set 101r is such that the set 101l is rotated 180 degrees and placed on the positive side in the X direction.

[0107] The M2 wiring 64l arranged above the third well region 211l of the diode 2l extends to the positive side in the X direction and is connected to the third electrode T3, and the M2 wiring 64r arranged above the seventh well region 211r of the diode 2r extends to the negative side in the X direction and is connected to the first electrode T1.

[0108] The planar layout of the well regions and diffusion regions of each of thyristor 1l and diode 2l is similar to the planar layout of the well regions and diffusion regions of thyristor 1 and diode 2 shown in Fig. 3, and therefore a description thereof will be omitted. Also, the planar layout of the well regions and diffusion regions of each of thyristor 1r and diode 2r is similar to the planar layout of the well regions and diffusion regions of thyristor 1 and diode 2 shown in Fig. 3 rotated 180° as a set, and therefore a description thereof will be omitted.

[0109] FIG. 13 is a plan view of metal wiring of an overvoltage protection element 101 according to a second embodiment. FIG. 13 shows a plan view of the M2 wiring arranged above the well region and diffusion region shown in FIG. 12, the contact between the M2 wiring and the M1 wiring, the M1 wiring, and the semiconductor substrate 3, as viewed from the normal direction of the main surface of the semiconductor substrate 3. However, the drawing is schematic, and the dimensional ratio in FIG. 13 is exaggerated for the sake of explanation, and therefore differs from that in FIG. 12. It should be noted that, as in FIG. 5, the contact between the M1 wiring and the diffusion region is not shown in FIG. 13 for the sake of explanation.

[0110] As described above, the overvoltage protection element 101 according to the second embodiment is configured by arranging two overvoltage protection elements 100 shown in FIG. 1 on the same semiconductor substrate 3 and connecting their electrodes. Therefore, the plan view of the metal wiring connecting the electrodes differs from the plan view of the metal wiring of the overvoltage protection element 100 shown in FIG. 5. The set 101l shown in FIG. 13 is the same as the set 101r shown in FIG. 5 except that "l" is added to the reference numerals of the constituent members to indicate symmetry with the set 101r. The overvoltage protection element 101 according to the second embodiment adds the configuration of the set 101r to the configuration of the set 101l. The set 101r is rotated 180° from the set 101l and positioned on the positive side of the X direction, and "r" is added to the reference numerals of the constituent members. Furthermore, the second electrode T2 in the set 101l is the fourth electrode T4 in the set 101r. The set 101r also has a substantial configuration similar to that shown in FIG.

[0111] The M2 wiring 64l extends to the positive side in the X direction and is connected to the third electrode T3. The M2 wiring 64r extends to the negative side in the X direction and is connected to the first electrode T1. As shown in FIG. 12, the pad portion 4l of the first electrode T1 and the pad portion 4r of the third electrode T3 are both circular, but are schematically depicted as rectangles with rounded corners in FIG. 13.

[0112] The cross-sectional views of the metal wiring in the cross-sectional views taken along X1-X2 and X3-X4 in Figures 10A and 11A, respectively, are cross-sectional views taken along the lines X1-X2 and X3-X4 in Figure 13. Moreover, the cross-sectional views of the metal wiring in the cross-sectional views taken along X5-X6 and X7-X8 in Figures 10B and 11B, respectively, are cross-sectional views taken along the lines X5-X6 and X7-X8 in Figure 13.

[0113] (Example of connection of an overvoltage protection element) Fig. 14 is a diagram showing a connection example when the overvoltage protection element 101 according to the second embodiment is used in combination with an IC 300. The same parts as those in the connection example of the overvoltage protection element 100 and IC 300 according to the first embodiment in Fig. 8 are given the same reference numerals, and their description will be omitted. Fig. 14 shows an example in which the overvoltage protection element 101 and IC 300 are separated onto different semiconductor substrates, but the overvoltage protection element 101 and IC 300 may also be formed on the same semiconductor substrate.

[0114] 14 differs from FIG. 8 in that the overvoltage protection element 101 has a fourth electrode T4. However, the fourth electrode T4 is not connected to the input signal wiring, and the connection of the input signal wiring is the same as in FIG. 8.

[0115] 11A and 11B, the overvoltage protection element 101 has bidirectional polarity. The first electrode T1 of the overvoltage protection element 101 is connected to a signal line through which an input signal S1 propagates, and the third electrode T3 is set to a ground potential GND. If the voltage of the input signal S1 is a first voltage V1, the overvoltage protection element 101 is in a state in which the first voltage V1 is applied to the first electrode T1 and the ground potential GND is applied to the third electrode T3.

[0116] When the input signal S1 has a voltage value within the normal voltage range defined in the specifications, the overvoltage protection element 101 does not allow current to flow between the first electrode T1 and the third electrode T3.

[0117] When an overvoltage surge of a positive voltage higher than the ground potential GND is superimposed on the input signal S1 and the first voltage V1 becomes a voltage higher than the first differential voltage with respect to the ground potential GND, the overvoltage protection element 101 operates to release the voltage of the first electrode T1 to the third electrode T3. This operation pulls down the voltage of the input signal S1 toward the ground potential GND, thereby protecting the input circuit of the circuit block block1 of the IC300.

[0118] Now consider a case where an overvoltage surge on the negative voltage side lower than the ground potential is superimposed on the input signal S1, causing the first voltage V1 to become lower than the second differential voltage relative to the ground potential GND. In other words, this corresponds to a case where the ground potential GND becomes higher than the second differential voltage relative to the first voltage V1, so the overvoltage protection element 101 operates to pass current from the third electrode T3 to the first electrode T1. This operation pulls the negative voltage of the input signal S1 up toward the ground potential GND, thereby protecting the input circuit of circuit block block 1 of IC300.

[0119] As described above, the overvoltage protection element 101 operates in a bidirectional manner, discharging the first voltage V1 to the ground potential GND when the first voltage V1, which is the voltage of the input signal S1, becomes a voltage higher than the first differential voltage with respect to the ground potential GND, or when it becomes a voltage lower than the second differential voltage.

[0120] (Package configuration including overvoltage protection element) Next, a package 201 including an overvoltage protection device 101 according to the second embodiment will be described.

[0121] The overall plan view of the overvoltage protection device 101 according to the second embodiment in FIG. 12 is compared with the overall plan view of the overvoltage protection device 100 according to the first embodiment shown in FIG. 7 and the plan view of the package 200 shown in FIG. Similar to FIGS. 7 and 12, the electrodes appearing on the pads are the first electrode T1 and the third electrode T3. In FIG. 7, the pads 4t and 4b are arranged at the same position in the X direction but at different positions in the Y direction, sandwiching the thyristor 1 and the diode 2. In FIG. 9A, the semiconductor substrate 3 of the overvoltage protection device 100 in FIG. 7 is rotated 90° counterclockwise. On the other hand, FIG. 12 differs in that the pads 4l and 4r are arranged at different positions in the X direction as well as the Y direction on diagonal lines of the semiconductor substrate 3.

[0122] In the overvoltage protection element 101, the pad portions 4l and 4r are arranged diagonally on the semiconductor substrate 3, so when the semiconductor substrate 3 is arranged in the package 201, it can be connected to the first and second terminals arranged in the same manner as in the package 200 of FIG. 9A without having to rotate it from the orientation of FIG. 7.

[0123] Based on the above, a package 201 including an overvoltage protection element 101 according to the second embodiment will be described. Assume that the semiconductor substrate 3 of the overvoltage protection element 101 of FIG. 12 is placed in the package 201 in the orientation shown in the plan view of FIG. 12. The plan view of the package 201 is the same as that shown in FIG. 9A , except for the position of the third electrode T3 and the position of the bonding wire 92 connecting the third electrode T3 and the second terminal 82, as compared to the plan view of the package 200 including the overvoltage protection element 100 according to the first embodiment shown in FIG. 9A . Furthermore, a front view of the package 201 is the same as that of the package 200 shown in FIG. 9B .

[0124] As described above, package 201 is the same as that shown in Figures 9A and 9B except that the position of third electrode T3 and the position of bonding wire 92 connecting third electrode T3 and second terminal 82 are shifted from those shown in Figure 9A, and therefore is not shown in the figures.

[0125] The package 201 including the overvoltage protection element 101 can reduce the volume occupied by the overvoltage protection element, as well as the parasitic capacitance connected to the signal line and manufacturing costs, compared to mounting an overvoltage protection element using multiple unidirectional vertical overvoltage protection chips.

[0126] (Effects of the second embodiment) The overvoltage protection element 101 can provide a bidirectional overvoltage protection element formed on the upper surface of a single semiconductor substrate 3, in which a surge current flows along the main surface of the semiconductor substrate 3. The overvoltage protection element 101 can protect a downstream IC by dissipating the first voltage V1, regardless of whether the first voltage V1 at the first electrode T1 is higher than the first differential voltage or lower than the second differential voltage with respect to the second voltage V2 at the third electrode T3. Compared to constructing an overvoltage protection element with bidirectional polarity using multiple unidirectional vertical overvoltage protection chips, the volume occupied by the overvoltage protection element can be reduced, and the parasitic capacitance connected to the signal lines and manufacturing costs can be reduced.

[0127] [Third embodiment] (Configuration of overvoltage protection element) 15A and 15B are cross-sectional views of an overvoltage protection element 102 according to a third embodiment. Fig. 15A is a cross-sectional view taken along lines XV1-XV2 and XV3-XV4 in the plan view of Fig. 18, which will be described later. Fig. 15B is a cross-sectional view taken along lines XV5-XV6 and XV7-XV8 in the plan view of Fig. 18, which will be described later. Figs. 15A and 15B are separated due to space limitations, but are disposed on the same semiconductor substrate 3 and connected at connection points C and D.

[0128] The overvoltage protection element 102 in FIGS. 15A and 15B differs from the overvoltage protection element 101 shown in FIGS. 10A and 10B in the following respects. In FIG. 10B, the M2 wirings 61r, 62r, 63r, and 64r are connected to the third electrode T3, the fourth electrode T4, the fourth electrode T4, and the first electrode T1, respectively. In contrast, in FIG. 15B, the M2 wirings 61r, 62r, 63r, and 64r are connected to the fourth electrode T4, the third electrode T3, the third electrode T3, and the first electrode T1. That is, the connections between the electrodes are different in FIGS. 15A and 15B compared to FIGS. 10A and 10B. Other than the connections between the electrodes, the well regions, diffusion regions, and metal wiring in FIGS. 15A and 15B are the same as those in FIGS. 10A and 10B. Therefore, the same reference numerals are used to designate the same parts as in FIGS. 10A and 10B, and their descriptions will be omitted. However, as will be described later with reference to FIG. 18, the direction in which the cross section of FIG. 15B is viewed is different from the direction in which the cross section of FIG. 10B is viewed.

[0129] 16A and 16B are diagrams showing current paths in the overvoltage protection device 102 according to the third embodiment. The same parts as those in FIGS. 15A and 15B are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0130] 16A and 16B, a first voltage V1 is input to the first electrode T1, and a second voltage V2 is input to the fourth electrode T4. Each of the overvoltage protection elements 102 shown in FIGS. 16A and 16B has a unidirectional polarity, but by connecting them, bidirectional polarity is achieved.

[0131] When the first voltage V1 is lower than the first differential voltage with respect to the second voltage V2, and the second voltage V2 is lower than the second differential voltage with respect to the first voltage V1, no current flows between the first electrode T1 and the fourth electrode T4 of the overvoltage protection element 102.

[0132] Here, the first differential voltage and the second differential voltage may be, for example, in the range of 5 V or more and 50 kV or less, or may be in the range of 8 V or more and 12 V or less.

[0133] When the first voltage V1 becomes higher than the second voltage V2 by at least the first differential voltage, a current flows from the first electrode T1 to the fourth electrode T4 via the path indicated by the solid arrow in Figures 16A and 16B. Specifically, when the first voltage V1 becomes higher than the second voltage V2 by at least the first differential voltage, a voltage equal to or greater than the breakdown voltage is applied to the first pnpn junction in the well region pair 11l of the thyristor 1l in Figure 16A. Then, a current flows from the first electrode T1 to the second electrode T2 via the path indicated by the solid arrow in Figure 16A. Because a forward voltage equal to or greater than the voltage at which the first pn junction turns on is applied to the first pn junction in the diode 2l, the current that flows from the first electrode T1 through the first pnpn junction in the thyristor 1l to the second electrode T2 flows through the first pn junction in the diode 2l to the third electrode T3.

[0134] The current flowing through the third electrode T3 in FIG. 16A flows through connection point C to the third electrode T3 in FIG. 16B. In FIG. 16B, the voltage of the third electrode T3 is higher than the second voltage V2 of the fourth electrode T4 by at least the voltage at which the pn junction turns on. At the second pnpn junction in thyristor 1r, the tenth diffusion region 112br of the second conductivity type, the sixth well region 112r of the second conductivity type, the fifth well region 111r of the first conductivity type, and the seventh diffusion region 111ar of the first conductivity type form a pn junction. Because a forward voltage greater than or equal to the voltage at which the pn junction turns on is applied to this pn junction, the current flowing through the third electrode T3 flows to the fourth electrode T4 through a pn junction included in the second pnpn junction in thyristor 1r, as indicated by the solid arrow in FIG. 16B.

[0135] As described above, the overvoltage protection element 102 in FIGS. 16A and 16B differs from the overvoltage protection element 101 in FIGS. 11A and 11B in that the current path when the first voltage V1 is higher than the second voltage V2 by the first differential voltage or more includes a pn junction included in the second pnpn junction in the thyristor 1r.

[0136] On the other hand, when the second voltage V2 becomes higher than the first voltage V1 by at least the second differential voltage, current flows from the fourth electrode T4 to the first electrode T1 via the path indicated by the dashed arrow in Figures 16B and 16A. Specifically, when the second voltage V2 becomes higher than the first voltage V1 by at least the second differential voltage, a voltage equal to or greater than the breakdown voltage is applied to the second pnpn junction in the well region pair 11r of the thyristor 1r in Figure 16B. Then, current flows from the fourth electrode T4 to the third electrode T3 via the path indicated by the dashed arrow in Figure 16B. Because a forward voltage equal to or greater than the voltage at which the second pn junction turns on is applied to the second pn junction in the diode 2r, the current flowing from the fourth electrode T4 through the second pnpn junction in the thyristor 1r to the third electrode T3 flows through the second pn junction in the diode 2r to the second electrode T2.

[0137] The current flowing through the second electrode T2 in FIG. 16B flows through connection point D to the second electrode T2 in FIG. 16A. In FIG. 16A, the voltage of the second electrode T2 is higher than the first voltage V1 of the first electrode T1 by at least the voltage at which the pn junction turns on. At the first pnpn junction in the thyristor 1l, the fourth diffusion region 112bl of the second conductivity type, the second well region 112l of the second conductivity type, the first well region 111l of the first conductivity type, and the first diffusion region 111al of the first conductivity type form a pn junction. Because a forward voltage greater than or equal to the voltage at which the pn junction turns on is applied to this pn junction, the current flowing through the second electrode T2 flows to the first electrode T1 through a pn junction included in the first pnpn junction in the thyristor 1l, as indicated by the dashed arrow in FIG. 16A.

[0138] As described above, the overvoltage protection element 102 in FIGS. 16A and 16B differs from the overvoltage protection element 101 in FIGS. 11A and 11B in that the current path when the second voltage V2 is higher than the first voltage V1 by the second differential voltage or more includes a pn junction included in the first pnpn junction in the thyristor 1l.

[0139] As described above, when the first voltage V1 input to the first electrode T1 is higher than the second voltage V2 input to the fourth electrode T1 by at least the first differential voltage, the overvoltage protection element 102 passes a current from the first electrode T1 to the fourth electrode T4, thereby dissipating the overvoltage input to the first electrode T1 to the fourth electrode T4. Furthermore, when the second voltage V2 input to the fourth electrode T4 is higher than the first voltage V1 input to the first electrode T1 by at least the second differential voltage, the overvoltage protection element 102 passes a current from the fourth electrode T4 to the first electrode T1, thereby dissipating the overvoltage input to the fourth electrode T4 to the first electrode T1. The current dissipating the overvoltage flows along the principal surface of the semiconductor substrate 3 of the overvoltage protection element 102. In this way, the overvoltage protection element 102 protects the input terminal of an IC or LSI connected downstream of the overvoltage protection element 102 from overvoltage.

[0140] The cross-sectional view and current paths of the overvoltage protection element 102 according to the third embodiment have been described above. Next, a plan view of the overvoltage protection element 102 will be described.

[0141] Fig. 17 is a plan view of the entire overvoltage protection device 102 according to the third embodiment. For convenience of explanation, Fig. 17 shows only the M2 wiring, the well region, and the semiconductor substrate, and other layers are omitted from the illustration.

[0142] The overvoltage protection element 102 includes a first electrode T1, a thyristor 1l, a second electrode T2, a diode 2l, a fourth electrode T4, a thyristor 1r, a third electrode T3, and a diode 2r. The first electrode T1 and the fourth electrode T4 include circular pad portions 4l and 4r, respectively, which are configured to be connectable to input signal wiring provided outside the overvoltage protection element 102. The arrangement of the first electrode T1, the thyristor 1l, and the second electrode T2 of the overvoltage protection element 102 is similar to the arrangement of the first electrode T1, the thyristor 1l, and the second electrode T2 of the overvoltage protection element 101 according to the second embodiment shown in FIG.

[0143] In the overvoltage protection element 102 of Fig. 17, the first electrode T1 including the pad portion 4l, the thyristor 1l, the second electrode T2, and the diode 2l constitute one set 102l. The fourth electrode T4 including the pad portion 4r, the thyristor 1r, the third electrode T3, and the diode 2r constitute one set 102r. The arrangement of the set 102r is such that the set 102l is flipped in the X direction and placed on the positive side in the X direction. However, the position of the diode 2r in a plan view is shifted in the Y direction compared to a plan view of the diode 2l flipped in the X direction.

[0144] The planar layout of the well region and diffusion region of thyristor 1l is similar to the planar layout of the well region and diffusion region of thyristor 1 shown in Fig. 3, and therefore a description thereof will be omitted. Also, the planar layout of the well region and diffusion region of thyristor 1r is similar to the planar layout of the well region and diffusion region of thyristor 1 shown in Fig. 3, which is flipped in the X direction as a set, and therefore a description thereof will be omitted.

[0145] The diode 2l in Fig. 17 includes a third well region 211l of a first conductivity type and a fourth well region 212l of a second conductivity type, similar to the diode 2l in Fig. 12. Here, the fourth well region 212l in Fig. 17 is actually divided into well regions 212lt and 212lb, and differs from Fig. 12 in that each is connected to a second electrode T2 arranged above to form the fourth well region 212l.

[0146] The diode 2r in Fig. 17 includes a seventh well region 211r of the first conductivity type and an eighth well region 212r of the second conductivity type, similar to the diode 2r in Fig. 12. Here, the eighth well region 212r in Fig. 17 is actually divided into well regions 212rt and 212rb, which are each connected to a third electrode T3 arranged above to form the eighth well region 212r, which is different from the diode 2r in Fig. 12.

[0147] 17 are arranged with their positions shifted in the Y direction to facilitate connection of the electrodes therebetween. A plan view of the M2 wiring arranged above the diodes 2l and 2r in FIG. 17 will be described later with reference to FIG.

[0148] FIG. 18 is a plan view of metal wiring of an overvoltage protection element 102 according to a third embodiment. FIG. 18 shows a plan view of the M2 wiring, the contact between the M2 wiring and the M1 wiring, the M1 wiring, and the semiconductor substrate 3, which are arranged above the well region and the diffusion region shown in FIG. 17 , as viewed from the normal direction of the main surface of the semiconductor substrate 3. Note that the drawing is schematic, and the dimensional ratio in FIG. 18 is exaggerated for ease of explanation and therefore differs from that in FIG. 17 . Note also that, as in FIG. 13 , the contact between the M1 wiring and the diffusion region is not shown in FIG. 18 for ease of explanation. As shown in FIG. 17 , the first electrode T1 and the fourth electrode T4 each have circular pad portions 4l and 4r on the positive side in the Y direction, but these are not shown in FIG. 18 . The same parts as in FIG. 13 are designated by the same reference numerals, and their description will be omitted.

[0149] The metal wiring of the overvoltage protection element 102 in Fig. 18 differs from the metal wiring of the overvoltage protection element 101 in Fig. 13 in the following respects. In the overvoltage protection element 101 shown in Fig. 13, the arrangement of the set 101r is such that the set 101l is rotated 180° and placed on the positive side of the X direction, whereas in the overvoltage protection element 102 in Fig. 18, the arrangement of the set 102r is such that the set 102l is inverted in the X direction and placed on the positive side of the X direction. Furthermore, in Fig. 18, the plan view of the M2 wiring placed above the diodes 2l and 2r differs from that in Fig. 13.

[0150] As described above, in FIG. 17, the fourth well region 212l of the diode 2l is actually divided into well regions 212lt and 212lb. As shown in FIG. 18, M1 wirings 43l and 45l are disposed above the well regions 212lt and 212lb, respectively. Contacts 53l and 55l are disposed on the upper surfaces of the M1 wirings 43l and 45l, and M2 wirings 63l and 65l are disposed above the contacts 53l and 55l, respectively. Furthermore, as shown in FIG. 18, an M1 wiring 44l is disposed above the third well region 211l of the diode 2l in FIG. 17, a contact 54l is disposed on the upper surface of the M1 wiring 44l, and an M2 wiring 64l is disposed above the contact 54l.

[0151] Similar to the fourth well region 212l of the diode 2l, in FIG. 17, the eighth well region 212r of the diode 2r is actually divided into well regions 212rt and 212rb. As shown in FIG. 18, M1 wirings 43r and 45r are disposed above the well regions 212rt and 212rb, respectively. Contacts 53r and 55r are disposed on the upper surfaces of the M1 wirings 43r and 45r, and M2 wirings 63r and 65r are disposed above the contacts 53r and 55r, respectively. Furthermore, as shown in FIG. 18, an M1 wiring 44r is disposed above the seventh well region 211r of the diode 2r in FIG. 17, a contact 54r is disposed on the upper surface of the M1 wiring 44r, and an M2 wiring 64r is disposed above the contact 54r.

[0152] The M2 wiring 65l extends to the positive side in the X direction and is connected to the M2 wiring 64r. The second electrode T2 includes M2 wirings 62l, 63l, 65l, and 64r. The M2 wiring 63r extends to the negative side in the X direction and is connected to the M2 wiring 64l. The third electrode T3 includes M2 wirings 62r, 63r, 65r, and 64l.

[0153] The cross-sectional views of the metal wiring in the cross-sectional views XV1-XV2 and XV3-XV4 in Figures 15A and 16A, respectively, are cross-sectional views taken along lines XV1-XV2 and XV3-XV4 in Figure 18. Furthermore, the cross-sectional views of the metal wiring in the cross-sectional views XV5-XV6 and XV7-XV8 in Figures 15B and 16B, respectively, are cross-sectional views taken along lines XV5-XV6 and XV7-XV8 in Figure 18. Comparing Figure 18 with Figure 13, the direction in which the cross section XV7-XV8 in Figure 18 is viewed is reversed in the X direction from the direction in which the cross section X7-X8 in Figure 13 is viewed.

[0154] (Example of connection of an overvoltage protection element) Fig. 19 is a diagram showing a connection example when the overvoltage protection element 102 according to the third embodiment is used in combination with an IC 300. The same parts as those in the connection example of the overvoltage protection element 101 and IC 300 according to the second embodiment in Fig. 14 are given the same reference numerals, and their description will be omitted. Fig. 19 shows an example in which the overvoltage protection element 102 and IC 300 are separated onto different semiconductor substrates, but the overvoltage protection element 102 and IC 300 may also be formed on the same semiconductor substrate.

[0155] 14, the third electrode T3 of the overvoltage protection element 101 is set to the ground potential GND, whereas in FIG. 19, the fourth electrode T4 of the overvoltage protection element 102 is set to the ground potential GND.

[0156] 16A and 16B, the overvoltage protection element 102 has bidirectional polarity. The first electrode T1 of the overvoltage protection element 102 is connected to a signal line through which the input signal S1 propagates, and the ground potential GND is set to the fourth electrode T4. If the voltage of the input signal S1 is a first voltage V1, the overvoltage protection element 102 is in a state in which the first voltage V1 is applied to the first electrode T1 and the ground potential GND is applied to the fourth electrode T4.

[0157] When the input signal S1 has a voltage value within the normal voltage range defined in the specifications, the overvoltage protection element 101 does not allow current to flow between the first electrode T1 and the fourth electrode T4.

[0158] When an overvoltage surge of a positive voltage higher than the ground potential GND is superimposed on the input signal S1 and the first voltage V1 becomes a voltage higher than the first differential voltage with respect to the ground potential GND, the overvoltage protection element 102 operates to release the voltage of the first electrode T1 to the fourth electrode T4. This operation reduces the voltage of the input signal S1 toward the ground potential GND, thereby protecting the input circuit of the circuit block block1 of the IC300.

[0159] On the other hand, when an overvoltage surge on the negative voltage side lower than the ground potential is superimposed on the input signal S1 and the first voltage V1 becomes a voltage lower than the ground potential GND by the second differential voltage, the overvoltage protection element 102 operates to pass a current from the fourth electrode T4 to the first electrode T1. This operation pulls up the negative voltage of the input signal S1 toward the ground potential GND, thereby protecting the input circuit of the circuit block block1 of the IC300.

[0160] As described above, the overvoltage protection element 102 operates in a bidirectional manner, discharging the first voltage V1 to the ground potential GND when the first voltage V1, which is the voltage of the input signal S1, becomes a voltage higher than the first differential voltage with respect to the ground potential GND, or when it becomes a voltage lower than the second differential voltage.

[0161] (Package configuration including overvoltage protection element) Next, a package 202 including an overvoltage protection device 102 according to the third embodiment will be described.

[0162] The overall plan view of the overvoltage protection device 102 according to the third embodiment in FIG. 17 is compared with the overall plan view of the overvoltage protection device 100 according to the first embodiment in FIG. 7 and the plan view of the package 200 in FIG. 9A. In FIG. 7, the pads 4t and 4b are arranged on the main surface of the semiconductor substrate 3 at positions that are the same in the X direction but different in the Y direction. In FIG. 9A, the semiconductor substrate 3 of the overvoltage protection device 100 in FIG. 7 is rotated 90° counterclockwise. In contrast, in FIG. 17, the pads 4l and 4r are arranged at positions that are the same in the Y direction but different in the X direction. When placing the semiconductor substrate 3 in the package 202, the pads 4l and 4r can be easily connected to the first and second terminals arranged similarly to the package 200 in FIG. 9A without rotating the semiconductor substrate 3 from the orientation shown in FIG. 17. Furthermore, the electrodes appearing on the pads in FIG. 7 are the first electrode T1 and the third electrode T3, whereas in FIG. 17, they are the first electrode T1 and the fourth electrode T4.

[0163] Based on the above, a package 202 including an overvoltage protection element 102 according to a third embodiment will be described. The semiconductor substrate 3 of the overvoltage protection element 102 of FIG. 17 is placed in the package 202 in the orientation shown in the plan view of FIG. 17. The plan view of the package 202 differs from the plan view of the package 200 shown in FIG. 9A in that the fourth electrode T4, rather than the third electrode T3, is connected to the second terminal 82 of the package 202. The spacing between the first electrode T1 and the fourth electrode T4 arranged on the semiconductor substrate 3 is different from the spacing between the first electrode T1 and the third electrode T3 in FIG. 9A. The rest of the package is the same as that shown in FIG. 9A. The front view of the package 202 is the same as that of the package 200 shown in FIG. 9B.

[0164] As described above, the package 202 including the overvoltage protection element 102 is the same as that shown in FIGS. 9A and 9B except that the third electrode T3 is replaced with the fourth electrode T4 and the spacing between the first electrode T1 and the fourth electrode T4 on the semiconductor substrate 3 is different from that shown in FIG. 9A, and therefore is not shown in the drawings.

[0165] The package 202 including the overvoltage protection element 102 can reduce the volume occupied by the overvoltage protection element, as well as the parasitic capacitance connected to the signal line and manufacturing costs, compared to mounting an overvoltage protection element using multiple unidirectional vertical overvoltage protection chips.

[0166] (Effects of the third embodiment) The overvoltage protection element 102 can provide a bidirectional overvoltage protection element formed on the upper surface of a single semiconductor substrate 3, in which a surge current flows along the main surface of the semiconductor substrate 3. The overvoltage protection element 102 can protect a downstream IC by dissipating the first voltage V1, regardless of whether the first voltage V1 at the first electrode T1 is higher than the first differential voltage or lower than the second differential voltage with respect to the second voltage V2 at the fourth electrode T4. Compared to constructing an overvoltage protection element with bidirectional polarity using multiple unidirectional vertical overvoltage protection chips, the volume occupied by the overvoltage protection element can be reduced, and the parasitic capacitance connected to the signal lines and manufacturing costs can be reduced.

[0167] [Fourth embodiment] (Configuration of overvoltage protection element) 20A and 20B are cross-sectional views of an overvoltage protection element 103 according to the fourth embodiment. FIG. 20A is a cross-sectional view taken along lines XX1-XX2 and XX3-XX4 in the plan view of FIG. 22, which will be described later. FIG. 20B is a cross-sectional view taken along lines XX5-XX6 and XX7-XX8 in the plan view of FIG. 22, which will be described later. Although FIGS. 20A and 20B are separated due to space limitations, they are disposed on the same semiconductor substrate 3 and connected at a connection point E.

[0168] The overvoltage protection element 103 in FIGS. 20A and 20B differs from the overvoltage protection element 101 shown in FIGS. 10A and 10B in the following respects. The cross-sectional view shown in FIG. 10B is a view obtained by inverting FIG. 10A with a line that passes through X1 in FIG. 10A and is perpendicular to the line connecting X1-X2 as the axis of symmetry. On the other hand, the cross-sectional view in FIG. 20B is oriented in the same direction as FIG. 20A. Also, while the letter "r" is added to the reference symbols of the constituent members in FIG. 10B, the letter "t" is added to the reference symbols of the constituent members in FIG. 20B.

[0169] 10B, M2 wirings 61r, 62r, 63r, and 64r are connected to the third electrode T3, the fourth electrode T4, the fourth electrode T4, and the first electrode T1, respectively. Meanwhile, in FIG. 20B, M2 wirings 61t, 62t, 63t, and 64t are connected to the fifth electrode T5, the fourth electrode T4, the fourth electrode T4, and the third electrode T3, respectively. In other words, the connections between electrodes are different between FIGS. 20A and 20B compared to FIGS. 10A and 10B.

[0170] Other than the above, the well regions, diffusion regions, and metal wiring in FIGS. 20A and 20B are the same as those in FIGS. 10A and 10B, and the same parts as those in FIGS. 10A and 10B are designated by the same reference numerals and will not be described.

[0171] 21A and 21B are diagrams showing current paths in an overvoltage protection device 103 according to the fourth embodiment. The same parts as those in FIGS. 20A and 20B are denoted by the same reference numerals, and descriptions thereof will be omitted.

[0172] In the overvoltage protection element 103 of FIGS. 21A and 21B, a first voltage V1 is input to the first electrode T1, a second voltage V2 is input to the third electrode T3, and a third voltage V3 is input to the fifth electrode T5. Each of FIGS. 21A and 21B has a unidirectional polarity. In the overvoltage protection element 103 of the fourth embodiment, the elements of FIGS. 21A and 21B are connected at the common third electrode T3, and the elements of FIGS. 21A and 21B are used in parallel, thereby realizing an overvoltage protection element having two current paths with a unidirectional polarity. Hereinafter, a current path through which the overvoltage protection element can release an overvoltage is also referred to as a "channel." Hereinafter, N is a natural number, and N current paths are referred to as "N channels."

[0173] The voltage relationship between the electrodes and the current path in each of FIGS. 21A and 21B are similar to those of the overvoltage protection device 100 according to the first embodiment shown in FIG. 2, and therefore detailed description thereof will be omitted.

[0174] When the first voltage V1 is lower than the second voltage V2 by a first differential voltage, no current flows between the first electrode T1 and the third electrode T3 of the overvoltage protection element 103. Similarly, when the third voltage V3 is lower than the second voltage V2 by a second differential voltage, no current flows between the fifth electrode T5 and the third electrode T3 of the overvoltage protection element 103.

[0175] Here, the first differential voltage and the second differential voltage may be, for example, in the range of 5 V or more and 50 kV or less. Furthermore, the first differential voltage and the second differential voltage may be, for example, in the range of 8 V or more and 12 V or less.

[0176] When the first voltage V1 becomes higher than the second voltage V2 by at least a first differential voltage, a current flows from the first electrode T1 to the third electrode T3 along the path indicated by the solid arrow in Fig. 21A. Similarly, when the third voltage V3 becomes higher than the second voltage V2 by at least a second differential voltage, a current flows from the fifth electrode T5 to the third electrode T3 along the path indicated by the dashed arrow in Fig. 21B.

[0177] On the other hand, when the second voltage V2 is higher than the first voltage V1 by at least the first differential voltage, no current flows between the third electrode T3 and the first electrode T1. Similarly, when the second voltage V2 is higher than the third voltage V3 by at least the second differential voltage, no current flows between the third electrode T3 and the fifth electrode T5.

[0178] As described above, when the first voltage V1 input to the first electrode T1 is higher than the second voltage V2 input to the third electrode by at least the first differential voltage, the overvoltage protection element 103 passes a current from the first electrode T1 to the third electrode T3, thereby discharging the overvoltage input to the first electrode T1 to the third electrode T3. Furthermore, when the third voltage V3 input to the fifth electrode T5 is higher than the second voltage V2 input to the third electrode by at least the second differential voltage, the overvoltage protection element 103 passes a current from the fifth electrode T5 to the third electrode T3, thereby discharging the overvoltage input to the fifth electrode T5 to the third electrode T3. By discharging the overvoltage input to the first electrode T1 or the fifth electrode T5, the input terminal of an IC or LSI connected downstream of the overvoltage protection element 103 is protected from overvoltage.

[0179] That is, the overvoltage protection element 103 has two channels that can release overvoltage. In other words, the overvoltage protection element 103 realizes an overvoltage protection element with two channels and unidirectional polarity on one semiconductor substrate 3.

[0180] The cross-sectional view and current path of the overvoltage protection element 103 according to the fourth embodiment have been described above. Next, a plan view of the overvoltage protection element 103 will be described.

[0181] Fig. 22 is a plan view of the entire overvoltage protection element 103 according to the fourth embodiment. For convenience of explanation, Fig. 22 shows only the M2 wiring, the well region, and the semiconductor substrate, and it should be noted that other layers are not shown.

[0182] The overvoltage protection element 103 includes a first electrode T1, a thyristor 1l, a second electrode T2, a diode 2l, a third electrode T3, a fifth electrode T5, a thyristor 1t, a fourth electrode T4, and a diode 2t. The overvoltage protection element 103 further includes a seventh electrode T7, a thyristor 1r, a sixth electrode T6, a diode 2r, a ninth electrode T9, a thyristor 1b, an eighth electrode T8, and a diode 2b. The first electrode T1, the third electrode T3, the fifth electrode T5, the seventh electrode T7, and the ninth electrode T9 each include a circular pad portion. The pad portion is configured to be connectable to an input signal wiring provided outside the overvoltage protection element 103.

[0183] The first electrode T1, the thyristor 11, the second electrode T2, the diode 21, and the third electrode T3 of the overvoltage protection element 103 form one set, and their arrangement is similar to that of the first electrode T1, the thyristor 11, the second electrode T2, the diode 21, and the third electrode T3 in the overvoltage protection element 101 according to the second embodiment shown in FIG.

[0184] Similarly, the fifth electrode T5, thyristor 1t, fourth electrode T4, diode 2t, and third electrode T3 of the overvoltage protection element 103 form one set. Here, the third electrode T3 is the same as the set including the first electrode T1. The arrangement of the set including the fifth electrode T5 is rotated 90° clockwise around the center of the pad portion of the third electrode T3 from the set including the first electrode T1.

[0185] Similarly, the seventh electrode T7, thyristor 1r, sixth electrode T6, diode 2r, and third electrode T3 of the overvoltage protection element 103 form one set, and the ninth electrode T9, thyristor 1b, eighth electrode T8, diode 2b, and third electrode T3 form another set. Here, the third electrode T3 is the same as the set including the first electrode T1. The arrangement of the set including the seventh electrode T7 is rotated 90° clockwise around the center of the pad portion of the third electrode T3 from the set including the fifth electrode T5. Furthermore, the arrangement of the set including the ninth electrode T9 is rotated 90° clockwise around the center of the pad portion of the third electrode T3 from the set including the seventh electrode T7.

[0186] The cross-sectional views shown in Figures 20A and 21A are cross-sectional views taken along lines XX1-XX2 and XX3-XX4 of a group including the first electrode T1 in Figure 22. The cross-sectional views shown in Figures 20B and 21B are cross-sectional views taken along lines XX8-XX7 and XX6-XX5 of a group including the fifth electrode T5 in Figure 22. The cross-sectional views of the group including the seventh electrode T7 and the group including the ninth electrode T9 in Figure 22 are similar, so the cross-sectional views are omitted.

[0187] In the plan view of the overvoltage protection element 103 according to the fourth embodiment shown in FIG. 22, the group including the first electrode T1, the group including the fifth electrode T5, the group including the seventh electrode T7, and the group including the ninth electrode T9 each function as an overvoltage protection element having unidirectional polarity. In other words, the overvoltage protection element 103 is configured as a four-channel overvoltage protection element having unidirectional polarity. Cross-sectional views and current paths of two of the channels are shown in FIGS. 20A, 20B, 21A, and 21B. The number of channels used by the overvoltage protection element 103 can be selected from one to four. The number of channels mounted on the semiconductor substrate 3 of the overvoltage protection element 103 may be two, three, or five or more.

[0188] (Example of connection of an overvoltage protection element) Fig. 23 is a diagram showing a connection example when the overvoltage protection element 103 according to the fourth embodiment is used in combination with an IC 303. Fig. 23 shows an example in which the overvoltage protection element 103 and the IC 303 are separated onto different semiconductor substrates, but the overvoltage protection element 103 and the IC 303 may be formed on the same semiconductor substrate.

[0189] The IC303 has input terminals TS1 and TS2, and an input signal S1 is input to the input terminal TS1, and an input signal S2 is input to the input terminal TS2. Inside the IC303, the input signals S1 and S2 are input to a circuit block block1.

[0190] As described above, the overvoltage protection element 103 is an example having four channels of unidirectionally polarized overvoltage protection elements. Two of these four channels will be described: one including a set of first electrodes T1 and the other including a set of fifth electrodes T5. The first electrode T1 of the overvoltage protection element 103 is connected to a signal line through which an input signal S1 propagates, the third electrode T3 is set to a ground potential GND, and the fifth electrode T5 is connected to a signal line through which an input signal S2 propagates. If the voltage of the input signal S1 is a first voltage V1 and the voltage of the input signal S2 is a third voltage V3, the overvoltage protection element 103 is in a state in which the first voltage V1 is applied to the first electrode T1, the ground potential GND is applied to the third electrode T3, and the third voltage V3 is applied to the fifth electrode T5.

[0191] When the input signals S1 and S2 have voltage values ​​within the normal voltage range defined in the specifications, the overvoltage protection element 103 does not allow current to flow between the first electrode T1 and the third electrode T3 or between the fifth electrode T5 and the third electrode T3. Now consider the case where an overvoltage surge is superimposed on the input signal S1 or the input signal S2. When the first voltage V1 becomes higher than the first differential voltage relative to the ground potential GND, or when the third voltage V3 becomes higher than the second differential voltage relative to the ground potential GND, the overvoltage protection element 103 releases the voltage of the first electrode T1 or the fifth electrode T5 to the third electrode T3. This action pulls down the voltage of the input signal S1 or the input signal S2 toward the ground potential GND, thereby protecting the input circuit of circuit block 1 of IC303.

[0192] (Package configuration including overvoltage protection element) Next, a package 203 including an overvoltage protection device 103 according to the fourth embodiment will be described.

[0193] 24A and 24B are a plan view and a front view, respectively, of a package 203 including an overvoltage protection device 103 according to the fourth embodiment.

[0194] The package 203 includes a first terminal 81, a second terminal 82, a third terminal 83, a fourth terminal 84, and a fifth terminal 85, each of which includes a conductor. The first electrode T1, the third electrode T3, the fifth electrode T5, the seventh electrode T7, and the ninth electrode T9 of the overvoltage protection element 103 are electrically connected to the first terminal 81, the second terminal 82, the third terminal 83, the fourth terminal 84, and the fifth terminal 85 of the package 203 by bonding wires 91, 92, 93, 94, and 95, respectively. Here, if the number of channels arranged or used in the overvoltage protection element 103 is less than four, the number of terminals in the package 203 may be reduced corresponding to the number of channels.

[0195] The package 203 including the overvoltage protection element 103 can reduce the volume occupied by the overvoltage protection element, the parasitic capacitance connected to the signal line, and manufacturing costs compared to using four unidirectional vertical overvoltage protection chips to mount a four-channel overvoltage protection element.

[0196] (Effects of the fourth embodiment) The overvoltage protection element 103 can provide an overvoltage protection element that includes a thyristor 1 and a diode 2 that are connected in series and configured on the upper surface of a single semiconductor substrate 3, and through which a surge current flows along the main surface of the semiconductor substrate 3. Compared to configuring a unidirectional overvoltage protection element with multiple channels in which thyristors and diodes are connected in series using multiple vertical overvoltage protection chips with unidirectional polarity, the volume occupied by the overvoltage protection element can be reduced, and the parasitic capacitance connected to the signal line and manufacturing costs can be reduced.

[0197] [Fifth embodiment] (Configuration of overvoltage protection element) Fig. 25 is an enlarged plan view of the well region and diffusion region of the overvoltage protection element 104 according to the fifth embodiment. Fig. 25 shows the same area as the enlarged plan view of the well region and diffusion region of the overvoltage protection element 100 according to the first embodiment shown in Fig. 4, and shows only the semiconductor substrate 3, the well region, and the diffusion region.

[0198] 25 differs from FIG. 4 in the following respects. In FIG. 25, connection regions 1131 and 1132 connecting first well region 111 and second well region 112 are arranged in a partial region of semiconductor substrate 3 between first well region 111 and second well region 112 included in well region pair 11. Here, first well region 111 is of a first conductivity type, that is, n-type, and second well region 112 and connection regions 1131 and 1132 are of a second conductivity type, that is, p-type. Similarly, connection regions 1231 and 1232 are arranged in a partial region between well regions 121 and 122 included in well region pair 12, and connection regions 1331 and 1332 are arranged in a partial region between well regions 131 and 132 included in well region pair 13.

[0199] Fig. 26A is a cross-sectional view taken along line XXVI1-XXVI1 in Fig. 25. Fig. 26B is a cross-sectional view taken along line XXVI2-XXVI2 in Fig. 25.

[0200] The cross-sectional view of FIG. 26B is similar to that of FIG. 1, where two cross-sectional views taken along line I1-I2 of the overvoltage protection device 100 according to the first embodiment are arranged along the X direction. The arrangement of the second diffusion region 111b, the first well region 111, the semiconductor substrate 3, the second well region 112, and the third diffusion region 112a constitutes a thyristor having a pnipn structure. On the other hand, FIG. 26A differs from FIG. 26B in the following respects: a connection region 1131 is arranged between the first well region 111 and the second well region 112, connecting the first well region 111 and the second well region 112; and a connection region 1231 is arranged between the well regions 121 and 122, connecting the well regions 121 and 122. The region shown in FIG. 26A constitutes a thyristor having a pnpn structure.

[0201] The overvoltage protection element 104 according to the fifth embodiment shown in Figures 25, 26A, and 26B is the same as the overvoltage protection element 100 according to the first embodiment shown in Figures 1 and 4, except that connection regions such as the connection region 1131 are arranged, and therefore detailed description thereof will be omitted.

[0202] The purpose and effect of arranging the connection regions as shown in Figures 25 and 26A will be explained below. Generally, the breakdown voltage at which an overvoltage protection element turns on and acts to release an overvoltage surge in the input signal is set to an appropriate value based on the operating voltage of the downstream IC and the withstand voltage requirements of the input circuit. If the voltage at which the overvoltage protection element turns on is too high compared to the withstand voltage of the downstream IC, the downstream IC may be damaged before the input signal voltage reaches the voltage at which the overvoltage protection element turns on.

[0203] 25, an i-type silicon substrate, for example, is used as the semiconductor substrate 3. When an i-type silicon substrate is used, the breakdown voltage is, for example, 52V.

[0204] 25 and 26A, the pnipn structure included in the thyristor becomes a pnpn structure, and the breakdown voltage can be reduced to, for example, 12 V. The breakdown voltage depends on the distance between the connection regions 1131, 1132 and the third diffusion region 112a in the second well region 112, so this distance is set so that the breakdown voltage is appropriate. As described above, if the breakdown voltage required by the subsequent IC is, for example, 8 to 12 V, and the breakdown voltage of the i-type semiconductor substrate 3 is too high at 52 V, the breakdown voltage can be set to an appropriate value, for example, 12 V, by arranging the connection regions.

[0205] On the other hand, when the first electrode T1 of the overvoltage protection element 104 is connected to the signal line through which the input signal S1 propagates, the capacitance of the first electrode T1 is added to the wiring for the input signal S1. The capacitance of the first electrode T1 increases as the area of ​​the well region and diffusion region, including the connection region, electrically connected to the first electrode T1 increases. Therefore, the layout area of ​​the connection region is set so that the capacitance added to the wiring for the input signal S1 can be maintained at an appropriate value.

[0206] (Effects of the fifth embodiment) The overvoltage protection element 104 can provide an overvoltage protection element that includes a thyristor 1 and a diode 2 that are connected in series and that are configured on the upper surface of a single semiconductor substrate 3, and through which a surge current flows along the main surface of the semiconductor substrate 3. The overvoltage protection element 104 can set the breakdown voltage of the thyristor configured on the upper surface of the semiconductor substrate 3 to an appropriate value while maintaining the capacitance added to the wiring of the input signal at an appropriate value.

[0207] [Sixth embodiment] (Configuration of overvoltage protection element) Fig. 27 is a plan view of the thyristor 1 of the overvoltage protection element 105 according to the sixth embodiment. Fig. 27 shows the same areas as the plan view of the well region and diffusion region of the thyristor 1 of the overvoltage protection element 100 according to the first embodiment shown in Fig. 3, and shows only the semiconductor substrate 3, the well region, and the diffusion region.

[0208] As in FIG. 3, in FIG. 27, thyristor 1 includes a plurality of well region pairs, as indicated by well region pairs 11 to 13. FIG. 27 differs from FIG. 3 in the following respects. In FIG. 27, connection regions 1131 to 1134 connecting first well region 111 and second well region 112 are arranged in a partial region of semiconductor substrate 3 between first well region 111 and second well region 112 included in well region pair 11. Similarly, connection regions 1231 to 1235 are arranged in a partial region between well regions 121 and 122 included in well region pair 12, and connection regions 1331 to 1334 are arranged in a partial region between well regions 131 and 132 included in well region pair 13.

[0209] The plan view and cross-sectional view of one connection region are similar to those described in FIGS. 25 and 26A. Figure 27 differs from Figure 25 in the following respects. In Figure 25, the positions of the connection regions in the Y direction are consistent between adjacent well region pairs 11, 12, and 13. On the other hand, in Figure 27, in three adjacent well region pairs 11, 12, and 13, the positions of connection regions 1131, 1231, and 1331 in the Y direction are different between adjacent well region pairs, and are arranged so that every other connection region is the same. The same is true for connection regions 1131, 1232, and 1331, and the distances between connection regions 1131, 1231, 1331, and 1232 are arranged so that they are substantially equal.

[0210] The purpose and effect of arranging the connection regions as shown in Figure 27 will be explained. If the arrangement positions of the connection regions in the Y direction are the same between pairs of adjacent well regions, the current paths may be concentrated at the same position in the Y direction, which may result in a decrease in breakdown voltage. By arranging the connection regions as shown in Figure 27, the positions of the current paths in the Y direction are dispersed, thereby improving the breakdown voltage.

[0211] (Effects of the sixth embodiment) The overvoltage protection element 105 can provide an overvoltage protection element that includes a thyristor 1 and a diode 2 that are connected in series and that are configured on the upper surface of a single semiconductor substrate 3, and through which a surge current flows along the main surface of the semiconductor substrate 3. The overvoltage protection element 105 can set the breakdown voltage of the thyristor configured on the upper surface of the semiconductor substrate 3 to an appropriate value while maintaining an appropriate value of capacitance added to the wiring of the input signal. Furthermore, the overvoltage protection element 105 can improve the withstand voltage.

[0212] [Seventh embodiment] (Configuration of overvoltage protection element) Fig. 28 is an enlarged plan view of the well region and diffusion region of the overvoltage protection element 106 according to the seventh embodiment. Fig. 28 shows the same area as the enlarged plan view of the well region and diffusion region of the overvoltage protection element 104 according to the fifth embodiment shown in Fig. 25, and shows only the semiconductor substrate 3, the well region, and the diffusion region.

[0213] 28 differs from FIG. 25 in the following respects: In FIG. 28, the width in the X direction of first well region 111 is relatively large near the portions where it contacts connection regions 1131 and 1132, and is relatively small in portions away from the portions where it contacts connection regions 1131 and 1132. Similarly, the width in the X direction of well regions 121 and 131 is relatively large near the portions where it contacts connection regions 1231, 1232, 1331, and 1332, and is relatively small in portions away from the portions where it contacts connection regions 1231, 1232, 1331, and 1332.

[0214] The purpose and effect of setting the width of the well region in the X direction as shown in FIG. 28 will be described. By arranging the connection regions as shown in FIG. 28, the current that dissipates an overvoltage surge flows mainly to the connection region with low resistivity. Specifically, when dissipating an overvoltage surge, the current that flows from the second diffusion region 111b to the first well region 111 flows mainly through the connection regions 1131 and 1132 with low resistivity to the second well region 112 and then to the third diffusion region 112a. The current flowing in the portion of the first well region 111 away from the vicinity of the portion that contacts the connection regions 1131 and 1132 is relatively small. Therefore, even if the width of the first well region 111 in the X direction is relatively narrowed in the portion away from the vicinity of the portion that contacts the connection regions 1131 and 1132, the current dissipation capability and the breakdown voltage are hardly reduced.

[0215] On the other hand, by relatively narrowing the width of the first well region 111 in the X direction, the area of ​​the well region connected to the first electrode T1 can be reduced, and the capacitance added to the wiring for the input signal can be reduced.

[0216] (Effects of the Seventh Embodiment) The overvoltage protection element 106 can provide an overvoltage protection element that includes a thyristor 1 and a diode 2 that are connected in series and that are configured on the upper surface of a single semiconductor substrate 3, and through which a surge current flows along the main surface of the semiconductor substrate 3. The overvoltage protection element 106 can set the breakdown voltage of the thyristor configured on the upper surface of the semiconductor substrate 3 to an appropriate value while maintaining the capacitance added to the wiring of the input signal at an appropriate value. Furthermore, the overvoltage protection element 106 can reduce the capacitance added to the wiring of the input signal.

[0217] [Eighth embodiment] (Package configuration including overvoltage protection element) 29A and 29B are a plan view and a front view, respectively, of a package 207 including an overvoltage protection element according to the eighth embodiment. FIG. 29A is a plan view of the back surface of FIG. 29B, viewed from the negative side to the positive side in the Z direction. The package 207 in FIGS. 29A and 29B shows an example in which the semiconductor substrate 3 of the overvoltage protection element 100 according to the first embodiment is used. However, this is not a limitation, and the semiconductor substrate 3 of any of the overvoltage protection elements 101 to 106 may be used.

[0218] 29A and 29B show a case where the semiconductor substrate 3 of the overvoltage protection element 100 is disposed in a package 207, which is a chip size package (CSP). The main surface of the semiconductor substrate 3 is disposed facing the negative Z direction, and solder balls 96 and 97 are disposed on the first electrode T1 and the third electrode T3 on the main surface of the semiconductor substrate 3 to enable connection to the outside of the package. In addition, a protective film 98 containing resin is disposed on the back surface opposite the main surface of the semiconductor substrate 3 to protect the semiconductor substrate 3 from external impacts. According to the package 207, by disposing the overvoltage protection element 100 in a CSP, the volume occupied by the package can be further reduced, and the parasitic capacitance connected to the signal lines can be reduced.

[0219] (Effects of the eighth embodiment) The package 207 including the overvoltage protection element 100 can provide an overvoltage protection element that includes a thyristor 1 and a diode 2 that are connected in series and configured on the upper surface of a single semiconductor substrate 3, and through which a surge current flows along the main surface of the semiconductor substrate 3. The package 207 can further reduce the volume occupied by the package including the overvoltage protection element, and can also reduce the parasitic capacitance connected to the signal line.

[0220] [Other embodiments] Although several embodiments of the present disclosure have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. One or more elements of one embodiment can be combined with one or more elements of another embodiment. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are intended to be included within the scope and spirit of the invention, as well as within the scope of the invention and its equivalents as defined in the claims.

[0221] For example, in the overvoltage protection elements according to the first to eighth embodiments of the present disclosure, the semiconductor substrate 3 is an i-type, but the semiconductor substrate may be a p-type. Also, the semiconductor substrate 3 is not limited to a silicon (Si) substrate, and may be, for example, a silicon carbide (SiC) substrate.

[0222] (Addendum) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0223] (Appendix 1) Each of the overvoltage protection elements 100 to 106 according to an embodiment of the present disclosure includes a semiconductor substrate 3, a first well region 111 of a first conductivity type embedded in the upper surface of the semiconductor substrate 3, and a second well region 112 of a second conductivity type embedded in the upper surface of the semiconductor substrate 3 and spaced apart from the first well region 111. The overvoltage protection elements 100 to 106 further include a third well region 211 of the first conductivity type and a fourth well region 212 of the second conductivity type embedded in the upper surface of the semiconductor substrate 3 and spaced apart from the first well region 111 and the second well region 112. The third well region 211 and the fourth well region 212 are embedded and spaced apart from each other.

[0224] A first diffusion region 111a of a first conductivity type and a second diffusion region 111b of a second conductivity type are embedded and spaced apart from each other in a portion of the upper surface of the first well region 111. A third diffusion region 112a of a first conductivity type and a fourth diffusion region 112b of a second conductivity type are embedded and spaced apart from each other in a portion of the upper surface of the second well region 112. A fifth diffusion region 211a of a first conductivity type is embedded in a portion of the upper surface of the third well region 211. A sixth diffusion region 212b of a second conductivity type is embedded in a portion of the upper surface of the fourth well region 212.

[0225] The overvoltage protection elements 100 to 106 further include a first electrode T1, a second electrode T2, and a third electrode T3. The first electrode T1 is electrically connected to the first diffusion region 111a and the second diffusion region 111b. The second electrode T2 is electrically connected to the third diffusion region 112a, the fourth diffusion region 112b, and the sixth diffusion region 212b. The third electrode T3 is electrically connected to the fifth diffusion region 211a. The arrangement of the second diffusion region 111b, the first well region 111, the second well region 112, and the third diffusion region 112a forms a first pnpn junction, and the arrangement of the fourth well region 212 and the third well region 211 forms a second pn junction.

[0226] The overvoltage protection elements 100 to 106 can provide overvoltage protection elements that include a thyristor 1 and a diode 2 that are connected in series and configured on the upper surface of a single semiconductor substrate 3, and through which a surge current flows along the main surface of the semiconductor substrate 3. Compared to configuring an overvoltage protection element in which a thyristor and a diode are connected in series using two unidirectional vertical overvoltage protection chips, the volume occupied by the overvoltage protection element can be reduced, and the parasitic capacitance connected to the signal line and manufacturing costs can be reduced.

[0227] (Appendix 2) In the overvoltage protection elements 100 to 106 described in Supplementary Note 1, a first voltage V1 is input to the first electrode T1, and a second voltage V2 is input to the third electrode T3. When the first voltage V1 is higher than the second voltage V2 by a first differential voltage or more, a voltage equal to or greater than the breakdown voltage or breakover voltage is applied to the first pnpn junction.

[0228] (Appendix 3) The overvoltage protection elements 101 to 103 described in Appendix 1 further include a fifth well region 111r of a first conductivity type and a sixth well region 112r of a second conductivity type, which are embedded in the upper surface of the semiconductor substrate 3 at a distance from the first well region 111l (111) to the fourth well region 212l (212). The fifth well region 111r and the sixth well region 112r are embedded at a distance from each other. A seventh diffusion region 111ar of a first conductivity type and an eighth diffusion region 111br of a second conductivity type are embedded at a distance from each other in a part of the upper surface of the fifth well region 111r. A ninth diffusion region 112ar of a first conductivity type and a tenth diffusion region 112br of a second conductivity type are embedded at a distance from each other in a part of the upper surface of the sixth well region 112r.

[0229] The overvoltage protection elements 101 to 103 described in Appendix 1 further include a seventh well region 211r of a first conductivity type and an eighth well region 212r of a second conductivity type, which are embedded in the upper surface of the semiconductor substrate 3 and isolated from the first well region 111l (111) to the sixth well region 112r. The seventh well region 211r and the eighth well region 212r are embedded and isolated from each other. An eleventh diffusion region 211ar of the first conductivity type is embedded in a portion of the upper surface of the seventh well region 211r. A twelfth diffusion region 212br of the second conductivity type is embedded in a portion of the upper surface of the eighth well region 212r.

[0230] The arrangement of the eighth diffusion region 111br, the fifth well region 111r, the sixth well region 112r, and the ninth diffusion region 112ar forms a second pnpn junction, and the arrangement of the eighth well region 212r and the seventh well region 211r forms a second pn junction.

[0231] (Appendix 4) The overvoltage protection device 101 described in Supplementary Note 3 further includes a fourth electrode T4 electrically connected to the ninth diffusion region 112ar, the tenth diffusion region 112br, and the twelfth diffusion region 212br. The eleventh diffusion region 211ar is electrically connected to the first electrode T1, and the seventh diffusion region 111ar and the eighth diffusion region 111br are electrically connected to the third electrode T3.

[0232] (Appendix 5) In the overvoltage protection element 101 described in Supplementary Note 4, a first voltage V1 is input to the first electrode T1, and a second voltage V2 is input to the third electrode T3. When the first voltage V1 is higher than the second voltage V2 by a first differential voltage or more, a voltage equal to or greater than the breakdown voltage or breakover voltage is applied to the first pnpn junction. When the second voltage V2 is higher than the first voltage V1 by a second differential voltage or more, a voltage equal to or greater than the breakdown voltage or breakover voltage is applied to the second pnpn junction.

[0233] The overvoltage protection element 101 can provide a bidirectional overvoltage protection element formed on the upper surface of a single semiconductor substrate 3, in which a surge current flows along the main surface of the semiconductor substrate 3. The overvoltage protection element 101 can protect a downstream IC by dissipating the first voltage V1, regardless of whether the first voltage V1 at the first electrode T1 is higher than the first differential voltage or lower than the second differential voltage with respect to the second voltage V2 at the third electrode T3. Compared to constructing an overvoltage protection element with bidirectional polarity using multiple unidirectional vertical overvoltage protection chips, the volume occupied by the overvoltage protection element can be reduced, and the parasitic capacitance connected to the signal lines and manufacturing costs can be reduced.

[0234] (Appendix 6) The overvoltage protection element 102 described in Supplementary Note 3 further includes a fourth electrode T4 electrically connected to the seventh diffusion region 111ar and the eighth diffusion region 111br. The ninth diffusion region 112ar, the tenth diffusion region 112br, and the twelfth diffusion region 212br are electrically connected to the third electrode T3, and the eleventh diffusion region 211ar is electrically connected to the second electrode T2.

[0235] (Appendix 7) In the overvoltage protection element 102 described in Supplementary Note 6, a first voltage V1 is input to the first electrode T1, and a second voltage V2 is input to the fourth electrode T4. When the first voltage V1 is higher than the second voltage V2 by a first differential voltage or more, a voltage equal to or greater than the breakdown voltage or breakover voltage is applied to the first pnpn junction. When the second voltage V2 is higher than the first voltage V1 by a second differential voltage or more, a voltage equal to or greater than the breakdown voltage or breakover voltage is applied to the second pnpn junction.

[0236] The overvoltage protection element 102 can provide a bidirectional overvoltage protection element formed on the upper surface of a single semiconductor substrate 3, in which a surge current flows along the main surface of the semiconductor substrate 3. The overvoltage protection element 102 can protect a downstream IC by dissipating the first voltage V1, regardless of whether the first voltage V1 at the first electrode T1 is higher than the first differential voltage or lower than the second differential voltage with respect to the second voltage V2 at the fourth electrode T4. Compared to constructing an overvoltage protection element with bidirectional polarity using multiple unidirectional vertical overvoltage protection chips, the volume occupied by the overvoltage protection element can be reduced, and the parasitic capacitance connected to the signal lines and manufacturing costs can be reduced.

[0237] (Appendix 8) The overvoltage protection element 103 described in Supplementary Note 3 further includes a fourth electrode T4 electrically connected to the ninth diffusion region 112at, the tenth diffusion region 112bt, and the twelfth diffusion region 212bt, and a fifth electrode T5 electrically connected to the seventh diffusion region 111at and the eighth diffusion region 111bt. The eleventh diffusion region 211at is electrically connected to the third electrode T3.

[0238] (Appendix 9) In the overvoltage protection element 103 described in Supplementary Note 8, a first voltage V1 is input to the first electrode T1, a second voltage V2 is input to the third electrode T3, and a third voltage V3 is input to the fifth electrode T5. When the first voltage V1 is higher than the second voltage V2 by a first differential voltage or more, a voltage equal to or greater than the breakdown voltage or breakover voltage is applied to the first pnpn junction. When the third voltage V3 is higher than the second voltage V2 by a second differential voltage or more, a voltage equal to or greater than the breakdown voltage or breakover voltage is applied to the second pnpn junction.

[0239] The overvoltage protection element 103 can provide an overvoltage protection element having unidirectional polarity and multiple channels, including thyristors 1 and diodes 2 connected in series and configured on the upper surface of a single semiconductor substrate 3, through which surge current flows along the main surface of the semiconductor substrate 3. Compared to configuring a unidirectional overvoltage protection element having multiple channels in which thyristors and diodes are connected in series using multiple vertical overvoltage protection chips with unidirectional polarity, the volume occupied by the overvoltage protection element can be reduced, and the parasitic capacitance connected to signal lines and manufacturing costs can be reduced.

[0240] (Appendix 10) In the overvoltage protection element according to any one of Supplementary Notes 2, 5, 7, and 9, the first differential voltage may be in the range of 5 V to 50 kV.

[0241] (Appendix 11) In the overvoltage protection element according to any one of Supplementary Notes 2, 5, 7, and 9, the first differential voltage may be in the range of 8V or more and 12V or less.

[0242] (Appendix 12) In the overvoltage protection element according to any one of Supplementary Notes 5, 7, and 9, the first differential voltage and the second differential voltage may be in the range of 5 V or more and 50 kV or less.

[0243] (Appendix 13) In the overvoltage protection element according to any one of Supplementary Notes 5, 7, and 9, the first differential voltage and the second differential voltage may be in the range of 8V or more and 12V or less.

[0244] (Appendix 14) In the overvoltage protection element according to any one of Supplementary Notes 1 to 13, the semiconductor substrate 3 is p-type.

[0245] (Appendix 15) In the overvoltage protection element according to any one of Supplementary Notes 1 to 13, the semiconductor substrate 3 is an intrinsic semiconductor.

[0246] (Appendix 16) In the overvoltage protection element described in any one of Supplementary Notes 1 to 15, the first well region 111 and the second well region 112 extend in a first direction, that is, a Y direction, and are arranged adjacent to each other in a second direction, that is, an X direction, that intersects with the first direction. The first diffusion region 111a, the second diffusion region 111b, the third diffusion region 112a, and the fourth diffusion region 112b are arranged to extend in the first direction.

[0247] (Appendix 17) In the overvoltage protection element described in Supplementary Note 16, the third well region 211, the fourth well region 212, the fifth diffusion region 211a, and the sixth diffusion region 212b are arranged to extend in the second direction.

[0248] (Appendix 18) In the overvoltage protection element described in any one of Supplementary Notes 3 to 9, the first well region 111l, the second well region 112l, the fifth well region 111r, and the sixth well region 112r are arranged to extend in a first direction. The first well region 111l and the second well region 112l are arranged adjacent to each other in a second direction intersecting the first direction, and the fifth well region 111r and the sixth well region 112r are arranged adjacent to each other in the second direction. The first diffusion region 111al to the fourth diffusion region 112bl and the seventh diffusion region 111ar to the tenth diffusion region 112br are arranged to extend in the first direction.

[0249] (Appendix 19) In the overvoltage protection element described in Supplementary Note 18, the third well region 211l, the fourth well region 212l, the seventh well region 211r, and the eighth well region 212r are arranged to extend in the second direction, and the fifth diffusion region 211al, the sixth diffusion region 212bl, the eleventh diffusion region 211ar, and the twelfth diffusion region 212br are arranged to extend in the second direction.

[0250] (Appendix 20) In the overvoltage protection element described in any one of Supplementary Notes 3 to 9, the first well region 111l and the second well region 112l are arranged to extend in a first direction. The first well region 111l and the second well region 112l are arranged adjacent to each other in a second direction intersecting the first direction. The first diffusion region 111al to the fourth diffusion region 112bl are arranged to extend in the first direction. In the overvoltage protection element described in any one of Supplementary Notes 3 to 9, the fifth well region 111t and the sixth well region 112t are arranged to extend in the second direction. The fifth well region 111t and the sixth well region 112t are arranged adjacent to each other in the first direction. The seventh diffusion region 111at to the tenth diffusion region 112bt are arranged to extend in the second direction.

[0251] (Appendix 21) In the overvoltage protection element described in Supplementary Note 20, the third well region 211l, the fourth well region 212l, the fifth diffusion region 211al, and the sixth diffusion region 212bl are arranged to extend in the second direction, and the seventh well region 211t, the eighth well region 212t, the eleventh diffusion region 211at, and the twelfth diffusion region 212bt are arranged to extend in the first direction.

[0252] (Appendix 22) The overvoltage protection elements 104 to 106 described in any one of Supplementary Notes 1 to 21 may further include a second conductivity type connection region 1131 that connects the first well region 111 and the second well region 112 in a portion of the region between the first well region 111 and the second well region 112.

[0253] The overvoltage protection elements 104 to 106 allow the breakdown voltage of the thyristor formed on the upper surface of the semiconductor substrate 3 to be set to an appropriate value while maintaining the capacitance added to the wiring of the input signal at an appropriate value.

[0254] (Appendix 23) In the overvoltage protection elements 104 to 106 described in Supplementary Note 22, the distance between the connection region 1131 and the third diffusion region 112a in the second direction may be set so that the first differential voltage is in the range of 8V or more and 12V or less.

[0255] (Appendix 24) In the overvoltage protection element 105 described in Appendix 22, the first pnpn junction has a plurality of well region pairs, each including a first well region 111 and a second well region 112, arranged along the second direction, and the positions of the connection regions in the first direction may be different from each other in adjacent well region pairs.

[0256] (Appendix 25) In the overvoltage protection element 105 described in Supplementary Note 23, the positions of the connection regions in the first direction may be set so that the intervals between the connection regions are substantially equal in three pairs of well regions that are arranged closely to each other.

[0257] The overvoltage protection element 105 described in Supplementary Note 24 or 25 can set the breakdown voltage of the thyristor formed on the upper surface of the semiconductor substrate 3 to an appropriate value while maintaining an appropriate capacitance added to the wiring of the input signal. Furthermore, the overvoltage protection element 105 can improve the breakdown voltage.

[0258] (Appendix 26) In the overvoltage protection element 106 described in Supplementary Note 22, the width of the first well region 111 may be relatively large near the portion in contact with the connection region 1131 and relatively small in a portion away from the portion in contact with the connection region 1131.

[0259] The overvoltage protection element 106 can maintain an appropriate capacitance added to the wiring of the input signal, while setting an appropriate breakdown voltage for the thyristor formed on the upper surface of the semiconductor substrate 3. Furthermore, the overvoltage protection element 106 can reduce the capacitance added to the wiring of the input signal.

[0260] (Appendix 27) In the overvoltage protection element according to any one of Supplementary Notes 1 to 26, the first conductivity type is n-type, and the second conductivity type is p-type.

[0261] (Appendix 28) A package 200, 201 including an overvoltage protection element according to an embodiment of the present disclosure includes the overvoltage protection element 100, 101 described in any one of Supplementary Notes 1 to 5, a first terminal 81 electrically connected to the first electrode T1, and a second terminal 82 electrically connected to the third electrode T3. In the package, a semiconductor substrate 3 is disposed so as to overlap both a portion of the first terminal 81 and a portion of the second terminal 82 when viewed from the normal direction of the main surface of the semiconductor substrate 3.

[0262] (Appendix 29) In the packages 200 and 201 described in Supplementary Note 28, the first terminal 81 is connected to the first electrode T1 by a bonding wire 91, and the second terminal 82 is connected to the third electrode T3 by a bonding wire 92.

[0263] (Appendix 30) A package 202 including an overvoltage protection element according to one embodiment of the present disclosure includes the overvoltage protection element 102 described in Supplementary Note 6 or 7, a first terminal 81 electrically connected to the first electrode T1, and a second terminal 82 electrically connected to the fourth electrode T4. In the package 202, the semiconductor substrate 3 is disposed so as to overlap both a portion of the first terminal 81 and a portion of the second terminal 82 when viewed from the normal direction of the main surface of the semiconductor substrate 3.

[0264] (Appendix 31) In the package 202 described in Supplementary Note 30, the first terminal 81 is connected to the first electrode T1 by a bonding wire 91, and the second terminal 82 is connected to the fourth electrode T4 by a bonding wire 92.

[0265] (Appendix 32) A package 203 including an overvoltage protection element according to one embodiment of the present disclosure comprises an overvoltage protection element 103 described in Appendix 8 or 9, a first terminal 81 electrically connected to the first electrode T1, a second terminal 82 electrically connected to the third electrode T3, and a third terminal 83 electrically connected to the fifth electrode T5.

[0266] (Appendix 33) In the package 203 described in Appendix 31, the first terminal 81 is connected to the first electrode T1 by a bonding wire 91, the second terminal 82 is connected to the third electrode T3 by a bonding wire 92, and the third terminal 83 is connected to the fifth electrode T5 by a bonding wire 93.

[0267] (Appendix 34) A package 207 including an overvoltage protection element according to one embodiment of the present disclosure includes an overvoltage protection element 100-106 described in any one of Appendices 1 to 27, and a protective film 98 disposed on the back surface of a semiconductor substrate 3 opposite to the main surface on which the overvoltage protection elements 100-106 are formed. [Explanation of symbols]

[0268] 1, 1b, 1l, 1r, 1t thyristors 1a, 1b area 2, 2b, 2l, 2r, 2t diodes 3. Semiconductor substrate 4b, 4l, 4r, 4t pad section 11, 11l, 11r, 12, 13 well area pairs 31a~34a, 31ar~34ar, 31b~34b, 31br~34br, 51~54, 51r~54r Contact 41~48, 41r~44r M1 wiring 61~64, 61l~65l, 61r~65r, 61t~64t M2 wiring 71, 72 Insulating film 81~85 1st~5th terminal 91, 92, 93, 94, 95 Bonding wire 96, 97 Solder balls 98 Protective film 100~106 Overvoltage protection element 101l, 101r, 102l, 102r set 111, 111l First well region 111a, 111al First diffusion region 111ar, 111at 7th diffusion region 111b, 111bl Second diffusion region 111br, 111bt 8th diffusion region 111r, 111t 5th well region 112, 112l Second well region 112a, 112al third diffusion region 112ar, 112at 9th diffusion region 112b, 112bl Fourth diffusion region 112br, 112bt 10th diffusion region 112r, 112t 6th well region 121, 122, 131, 132 well areas 200, 201, 202, 203, 207 packages 211, 211l Third well region 211a, 211al 5th diffusion region 211ar, 211at 11th diffusion region 211r, 211t 7th well region 212, 212l 4th well region 212b, 212bl 6th diffusion region 212br, 212bt 12th diffusion region 212r, 212t 8th well region 1131~1134, 1231~1235, 1331~1334 connection area A, B, C, D, E connection points block1 circuit block GND Ground potential S1, S2 input signal T1~T9 1st~9th electrode TS1, TS2 input terminals V1 First voltage V2 Second voltage V3 Third voltage

Claims

1. a semiconductor substrate; a first well region of a first conductivity type buried in an upper surface of the semiconductor substrate; a first diffusion region of a first conductivity type and a second diffusion region of a second conductivity type, the first diffusion region and the second diffusion region being embedded in a portion of an upper surface of the first well region and spaced apart from each other; a second well region of a second conductivity type embedded in the upper surface of the semiconductor substrate and spaced apart from the first well region; a third diffusion region of the first conductivity type and a fourth diffusion region of the second conductivity type, the third diffusion region and the fourth diffusion region being spaced apart from each other and embedded in a portion of an upper surface of the second well region; a third well region of the first conductivity type embedded in the upper surface of the semiconductor substrate and isolated from the first well region and the second well region; a fifth diffusion region of the first conductivity type embedded in a portion of an upper surface of the third well region; a fourth well region of a second conductivity type embedded in the upper surface of the semiconductor substrate and spaced apart from the first well region, the second well region, and the third well region; a sixth diffusion region of the second conductivity type embedded in a portion of an upper surface of the fourth well region; a first electrode electrically connected to the first diffusion region and the second diffusion region; a second electrode electrically connected to the third diffusion region, the fourth diffusion region, and the sixth diffusion region; a third electrode electrically connected to the fifth diffusion region; Equipped with a first pnpn junction is formed by an arrangement of the second diffusion region, the first well region, the second well region, and the third diffusion region; a first pn junction is formed by the arrangement of the fourth well region and the third well region; Overvoltage protection element.

2. a first voltage is applied to the first electrode; a second voltage is input to the third electrode; When the first voltage becomes higher than the second voltage by a first differential voltage or more, a voltage equal to or greater than a breakdown voltage or a breakover voltage is applied to the first pnpn junction. The overvoltage protection device according to claim 1 .

3. a fifth well region of the first conductivity type embedded in the upper surface of the semiconductor substrate and spaced apart from the first to fourth well regions; a seventh diffusion region of the first conductivity type and an eighth diffusion region of the second conductivity type, the seventh diffusion region and the eighth diffusion region being spaced apart from each other and embedded in a portion of an upper surface of the fifth well region; a sixth well region of a second conductivity type embedded in the upper surface of the semiconductor substrate and spaced apart from the first to fifth well regions; a ninth diffusion region of the first conductivity type and a tenth diffusion region of the second conductivity type, the ninth diffusion region and the tenth diffusion region being spaced apart from each other and embedded in a portion of an upper surface of the sixth well region; a seventh well region of the first conductivity type embedded in the upper surface of the semiconductor substrate and isolated from the first to sixth well regions; an eleventh diffusion region of the first conductivity type embedded in a portion of an upper surface of the seventh well region; an eighth well region of a second conductivity type embedded in the upper surface of the semiconductor substrate and spaced apart from the first to seventh well regions; a twelfth diffusion region of the second conductivity type embedded in a portion of an upper surface of the eighth well region; Further provided with a second pnpn junction is formed by an arrangement of the eighth diffusion region, the fifth well region, the sixth well region, and the ninth diffusion region; a second pn junction is formed by the arrangement of the eighth well region and the seventh well region; The overvoltage protection device according to claim 1 .

4. a fourth electrode electrically connected to the ninth diffusion region, the tenth diffusion region, and the twelfth diffusion region; the eleventh diffusion region is electrically connected to the first electrode; the seventh diffusion region and the eighth diffusion region are electrically connected to the third electrode; The overvoltage protection device according to claim 3 .

5. a first voltage is applied to the first electrode; a second voltage is input to the third electrode; when the first voltage becomes higher than the second voltage by a first differential voltage or more, a voltage equal to or greater than a breakdown voltage or a breakover voltage is applied to the first pnpn junction, When the second voltage becomes higher than the first voltage by a second voltage difference or more, a voltage equal to or greater than a breakdown voltage or a breakover voltage is applied to the second pnpn junction. The overvoltage protection device according to claim 4 .

6. a fourth electrode electrically connected to the seventh diffusion region and the eighth diffusion region; the ninth diffusion region, the tenth diffusion region, and the twelfth diffusion region are electrically connected to the third electrode; the eleventh diffusion region is electrically connected to the second electrode; The overvoltage protection device according to claim 3 .

7. a first voltage is applied to the first electrode; a second voltage is input to the fourth electrode; when the first voltage becomes higher than the second voltage by a first differential voltage or more, a voltage equal to or greater than a breakdown voltage or a breakover voltage is applied to the first pnpn junction, When the second voltage becomes higher than the first voltage by a second voltage difference or more, a voltage equal to or greater than a breakdown voltage or a breakover voltage is applied to the second pnpn junction. The overvoltage protection device according to claim 6 .

8. 8. The overvoltage protection element according to claim 2, wherein the first differential voltage is in the range of 5 V to 50 kV.

9. 8. The overvoltage protection device according to claim 1, wherein the semiconductor substrate is p-type.

10. 8. The overvoltage protection device according to claim 1, wherein the semiconductor substrate is an intrinsic semiconductor.

11. the first well region and the second well region extend in a first direction and are disposed adjacent to each other in a second direction intersecting the first direction; the first diffusion region, the second diffusion region, the third diffusion region, and the fourth diffusion region are arranged to extend in the first direction; The overvoltage protection element according to claim 1 .

12. The overvoltage protection element according to claim 11 , further comprising a connection region of a second conductivity type connecting the first well region and the second well region in a portion of a region between the first well region and the second well region.

13. the first pnpn junction includes a plurality of well region pairs, each including the first well region and the second well region, arranged along the second direction; In the pair of adjacent well regions, the positions of the connection regions in the first direction are different from each other. The overvoltage protection device of claim 12.

14. In the three pairs of well regions that are closely arranged, the positions of the connection regions in the first direction are set so that the intervals between the connection regions are substantially equal.

14. The overvoltage protection device of claim 13.

15. the width of the first well region is relatively large in the vicinity of a portion in contact with the connection region and is relatively small in a portion away from the vicinity of the portion in contact with the connection region; The overvoltage protection device of claim 12.

16. 8. The overvoltage protection device according to claim 1, wherein the first conductivity type is n-type and the second conductivity type is p-type.

17. An overvoltage protection element according to any one of claims 1, 2, 4, and 5; a first terminal electrically connected to the first electrode; a second terminal electrically connected to the third electrode; Equipped with the semiconductor substrate is disposed so as to overlap both a portion of the first terminal and a portion of the second terminal when viewed in a normal direction of a main surface of the semiconductor substrate; package.

18. the first terminal is connected to the first electrode by a bonding wire; the second terminal is connected to the third electrode by a bonding wire; 18. The package of claim 17.

19. An overvoltage protection element according to any one of claims 1 to 7; a protective film disposed on a rear surface of the semiconductor substrate opposite to a main surface on which the overvoltage protection element is formed; Equipped with package.

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