Pixel circuit, display device including the pixel circuit, and electronic device including the display device

Abstract

To provide a pixel circuit suitable for realizing a display device having high resolution.SOLUTION: A first transistor including a control electrode connected to a first node, a first electrode receiving a first power supply voltage, and a second electrode connected to a second node, a second transistor including a control electrode receiving a write gate signal, a first electrode receiving a data voltage, and a second electrode connected to a third node, a third transistor including a control electrode receiving a compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the second node, a control electrode receiving an initialization gate signal; A fourth transistor including a first electrode connected to the second node and a second electrode receiving the initialization voltage, a storage capacitor including a first electrode connected to the third node and a second electrode connected to the first node, and a light emitting element including an anode electrode connected to the second node and a second electrode receiving the second power supply voltage.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a pixel circuit, a display device including the pixel circuit, and an electronic device including the display device. [Background technology]

[0002] The display device includes a display panel and a display panel driver. The display panel includes gate lines, data lines, and pixel circuits. The display panel driver includes a gate driver that provides gate signals to the gate lines, a data driver that provides data voltages to the data lines, and a driver controller that controls the gate driver and the data driver.

[0003] Generally, a pixel circuit includes a source follower structure to compensate for a shift in the threshold voltage of a driving transistor included in the pixel circuit due to degradation of the pixel circuit. A parasitic capacitor is formed by a light emitting element included in the pixel circuit. Deterioration of the pixel circuit can change the capacitance of the parasitic capacitor. The change in the capacitance of the parasitic capacitor can cause a deviation in the threshold voltage compensation value provided by the source follower structure, which can prevent the pixel circuit from accurately emitting light at a target brightness. Furthermore, when a pixel circuit includes a source follower structure, the compensation time for the threshold voltage of the driving transistor is insufficient. Therefore, in a pixel circuit including a source follower structure, the threshold voltage of the driving transistor is not sufficiently compensated, and as a result, the pixel circuit including a source follower structure cannot accurately emit light at a target brightness.

[0004] Recently, display devices that provide virtual reality (VR) or augmented reality (AR) have become prominent. To this end, display devices are required to have a high pixel per inch (PPI) and high resolution, but pixel circuits including a source follower structure have limitations in implementing display devices with high PPI and high resolution. Summary of the Invention [Problem to be solved by the invention]

[0005] An object of the present invention is to provide a pixel circuit with high PPI and high integration.

[0006] Another object of the present invention is to provide a display device including the pixel circuit.

[0007] It is still another object of the present invention to provide an electronic device including the display device.

[0008] However, the object of the present invention is not limited to the above-mentioned object, and can be expanded in various ways without departing from the spirit and scope of the present invention. [Means for solving the problem]

[0009] In order to achieve the object of the present invention, a pixel circuit according to an embodiment of the present invention is characterized by including: (1) a first transistor including a control electrode connected to a first node, a first electrode for receiving a first power supply voltage, and a second electrode connected to a second node; (2) a second transistor including a control electrode for receiving a write gate signal, a first electrode for receiving a data voltage, and a second electrode connected to a third node; (3) a third transistor including a control electrode for receiving a compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the second node; (4) a fourth transistor including a control electrode for receiving an initialization gate signal, a first electrode connected to the second node, and a second electrode for receiving an initialization voltage; (5) a holding capacitor including a first electrode connected to the third node and a second electrode connected to the first node; and (6) a light-emitting element including an anode electrode connected to the second node and a second electrode for receiving a second power supply voltage.

[0010] The light emitting device may sequentially operate in a first interval in which the first node, the second node, and the third node are initialized, a second interval in which a threshold voltage of the first transistor is compensated, a third interval in which the data voltage is transmitted to the third node, a fourth interval in which the anode electrode of the light emitting element is initialized, and a fifth interval in which the light emitting element emits light at a brightness corresponding to the data voltage.

[0011] In the first interval, the write gate signal may have an activation level, the compensation gate signal may have an activation level, the initialization gate signal may have an activation level, the data voltage may have a first data voltage level, and the first power supply voltage applied to the first transistor may have a first power supply voltage level.

[0012] In the second interval, the write gate signal may have the activation level, the compensation gate signal may have the activation level, the initialization gate signal may have a deactivation level, the data voltage may have the first data voltage level, and the first power supply voltage may have a second power supply voltage level higher than the first power supply voltage level.

[0013] The data voltage having the first data voltage level may be the data voltage corresponding to the minimum gray scale.

[0014] In the third period, the write gate signal may have the activation level, the compensation gate signal may have the activation level, the initialization gate signal may have the deactivation level, the data voltage may have a second data voltage level corresponding to a target brightness, and the first power supply voltage may have the second power supply voltage level.

[0015] In the fourth period, the write gate signal may have an inactive level, the compensation gate signal may have an inactive level, the initialization gate signal may have the activated level, the data voltage may have a third data voltage level, and the first power supply voltage may have the second power supply voltage level.

[0016] In the fifth period, the write gate signal may have the activation level, the compensation gate signal may have the deactivation level, the initialization gate signal may have the deactivation level, the data voltage may have the third data voltage level, and the first power supply voltage may have the second power supply voltage level.

[0017] The data voltage having the third data voltage level may be a reference voltage.

[0018] In order to achieve another object of the present invention, a display device according to the present invention includes a display panel including a pixel circuit, and a display panel driver for driving the display panel, wherein the pixel circuit includes: (1) a first transistor including a control electrode connected to a first node, a first electrode for receiving a first power supply voltage, and a second electrode connected to a second node; (2) a second transistor including a control electrode for receiving a write gate signal, a first electrode for receiving a data voltage, and a second electrode connected to a third node; (3) a third transistor including a control electrode for receiving a compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the second node; (4) a fourth transistor including a control electrode for receiving an initialization gate signal, a first electrode connected to the second node, and a second electrode for receiving an initialization voltage; (5) a holding capacitor including a first electrode connected to the third node and a second electrode connected to the first node; and (6) a light-emitting element including an anode electrode connected to the second node and a second electrode for receiving a second power supply voltage.

[0019] The pixel circuit may sequentially operate in a first interval in which the first node, the second node, and the third node are initialized, a second interval in which a threshold voltage of the first transistor is compensated, a third interval in which the data voltage is transmitted to the third node, a fourth interval in which the anode electrode of the light-emitting element is initialized, and a fifth interval in which the light-emitting element emits light at a luminance corresponding to the data voltage.

[0020] In the first interval, the write gate signal may have an activation level, the compensation gate signal may have an activation level, the initialization gate signal may have an activation level, the data voltage may have a first data voltage level, and the first power supply voltage applied to the first transistor may have a first power supply voltage level.

[0021] In the second interval, the write gate signal may have the activation level, the compensation gate signal may have the activation level, the initialization gate signal may have a deactivation level, the data voltage may have the first data voltage level, and the first power supply voltage may have a second power supply voltage level higher than the first power supply voltage level.

[0022] In the third period, the write gate signal may have the activation level, the compensation gate signal may have the activation level, the initialization gate signal may have the deactivation level, the data voltage may have a second data voltage level corresponding to a target brightness, and the first power supply voltage may have the second power supply voltage level.

[0023] In the fourth period, the write gate signal may have an inactive level, the compensation gate signal may have an inactive level, the initialization gate signal may have the activated level, the data voltage may have a third data voltage level, and the first power supply voltage may have the second power supply voltage level.

[0024] In the fifth period, the write gate signal may have the activation level, the compensation gate signal may have the deactivation level, the initialization gate signal may have the deactivation level, the data voltage may have the third data voltage level, and the first power supply voltage may have the second power supply voltage level.

[0025] The pixel circuit and other pixel circuits included in the display panel are commonly connected to a first global signal line, and the pixel circuit and the other pixel circuits can simultaneously receive the compensation gate signal via the first global signal line.

[0026] The pixel circuit and other pixel circuits included in the display panel are commonly connected to a second global signal line, and the pixel circuit and the other pixel circuits can simultaneously receive the initialization gate signal via the second global signal line.

[0027] In order to achieve still another object of the present invention, an electronic device according to the present invention includes a processor that provides an input control signal and input image data, a memory that stores data information for the operation of the processor, a display panel including a pixel circuit, and a display panel driver that drives the display panel based on the input control signal and the input image data, wherein the pixel circuit includes: (1) a first transistor including a control electrode connected to a first node, a first electrode that receives a first power supply voltage, and a second electrode that is connected to a second node; and (2) a control electrode that receives a write gate signal, a first electrode that receives a data voltage, and a second electrode that is connected to a third node. (3) a third transistor including a control electrode for receiving a compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the second node; (4) a fourth transistor including a control electrode for receiving an initialization gate signal, a first electrode connected to the second node, and a second electrode for receiving an initialization voltage; (5) a holding capacitor including a first electrode connected to the third node and a second electrode connected to the first node; and (6) a light-emitting element including an anode electrode connected to the second node and a second electrode for receiving a second power supply voltage.

[0028] The pixel circuit and other pixel circuits included in the display panel may be commonly connected to a first global signal line, and the pixel circuit and the other pixel circuits may simultaneously receive the compensation gate signal via the first global signal line, and the pixel circuit and the other pixel circuits may be commonly connected to a second global signal line, and the pixel circuit and the other pixel circuits may simultaneously receive the initialization gate signal via the second global signal line. [Effects of the Invention]

[0029] Since the pixel circuit according to the present invention includes fewer transistors and capacitors than conventional pixel circuits that include five or more transistors and one or more capacitors, the area occupied by one pixel circuit on a display panel can be reduced, and the integration density of the pixel circuit can be increased.

[0030] In addition, since a series of pixel circuits are commonly connected to a first global signal line and simultaneously receive a compensation gate signal via the first global signal line, and a series of pixel circuits are commonly connected to a second global signal line and simultaneously receive an initialization gate signal via the second global signal line, a separate scan driver for outputting a compensation gate signal that is provided differently for each pixel row and an initialization gate signal that is provided differently for each pixel row may not be required. As a result, dead space and power consumption of the display device may be reduced. Since the dead space of the display device is reduced, the integration density of the pixel circuits may be increased.

[0031] As the integration density of pixel circuits increases, the display device can have a high PPI and a high resolution, and the display quality of the display device can be improved. [Brief explanation of the drawings]

[0032] [Figure 1] FIG. 1 is a block diagram showing a display device according to an embodiment of the present invention. [Figure 2] FIG. 2 is a circuit diagram showing an example of a pixel circuit included in a display panel included in the display device of FIG. [Figure 3a] FIG. 3a is a diagram showing the operation when a compensation gate signal and an initialization gate signal are applied to the pixel circuit of FIG. [Figure 3b] FIG. 3b is a diagram illustrating the operation when a write gate signal is applied to the pixel circuit of FIG. [Figure 4] FIG. 4 is a timing diagram showing the operation of the pixel circuit of FIG. [Figure 5] FIG. 5 is a circuit diagram showing the operation of the pixel circuit of FIG. 2 in the first interval of the timing diagram of FIG. [Figure 6] FIG. 6 is a circuit diagram showing the operation of the pixel circuit of FIG. 2 in the second interval of the timing diagram of FIG. [Figure 7] FIG. 7 is a circuit diagram showing the operation of the pixel circuit of FIG. 2 in the third interval of the timing diagram of FIG. [Figure 8] FIG. 8 is a circuit diagram showing the operation of the pixel circuit of FIG. 2 in the fourth interval of the timing chart of FIG. [Figure 9] FIG. 9 is a circuit diagram showing the operation of the pixel circuit of FIG. 2 in the fifth interval of the timing chart of FIG. [Figure 10] FIG. 10 is a circuit diagram showing another example of a pixel circuit included in a display panel included in the display device of FIG. [Figure 11] FIG. 11 is a timing diagram showing the operation of the pixel circuit of FIG. [Figure 12] FIG. 12 is a block diagram illustrating an electronic device according to an embodiment of the present invention. [Figure 13] FIG. 13 is a schematic diagram showing the electronic device of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0033] The present invention will now be described in more detail with reference to the accompanying drawings.

[0034] FIG. 1 is a block diagram showing a display device 1 according to an embodiment of the present invention.

[0035] 1, the display device 1 includes a display panel 100 and a display panel driver 500. The display panel driver 500 includes a driver control unit 200, a gate driver 300, and a data driver 400.

[0036] For example, the drive control unit 200 and the data driver 400 are formed on one chip. A drive module in which the drive control unit 200 and the data driver 400 are formed on one chip is called a timing controller embedded data driver (TED).

[0037] The display panel 100 includes a display section that displays an image and a peripheral section that is disposed adjacent to the display section. For example, the peripheral section is called a bezel.

[0038] The display panel 100 includes gate lines (GL), data lines (DL), and pixel circuits (PX). For example, the gate lines (GL) extend in a first direction (D1), and the data lines (DL) extend in a second direction (D2) that intersects with the first direction (D1).

[0039] In one embodiment, the pixel circuit (PX) includes first to fourth transistors, a storage capacitor, and a light-emitting element. Compared to a conventional pixel circuit including five or more transistors and one or more capacitors, the number of transistors and capacitors included in the pixel circuit (PX) may be reduced. The reduction in the number of transistors and capacitors included in the pixel circuit (PX) may reduce the area occupied by one pixel circuit (PX) on the display panel 100. The reduction in the area occupied by one pixel circuit (PX) on the display panel 100 increases the integration density of the pixel circuit (PX). The increased integration density of the pixel circuit (PX) allows the display device 1 to have a high PPI and high resolution. Therefore, the display quality of the display device 1 may be improved.

[0040] In one embodiment, the pixel circuit (PX) includes a drive transistor and a compensation transistor. The compensation transistor can diode-connect the control electrode of the drive transistor and the second electrode of the drive transistor in response to a compensation gate signal having an activation level. The diode-connected structure compensates for the threshold voltage of the drive transistor. Compensating for the threshold voltage of the drive transistor using the diode-connected structure allows the threshold voltage of the drive transistor to be accurately compensated for regardless of degradation of the parasitic capacitor of the light-emitting element. That is, even if the parasitic capacitor of the light-emitting element degrades, the threshold voltage of the drive transistor can be accurately compensated for. Since the threshold voltage of the drive transistor is accurately compensated, the pixel circuit (PX) can accurately emit light at a target luminance. This can improve the display quality of the display device 1.

[0041] In one embodiment, a series of pixel circuits (PX) included in the display panel 100 may be commonly connected to a first global signal line. Since the series of pixel circuits (PX) are commonly connected to the first global signal line, the series of pixel circuits (PX) can simultaneously receive a compensation gate signal via the first global signal line. Furthermore, a series of pixel circuits (PX) included in the display panel 100 may be commonly connected to a second global signal line. Since the series of pixel circuits (PX) are commonly connected to the second global signal line, the series of pixel circuits (PX) can simultaneously receive an initialization gate signal via the second global signal line.

[0042] Since the pixel circuits (PX) simultaneously receive the compensation gate signals via the first global signal line, a separate scan driver is not required to generate and output the compensation gate signals provided differently for each pixel row. Furthermore, since the pixel circuits (PX) simultaneously receive the initialization gate signals via the second global signal line, a separate scan driver is not required to generate and output the initialization gate signals provided differently for each pixel row. Since a separate scan driver is not required, the dead space and power consumption of the display device 1 can be reduced. Furthermore, since the dead space of the display device 1 is reduced, the number of pixel circuits (PX) included in the display panel 100 can be increased. In other words, the integration density of the pixel circuits (PX) can be increased. By increasing the integration density of the pixel circuits (PX), the display device 1 can have a high PPI and high resolution. Therefore, the display quality of the display device 1 can be improved.

[0043] The drive control unit 200 receives input image data (IMG) and input control signals (CONT) from an external device. For example, the input image data (IMG) includes red image data, green image data, and blue image data. According to an embodiment, the input image data (IMG) further includes white image data. For example, the input image data (IMG) includes magenta image data, yellow image data, and cyan image data. The input control signals (CONT) include a master clock signal and a data enable signal. The input control signals (CONT) further include a vertical synchronization signal and a horizontal synchronization signal.

[0044] The drive control unit 200 generates a gate control signal (CONT1), a data control signal (CONT2), and a data signal (DATA) based on the input image data (IMG) and the input control signal (CONT).

[0045] The driving control unit 200 generates a gate control signal (CONT1) for controlling the operation of the gate driver 300 based on the input control signal (CONT), and outputs the signal to the gate driver 300. The gate control signal (CONT1) includes a vertical start signal and a gate clock signal.

[0046] The driving control unit 200 generates a data control signal (CONT2) for controlling the operation of the data driver 500 based on the input control signal (CONT), and outputs the data control signal (CONT2) to the data driver 400. The data control signal (CONT2) includes a horizontal start signal and a load signal.

[0047] The driving control unit 200 generates a data signal (DATA) based on input image data (IMG), and outputs the data signal (DATA) to the data driver 400.

[0048] The gate driver 300 generates gate signals to be transmitted to the pixel circuits (PX) via the gate lines (GL) in response to the gate control signals (CONT1) input from the drive controller 200. The gate driver 300 outputs the gate signals via the gate lines (GL). For example, the gate driver 300 is mounted on the periphery of the display panel 100.

[0049] The data driver 400 receives a data control signal CONT2 and a data signal DATA from the drive controller 200. The data driver 400 converts the digital data signal DATA into an analog data voltage VDATA. The data driver 400 outputs the data voltage VDATA through the data line DL.

[0050] FIG. 2 is a circuit diagram showing an example of a pixel circuit (PX) included in the display panel 100 included in the display device 1 of FIG.

[0051] As shown in FIG. 2, the pixel circuit (PX) includes first to fourth transistors (T1 to T4), a holding capacitor (CHOLD), and a light-emitting element (EE).

[0052] The display panel 100 includes first to m-th pixel rows extending in a first direction (D1), where m is an integer equal to or greater than 2. Each of the first to m-th pixel rows includes a series of pixel circuits (PX). For ease of explanation, however, it is assumed that the pixel circuit (PX) in FIG. 2 is the pixel circuit (PX) included in the n-th pixel row, where n is an integer equal to or greater than 1 and equal to or less than m.

[0053] The first transistor (T1) includes a control electrode connected to the first node (N1), a first electrode receiving the first power supply voltage (V1), and a second electrode connected to the second node (N2). The first transistor (T1) generates a drive current based on the data voltage (VDATA). The first transistor (T1) is referred to as a drive transistor.

[0054] The second transistor (T2) includes a control electrode that receives the nth write gate signal (GW[n]), a first electrode that receives the data voltage (VDATA), and a second electrode that is connected to the third node (N3).

[0055] The third transistor (T3) includes a control electrode for receiving a compensation gate signal (GC), a first electrode connected to the first node (N1), and a second electrode connected to the second node (N2), and is referred to as a compensation transistor.

[0056] The control electrode of the third transistor (T3) is connected to the first global signal line, and the control electrode of the third transistor (T3) receives the compensation gate signal (GC) via the first global signal line.

[0057] The fourth transistor (T4) includes a control electrode for receiving an initialization gate signal (GI), a first electrode connected to the second node (N2), and a second electrode for receiving an initialization voltage (VINT).

[0058] The control electrode of the fourth transistor (T4) is connected to the second global signal line, i.e., the control electrode of the fourth transistor (T4) receives the initialization gate signal (GI) via the second global signal line.

[0059] The holding capacitor (CHOLD) includes a first electrode connected to the third node (N3) and a second electrode connected to the first node (N1).

[0060] The light emitting element (EE) includes an anode electrode connected to the second node (N2) and a cathode electrode to which the second power supply voltage (ELVSS) is applied.

[0061] The first to fourth transistors (T1 to T4) are PMOS (P-channel Metal Oxide Semiconductor) transistors. When the first transistor (T1) is a PMOS transistor, the driving current generated by the first transistor (T1) can be increased compared to when the first transistor (T1) is an NMOS (N-channel Metal Oxide Semiconductor) transistor. Since the driving current generated by the first transistor (T1) is increased, the stability of the pixel circuit (PX) can be increased.

[0062] Compared to a conventional pixel circuit including five or more transistors and one or more capacitors, the number of transistors and capacitors included in the pixel circuit (PX) can be reduced. The reduction in the number of transistors and capacitors included in the pixel circuit (PX) can reduce the area occupied by one pixel circuit (PX) on the display panel 100. The reduction in the area occupied by one pixel circuit (PX) on the display panel 100 can increase the integration density of the pixel circuit (PX). The increased integration density of the pixel circuit (PX) allows the display device 1 to have a high PPI and high resolution. Therefore, the display quality of the display device 1 can be improved.

[0063] The third transistor (T3) may diode-connect the first node (N1) and the second node (N2) in response to a compensation gate signal (GC) having an activation level. The diode-connected structure may compensate for the threshold voltage of the first transistor (T1). Compensating for the threshold voltage of the first transistor (T1) through the diode-connected structure may accurately compensate for the threshold voltage of the first transistor (T1) regardless of degradation of the parasitic capacitor of the light-emitting element (EE). That is, even if the parasitic capacitor of the light-emitting element (EE) degrades, the threshold voltage of the first transistor (T1) may be accurately compensated for. Since the threshold voltage of the first transistor (T1) is accurately compensated, the pixel circuit (PX) may accurately emit light at a target luminance. Therefore, the display quality of the display device 1 may be improved.

[0064] A series of pixel circuits (PX) included in the display panel 100 may be commonly connected to a first global signal line that transmits a compensation gate signal (GC). Specifically, a control electrode of a third transistor (T3) included in each of the series of pixel circuits (PX) may be connected to the first global signal line. Since the series of pixel circuits (PX) are commonly connected to the first global signal line, the pixel circuits (PX) can simultaneously receive the compensation gate signal (GC) via the first global signal line. Furthermore, a series of pixel circuits (PX) included in the display panel 100 are commonly connected to a second global signal line that transmits an initialization gate signal (GI). Specifically, a control electrode of a fourth transistor (T4) included in each of the pixel circuits (PX) is connected to the second global signal line. Since the series of pixel circuits (PX) are commonly connected to the second global signal line, the series of pixel circuits (PX) can simultaneously receive the initialization gate signal (GI) via the second global signal line.

[0065] In contrast, the write gate signal (GW) may be provided differently for each pixel row via the write gate signal line. For example, a first write gate signal may be provided to the pixel circuits (PX) of the first pixel row via the first write gate line. A second write gate signal may be provided to the pixel circuits (PX) of the second pixel row via the second write gate line. In this manner, an nth write gate signal (GW[n]) may be provided to the pixel circuits (PX) of the nth pixel row via the nth write gate line.

[0066] Since the pixel circuits (PX) simultaneously receive the compensation gate signal (GC) via the first global signal line, a separate scan driver for generating and outputting a compensation gate signal provided differently for each pixel row may be unnecessary. Furthermore, since the pixel circuits (PX) simultaneously receive the initialization gate signal (GI) via the second global signal line, a separate scan driver for generating and outputting an initialization gate signal provided differently for each pixel row may be unnecessary. Because a separate scan driver is unnecessary, the dead space and power consumption of the display device 1 can be reduced. Furthermore, since the dead space of the display device 1 is reduced, the number of pixel circuits (PX) included in the display panel 100 can be increased. That is, the integration density of the pixel circuits (PX) can be increased. By increasing the integration density of the pixel circuits (PX), the display device 1 can have a high PPI and high resolution. Therefore, the display quality of the display device 1 can be improved.

[0067] Fig. 3a is a diagram showing an operation in which a compensation gate signal (GC) and an initialization gate signal (GI) are applied to the pixel circuit (PX) of Fig. 2. Fig. 3b is a diagram showing an operation in which a write gate signal (GW) is applied to the pixel circuit (PX) of Fig. 2.

[0068] 3a and 3b, the compensation gate signal (GC) may be simultaneously provided to the pixel circuits (PX) included in the display panel 100. Also, the initialization gate signal (GI) may be simultaneously provided to the pixel circuits (PX) included in the display panel 100. Meanwhile, the write gate signal (GW) may be provided differently for each pixel row via the write gate line.

[0069] A series of pixel circuits (PX) included in the display panel 100 can be commonly connected to a first global signal line (GSL1) that transmits a compensation gate signal (GC). Since the series of pixel circuits (PX) are commonly connected to the first global signal line (GSL1), the series of pixel circuits (PX) can simultaneously receive the compensation gate signal (GC).

[0070] In addition, a series of pixel circuits (PX) included in the display panel 100 can be commonly connected to a second global signal line (GSL2) that transmits an initialization gate signal (GI). Since the series of pixel circuits (PX) are commonly connected to the second global signal line (GSL2), the series of pixel circuits (PX) can simultaneously receive the initialization gate signal (GI).

[0071] On the other hand, the write gate signal (GW) can be provided differently for each pixel row via the write gate line (GWL).

[0072] For example, a first write gate signal may be provided to the pixel circuits (PX) of a first pixel row via a first write gate line, a second write gate signal may be provided to the pixel circuits (PX) of a second pixel row via a second write gate line, and in this manner, an nth write gate signal (GW[n]) may be provided to the pixel circuits (PX) of an nth pixel row via an nth write gate line (GWL[n]).

[0073] For example, write gate signals (GW) having an activation level may be sequentially provided to a series of pixel rows. After a first write gate signal having an activation level is provided to a first write gate line, a second write gate signal having an activation level may be provided to a second write gate line. Also, after the second write gate signal having an activation level is provided to the second write gate line, a third write gate signal having an activation level may be provided to the third write gate line. In this manner, after an (m-1)th write gate signal having an activation level is provided to the (m-1)th write gate line, an mth write gate signal having an activation level may be provided to the mth write gate line.

[0074] FIG. 4 is a timing diagram showing the operation of the pixel circuit (PX) of FIG. 2. FIG. 5 is a circuit diagram showing the operation of the pixel circuit (PX) of FIG. 2 in a first interval (P1) of the timing diagram of FIG. 4. FIG. 6 is a circuit diagram showing the operation of the pixel circuit (PX) of FIG. 2 in a second interval (P2) of the timing diagram of FIG. 4. FIG. 7 is a circuit diagram showing the operation of the pixel circuit (PX) of FIG. 2 in a third interval (P3) of the timing diagram of FIG. 4. FIG. 8 is a circuit diagram showing the operation of the pixel circuit (PX) of FIG. 2 in a fourth interval (P4) of the timing diagram of FIG. 4. FIG. 9 is a circuit diagram showing the operation of the pixel circuit (PX) of FIG. 2 in a fifth interval (P4) of the timing diagram of FIG. 4.

[0075] As shown in FIG. 4, the sections in which the pixel circuit (PX) operates include a first section (P1), a second section (P2), a third section (P3), a fourth section (P4), and a fifth section (P5). Here, since the first to fourth transistors (T1 to T4) are PMOS transistors, the activation level of the compensation gate signal (GC) is low, and the inactivation level of the compensation gate signal (GC) is high, which is higher than the low level. Also, the activation level of the initialization gate signal (GI) is low, and the inactivation level of the initialization gate signal (GI) is high. Also, the activation level of the write gate signal (GW) is low, and the inactivation level of the write gate signal (GW) is high.

[0076] The first section (P1) is a first initialization section in which the first to third nodes (N1 to N3) are initialized. The second section (P2) is a compensation section in which the threshold voltage of the first transistor (T1) is compensated. The third section (P3) is a data transmission section in which the data voltage (VDATA) is transmitted to the third node (N3). The fourth section (P4) is a second initialization section in which the anode electrode of the light-emitting element (EE) is initialized. The fifth section (P5) is an emission section in which the light-emitting element (EE) emits light.

[0077] In the first section (P1), the first to m-th write gate signals (GW[1] to GW[m]) have an activation level. In the second section (P2), the first to m-th write gate signals (GW[1] to GW[m]) have an activation level. In the fourth section (P4), the first to m-th write gate signals (GW[1] to GW[m]) have a deactivation level. In addition, in the fifth section (P5), the first to m-th write gate signals (GW[1] to GW[m]) have an activation level.

[0078] In contrast, in the third period (P3), write gate signals (GW) having an activation level may be sequentially provided to a series of pixel rows via the write gate lines (GWL). For example, in the third period (P3), a first write gate signal (GW[1]) having an activation level is provided to the first pixel row. At this time, the second to m-th write gate signals (GW[2] to GW[m]) have inactive levels. After the first write gate signal (GW[1]) having an activation level is provided to the first pixel row, a second write gate signal (GW[2]) having an activation level is provided to the second pixel row. At this time, the first write gate signal (GW[1]) and the third to m-th write gate signals (GW[3] to GW[m]) have inactive levels. In this manner, after the (m-1)th write gate signal (GW[m-1]) having an activation level is provided to the (m-1)th pixel row, the mth write gate signal (GW[m]) having an activation level is provided to the mth pixel row, and the first to (m-1)th write gate signals (GW[1] to GW[m-1]) have a deactivation level.

[0079] For convenience of explanation, the following description will be given based on the pixel circuit PX included in the nth pixel row that receives the nth write gate signal GW[n].

[0080] As shown in FIGS. 4 and 5, in the first period (P1), the compensation gate signal (GC) has an activated level. The initialization gate signal (GI) has an activated level. The n-th write gate signal (GW[n]) has an activated level. Also, the data voltage (VDATA) has a first data voltage level (VBLACK). The data voltage (VDATA) having the first data voltage level (VBLACK) may correspond to the minimum grayscale. That is, the data voltage (VDATA) having the first data voltage level (VBLACK) may correspond to black luminance. Also, the first power supply voltage (V1) may have a first power supply voltage level (ELVSS'). The first power supply voltage level (ELVSS') may be the same as the level of the second power supply voltage (ELVSS).

[0081] In response to the nth write gate signal (GW[n]) having an activation level, the second transistor (T2) can be turned on, in response to the compensation gate signal (GC) having an activation level, the third transistor (T3) can be turned on, and in response to the initialization gate signal (GI) having an activation level, the fourth transistor (T4) can be turned on.

[0082] The turned-on second transistor T2 transfers the data voltage VDATA having the first data voltage level VBLACK to the third node N3, and the third node N3 is thus initialized to the data voltage VDATA having the first data voltage level VBLACK.

[0083] The turned-on fourth transistor T4 transfers the initialization voltage VINT to the second node N2, so that the second node N2 is initialized to the initialization voltage VINT.

[0084] The turned-on third transistor (T3) transfers the initialization voltage (VINT) of the second node (N2) to the first node (N1), and the first node (N1) is thus initialized to the initialization voltage (VINT).

[0085] A control electrode of the first transistor (T1) may have an initialization voltage (VINT), and a first electrode of the first transistor (T1) may have a first power supply voltage (V1) having a first power supply voltage level (ELVSS').

[0086] Here, the magnitude of the difference between the initialization voltage (VINT) and the first power supply voltage (V1) having the first power supply voltage level (ELVSS') may be smaller than the threshold voltage of the first transistor (T1). Accordingly, the magnitude of the difference between the voltage of the control electrode of the first transistor (T1) and the voltage of the first electrode of the first transistor (T1) may be smaller than the threshold voltage of the first transistor (T1). Since the magnitude of the difference between the voltage of the control electrode of the first transistor (T1) and the voltage of the first electrode of the first transistor (T1) is smaller than the threshold voltage of the first transistor (T1), the first transistor (T1) may be turned off.

[0087] Meanwhile, in the first section (P1), the series of pixel circuits (PX) can simultaneously receive a compensation gate signal (GC) having an activation level via the first global signal line (GSL1). The series of pixel circuits (PX) receive an initialization gate signal (GI) having an activation level via the second global signal line (GSL2). At this time, the first to mth write gate signals (GW[1] to GW[m]) have activation levels. Because the compensation gate signal (GC) has an activation level, the initialization gate signal (GI) has an activation level, and the first to mth write gate signals (GW[1] to GW[m]) have activation levels, the series of pixel circuits (PX) can simultaneously perform an initialization operation to initialize the first node (N1). The series of pixel circuits (PX) can simultaneously perform an initialization operation to initialize the second node (N2). Furthermore, the series of pixel circuits (PX) can simultaneously perform an initialization operation to initialize the third node (N3).

[0088] As shown in FIGS. 4 and 6, in the second period (P2), the compensation gate signal (GC) has an activated level, the initialization gate signal (GI) has a deactivated level, the nth write gate signal (GW[n]) has an activated level, the data voltage (VDATA) has a first data voltage level (VBLACK), and the first power supply voltage (V1) has a second power supply voltage level (ELVDD). The second power supply voltage level (ELVDD) is higher than the level of the second power supply voltage (ELVSS).

[0089] The second transistor T2 may be turned on in response to the nth write gate signal GW[n] having an activation level, the third transistor T3 may be turned on in response to the compensation gate signal GC having an activation level, and the fourth transistor T4 may be turned off in response to the initialization gate signal GI having an inactivation level.

[0090] The turned-on second transistor T2 may transmit a data voltage VDATA having a first data voltage level VBLACK to the third node N3, so that the third node N3 may maintain the data voltage VDATA having the first data voltage level VBLACK.

[0091] A control electrode of the first transistor (T1) may have an initialization voltage (VINT), and a first electrode of the first transistor (T1) may have a first power supply voltage (V1) having a second power supply voltage level (ELVDD).

[0092] In this case, the difference between the initialization voltage (VINT) and the first power supply voltage (V1) having the second power supply voltage level (ELVDD) may be greater than the threshold voltage of the first transistor (T1). Accordingly, the difference between the voltage of the control electrode of the first transistor (T1) and the voltage of the first electrode of the first transistor (T1) may be greater than the threshold voltage of the first transistor (T1). Because the difference between the voltage of the control electrode of the first transistor (T1) and the voltage of the first electrode of the first transistor (T1) is greater than the threshold voltage of the first transistor (T1), the first transistor (T1) may be turned on, and the voltage of the second node (N2) may increase.

[0093] The turned-on third transistor T3 may transfer the voltage of the second node N2 to the first node N1. As a result, the voltage of the second node N2 increases, and the voltage of the first node N1 also increases. That is, the voltage of the control electrode of the first transistor T1 may increase.

[0094] When the difference between the voltage of the control electrode of the first transistor T1 and the voltage of the first electrode of the first transistor T1 is equal to the threshold voltage of the first transistor T1, the first transistor T1 may be turned off. Here, the voltage of the first node N1 may be calculated using Equation 1: ELVDD+Vth. Here, ELVDD refers to the first power supply voltage V1 having the second power supply voltage level ELVDD, and Vth refers to the threshold voltage of the first transistor T1.

[0095] The holding capacitor (CHOLD) may store the difference between the voltage of the third node (N3) and the voltage of the first node (N1). The voltage stored in the holding capacitor (CHOLD) may be calculated by Equation 2: "VBLACK-(ELVDD+Vth)", where VBLACK represents the data voltage (VDDATA) having a first data voltage level (VBLACK), ELVDD represents the first power supply voltage (V1) having a second power supply voltage level (ELVDD), and Vth represents the threshold voltage of the first transistor (T1).

[0096] Meanwhile, in the second period (P2), the series of pixel circuits (PX) may simultaneously receive the compensation gate signal (GC) having an activation level via the first global signal line (GSL1). Here, the first to mth write gate signals (GW[1] to GW[m]) may have activation levels. Because the compensation gate signal (GC) has an activation level and the first to mth write gate signals (GW[1] to GW[m]) have activation levels, the series of pixel circuits (PX) may simultaneously perform compensation operations to compensate for the threshold voltages of the first transistors (T1).

[0097] As shown in FIGS. 4 and 7, in the third period (P3), the compensation gate signal (GC) may have an activated level. The initialization gate signal (GI) may have a deactivated level. The nth write gate signal (GW[n]) may have an activated level. The data voltage (VDATA) may have a second data voltage level (D[n]). The data voltage (VDATA) having the second data voltage level (D[n]) may correspond to a target luminance of the pixel circuit (PX). The first power supply voltage (V1) may have a second power supply voltage level (ELVDD).

[0098] In response to the nth write gate signal (GW[n]) having an activation level, the second transistor (T2) may be turned on, in response to the compensation gate signal (GC) having an activation level, the third transistor (T3) may be turned on, and in response to the initialization gate signal (GI) having an inactivation level, the fourth transistor (T4) may be turned off.

[0099] The turned-on second transistor T2 may transmit a data voltage VDATA having a second data voltage level D[n] to the third node N3. Accordingly, the voltage level of the third node N3 may change from the first data voltage level VBLACK to the second data voltage level D[n]. That is, the third node N3 may have a data voltage VDATA having the second data voltage level D[n].

[0100] Since the voltage level of the third node (N3) changes, the voltage of the first node (N1) may change due to the coupling operation of the holding capacitor (CHOLD). The voltage of the first node (N1) may be calculated by Equation 3: ELVDD+Vth+(D[n]-VBLACK) where D[n] represents the data voltage (VDATA) having the second data voltage level (D[n]), VBLACK represents the data voltage (VDATA) having the first data voltage level (VBLACK), ELVDD represents the first power supply voltage (V1) having the second power supply voltage level (ELVDD), and Vth represents the threshold voltage of the first transistor (T1).

[0101] The voltage of the control electrode of the first transistor (T1) may be the same as the voltage of the first node (N1), and the first electrode of the first transistor (T1) may have a first power supply voltage (V1) having a second power supply voltage level (ELVDD).

[0102] Here, the magnitude of the difference between the voltage of the first node (N1) and the first power supply voltage (V1) having the second power supply voltage level (ELVDD) may be greater than the threshold voltage of the first transistor (T1). Accordingly, the magnitude of the difference between the voltage of the control electrode of the first transistor (T1) and the voltage of the first electrode of the first transistor (T1) may be greater than the threshold voltage of the first transistor (T1). Because the magnitude of the difference between the voltage of the control electrode of the first transistor (T1) and the voltage of the first electrode of the first transistor (T1) is greater than the threshold voltage of the first transistor (T1), the first transistor (T1) may be turned on, and the voltage of the second node (N2) may increase.

[0103] The turned-on third transistor T3 may transfer the voltage at the second node N2 to the first node N1. As the voltage at the second node N2 increases, the voltage at the first node N1 may also increase. That is, the voltage at the control electrode of the first transistor T1 may increase.

[0104] When the difference between the voltage of the control electrode of the first transistor T1 and the voltage of the first electrode of the first transistor T1 is equal to the threshold voltage of the first transistor T1, the first transistor T1 may be turned off. Here, the voltage of the first node N1 may be calculated using Equation 1: ELVDD+Vth. Here, ELVDD refers to the first power supply voltage V1 having the second power supply voltage level ELVDD, and Vth refers to the threshold voltage of the first transistor T1.

[0105] Meanwhile, in the third period (P3), the first to m-th write gate signals (GW[1] to GW[m]) may have an activation level in sequence. Since the first to m-th write gate signals (GW[1] to GW[m]) have an activation level in sequence, the data voltage (VDATA) having the second data voltage level (D[n]) may be sequentially transmitted to the third node (N3).

[0106] 4 and 8, in the fourth period (P4), the compensation gate signal (GC) may have an inactive level, the initialization gate signal (GI) may have an active level, the nth write gate signal (GW[n]) may have an inactive level, the data voltage (VDATA) may have a third data voltage level (VREF), and the first power supply voltage (V1) may have a second power supply voltage level (ELVDD).

[0107] For example, the data voltage (VDATA) having the third data voltage level (VREF) may be a reference voltage. For example, the reference voltage may be smaller than the data voltage (VDATA) having the first data voltage level (VBLACK) corresponding to the minimum grayscale. For example, the reference voltage may be the same as the data voltage (VDATA) having the first data voltage level (VBLACK) corresponding to the minimum grayscale.

[0108] In response to the nth write gate signal (GW[n]) having an inactive level, the second transistor (T2) may be turned off, in response to the compensation gate signal (GC) having an inactive level, the third transistor (T3) may be turned off, and in response to the initialization gate signal (GI) having an active level, the fourth transistor (T4) may be turned on.

[0109] The turned-on fourth transistor T4 may transfer the initialization voltage VINT to the second node N2. Accordingly, the second node N2 may be initialized to the initialization voltage VINT. That is, the anode electrode of the light emitting element EE may be initialized to the initialization voltage VINT.

[0110] Meanwhile, in the fourth period (P4), the series of pixel circuits (PX) may receive the initialization gate signal (GI) having an activation level via the second global signal line (GSL2). Since the series of pixel circuits (PX) simultaneously receive the initialization gate signal (GI) having an activation level, the series of pixel circuits (PX) can simultaneously perform an initialization operation to initialize the second node (N2). That is, the pixel circuits (PX) can simultaneously perform an initialization operation to initialize the anode electrodes of the light-emitting elements (EE).

[0111] As shown in FIGS. 4 and 9, in the fifth period (P5), the compensation gate signal (GC) may have an inactive level, the initialization gate signal (GI) may have an inactive level, the nth write gate signal (GW[n]) may have an active level, the data voltage (VDATA) may have a third data voltage level (VREF), and the first power supply voltage (V1) may have a second power supply voltage level (ELVDD).

[0112] The second transistor (T2) may be turned on in response to the nth write gate signal (GW[n]) having an activated level, the third transistor (T3) may be turned off in response to the compensation gate signal (GC) having an inactivated level, and the fourth transistor (T4) may be turned off in response to the initialization gate signal (GI) having an inactivated level.

[0113] The turned-on second transistor T2 may transmit a data voltage VDATA having a third data voltage level VREF to the third node N3. Accordingly, the voltage level of the third node N3 may change from the second data voltage level D[n] to the third data voltage level VREF. That is, the third node N3 may have a data voltage VDATA having the third data voltage level VREF.

[0114] Since the voltage level of the third node (N3) changes, the voltage of the first node (N1) may change due to the coupling operation of the holding capacitor (CHOLD). Here, the voltage of the first node (N1) may be calculated by Equation 4: ELVDD + Vth + (VREF-D[n]) where D[n] represents the data voltage (VDATA) having the second data voltage level (D[n]), VREF represents the data voltage (VDATA) having the third data voltage level (VREF), ELVDD represents the first power supply voltage (V1) having the second power supply voltage level (ELVDD), and Vth represents the threshold voltage of the first transistor (T1).

[0115] The voltage of the control electrode of the first transistor (T1) may be the same as the voltage of the first node (N1), and the first electrode of the first transistor (T1) may have a first power supply voltage (V1) having a second power supply voltage level (ELVDD).

[0116] Here, the magnitude of the difference between the voltage of the first node (N1) and the first power supply voltage (V1) having the second power supply voltage level (ELVDD) may be greater than the threshold voltage of the first transistor (T1). Accordingly, the magnitude of the difference between the voltage of the control electrode of the first transistor (T1) and the voltage of the first electrode of the first transistor (T1) may be greater than the threshold voltage of the first transistor (T1). Since the magnitude of the difference between the voltage of the control electrode of the first transistor (T1) and the voltage of the first electrode of the first transistor (T1) is greater than the threshold voltage of the first transistor (T1), the first transistor (T1) may be turned on.

[0117] The turned-on first transistor (T1) may generate a drive current based on the voltage at the control electrode of the first transistor (T1) and the voltage at the first electrode of the first transistor (T1).

[0118] Here, the drive current is expressed by the following formula: "Id = k * (Vsg + Vth)^2" (Id = k × (Vsg + Vth)2 ) where Id denotes the drive current, k denotes a constant (e.g., a transconductance parameter of the first transistor (T1)), and Vsg denotes the difference between the voltage of the first electrode of the first transistor (T1) and the voltage of the control electrode of the first transistor (T1).

[0119] The voltage of the first electrode of the first transistor T1 has a second power supply voltage level (ELVDD), and the voltage of the control electrode of the first transistor T1 is calculated by Equation 4: ELVDD + Vth + (VREF - D[n]), so the difference between the voltage of the first electrode of the first transistor T1 and the voltage of the control electrode of the first transistor T1 can be calculated by Equation 6: Vsg = -Vth - (VREF - D[n]), where Vsg refers to the difference between the voltage of the first electrode of the first transistor T1 and the voltage of the control electrode of the first transistor T1, Vth refers to the threshold voltage of the first transistor, VREF refers to the data voltage (VDATA) having the third data voltage level (VREF), and D[n] refers to the data voltage (VDATA) having the second data voltage level (D[n]).

[0120] The difference between the voltage of the first electrode of the first transistor (T1) and the voltage of the control electrode of the first transistor (T1) is calculated by "Equation 6: 'Vsg = -Vth-(VREF-D[n])'", so the drive current is calculated by "Equation 7: 'Id = k * (VREF - D[n])^2' (Id = k × (VREF - D[n]) 2 ) where Id denotes the drive current, k denotes a constant (e.g., a transconductance parameter of the first transistor (T1)), Vth denotes the threshold voltage of the first transistor (T1), VREF denotes the data voltage (VDATA) having the third data voltage level (VREF), and D[n] denotes the data voltage (VDATA) having the second data voltage level (D[n]).

[0121] That is, in the fifth section (P5), the driving current may be determined based on the difference between the data voltage (VATA) having the third data voltage level (VREF) and the data voltage (VDATA) having the second data voltage level (D[n]). The driving current may be proportional to the square of the difference between the data voltage (VATA) having the third data voltage level (VREF) and the data voltage (VDATA) having the second data voltage level (D[n]).

[0122] The light emitting element (EE) may emit light at the target luminance based on the driving current generated by the first transistor (T1). Also, since the pixel circuits (PX) simultaneously receive the compensation gate signals (GC) having the inactivation level, the pixel circuits (PX) simultaneously receive the initialization gate signals (GI) having the inactivation level, and the first to mth write gate signals (GW[1] to GW[m]) have the activation level, the pixel circuits (PX) included in the display panel 100 may simultaneously emit light at the target luminance in the fifth period (P5).

[0123] Compared to a conventional pixel circuit including five or more transistors and one or more capacitors, the number of transistors and capacitors included in the pixel circuit (PX) may be reduced. Because the number of transistors and capacitors included in the pixel circuit (PX) may be reduced, the area occupied by one pixel circuit (PX) on the display panel 100 may be reduced. As the area occupied by one pixel circuit (PX) on the display panel 100 is reduced, the integration degree of the pixel circuit (PX) may be increased. As the integration degree of the pixel circuit (PX) is increased, the display device 1 may have a high PPI and high resolution. As a result, the display quality of the display device 1 may be improved.

[0124] Furthermore, in the second section (P2), the third transistor (T3) may diode-connect the first node (N1) and the second node (N2) in response to the compensation gate signal (GC) having an activation level. The diode-connected structure may compensate for the threshold voltage of the first transistor (T1). Since the diode-connected structure compensates for the threshold voltage of the first transistor (T1), the threshold voltage of the first transistor (T1) can be accurately compensated regardless of degradation of the parasitic capacitor of the light-emitting element (EE). That is, even if the parasitic capacitor of the light-emitting element (EE) degrades, the threshold voltage of the first transistor (T1) can be accurately compensated. Since the threshold voltage of the first transistor (T1) is accurately compensated, the pixel circuit (PX) can accurately emit light at a target luminance. This may improve the display quality of the display device 1.

[0125] Since the pixel circuits (PX) simultaneously receive the compensation gate signal (GC) via the first global signal line (GSL1), a separate scan driver for generating and outputting a compensation gate signal provided differently for each pixel row may be unnecessary. Furthermore, since the pixel circuits (PX) simultaneously receive the initialization gate signal (GI) via the second global signal line (GSL2), a separate scan driver for generating and outputting an initialization gate signal provided differently for each pixel row may be unnecessary. Because a separate scan driver is unnecessary, the dead space and power consumption of the display device 1 may be reduced. Furthermore, since the dead space of the display device 1 is reduced, the number of pixel circuits (PX) included in the display panel 100 may be increased. That is, the integration density of the pixel circuits (PX) may be increased. With the increased integration density of the pixel circuits (PX), the display device 1 may have a high PPI and high resolution. Accordingly, the display quality of the display device 1 may be improved.

[0126] Fig. 10 is a circuit diagram showing another example of the pixel circuit (PX') included in the display panel 100 included in the display device 1 of Fig. 1. Fig. 11 is a timing diagram showing the operation of the pixel circuit (PX') in Fig. 10.

[0127] 10, the pixel circuit (PX') may include first to fourth transistors (T1 to T4'), a holding capacitor (CHOLD), and a light emitting element (EE). Here, the pixel circuit (PX') is substantially the same as the pixel circuit (PX) of FIG. 2 except for the types of the second to fourth transistors (T2' to T4'). Therefore, the same reference numerals are used for the same or similar components, and redundant descriptions will be omitted.

[0128] In one embodiment, the second to fourth transistors (T2' to T4') may be transistors of a different type from the first transistor (T1). That is, the first transistor (T1) may be a first type transistor, and the second to fourth transistors (T2' to T4') may be a second type transistor.

[0129] For example, the first transistor (T1) may be a PMOS transistor, and the second to fourth transistors (T2' to T4') may be NMOS (N-channel Metal Oxide Semiconductor) transistors.

[0130] When the first transistor (T1) is a PMOS transistor, the drive current generated by the first transistor (T1) may be increased compared to when the first transistor (T1) is an NMOS transistor, and since the drive current generated by the first transistor (T1) is increased, the stability of the pixel circuit (PX') may be increased.

[0131] When the second to fourth transistors (T2' to T4') are NMOS transistors, the leakage current of the second to fourth transistors (T2' to T4') can be reduced compared to when the second to fourth transistors (T2' to T4') are PMOS transistors, which can increase the stability of the pixel circuit (PX').

[0132] For example, when the first transistor (T1) is a PMOS transistor and the second to fourth transistors (T2' to T4') are NMOS transistors, the second to fourth transistors (T2' to T4') may be arranged on a different layer from the first transistor (T1). When the second to fourth transistors (T2' to T4') are arranged on a different layer from the first transistor (T1), the area occupied by one pixel circuit (PX') on the display panel 100 may be smaller than the area occupied by one pixel circuit (PX') on the display panel 100 when the first to fourth transistors (T1 to T4') are arranged on the same layer. In other words, when the second to fourth transistors (T2' to T4') are arranged on a different layer from the first transistor (T1), the area occupied by one pixel circuit (PX') on the display panel 100 is reduced, and the integration density of the pixel circuits (PX)' may be increased. By increasing the integration density of the pixel circuits (PX'), the display device 1 can have a high PPI and a high resolution, which can improve the display quality of the display device 1.

[0133] 11, the intervals in which a signal is applied to the pixel circuit (PX') may include a first interval (P1'), a second interval (P2'), a third interval (P3'), a fourth interval (P4'), and a fifth interval (P5'). Here, the timing diagram is substantially the same as that of FIG. 4 except for the activation level of the compensation gate signal (GC'), the inactivation level of the compensation gate signal (GC'), the activation level of the initialization gate signal (GI'), the inactivation level of the initialization gate signal (GI'), the activation level of the write gate signal (GW'), and the inactivation level of the write gate signal (GW'). Therefore, the same reference numerals are used for the same or similar components, and redundant description will be omitted.

[0134] In one embodiment, since the first transistor (T1) is a PMOS transistor and the second to fourth transistors (T2' to T4') are NMOS transistors, the activation level of the compensation gate signal (GC') may be high and the inactivation level of the compensation gate signal (GC') may be low. Also, the activation level of the initialization gate signal (GI') may be high and the inactivation level of the initialization gate signal (GI') may be low. Also, the activation level of the write gate signal (GW') may be high and the inactivation level of the write gate signal (GW') may be low.

[0135] Compared to a conventional pixel circuit including five or more transistors and one or more capacitors, the number of transistors and capacitors included in the pixel circuit (PX') may be reduced. The reduction in the number of transistors and capacitors included in the pixel circuit (PX') may reduce the area occupied by one pixel circuit (PX') on the display panel 100. The reduction in the area occupied by one pixel circuit (PX') on the display panel 100 may increase the integration density of the pixel circuit (PX'). The increased integration density of the pixel circuit (PX') may enable the display device 1 to have a high PPI and high resolution. Accordingly, the display quality of the display device 1 may be improved.

[0136] Furthermore, in the second section (P2'), the third transistor (T3') may diode-connect the first node (N1) and the second node (N2) in response to the compensation gate signal (GC') having an activation level. The diode-connected structure may compensate for the threshold voltage of the first transistor (T1). Since the threshold voltage of the first transistor (T1) is compensated for by the diode-connected structure, the threshold voltage of the first transistor (T1) can be accurately compensated for regardless of degradation of the parasitic capacitor of the light-emitting element (EE). That is, even if the parasitic capacitor of the light-emitting element (EE) degrades, the threshold voltage of the first transistor (T1) can be accurately compensated for. Since the threshold voltage of the first transistor (T1) is accurately compensated for, the pixel circuit (PX) can accurately emit light at a target luminance. This may improve the display quality of the display device 1.

[0137] Because the pixel circuits PX' simultaneously receive the compensation gate signal GC' via the first global signal line GSL1, a separate scan driver is not required to generate and output a compensation gate signal that is provided differently for each pixel row. Furthermore, because the pixel circuits PX' simultaneously receive the initialization gate signal GI' via the second global signal line GSL2, a separate scan driver is not required to generate and output an initialization gate signal that is provided differently for each pixel row. Because a separate scan driver is not required, the dead space and power consumption of the display device 1 can be reduced. Furthermore, because the dead space of the display device 1 is reduced, the number of pixel circuits PX' included in the display panel 100 can be increased. That is, the integration density of the pixel circuits PX' can be increased. By increasing the integration density of the pixel circuits PX', the display device 1 can have a high PPI and high resolution. Accordingly, the display quality of the display device 1 can be improved.

[0138] 12 is a block diagram illustrating an electronic device 10 according to an embodiment of the present invention. FIG. 13 is a schematic diagram illustrating the electronic device 10 of FIG.

[0139] As shown in FIG. 12, an electronic device 10 according to one embodiment may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0140] A display device 1 according to an embodiment of the present invention may be applied to various electronic devices. In one embodiment, the electronic device 10 may include the display device 1 of FIG. 1. In one embodiment, the operation of the display device 1 included in the electronic device 10 may be the same as the operation of the display device 1 described with reference to FIGS. 1 to 9. In one embodiment, the operation of the display device 1 included in the electronic device 10 may be the same as the operation of the display device 1 described with reference to FIGS. 10 and 11. In one embodiment, the electronic device 10 may further include, in addition to the display device 1, modules or devices having other additional functions.

[0141] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0142] In one embodiment, the processor 12 may provide the input control signal (CONT) of FIG. 1 and the input image data (IMG) of FIG. 1 to the drive control unit 200 included in the display device 1 of FIG.

[0143] In one embodiment, the processor 12 may be provided in two or more forms, functionally or structurally. For example, the processor 12 may include (1) a main processor in the form of a first driver chip including a central processing unit, and (2) an auxiliary processor in the form of a second driver chip including a controller that receives image signals from the main processor and processes the image signals to conform to the interface specifications of the display module 11. Here, the auxiliary processor may include the drive control unit 200 included in the display device 1 of FIG. 1. The main processor may provide the input control signal (CONT) and input image data (IMG) of FIG. 1 to the auxiliary processor. The auxiliary processor may process the image signals based on the input control signal (CONT) and input image data (IMG).

[0144] The memory 13 may include at least one of a non-volatile memory and a volatile memory. The memory 13 may store data information for the operation of the processor 12 and the display module 11. When the processor 12 executes an application stored in the memory 13, an input control signal (CONT) and / or input image data (IMG) may be transmitted to the display module 11. The display module 11 may process the input control signal (CONT) and / or input image data (IMG) provided from the processor 12 and output image information via a display panel.

[0145] The power supply module 14 may include a power supply module such as a power adapter or a battery device, and a power conversion module that converts the power supplied by the power supply module to generate the power required to operate the electronic device 10.

[0146] At least one of the components of the electronic device 10 may be included in the display device 1 according to an embodiment of the present invention. Also, some of the individual modules functionally included in one module may be included in the display device 1, while other modules may be provided separately from the display device 1. For example, the display device 1 may include a display module 11, and the processor 12, memory 13, and power supply module 14 may be provided in the form of other devices within the electronic device 10 rather than the display device 1.

[0147] As shown in FIG. 13 , various electronic devices to which the display device 1 according to the present embodiment is applied may include image display electronic devices such as a smartphone 10_1a, a tablet PC 10_1b, a laptop 10_1c, a TV 10_1d, and a desk monitor 10_1e. Furthermore, various electronic devices may include wearable electronic devices including a display module, such as smart glasses 10_2a, a head-mounted display 10_2b, and a smart watch 10_2c. Furthermore, various electronic devices may include vehicular electronic devices 10_3 including a display module, such as a CID (Center Information Display) or a Room Mirror Display (ROMD) disposed on an instrument panel, center fascia, or dashboard of an automobile. The electronic device 10 is not limited to an image display electronic device, a wearable electronic device, and a vehicular electronic device 10_3.

[0148] In one embodiment, the display device 1 included in the electronic device 10 may include a display panel 100. The display panel 100 may include a pixel circuit (PX). The pixel circuit (PX) may include first to fourth transistors (T1 to T4), a holding capacitor (CHOLD), and a light-emitting element (EE).

[0149] Compared to a conventional pixel circuit including five or more transistors and one or more capacitors, the number of transistors and capacitors included in the pixel circuit (PX) may be reduced. The reduction in the number of transistors and capacitors included in the pixel circuit (PX) may reduce the area occupied by one pixel circuit (PX) on the display panel 100. The reduction in the area occupied by one pixel circuit (PX) on the display panel 100 may increase the integration degree of the pixel circuit (PX). The increased integration degree of the pixel circuit (PX) may enable the display device 1 to have a high PPI and high resolution. Accordingly, the display quality of the display device 1 may be improved.

[0150] Furthermore, in a compensation section in which the threshold voltage of the first transistor is compensated, the third transistor (T3) may diode-connect the first node (N1) and the second node (N2) in response to a compensation gate signal (GC) having an activation level. The threshold voltage of the first transistor (T1) may be compensated for using a diode-connected structure. Since the threshold voltage of the first transistor (T1) is compensated for using a diode-connected structure, the threshold voltage of the first transistor (T1) may be accurately compensated for regardless of degradation of the parasitic capacitor of the light-emitting element (EE). That is, even if the parasitic capacitor of the light-emitting element (EE) degrades, the threshold voltage of the first transistor (T1) may be accurately compensated for. Since the threshold voltage of the first transistor (T1) is accurately compensated for, the pixel circuit (PX) may accurately emit light at a target luminance. This may improve the display quality of the display device 1.

[0151] Because a series of pixel circuits (PX) simultaneously receive the compensation gate signal (GC) via the first global signal line (GSL1), a separate scan driver for generating and outputting a compensation gate signal provided differently for each pixel row may be unnecessary. Furthermore, because a series of pixel circuits (PX) simultaneously receive the initialization gate signal (GI) via the second global signal line (GSL2), a separate scan driver for generating and outputting an initialization gate signal provided differently for each pixel row may be unnecessary. Because a separate scan driver is unnecessary, dead space and power consumption of the display device 1 may be reduced. Furthermore, because the dead space of the display device 1 is reduced, the number of pixel circuits (PX) included in the display panel 100 may be increased. That is, the integration density of the pixel circuits (PX) may be increased. By increasing the integration density of the pixel circuits (PX), the display device 1 may have a high PPI and high resolution. Accordingly, the display quality of the display device 1 may be improved.

[0152] According to a specific preferred embodiment, it is as follows:

[0153] The background and issues of this case are as follows (i) to (vi).

[0154] (i) Light-emitting display panels, which have light-emitting elements such as organic light-emitting diodes (OLEDs) and micro LEDs arranged in a matrix, can produce high-definition, high-brightness, and high-contrast images. Due to their excellent properties, such as being lightweight, thin, and highly luminous, they are widely used or being considered for use in smartphones, tablet PCs, smart watches, and wearable devices such as headsets and glasses.

[0155] (ii) In particular, wearable devices such as smart glasses and AR glasses generally have high resolution of 1000 PPI or more, 2000 PPI or more, 2500 PPI or more, or 3000 PPI or more, and devices with resolutions of 4000 PPI or more and approximately 5,000 PPI (pixels with a vertical and horizontal dimension of 5.1 μm) are also being developed and considered.

[0156] (iii) In order to realize such high-definition image display, it is necessary to configure the pixel circuit provided for each sub-pixel in a compact (small area) configuration.

[0157] (iv) However, each pixel circuit requires a drive transistor (T1) that supplies a drive current to the light-emitting element, a write transistor (T2) that writes to the gate electrode (control electrode N1) of the drive transistor in response to a data signal, multiple initialization transistors that initialize the voltage levels of the gate electrode (control electrode N1) of the drive transistor and the anode of the light-emitting element, and at least one capacitor (Cst) that retains charge at the gate electrode (control electrode N1) of the drive transistor, etc. Therefore, typically, each pixel circuit is provided with 5 to 7 transistors and two capacitors.

[0158] (v) In particular, a data signal is supplied to a series of pixel circuits belonging to one pixel row, and an initialization signal for initializing the preceding pixel row is supplied, and multiple initialization power supplies are connected to each pixel circuit to initialize each node.

[0159] (vi) In the case of organic light emitting devices (OLEDs), the color may deviate from the target hue due to deterioration of the light emitting device, particularly due to fluctuations in the parasitic capacitance of the light emitting device.

[0160] Based on their focus or discovery on the above problems (v) to (vi), the present inventors have discovered that good driving performance can be achieved with a very simple pixel circuit structure. In a specific embodiment of the present application, the compound is at least one of the following A1 to 2, A1-1 to A1-6, and A2-1 to A2-5.

[0161] A1 Each pixel circuit (PX) consists of four (four types) transistors (first to fourth transistors T1 to T4) and one capacitor (CHOLD), and in addition to the upstream drive power supply (V1) and downstream drive power supply (ELVSS), it is connected to only one initialization power supply (VINT) and only three (three types) control power supply lines (GW[n], GC, GI) including the scanning line (GW[n]).

[0162] A1-1 The driving transistor (first transistor T1) has two input and output electrodes directly connected to the upstream driving power supply (V1) and the anode (second node N2) of the light emitting element (EE), respectively. A1-2 The gate electrode (control electrode; first node N1) of the drive transistor (first transistor T1) is connected to the output electrode (third node N3) of the write transistor (second transistor T2) only via the capacitor (CHOLD).

[0163] A1-3 "compensation transistor" (third transistor T3) is provided between the gate electrode (control electrode; first node N1) of the drive transistor (first transistor T1) and the anode (second node N2) of the light-emitting element (EE) so that a diode connection can be realized therebetween. A compensation gate signal (GC) is supplied to the gate electrode (control electrode) of the "compensation transistor" (third transistor T3). The anode (second node N2) of the A1-4 light emitting element (EE) is connected to the initialization power supply (VINT) via the initialization transistor (fourth transistor T4).

[0164] A1-5 The upstream drive power supply (V1) is switchable between a drive voltage level for light emission and a non-light emission voltage level that is the same as the downstream drive power supply (ELVSS). A kind of initialization voltage (black voltage) is supplied to the A1-6 data line (VDATA) during the initialization period (first section P1) preceding the writing period (third section P3).

[0165] A2 Between a write interval (third interval P3) in which an on-voltage is sequentially supplied to a series of pixel rows to write data signals, and the initialization period (first interval P1) preceding this, there is provided a “compensation period” (second interval P2) in which the voltage of an upstream drive power supply (V1) at the drive voltage level is supplied to the gate electrode (control electrode; first node N1) of the drive transistor (first transistor T1).

[0166] During the initialization period (first section P1; FIG. 5), the write, "compensation" and initialization transistors (second to fourth transistors T2 to T4) are turned on to initialize all nodes (first to third nodes N1 to N3). At this time, the upstream drive power supply (V1) is at the same non-light-emitting voltage level as the downstream drive power supply (ELVSS).

[0167] A2-2 During the "compensation period" (second section P2; FIG. 6), only the initialization transistor (fourth transistor T4) is turned off, and the drive transistor (first transistor T1) and the "compensation transistor" (third transistor T3) are diode-connected. This supplies a non-light-emitting voltage level to the gate electrode (control electrode; first node N1) of the drive transistor (first transistor T1). At this time, the data line is left at a kind of initialization voltage (black voltage).

[0168] A2-3 During the write period (third section P3; FIG. 7), the gate electrodes of the write transistors (control electrodes of the second transistors T2) are turned on sequentially for a series of pixel rows to perform writing.

[0169] A2-4 During the next initialization period (fourth section P4; FIG. 8), only the initialization transistor (fourth transistor T4) is turned on, and the initialization power supply (VINT) is connected to the anode (second node N2) of the light-emitting element (EE).

[0170] A2-5 During the light emitting period (fifth section P5; FIG. 9), only the driving transistor (first transistor T1) and the writing transistor (second transistor T2) are turned on. [Industrial Applicability]

[0171] The present invention can be applied to a display device and an electronic device including the same, such as a TV, a digital TV, a 3D TV, a mobile phone, a smartphone, a tablet computer, a laptop computer, a personal computer (PC), a home electronic device, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, etc.

[0172] Although the present invention has been described above with reference to embodiments thereof, those skilled in the art will appreciate that various modifications and variations can be made to the present invention without departing from the spirit and scope of the invention as set forth in the claims below. [Explanation of symbols]

[0173] 1: Display device 10: Electronic equipment 11: Display module 12: Processor 13: Memory 14: Power supply module 100: Display panel 200: Drive control unit 300: Gate driver 400: Data Drive 500: Display panel driver PX, PX': pixel circuit T1: First transistor T2, T2': second transistor T3, T3': third transistor T4, T4': fourth transistor CHOLD: Holding capacitor EE: Light-emitting element

Claims

1. a first transistor including a control electrode connected to a first node, a first electrode receiving a first power supply voltage, and a second electrode connected to a second node; a second transistor including a control electrode for receiving a write gate signal, a first electrode for receiving a data voltage, and a second electrode connected to a third node; a third transistor including a control electrode for receiving a compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the second node; a fourth transistor including a control electrode for receiving an initialization gate signal, a first electrode connected to the second node, and a second electrode for receiving an initialization voltage; a holding capacitor including a first electrode connected to the third node and a second electrode connected to the first node; a pixel circuit comprising: an anode electrode connected to the second node; and a light-emitting element including a second electrode receiving a second power supply voltage.

2. 2. The pixel circuit of claim 1, which operates sequentially in a first interval in which the first node, the second node, and the third node are initialized, a second interval in which a threshold voltage of the first transistor is compensated, a third interval in which the data voltage is transmitted to the third node, a fourth interval in which the anode electrode of the light-emitting element is initialized, and a fifth interval in which the light-emitting element emits light at a luminance corresponding to the data voltage.

3. In the first section, the write gate signal has an activation level; the compensation gate signal has an activation level; the initialization gate signal has an activation level; the data voltage has a first data voltage level; 3. The pixel circuit of claim 2, wherein the first power supply voltage applied to the first transistor has a first power supply voltage level.

4. In the second section, the write gate signal has the activation level; the compensation gate signal has the activation level; the initialization gate signal has an inactive level; the data voltage has the first data voltage level; 4. The pixel circuit of claim 3, wherein the first power supply voltage has a second power supply voltage level that is higher than the first power supply voltage level.

5. 5. The pixel circuit of claim 4, wherein the data voltage having the first data voltage level is the data voltage corresponding to a minimum gray scale.

6. In the third section, the write gate signal has the activation level; the compensation gate signal has the activation level; the initialization gate signal has the inactivation level; the data voltage has a second data voltage level corresponding to a target luminance; 5. The pixel circuit of claim 4, wherein the first power supply voltage has the second power supply voltage level.

7. In the fourth section, the write gate signal has an inactive level; the compensation gate signal has an inactive level; the initialization gate signal has the activation level; the data voltage has a third data voltage level; 7. The pixel circuit of claim 6, wherein the first power supply voltage has the second power supply voltage level.

8. In the fifth section, the write gate signal has the activation level; the compensation gate signal has the inactivation level; the initialization gate signal has the inactivation level; the data voltage has the third data voltage level; 8. The pixel circuit of claim 7, wherein the first power supply voltage has the second power supply voltage level.

9. 9. The pixel circuit of claim 8, wherein the data voltage having the third data voltage level is a reference voltage.

10. a display panel including pixel circuits; a display panel driver that drives the display panel, The pixel circuit a first transistor including a control electrode connected to a first node, a first electrode receiving a first power supply voltage, and a second electrode connected to a second node; a second transistor including a control electrode for receiving a write gate signal, a first electrode for receiving a data voltage, and a second electrode connected to a third node; a third transistor including a control electrode for receiving a compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the second node; a fourth transistor including a control electrode for receiving an initialization gate signal, a first electrode connected to the second node, and a second electrode for receiving an initialization voltage; a holding capacitor including a first electrode connected to the third node and a second electrode connected to the first node; a light-emitting element including an anode electrode connected to the second node, and a second electrode receiving a second power supply voltage.

11. 11. The display device of claim 10, wherein the pixel circuit sequentially operates in a first interval in which the first node, the second node, and the third node are initialized, a second interval in which a threshold voltage of the first transistor is compensated, a third interval in which the data voltage is transmitted to the third node, a fourth interval in which the anode electrode of the light-emitting element is initialized, and a fifth interval in which the light-emitting element emits light at a luminance corresponding to the data voltage.

12. In the first section, the write gate signal has an activation level; the compensation gate signal has an activation level; the initialization gate signal has an activation level; the data voltage has a first data voltage level; 12. The display device according to claim 11, wherein the first power supply voltage applied to the first transistor has a first power supply voltage level.

13. In the second section, the write gate signal has the activation level; the compensation gate signal has the activation level; the initialization gate signal has an inactive level; the data voltage has the first data voltage level; 13. The display device according to claim 12, wherein the first power supply voltage has a second power supply voltage level higher than the first power supply voltage level.

14. In the third section, the write gate signal has the activation level; the compensation gate signal has the activation level; the initialization gate signal has the inactivation level; the data voltage has a second data voltage level corresponding to a target luminance; 14. The display device according to claim 13, wherein the first power supply voltage has the second power supply voltage level.

15. In the fourth section, the write gate signal has an inactive level; the compensation gate signal has an inactive level; the initialization gate signal has the activation level; the data voltage has a third data voltage level; 15. The display device of claim 14, wherein the first power supply voltage has the second power supply voltage level.

16. In the fifth section, the write gate signal has the activation level; the compensation gate signal has the inactivation level; the initialization gate signal has the inactivation level; the data voltage has the third data voltage level; 16. The display device of claim 15, wherein the first power supply voltage has the second power supply voltage level.

17. The pixel circuit and other pixel circuits included in the display panel are commonly connected to a first global signal line; 11. The display device of claim 10, wherein the pixel circuit and the other pixel circuit simultaneously receive the compensation gate signal via the first global signal line.

18. the pixel circuit and other pixel circuits included in the display panel are commonly connected to a second global signal line; 11. The display device according to claim 10, wherein the pixel circuit and the other pixel circuit simultaneously receive the initialization gate signal via the second global signal line.

19. a processor for providing input control signals and input image data; a memory containing data information for operation of said processor; a display panel including pixel circuits; a display panel driver that drives the display panel based on the input control signal and the input image data, The pixel circuit a first transistor including a control electrode connected to a first node, a first electrode for receiving a first power supply voltage, and a second electrode connected to a second node; a second transistor including a control electrode for receiving a write gate signal, a first electrode for receiving a data voltage, and a second electrode connected to a third node; a third transistor including a control electrode for receiving a compensation gate signal, a first electrode connected to the first node, and a second electrode connected to the second node; a fourth transistor including a control electrode for receiving an initialization gate signal, a first electrode connected to the second node, and a second electrode for receiving an initialization voltage; a holding capacitor including a first electrode connected to the third node and a second electrode connected to the first node; a light-emitting element including an anode electrode connected to the second node, and a second electrode receiving a second power supply voltage.

20. The pixel circuit and other pixel circuits included in the display panel are commonly connected to a first global signal line; the pixel circuit and the other pixel circuit simultaneously receive the compensation gate signal via the first global signal line; 20. The electronic device of claim 19, wherein the pixel circuit and the other pixel circuit are commonly connected to a second global signal line, and the pixel circuit and the other pixel circuit simultaneously receive the initialization gate signal via the second global signal line.

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