Semiconductor device

Abstract

To reduce power consumption when one of two kinds of scanning lines outputs an inverted signal or a substantially inverted signal of the other scanning line in a display device having a scanning line driving circuit composed of either an N-channel transistor or a P-channel transistor.SOLUTION: The display device is provided with a plurality of pulse output circuits each of which outputs a signal to one of two kinds of scan lines and a plurality of inverted pulse output circuits each of which outputs an inverted signal or a substantially inverted signal of the signal output from the pulse output circuit to the other of the two kinds of scan lines. Each of the plurality of inverted pulse output circuits is operated using at least two kinds of signals used for operation of the plurality of pulse output circuits. Thus, shoot-through current generated in the inverted pulse output circuit can be reduced.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a display device. The present invention relates to a display device having a shift register composed only of transistors. [Background technology]

[0002] Active matrix display devices are known. A switch is provided for each of the arranged pixels. A display device that displays at each pixel according to a desired potential (image signal) input via be.

[0003] In an active matrix display device, the potential of the scanning line is controlled to generate a signal for each pixel. A circuit (scanning line driving circuit) is required to control the switching of the switches. The line driver circuit is a combination of N-channel and P-channel transistors. Generally, it is composed of N-channel transistors and P-channel transistors. It is also possible to configure the system using either the former or the latter. The scanning line driving circuit can reduce power consumption more than the scanning line driving circuit configured by the latter. The scanning line driving circuit configured by the latter can be realized by the former. The number of manufacturing steps can be reduced compared to the conventional scanning line driver circuit.

[0004] Note that the transistors are either N-channel or P-channel. When the scanning line driving circuit is configured with the above, the potential output to the scanning line is The voltage fluctuates from the power supply voltage output to the circuit. When the scanning line driving circuit is configured by only the gates, the high power supply potential is applied to the scanning line driving circuit. At least one N-channel transistor is provided between the wiring supplying the signal and the scanning line. Therefore, the high potential that can be output to the scanning line is at least 1 / 3 of the high power supply potential. The threshold voltage of the N-channel transistor also drops. When the scanning line driver circuit is configured using only channel type transistors, The low potential that can be outputted by the scanning line driving circuit rises from the low power supply potential that is supplied to the scanning line driving circuit. becomes.

[0005] On the other hand, either an N-channel transistor or a P-channel transistor Although the scanning line driving circuit is configured in this manner, the power supplied to the scanning line driving circuit is A scanning line driver circuit that can output to the scanning lines without changing the source potential has been proposed. It has been done.

[0006] For example, in the scanning line driving circuit disclosed in Patent Document 1, a high power supply potential and a low power supply potential are kept constant. An N-channel transistor that controls the electrical connection between the periodically repeating clock signal and the scanning line. A high power supply potential is applied to the drain of the N-channel transistor. When an input is applied, the potential of the gate is increased by the capacitive coupling between the gate and source. As a result, in the scanning line driving circuit disclosed in Patent Document 1, A potential that is the same as or approximately the same as the high power supply potential is applied from the source of the channel type transistor to the scan line. It is possible to output to

[0007] By the way, the switches provided in each pixel of an active matrix display device There is not necessarily only one switch. Each pixel has multiple switches, and each switch There are also display devices that perform display by independently controlling the switching. In the display device disclosed in the publication, switching is controlled by separate scanning lines. Two types of transistors (P-channel transistor and N-channel transistor) are used for each pixel. Furthermore, two separate gates are provided to control the potential of two types of scanning lines. There are provided two types of scanning line driving circuits (scanning line driving circuit A and scanning line driving circuit B). In the display device disclosed in Patent Document 2, the scanning line driving circuit provided separately is substantially inverted. A configuration is disclosed in which a signal corresponding to the pixel voltage is output to a scanning line. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2008-122939 [Patent Document 2] Japanese Patent Application Laid-Open No. 2006-106786 Summary of the Invention [Problem to be solved by the invention]

[0009] As disclosed in Patent Document 2, a scanning line driving circuit drives one of two types of scanning lines. There are also display devices that perform display by outputting inverted or nearly inverted signals. Such a scanning line driving circuit is made up of N-channel transistors and P-channel transistors. For example, the driving mechanism disclosed in Patent Document 1 can be configured by either one of the above. The output signal for the scanning line of the scanning line driving circuit is output to one of the two types of scanning lines and an inverter. Then, the output signal of the inverter may be output to the other of the two types of scanning lines. stomach.

[0010] However, the inverter is composed of N-channel transistors and P-channel transistors. If only one of them is used, a large amount of through current will occur. This directly leads to an increase in power consumption in the display device.

[0011] Therefore, one embodiment of the present invention is a semiconductor device including an N-channel transistor and a P-channel transistor. In a display device having a scanning line driving circuit configured by either one of the two types of scanning The power consumption is reduced when outputting an inverted or nearly inverted signal for one of the scanning lines. One of the goals is to reduce this. [Means for solving the problem]

[0012] In one embodiment of the display device of the present invention, each of the display devices outputs a signal to one of two types of scanning lines. Multiple pulse output circuits, each of which outputs to the other of the two types of scanning lines. and a plurality of inversion pulse output circuits that output inverted or substantially inverted signals of the signals. Each of the plurality of inverted pulse output circuits is used for the operation of the plurality of pulse output circuits. It operates using signals.

[0013] Specifically, one aspect of the present invention is a method for manufacturing a multi-layered semiconductor device, comprising: a first scanning line electrically connected to the n number of pixels arranged in the first row, and a first scanning line electrically connected to the n number of pixels arranged in the first row; the m-th scanning line electrically connected to n pixels arranged in the m-th row, and m-th inverted scanning line, and the first scanning line to the m-th scanning line, and the first inverted scanning line to the m-th scanning line a shift register electrically connected to the mth inversion scanning line, The pixels arranged at the kth scanning line (a natural number) are turned on when a selection signal is input to the kth scanning line. a first switch that is turned on when a selection signal is input to the k-th inversion scanning line; 2 switches, and the shift register is connected to the first pulse output circuit to the mth pulse output circuit. and a first inversion pulse output circuit to an mth inversion pulse output circuit, The pulse output circuit of (s is a natural number less than or equal to (m-2)) outputs the start pulse (only when s is 1). A shift pulse output from the (s-1)th pulse output circuit is input, and A selection signal is output to the (s+1)th scanning line, and a shift signal is output to the (s+1)th pulse output circuit. A circuit that outputs a pulse, and the start pulse or the (s-1)th pulse output circuit outputs During the first period from when the input of the shift pulse to be a first transistor that is turned on during a first period; By utilizing the capacitive coupling between the gate and source of the The potential of the first clock signal is the same as or substantially the same as the potential of the first clock signal. The (s+1)th pulse output circuit outputs from the source of the transistor. The shift pulse output by the line is input, and the selection signal is sent to the (s+1)th scanning line. and outputs a shift pulse to the (s+2)th pulse output circuit. , the shift period has elapsed since the input of the shift pulse output from the sth pulse output circuit started. a second transistor that is turned on during a second period until the second period has elapsed; In the second transistor, the capacitance coupling between the gate and the source of the second transistor is utilized. A potential that is the same as or approximately the same as the potential of the second clock signal input to the drain of the transistor is output as a shift pulse from the source of the second transistor, and the sth inversion pulse output circuit The path receives the shift pulse output from the sth pulse output circuit and receives the second clock signal. A signal is input to the sth inversion scanning line, and a selection signal is output to the sth inversion scanning line. The voltage of the second clock signal is increased from the time when the input of the shift pulse output by the pulse output circuit starts. a third transistor that is turned off during a third period until the potential changes, After the period, the source of the third transistor outputs a selection signal for the sth inversion scanning line. It is a display device.

[0014] In the display device, the second clock input to the sth inversion pulse output circuit The present invention also provides a display device in which the signal is replaced with a shift pulse output by the (s+1)th pulse output circuit. This is one aspect of clarity. [Effects of the Invention]

[0015] In one aspect of the display device of the present invention, the operation of the inversion pulse output circuit is controlled by at least two types of signals. This reduces the through current that occurs in the inverted pulse output circuit. In addition, the two types of signals can be used to operate multiple pulse output circuits. In other words, the inverted pulse output circuit applies a signal that is generated without generating a separate signal. It is possible to operate the following. [Brief explanation of the drawings]

[0016] [Figure 1] FIG. 1 illustrates an example of the configuration of a display device. [Figure 2] FIG. 1A is a diagram showing an example of the configuration of a scanning line driving circuit; FIG. 1B is a diagram showing an example of waveforms of various signals; FIG. 1C is a diagram showing terminals of a pulse output circuit; and FIG. 1D is a diagram showing terminals of an inverted pulse output circuit. [Figure 3] 1A is a diagram showing a configuration example of a pulse output circuit, FIG. 1B is a diagram showing an operation example, and FIG. 1C is a diagram showing a configuration example of an inverted pulse output circuit, FIG. 1D is a diagram showing an operation example. [Figure 4] FIG. 1A shows an example of the configuration of a pixel, and FIG. 1B shows an example of its operation. [Figure 5] FIG. 10 is a diagram showing a modified example of a scanning line driving circuit. [Figure 6] 1A is a diagram showing a modified example of a scanning line driving circuit, and FIG. 1B is a diagram showing an example of waveforms of various signals. [Figure 7] FIG. 10 is a diagram showing a modified example of a scanning line driving circuit. [Figure 8] 10A and 10B are diagrams showing modified examples of the pulse output circuit. [Figure 9] 10A and 10B are diagrams showing modified examples of the pulse output circuit. [Figure 10] 10A to 10C are diagrams showing modified examples of an inversion pulse output circuit. [Figure 11] 1A to 1D are cross-sectional views showing specific examples of transistors. [Figure 12] 1A to 1D are cross-sectional views showing specific examples of transistors. [Figure 13] (A) and (B) are top views showing specific examples of transistors. [Figure 14] 1A to 1F are diagrams showing examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0017] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following description, and various modifications may be made without departing from the spirit and scope of the present invention. It will be readily apparent to those skilled in the art that various modifications may be made to the details. The present invention should not be construed as being limited to the description of the following embodiments.

[0018] First, a structural example of a display device according to one embodiment of the present invention will be described with reference to FIGS.

[0019] <Example of display device configuration> FIG. 1 is a diagram showing an example of the configuration of a display device. The display device shown in FIG. 1 is arranged in m rows and n columns. A plurality of pixels 10, a scanning line driving circuit 1, a signal line driving circuit 2, and a current source 3, each of which A scanning line driver is electrically connected to the pixels arranged in any one row of the plurality of pixels 10. The potential of m scanning lines 4 and m inverted scanning lines 5 is controlled by the driving circuit 1, and each of them has multiple The signal line is electrically connected to the pixels arranged in any one of the several pixels 10. The potential of the n signal lines 6 is controlled by the circuit 2, and a plurality of branch lines are provided. and a power line 7 electrically connected to the power source 3.

[0020] <Configuration example of scanning line driving circuit> FIG. 2A is a diagram showing an example of the configuration of the scanning line driving circuit 1 included in the display device shown in FIG. The scanning line driving circuit 1 shown in FIG. 2A generates a first scanning line driving circuit clock signal (GCK 1) to the wiring that supplies the clock signal (GCK4) for the fourth scanning line driving circuit and a wiring for supplying the first pulse width control signal (PWC1) to a wiring for supplying the fourth pulse width control signal (P WC4) and the pixels 10 arranged in one row are electrically connected to the wiring via the scanning line 4_1. The first pulse output circuit 20_1 connected to the scanning line 4_m is connected to the pixels arranged in the mth row. 10, and the mth pulse output circuit 20_m electrically connected to the inverted scanning line 5_1. The first inversion pulse output circuit 60_1 to the first inversion pulse output circuit 60_2 electrically connected to the pixels 10 arranged in one row The mth inversion pulse is electrically connected to the pixel 10 arranged in the mth row via the scanning line 5_m. and a signal output circuit 60_m.

[0021] The first pulse output circuit 20_1 to the m-th pulse output circuit 20_m are The start pulse (GSP) for the scanning line driving circuit input to the scan output circuit 20_1 is input. As a result, the first shift pulse is shifted sequentially for each shift period. After the start pulse (GSP) for the scanning line driving circuit is input, the pulse output circuit 20_1 Then, the shift pulse is output to the second pulse output circuit 20_2 over the shift period. Next, the second pulse output circuit 20_2 outputs the shift pulse signal output by the first pulse output circuit. After the pulse is input, the third pulse output circuit 20_3 is supplied with a shift pulse over a shift period. After that, a shift pulse is input to the m-th pulse output circuit 20_m. The above operation is repeated until

[0022] Furthermore, each of the first pulse output circuit 20_1 to the m-th pulse output circuit 20_m is When the shift pulse is input, the pixel has a function of outputting a selection signal to the scanning line. The selection signal is a signal that turns on a switch whose switching is controlled by the potential of the scanning line. This refers to a signal that puts the device into an ON state.

[0023] FIG. 2B is a diagram showing an example of a specific waveform of the above signal.

[0024] Specifically, the first scanning line driving circuit clock signal (GCK1) shown in FIG. 2(B) is A high-level potential (high power supply potential (Vdd)) and a low-level potential (low power supply potential ( Vss)) and the duty ratio is about 1 / 4. The clock signal for the first scanning line driving circuit (GCK2) is a clock signal for the first scanning line driving circuit (GCK1). The third scanning line driving circuit clock signal (GCK 3) is a clock signal for the first scanning line driving circuit (GCK1) that is shifted in phase by 1 / 2 cycle. The fourth scanning line driving circuit clock signal (GCK4) is a signal for the first scanning line driving circuit. This signal is three-quarters of a cycle out of phase with the road clock signal (GCK1).

[0025] The first pulse width control signal (PWC1) is a clock signal for the first scanning line driving circuit. The potential of (GCK1) becomes a high level potential before the potential of (GCK1) becomes a high level potential, and the first During the period when the potential of the clock signal (GCK1) for the scanning line driving circuit is at a high level, The second pulse width is a signal with a duty ratio of less than 1 / 4, which is a low-level potential. The control signal (PWC2) is shifted in phase by a quarter period from the first pulse width control signal (PWC1). The third pulse width control signal (PWC3) is a signal obtained by WC1), and is a signal shifted in phase by 1 / 2 cycle from the fourth pulse width control signal (PWC4) is a signal that is shifted in phase by 3 / 4 cycle from the first pulse width control signal (PWC1).

[0026] In the display device shown in FIG. 2(A), the first pulse output circuit 20_1 to the m-th pulse A circuit having the same configuration as the output circuit 20_m can be applied. The electrical connection relationship between the multiple terminals of the pulse output circuit differs for each pulse output circuit. The physical connection relationships will be described with reference to FIGS.

[0027] Each of the first pulse output circuit 20_1 to the m-th pulse output circuit 20_m has a terminal 2 Terminals 21 to 27 are input terminals, and terminals 21 to 24 and 26 are input terminals. Terminals 25 and 27 are output terminals.

[0028] First, the terminal 21 will be described. The terminal 21 of the first pulse output circuit 20_1 is connected to the scanning line It is electrically connected to the wiring that supplies the start pulse (GSP) for the drive circuit, and the second pulse The terminals 21 of the output circuit 20_2 to the m-th pulse output circuit 20_m are connected to the terminals 21 of the preceding pulse output circuit The terminal 27 is electrically connected to the terminal 27.

[0029] Next, the terminal 22 will be described. The pulse output circuit (4a-3) (a is m / 4 or more) The terminal 22 (next natural number) supplies a clock signal (GCK1) for the first scanning line driving circuit. The terminal 22 of the (4a-2) pulse output circuit is electrically connected to the wiring of the second scanning The clock signal (GCK2) for the line driver circuit is electrically connected to the line (4a- The terminal 22 of the pulse output circuit 1) is a clock signal (GCK3) for the third scanning line driving circuit. The terminal 22 of the 4a pulse output circuit is electrically connected to the wiring that supplies the 4a pulse. It is electrically connected to a wiring that supplies a clock signal (GCK4) for the line driver circuit.

[0030] Next, the terminal 23 will be described. The terminal 23 of the pulse output circuit (4a-3) is The second scanning line driver circuit is electrically connected to a wiring that supplies a clock signal (GCK2) for the second scanning line driver circuit. The terminal 23 of the pulse output circuit (4a-2) receives the clock signal (G CK3), and the terminal 2 of the pulse output circuit (4a-1) is electrically connected to the wiring that supplies 3 is electrically connected to the wiring that supplies the clock signal (GCK4) for the fourth scanning line driving circuit. The terminal 23 of the 4a pulse output circuit receives the first scanning line driving circuit clock signal (G CK1).

[0031] Next, the terminal 24 will be described. The terminal 24 of the pulse output circuit (4a-3) is The first pulse width control signal (PWC1) is electrically connected to the wiring that supplies the first pulse width control signal (PWC1), and the second pulse width control signal (PWC2) is electrically connected to the wiring that supplies the first pulse width control signal (PWC2). The terminal 24 of the pulse output circuit is connected to the wiring that supplies the second pulse width control signal (PWC2). The terminal 24 of the (4a-1) pulse output circuit is electrically connected to the third pulse width control The terminal 2 of the 4a pulse output circuit is electrically connected to the wiring that supplies the signal (PWC3). 4 is electrically connected to a wiring that supplies a fourth pulse width control signal (PWC4).

[0032] Next, we will discuss terminal 25. The terminal 25 is electrically connected to the scanning line 4_x arranged in the xth row.

[0033] Next, the terminal 26 will be described. The yth pulse output circuit (y is the (m-1)th or less) The terminal 26 of the (y+1)th pulse output circuit is electrically connected to the terminal 27 of the (y+1)th pulse output circuit, Terminal 26 of the mth pulse output circuit provides a stop signal (STP) for the mth pulse output circuit. The m-th pulse output circuit stop signal (S TP) is, if the (m+1)th pulse output circuit is provided, the (m+1)th This signal corresponds to the signal output from terminal 27 of the pulse output circuit. These signals can be obtained by actually providing an (m+1)th pulse output circuit as a dummy circuit, or Supplying the m-th pulse output circuit with the signal by directly inputting it from the outside can be done.

[0034] The connection relationship of the terminals 27 of each pulse output circuit has already been explained. The following will be cited.

[0035] In the display device shown in FIG. 2(A), the first inversion pulse output circuit 60_1 to the A circuit having the same configuration can be applied as the inversion pulse output circuit 60_m of However, the electrical connection relationship between the multiple terminals of the inverted pulse output circuit is The specific connection relationships are different for each output circuit. .

[0036] Each of the first inversion pulse output circuit 60_1 to the m-th inversion pulse output circuit 60_m is , terminals 61 to 63. Terminals 61 and 62 are input terminals, and terminal 6 3 is the output terminal.

[0037] First, the terminal 61 will be described. The terminal 61 of the (4a-3) inversion pulse output circuit is electrically connected to a wiring that supplies a clock signal (GCK2) for the second scanning line driving circuit; The terminal 61 of the (4a-2) inversion pulse output circuit is connected to the clock signal for the third scanning line driving circuit. The inverted pulse output circuit (4a-1) is electrically connected to the wiring that supplies the signal (GCK3). The terminal 61 of the line is connected to the line that supplies the clock signal (GCK4) for the fourth scanning line driving circuit. The terminal 61 of the 4a pulse output circuit is electrically connected to the clock for the first scanning line driving circuit. The gate is electrically connected to a wiring that supplies a clock signal (GCK1).

[0038] Next, the terminal 62 will be described. The terminal 62 of the xth inverted pulse output circuit is It is electrically connected to terminal 27 of the pulse output circuit.

[0039] Next, terminal 63 will be described. The terminal 63 of the xth inverted pulse output circuit is The pixel electrodes 5 are electrically connected to the inverted scanning lines 5_x.

[0040] <Configuration example of a pulse output circuit> FIG. 3A is a diagram showing an example of the configuration of the pulse output circuit shown in FIGS. 2A and 2C. The pulse output circuit shown in FIG. 3(A) includes transistors 31 to 39.

[0041] In the transistor 31, one of the source and drain supplies a high power supply potential (Vdd). The gate is electrically connected to the terminal 21. is connected.

[0042] In the transistor 32, one of the source and drain supplies a low power supply potential (Vss). The other of the source and the drain is electrically connected to a wiring (hereinafter also referred to as a low power supply potential line). It is electrically connected to the other of the source and drain of the transistor 31 .

[0043] In the transistor 33, one of the source and the drain is electrically connected to the terminal 22, and The other of the source and drain is electrically connected to terminal 27, and the gate is connected to the source of transistor 31. and the other of the source and drain of transistor 32. It continues.

[0044] In the transistor 34, one of the source and the drain is electrically connected to the low power supply line. The other of the source and drain is electrically connected to the terminal 27, and the gate is connected to the transistor 32. is electrically connected to the gate of

[0045] In the transistor 35, one of the source and the drain is electrically connected to the low power supply potential line. , the other of the source and drain is the gate of transistor 32 and the gate of transistor 34 and the gate is electrically connected to terminal 21.

[0046] In the transistor 36, one of the source and the drain is electrically connected to the high power supply potential line. , the other of the source and drain is the gate of transistor 32, the gate of transistor 34, and the other of the source and drain of transistor 35, and the gate is connected to terminal 2 6 is electrically connected to

[0047] In the transistor 37, one of the source and the drain is electrically connected to the high power supply potential line. , the other of the source and drain is the gate of transistor 32, the gate of transistor 34, The other of the source and drain of transistor 35 and the other of the source and drain of transistor 36 The other end of the input is electrically connected to the input terminal, and the gate is electrically connected to terminal 23.

[0048] In the transistor 38, one of the source and drain is electrically connected to the terminal 24, and The other of the source and drain is electrically connected to terminal 25, and the gate is connected to the source of transistor 31. the other of the source and drain of transistor 32, and the other of the source and drain of transistor 33. The gate of the transistor 33 is electrically connected to the transistor 33.

[0049] In the transistor 39, one of the source and the drain is electrically connected to the low power supply potential line. , the other of the source and drain is electrically connected to the terminal 25, and the gate is connected to the transistor 32 the gate of transistor 34; the other of the source and drain of transistor 35; The other of the source and drain of transistor 36 and the other of the source and drain of transistor 37 The other input is electrically connected to the other input.

[0050] In the following, the other of the source and drain of the transistor 31, The other of the source and drain of transistor 32, the gate of transistor 33, and the The node electrically connected to the gate is called node A. The gate of transistor 32, The gate of transistor 34, the other of the source and drain of transistor 35, the other of the source and drain of transistor 36, the other of the source and drain of transistor 37, and The node to which the gate of transistor 39 is electrically connected is called node B.

[0051] <Example of pulse output circuit operation> An example of the operation of the pulse output circuit described above will be described with reference to FIG. 3B shows the first pulse when a shift pulse is input from the first pulse output circuit 20_1. Signals input to and output from the respective terminals of the pulse output circuit 20_2 of , and the potentials of the nodes A and B. The signal output from terminal 25 of 20_3 (Gout3) and the signal output from terminal 27 (SRout3=signal input to the terminal 26 of the second pulse output circuit 20_2) In the figure, Gout indicates the output signal to the scanning line of the pulse output circuit. SRout represents the output signal of the pulse output circuit to the subsequent pulse output circuit. It represents.

[0052] First, referring to FIG. 3B, the second pulse output circuit 20_2 is connected to the first pulse output circuit 20_3. A case where a shift pulse is input from 20_1 will be described.

[0053] During the period t1, a high-level potential (high power supply potential (Vdd)) is input to the terminal 21. This turns on the transistors 31 and 35. As a result, the potential of the node A is a high-level potential (a drop from the high power supply potential (Vdd) by the threshold voltage of the transistor 31) The potential at node B rises to the low power supply potential (Vss). Accordingly, the transistors 33 and 38 are turned on, and the transistors 32, 34 and 39 are turned off. As a result, during the period t1, the signal output from the terminal 27 is The signal input to terminal 25 is the signal input to terminal 24. Here, during the period t1, the signals input to the terminals 22 and 24 are both low. Therefore, in the period t1, the second The pulse output circuit 20_2 is connected to the terminal 21 of the third pulse output circuit 20_3 and the pixel portion. and outputs a low-level potential (low power supply potential (Vss)) to the scanning line arranged in the second row. .

[0054] During period t2, the signals input to each terminal do not change from those during period t1. The signals output from the terminal 25 and the terminal 27 do not change, and both are at a low level potential (low power supply potential (Vss)).

[0055] During the period t3, a high-level potential (high power supply potential (Vdd)) is input to the terminal 24. The potential of the node A (potential of the source of the transistor 31) is The potential of the high level (Vdd) is lowered by the threshold voltage of the transistor 31. Therefore, the transistor 31 is in an off state. When a high-level potential (high power supply potential (Vdd)) is input to the terminal 24, the transistor The potential at node A (transistor 38) is The voltage at the gate of the transistor (potential at the gate of the transistor) further rises (bootstrap operation). By performing the flip-flop operation, the signal output from terminal 25 becomes the high-level signal input to terminal 24. Therefore, during the period t3, In the pixel section, the second pulse output circuit 20_2 outputs a pulse to the scanning line arranged in the second row. A high-level potential (high power supply potential (Vdd) = selection signal) is output.

[0056] During a period t4, a high-level potential (high power supply potential (Vdd)) is input to the terminal 22. Here, the potential of node A is increased by the bootstrap operation, so The signal output from 27 is a high-level potential (high power supply potential (Vdd Therefore, during the period t4, the voltage at terminal 27 does not drop from terminal 22. The high-level potential (high power supply potential (Vdd)) input to the second The first pulse output circuit 20_2 outputs a high level signal to the terminal 21 of the third pulse output circuit 20_3. During the period t4, the terminal The signal input to the input terminal 24 is maintained at a high level potential (high power supply potential (Vdd)). The second pulse output circuit 20_2 outputs a pulse to the scanning line arranged in the second row in the pixel section. The input signal remains at a high level potential (high power supply potential (Vdd)=selection signal). Although it is not directly related to the output signal of the pulse output circuit during the period t4, the terminal 21 Since a low-level potential (low power supply potential (Vss)) is input to This is the state.

[0057] During a period t5, a low-level potential (low power supply potential (Vss)) is input to the terminal 24. Here, the transistor 38 remains on. Therefore, during the period t5, The pulse output circuit 20_1 of the first row outputs a signal to the scanning line arranged in the second row in the pixel section. The signal outputted becomes a low-level potential (low power supply potential (Vss)).

[0058] During the period t6, the signals input to each terminal do not change from the period t5. The signals output from terminal 25 and terminal 27 do not change, and terminal 25 is at a low level potential ( A low power supply potential (Vss) is output, and a high-level potential (high power supply potential (V dd) = shift pulse) is output.

[0059] During the period t7, a high-level potential (high power supply potential (Vdd)) is input to the terminal 23. This turns on the transistor 37. As a result, the potential of the node B becomes high. The potential of the level (a potential lowered by the threshold voltage of the transistor 37 from the high power supply potential (Vdd)) In other words, the transistors 32, 34, and 39 are turned on. As a result, the potential of node A drops to a low level potential (low power supply potential (Vss)). That is, the transistors 33 and 38 are turned off. The signals output from the terminals 25 and 27 are both at the low power supply potential (Vss). That is, in a period t7, the second pulse output circuit 20_2 outputs the pulses A low power supply potential (Vss) is applied to the terminal 21 of the third row and the scanning line arranged in the second row in the pixel section. Output.

[0060] <Configuration example of an inverted pulse output circuit> FIG. 3C is a diagram showing an example of the configuration of the inversion pulse output circuit shown in FIGS. 2A and 2D. The inverted pulse output circuit shown in FIG. 3C includes transistors 71 to 74. do.

[0061] In the transistor 71, one of the source and the drain is electrically connected to the high power supply potential line. , and the gate is electrically connected to terminal 61.

[0062] In the transistor 72, one of the source and the drain is electrically connected to the low power supply line. , the other of the source and drain is electrically connected to the other of the source and drain of the transistor 71. The gate is electrically connected to terminal 62.

[0063] In the transistor 73, one of the source and the drain is electrically connected to the high power supply potential line. The other of the source and drain is electrically connected to the terminal 63, and the gate is connected to the transistor 71. and the other of the source and drain of transistor 72. are actively connected.

[0064] In the transistor 74, one of the source and the drain is electrically connected to the low power supply line. The other of the source and drain is electrically connected to a terminal 63, and the gate is electrically connected to a terminal 62. is connected to.

[0065] In the following description, the other of the source and drain of the transistor 71 is referred to as the transistor The other of the source and drain of the transistor 72 and the gate of the transistor 73 are electrically connected The node is called node C.

[0066] <Example of operation of inverted pulse output circuit> An example of the operation of the above-mentioned inversion pulse output circuit will be described with reference to FIG. In FIG. 3(D), the second inversion pulse is generated during the period t1 to the period t7 shown in FIG. 3(B). The potentials of the signals input to and output from the terminals of the output circuit 20_2, and the node In Figure 3(D), the signals input to each terminal are written in parentheses. In the figure, GBout corresponds to the inversion scanning line of the inversion pulse output circuit. The figure represents the output signal.

[0067] During periods t1 to t3, a low-level potential is input to the terminals 61 and 62. This turns off the transistors 71, 72, and 74. The potential is maintained at a high level. The potential of the node C is also in the state of the gate and source of the transistor 73 (during the period t1 During period t3, the other of the source and drain electrically connected to terminal 63 is connected to the source. The capacitive coupling between the high power supply potential (Vdd) and the threshold voltage of the transistor 73 The potential is higher than the potential obtained by adding During t1 to t3, the signal output from the terminal 63 is at the high power supply potential (Vdd). That is, in the period t1 to the period t3, the second inversion pulse output circuit 60_2 outputs Then, a high power supply potential (Vdd) is output to the inversion scanning line arranged in the second row.

[0068] During the period t4, a high-level potential (high power supply potential (Vdd)) is input to the terminal 62. This turns on the transistors 72 and 74. As a result, the potential of the node C falls to a low level potential (low power supply potential (Vss)), and the transistor 73 is turned off. As a result, during the period t4, the signal output from the terminal 63 is at the low power supply potential (V That is, in the period t4, the second inversion pulse output circuit 60_2 outputs the In the element section, a low power supply potential (Vss) is output to the inversion scanning line arranged in the second row.

[0069] During periods t5 and t6, the signals input to the terminals do not change from those during period t4. Therefore, the signal output from the terminal 63 does not change, and the low-level potential (low power supply potential (V ss)).

[0070] During the period t7, a high-level potential (high power supply potential (Vdd)) is input to the terminal 61. In addition, a low level potential (low power supply potential (Vss)) is input to the terminal 62. Therefore, the transistor 71 is turned on and the transistors 72 and 74 are turned off. Therefore, the potential of the node C becomes a high level potential (high power supply potential (Vdd) to the transistor 71 The potential drops to a potential lower than the threshold voltage of the transistor 73, and the transistor 73 turns on. The potential of node C is increased by the capacitive coupling between the gate and source of transistor 73. The potential is higher than the potential (Vdd) plus the threshold voltage of the transistor 73 (block As a result, during the period t7, the signal output from the terminal 63 is That is, in the period t7, the second inversion pulse output circuit The line 60_2 supplies a high power supply potential (Vdd) to the inversion scanning line arranged in the second row in the pixel section. Output.

[0071] <Pixel configuration example> FIG. 4A is a circuit diagram showing an example of the configuration of the pixel 10 shown in FIG. The element 10 includes transistors 11 to 16, a capacitor 17, and a pair of electrodes that are electrically excited to generate a current. An element having an organic material that emits light by light emitted from the organic material (hereinafter referred to as an organic electroluminescence (EL) element) (also called) 18.

[0072] In the transistor 11, one of the source and the drain is electrically connected to the signal line 6, and the gate The port is electrically connected to the scanning line 4 .

[0073] In the transistor 12, one of the source and the drain is electrically connected to a wiring that supplies a common potential. and the gate is electrically connected to the scanning line 4. Here, the common potential is , which is a lower potential than the potential applied to the power supply line 7.

[0074] The transistor 13 has a gate electrically connected to the scanning line 4 .

[0075] In the transistor 14, one of the source and the drain is electrically connected to the power supply line 7. The other of the source and drain is electrically connected to one of the source and drain of transistor 13. The gate is electrically connected to the inversion scanning line 5 .

[0076] In transistor 15, one of the source and drain is connected to the source and drain of transistor 13. and the other of the source and drain of transistor 14, The other of the source and drain is electrically connected to the other of the source and drain of the transistor 11. The gate is electrically connected to the other of the source and drain of the transistor 13. do.

[0077] In transistor 16, one of the source and drain is connected to the source and drain of transistor 11. the other of the source and drain of the transistor 15; The other of the source and drain is electrically connected to the other of the source and drain of the transistor 12. The gate is electrically connected to an inversion scanning line 5 .

[0078] In the capacitor 17, one electrode is connected to the other of the source and drain of the transistor 13, and and the gate of transistor 15, and the other electrode is electrically connected to the source of transistor 12. and the other of the source and drain of transistor 16. It continues.

[0079] In the organic EL element 18, the anode is the other of the source and drain of the transistor 12, The other of the source and drain of the transistor 16 and the other electrode of the capacitor 17 are electrically connected. The cathode is electrically connected to a wiring that supplies a common potential. The common terminal is provided to a wiring to which one of the source and drain of the transistor 12 is electrically connected. Even if the applied potential and the common potential applied to the cathode of the organic EL element 18 are different potentials, good.

[0080] In the following description, the other of the source and drain of the transistor 13 is referred to as the transistor The node where the gate of the capacitor 15 and one electrode of the capacitor 17 are electrically connected is referred to as node D. Also, one of the source and drain of the transistor 13 and the source of the transistor 14 The other of the drain and the source of the transistor 15 are electrically connected. The node at which the voltage Vcc is applied is called node E. The other of the source and drain of transistor 15 and the other of the source and drain of transistor 16 The node electrically connected to one of the transistors is called node F. and the other of the drain, the other of the source and drain of the transistor 16, The node to which the other electrode and the anode of the organic EL element 18 are electrically connected is called node G. Boo.

[0081] <Pixel operation example> An example of the operation of the pixel described above will be described with reference to FIG. ) in the pixel section during periods t1 to t7 shown in FIG. 3(B) and FIG. 3(D), The potentials of the scanning line 4_2 and the inverted scanning line 5_2 arranged in the second row and the potentials input to the signal line 6 are In FIG. 4(B), the signals input to each wiring are shown in parentheses. In the figure, DATA represents an image signal.

[0082] During the periods t1 and t2, no selection signal is input to the scanning line 4_2, and the inversion scanning A selection signal is input to the line 5_2, which turns off the transistors 11, 12, and 13. The transistors 14 and 16 are turned on. A current corresponding to the gate potential (potential of node D) is supplied from the power supply line to the organic EL element 18. That is, in the pixel 10, the image signal held by the capacitor 17 is During periods t1 and t2, the first line of the signal line 6 is displayed. An image signal (data_1) for the pixels arranged in There are.

[0083] During a period t3, a selection signal is input to the scanning line 4_2. 11, 12, and 13 are turned on. As a result, one electrode of the capacitor 17 is connected to the signal line 6 and the power supply line 7. The image signal disappears (initialization).

[0084] During the period t4, the selection signal is not input to the inverted scanning line 5_2. The resistors 14 and 16 are turned off. Therefore, the potential of the node F is equal to the image signal ( The potential is shown as data_2).

[0085] During the period t4, the potentials of the nodes D and E are the potentials representing the image signal (data_2). The potential is obtained by adding the threshold voltage of the transistor 15 to the potential (hereinafter referred to as data potential). This is because if the potentials of the nodes D and E are higher than the data potential, the transistor 15 The transistor is turned on, and the potentials of the nodes D and E drop to the data potential. Transistors 14 and 16 are turned off, and transistor 15 is turned off (nodes D and E (The potential of the node F is equal to the potential of the node F plus the threshold voltage of the transistor 15.) After this, the potential of node F changes to the potential indicating the image signal (data_2). Even if there is a voltage difference between node D and node F, the voltage at node D will fluctuate due to the capacitive coupling between node D and node F. Therefore, in this case as well, the potentials of nodes D and E become the data potential.

[0086] During the period t4, the potential of the node G becomes the common potential. This is because the common potential is short-circuited to the wiring that supplies the common potential via 12.

[0087] Therefore, during the period t4, the voltage applied to the capacitor 17 is the data potential (node This is the potential difference between the potential at node D and the common potential (potential at node G).

[0088] During periods t5 and t6, no selection signal is input to the scanning line 4_2. Transistors 11, 12, and 13 are turned off.

[0089] During the period t7, a selection signal is input to the inverted scanning line 5_2. The drain current in the saturation region of the transistor is is the square of the potential difference between the gate-source voltage of the transistor and the threshold voltage of the transistor Here, the gate-source voltage of the transistor 15 is proportional to The voltage applied to the capacitor 17 (data potential (potential indicating the image signal (data_2)) The sum of the threshold voltages of the transistors 15 and the potential difference between the common potential are obtained. The drain current in the saturation region of the transistor 15 is equal to the potential representing the image signal (data_2). In this case, in the saturation region of the transistor 15, The drain current in the transistor 15 does not depend on the threshold voltage of the transistor 15.

[0090] The potential of the node G is equal to the current generated in the transistor 15 with respect to the organic EL element 18. If the potential of node G changes, the capacitor The potential of node D also fluctuates due to capacitive coupling via the resistor 17. Even if the voltage fluctuates, the transistor 15 supplies a constant current to the organic EL element 18. It is possible to supply

[0091] By the above operation, a display according to the image signal (data_2) is performed in the pixel 10. It can be done.

[0092] <Regarding the display device disclosed in this specification> The display device disclosed in this specification controls the operation of the inverted pulse output circuit by at least two types of signals. This reduces the through current that occurs in the inverted pulse output circuit. In addition, the two types of signals can be used to operate multiple pulse output circuits. In other words, the inverted pulse output is applied without generating a separate signal. The circuit can be operated.

[0093] <Modification> The above-described display device is one embodiment of the present invention, and a display device having a different configuration from the above-described display device may be used. The present invention also includes a device. Another embodiment of the present invention will be exemplified below. The present invention also includes a display device having a plurality of contents, which is exemplified as another embodiment of the present invention.

[0094] <Modifications of the display device> As the above-mentioned display device, a display device in which an organic EL element is provided in each pixel (hereinafter referred to as an EL display device) However, the display device of the present invention is not limited to an EL display device. For example, the display device of the present invention may be a display device that displays by controlling the orientation of liquid crystal ( It is also possible to apply a liquid crystal display device.

[0095] <Modification of the scanning line driving circuit> The configuration of the scanning line driver circuit of the display device is not limited to the configuration shown in FIG. For example, the scanning line driving circuits shown in FIGS. 5 to 7 may be used as the scanning line driving circuits of the above-mentioned display device. It can also be applied as a driving circuit.

[0096] The scanning line driving circuit 1 shown in FIG. 5 includes the y-th inversion pulse output circuit 60_y (where y is (m-1 ) (a natural number equal to or less than y) is electrically connected to the terminal 27 of the (y+1)th pulse output circuit. The terminal 61 of the m-th inverted pulse output circuit 60_m is connected to the m-th pulse output circuit stop The point electrically connected to the wiring that supplies the signal (STP) is the scanning line shown in Figure 2(A). 5A and 5B, the scanning line driving circuit 1 shown in FIG. It is possible to output signals similar to those of the driving circuit 1 to the scanning lines and the inverted scanning lines.

[0097] In addition, the scanning line driving circuit 1 shown in FIG. 2A has a smaller capacitance than the scanning line driving circuit 1 shown in FIG. As a result, a high level potential is input to the terminal 61 of the inverted pulse output circuit in a short cycle. The transistor 71 of the inverted pulse output circuit is turned on in a short period (FIG. 2(A)). (See Fig. 3(B), (D) and Fig. 3(C)). Therefore, the transistors in the inverted pulse output circuit The potential of the gate of the transistor 73 drops due to a leakage current generated in the transistor 72. Even if the potential is increased, the potential can be increased again. The probability that the potential output by the output circuit to the inverted scan line will be less than the high power supply potential (Vdd) It is possible to reduce the

[0098] On the other hand, the scanning line driving circuit 1 shown in FIG. 5 has a smaller capacitance than the scanning line driving circuit 1 shown in FIG. The wiring for supplying the clock signal (GCK1) for the first scanning line driving circuit to the wiring for supplying the clock signal (GCK2) for the fourth scanning line driving circuit This can reduce the parasitic capacitance of the wiring that supplies the clock signal (GCK4) for the operating circuit. Therefore, the scanning line driving circuit 1 shown in FIG. 5 has a larger capacitance than the scanning line driving circuit 1 shown in FIG. This makes it possible to reduce power consumption.

[0099] The scanning line driving circuit 1 shown in FIG. 6A generates two types of clock signals for the scanning line driving circuit and two types of 2A in that it operates using a pulse width control signal. In addition, the connection relationship between the pulse output circuit and the inverted pulse output circuit also changes accordingly ( See Figure 6(A)).

[0100] Specifically, the scanning line driving circuit 1 shown in FIG. 6A is a fifth scanning line driving circuit clock Wiring for supplying a signal (GCK5) and a clock signal (GCK6) for the sixth scanning line driving circuit a wiring for supplying a fifth pulse width control signal (PWC5) and a wiring for supplying a sixth pulse width control signal (PWC6) and a wiring for supplying a width control signal (PWC6).

[0101] FIG. 6B is a diagram showing an example of a specific waveform of the signal shown in FIG. 6A. The fifth scanning line driving circuit clock signal (GCK5) shown in (B) periodically goes high. The potential (high power supply potential (Vdd)) and the low level potential (low power supply potential (Vss)) are repeatedly switched. The duty ratio of the sixth scanning line driving circuit clock signal is about 1 / 2. (GCK6) is a clock signal for the fifth scanning line driving circuit (GCK5) with a phase difference of 1 / 2 period. The fifth pulse width control signal (PWC5) is a signal that is shifted. Before the potential of the circuit clock signal (GCK5) becomes high level, and the potential of the fifth scanning line driving circuit clock signal (GCK5) becomes a high level potential. It is a signal with a duty ratio of less than 1 / 2 that is at a low level potential during a period when it is at a high level. The sixth pulse width control signal (PWC6) is a pulse width control signal obtained by dividing the fifth pulse width control signal (PWC5) by the sixth pulse width control signal (PWC6). The signals are shifted in phase by 1 / 2 period.

[0102] The scanning line driving circuit 1 shown in FIG. 6A is similar to the scanning line driving circuit 1 shown in FIG. 2A. Similar signals can be output for the scan line and the inverse scan line.

[0103] The scanning line driving circuit 1 shown in FIG. 2A is the same as the scanning line driving circuit 1 shown in FIG. 6A. In comparison, the wiring for supplying the clock signal (GCK1) for the first scanning line driving circuit to the fourth scanning line driving circuit This reduces the parasitic capacitance of the wiring that supplies the clock signal (GCK4) for the scan line driver circuit. Therefore, the scanning line driving circuit 1 shown in FIG. 2A can be used in the scanning line driving circuit shown in FIG. Compared to Path 1, it is possible to reduce power consumption.

[0104] On the other hand, the scanning line driving circuit 1 shown in FIG. 6A is different from the scanning line driving circuit 1 shown in FIG. In comparison, it is possible to reduce the number of signals required for the operation of the scanning line driving circuit.

[0105] The scanning line driving circuit 1 shown in FIG. 7 operates without using a pulse width control signal, which is different from the operation shown in FIG. 2(A). 1. In addition, the pulse output circuit and the inversion pulse The connection relationship of the output circuit also changes (see Figure 7).

[0106] In the scanning line driving circuit 1 shown in FIG. 7, the pulse output circuit outputs a selection signal to the scanning line. The signal and the shift pulse output to the pulse output circuit at the subsequent stage are the same signal. The signal that the pulse output circuit outputs to the scanning line (the potential of the scanning line) and the inverted pulse output The signal that the circuit outputs to the inverted scanning line (potential of the inverted scanning line) is the inverted signal. The scanning line driving circuit 1 shown in FIG. 1 can also be applied as a scanning line driving circuit included in a display device. be.

[0107] In addition, the scanning line driving circuit 1 shown in FIG. 2A has a larger capacitance than the scanning line driving circuit 1 shown in FIG. The period in which a selection signal is output to the scanning line arranged in the yth row and the period in which a selection signal is output to the scanning line arranged in the (y+1)th row are There is a wider interval between the periods when the select signals are output for the scan lines provided. In the scanning line driving circuit 1 shown in FIG. 7, if the first scanning line driving circuit clock signal (GC Any of the clock signals (GCK1) to (GCK4) for the fourth scanning line driving circuit is delayed or rippled. Even if the shape is dull, the scanning line driving circuit 1 shown in FIG. 6(A) has a higher pixel density. It is possible to input image signals with high precision.

[0108] On the other hand, the scanning line driving circuit 1 shown in FIG. 7 has a smaller capacitance than the scanning line driving circuit 1 shown in FIG. This makes it possible to reduce the number of signals required for the operation of the scanning line driving circuit.

[0109] <Modification of pulse output circuit> The pulse output circuit of the scanning line driver circuit has the configuration shown in FIG. For example, the pulse output circuit shown in FIGS. It is also possible to apply it as a pulse output circuit.

[0110] The pulse output circuit shown in FIG. 8(A) is the pulse output circuit shown in FIG. 3(A) with a source and One of the source and drain is electrically connected to a high power supply potential line, and the other of the source and drain is a transistor. The gate of transistor 32, the gate of transistor 34, the source and drain of transistor 35 the other input, the other source and drain of transistor 36, and the source of transistor 37 The other of the drain and the gate of the transistor 39 are electrically connected to the reset terminal. The transistor 50 is electrically connected to the reset terminal (Reset). The reset terminal is supplied with a high level potential during the vertical blanking period of the display device. A configuration can be adopted in which a low-level potential is input during the period other than the period. This allows the potential of each node in the pulse output circuit to be initialized, preventing malfunction. This makes it possible to prevent such operations.

[0111] The pulse output circuit shown in FIG. 8(B) is the pulse output circuit shown in FIG. 3(A) with a source and The other of the source and drain of transistor 31 and the other of the source and drain of transistor 32 the other of the source and drain of the transistor. The gate of the transistor 33 is electrically connected to the gate of the transistor 38, and the gate of the transistor 38 is connected to the high power supply voltage. The transistor 51 electrically connected to the voltage line is added. The starter 51 is turned on during the period when the potential of the node A is at a high level (the period t Therefore, the transistor 51 is added to the configuration. By doing so, during the periods t1 to t6, the gate of the transistor 33 and the gate of the transistor 3 The gate of transistor 8, the other of the source and drain of transistor 31, and the source of transistor 32 This allows the electrical connection between the source and drain to be cut off. During the period from period t1 to period t6, the bootstrap performed in the pulse output circuit This makes it possible to reduce the load during the backup operation.

[0112] The pulse output circuit shown in FIG. 9(A) is a circuit similar to the pulse output circuit shown in FIG. 8(B) except that a source and One of the two terminals is connected to the gate of transistor 33 and the other to the source and drain of transistor 51. The other of the source and drain is electrically connected to the gate of transistor 38. A transistor 52 is added, the gate of which is electrically connected to the high power supply potential line. As described above, by providing the transistor 52, It is possible to reduce the load during the bootstrap operation performed in the pulse output circuit. .

[0113] The pulse output circuit shown in FIG. 9(B) is a circuit that outputs a transistor from the pulse output circuit shown in FIG. 9(A). The transistor 51 is removed, and one of the source and drain is the source and drain of the transistor 31. the other input, the other of the source and drain of transistor 32, and the other of the source and drain of transistor 52. The other of the source and drain is electrically connected to the transistor. 33, the gate of which is electrically connected to a high power supply potential line. As described above, the provision of the transistor 53 This reduces the load during the bootstrap operation performed in the pulse output circuit. In addition, the incorrect pulses generated in the pulse output circuit are transmitted to the transistor 33, It is possible to reduce the effect on switching of 38.

[0114] <Modification of the inverted pulse output circuit> The configuration of the inversion pulse output circuit of the above-mentioned scanning line driver circuit is shown in FIG. For example, the inversion pulse output circuit shown in FIG. It is also possible to apply the present invention as a pulse output circuit included in the

[0115] The inversion pulse output circuit shown in FIG. 10(A) is similar to the inversion pulse output circuit shown in FIG. 3(C). One electrode is the source and drain of transistor 71, the other is the source and drain of transistor 72. The other electrode is electrically connected to the other of the source and drain of the transistor 73 and the gate of the transistor 74. The capacitor 80 is electrically connected to the terminal 63. By providing the capacitor 80, fluctuations in the potential of the gate of the transistor 73 can be suppressed. On the other hand, the inverted pulse output circuit shown in FIG. 3(C) can be In comparison with an inverted pulse output circuit, the circuit area can be reduced.

[0116] The inversion pulse output circuit shown in FIG. 10(B) is the same as the inversion pulse output circuit shown in FIG. 10(A). The other of the source and drain of the transistor 71 is connected to the other of the source and drain of the transistor 72. The other of the source and drain of the transistor 72 is electrically connected to the The other terminal is electrically connected to the gate of the transistor 73 and one electrode of the capacitor 80. A transistor 81 whose gate is electrically connected to the high power supply potential line is added. By providing the transistor 81, the dielectric breakdown of the transistors 71 and 72 can be prevented. Specifically, the inversion pulse output circuit shown in FIG. In this case, the potential of node C fluctuates greatly due to the bootstrap operation described above. The source-drain voltages of the transistors 71 and 72 (particularly the source voltage of the transistor 72) As a result, the drain-to-drain voltages of the transistors 71 and 72 fluctuate significantly. In response to this, the inverted pulse output circuit shown in Figure 10(B) In this case, the potential of the gate of the transistor 73 rises due to the bootstrap operation. When the voltage Vcc is 0, the transistor 81 is turned off. Therefore, the potential of the node C does not fluctuate greatly. On the other hand, it is possible to reduce the fluctuation of the source-drain voltage in FIG. In the inversion pulse output circuit shown in FIG. 10(A), the inversion pulse output circuit shown in FIG. 10(B) In comparison with the above, it is possible to reduce the circuit area.

[0117] The inversion pulse output circuit shown in FIG. 10(C) is similar to the inversion pulse output circuit shown in FIG. 3(C). In this case, the wiring to which one of the source and drain of the transistor 73 is electrically connected is connected to a high power The potential line is replaced with a wiring that supplies a power supply potential (Vcc). The power supply potential (Vcc) is higher than the low power supply potential (Vss) and is equal to the high power supply potential ( Vdd) is lower than the inverted pulse output circuit. It is possible to reduce the possibility that the potential output to the inverted scanning line will fluctuate. It is also possible to suppress the above-mentioned dielectric breakdown. On the other hand, the reverse pulse output shown in Figure 3(C) In the circuit, the behavior of the inverted pulse output circuit is different from that of the inverted pulse output circuit shown in Figure 10(C). This makes it possible to reduce the number of power supply potentials required for operation.

[0118] <Modification of pixel> The pixel configuration of the display device is not limited to the configuration shown in FIG. For example, the pixel shown in FIG. 4A is composed of only N-channel transistors. However, the present invention is not limited to this structure. , a pixel can be constructed using only P-channel transistors, or a pixel can be constructed using only N-channel transistors. It is also possible to configure a pixel by combining a P-channel transistor and a N-channel transistor.

[0119] As shown in FIG. 4A, the transistors provided in the pixels are unipolar transistors. When only the semiconductor layer is applied, high integration of pixels can be achieved. When polarity is given to a transistor by implanting impurities through the It is necessary to provide a margin between the P-channel transistor and the P-channel transistor. On the other hand, when a pixel is configured using only transistors of the same conductivity type, the interval This is because it becomes unnecessary.

[0120] <Example of a transistor> Specific examples of transistors constituting the above-mentioned scanning line driving circuit will be described below with reference to FIG. 11. The following description will be made with reference to FIG. 12. Note that the transistors described below are used to drive the scanning line. It is also possible to configure both the image and the pixel.

[0121] Note that various types of semiconductor materials are suitable for forming the channel formation region of the transistor. For example, a group 14 element such as silicon or silicon germanium can be used. Semiconductor materials that contain metal oxides, etc. The material may be amorphous or crystalline.

[0122] As the oxide semiconductor material, various materials can be used, and preferably, In, Ga, S An oxide semiconductor containing at least one element selected from the group consisting of n and Zn can be used. For example, when an In-Sn-Zn-O oxide is used as the oxide semiconductor, high field-effect mobility can be obtained. This is preferable because it can provide a transistor with high efficiency and high reliability. In-Sn-Ga-Zn-O oxides and ternary metal oxides such as In- Ga-Zn-O oxide (also written as IGZO), In-Al-Zn-O oxide, Sn-Ga-Zn-O oxides, Al-Ga-Zn-O oxides, Sn-Al-Zn-O In-Hf-Zn-O oxides, In-La-Zn-O oxides, In-C e-Zn-O oxide, In-Pr-Zn-O oxide, In-Nd-Zn-O oxide , In-Pm-Zn-O oxide, In-Sm-Zn-O oxide, In-Eu-Zn- O-based oxides, In-Gd-Zn-O-based oxides, In-Tb-Zn-O-based oxides, In-D y-Zn-O oxide, In-Ho-Zn-O oxide, In-Er-Zn-O oxide , In-Tm-Zn-O oxide, In-Yb-Zn-O oxide, In-Lu-Zn- O-based oxides, binary metal oxides such as In-Zn-O-based oxides and Sn-Zn-O-based oxides compound, Al-Zn-O oxide, Zn-Mg-O oxide, Sn-Mg-O oxide, I n-Mg-O oxides, In-Ga-O oxides, and oxides of single metals such as In-O The same applies to the case where a Sn-O-based oxide, a Sn-O-based oxide, a Zn-O-based oxide, or the like is used.

[0123] 11 and 12 show specific examples of a transistor in which the channel is formed in an oxide semiconductor. 11 and 12 show a specific example of a transistor with a bottom gate structure. However, a transistor having a top gate structure is used as the transistor. 11 and 12 show specific examples of staggered transistors. However, it is also possible to use a coplanar transistor as the transistor. .

[0124] 11(A) to (D) show transistors (so-called channel-etched transistors). 1A to 1C are cross-sectional views showing the manufacturing process of the semiconductor device.

[0125] First, a conductive film is formed on a substrate 400 having an insulating surface, and then a photomass A gate electrode layer 401 is formed by a photolithography process using a mask.

[0126] The substrate 400 is preferably a glass substrate that can be mass-produced. When the temperature of the heat treatment to be performed in the subsequent step is high, the glass substrate used as the substrate 400 is It is preferable to use a material having a strain point of 730° C. or higher. Glasses such as silicate glass, aluminoborosilicate glass, and barium borosilicate glass Materials are used.

[0127] In addition, an insulating layer serving as a base layer may be provided between the substrate 400 and the gate electrode layer 401. The layer has a function of preventing the diffusion of impurity elements from the substrate 400, and is made of silicon nitride, oxide, etc. One or more layers selected from silicon, silicon nitride oxide, or silicon oxynitride The laminated structure can be formed by the above.

[0128] Silicon oxynitride is a material whose composition contains more oxygen than nitrogen. For example, oxygen is 50 atomic % or more and 70 atomic % or less, and nitrogen is 0.5 atomic % or more and 15 atomic % or less. Below, silicon is in the range of 25 atomic % to 35 atomic % and hydrogen is in the range of 0 atomic % to 10 atomic %. Silicon nitride oxide refers to a material that contains more silicon than oxygen in its composition. It indicates a material with a high nitrogen content. For example, oxygen is 5 atomic % or more and 30 atomic % or less, and nitrogen is 2 0 atomic % to 55 atomic %; silicon is 25 atomic % to 35 atomic %; hydrogen is 10 atomic % The content of the element in the range of 25 atomic % or more is 25 atomic % or less. However, the above range is based on the Rutherford Rutherford Backscattering Spec (RBS) trastometry and Hydrogen Forward Scattering (HFS) This is measured using scattering spectrometry. The composition of the constituent elements does not exceed 100 atomic percent in total.

[0129] The gate electrode layer 401 may be made of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, or Mo. , Ag, Ta and W, and their nitrides, oxides and alloys, and Alternatively, it may be used in a laminated state. Alternatively, an oxide or oxynitride containing at least In and Zn may be used. For example, an In-Ga-Zn-ON material may be used.

[0130] Next, the gate insulating layer 402 is formed over the gate electrode layer 401. After the gate electrode layer 401 is formed, the gate electrode layer 401 is deposited by sputtering, evaporation, or plasma deposition without being exposed to the atmosphere. Chemical vapor deposition (PCVD), pulsed laser deposition (PLD), atomic layer deposition ( The film is formed using the ALD method or the molecular beam epitaxy method (MBE method).

[0131] The gate insulating layer 402 is preferably formed using an insulating film that releases oxygen by heat treatment.

[0132] "Oxygen is released by heat treatment" refers to TDS (Thermal Desorption / Solvent) Thermal Desorption Spectrometry (TDE) analysis converts the amount of oxygen to The amount of oxygen released is 1.0×10 18 atoms / cm 3 or more, preferably 3.0 × 10 2 0 atoms / cm 3 This means that the above is the case.

[0133] Here, the method for measuring the amount of released oxygen converted into oxygen atoms in TDS analysis is as follows: Explained below.

[0134] The amount of gas released during TDS analysis is proportional to the integral value of the spectrum. The amount of released gas is calculated by the ratio of the integral value of the measured spectrum to the reference value of the standard sample. The reference value of a standard sample is the product of the spectrum of a sample containing a specific atom. is the ratio of atomic density to atomic mass.

[0135] For example, the TDS analysis results of a silicon wafer containing hydrogen at a predetermined density as a standard sample, From the results of TDS analysis of the insulating film, the amount of oxygen molecules released from the insulating film (N O2 ) is calculated using equation (1). Here, the spectrum detected at mass number 32 obtained by TDS analysis is It is assumed that all of them are derived from oxygen molecules. There is another compound with mass number 32, CH3OH, but it does not exist. It is not considered here as it is unlikely to exist. The oxygen molecule containing the oxygen atom with mass number 17 and the oxygen atom with mass number 18 also exists in nature. Not considered because its abundance is extremely small.

[0136]

number

[0137] In equation (1), N H2 is the density converted value of hydrogen molecules desorbed from the standard sample. .S H2 is the integral value of the spectrum when the standard sample is analyzed by TDS. The reference value of the sample is N H2 / S H2 Let's say S O2 is the spectrum obtained when the insulating film was analyzed by TDS. α is a coefficient that affects the spectral intensity in TDS analysis. For details of formula (1), please refer to Japanese Patent Application Laid-Open No. 6-275697. The amount of oxygen released from the film was measured using a thermal desorption analyzer EMD-WA1000S / W was used as the standard sample. 16 atoms / cm 3 Silicon dioxide containing hydrogen atoms Measurement is performed using a wafer.

[0138] In addition, some of the oxygen is detected as oxygen atoms in TDS analysis. The atomic ratio can be calculated from the ionization rate of oxygen molecules. Since it includes the ionization rate of the molecules, evaluating the amount of released oxygen molecules can be used to estimate the amount of released oxygen atoms. It is also possible to estimate.

[0139] In addition, N O2 is the amount of released oxygen molecules. The amount of released oxygen atoms is This is twice the amount of offspring released.

[0140] In the above structure, the film that releases oxygen by heat treatment is silicon oxide ( SiO X (X>2)) or silicon oxide (SiO X (X>2) ) is a material that contains more than twice the number of oxygen atoms per unit volume as the number of silicon atoms. The number of silicon atoms and oxygen atoms per unit volume was measured by Rutherford backscattering spectroscopy. This is the value.

[0141] Oxygen is supplied from the gate insulating layer 402 to the oxide semiconductor film, whereby the oxide semiconductor film The interface state density with the gate insulating layer 402 can be reduced. It is possible to suppress the capture of carriers at the interface with the insulating layer 402, and the deterioration of electrical characteristics is prevented. Therefore, a transistor with little degradation can be obtained.

[0142] Furthermore, charges may be generated due to oxygen vacancies in the oxide semiconductor film. The oxygen vacancies in the semiconductor film act as donors, releasing electrons as carriers. The threshold voltage of the transistor shifts in the negative direction. Oxygen is sufficiently supplied from the oxide semiconductor film 402 to the oxide semiconductor film provided in contact therewith. The oxide semiconductor film contains excess oxygen, which causes the threshold voltage to shift toward the negative direction. Oxygen vacancies in the oxide semiconductor film, which are a factor that causes a shift to the θ-axis direction, can be reduced.

[0143] The gate insulating layer 402 is required to have a sufficient flatness so that crystal growth of the oxide semiconductor film can be easily performed. It is preferable that the polymer has the following properties.

[0144] The gate insulating layer 402 may be made of silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride. Silicon, aluminum oxide, aluminum nitride, hafnium oxide, zirconium oxide, yttrium oxide, lanthanum oxide, cesium oxide, tantalum oxide and magnesium oxide One or more species may be selected and used in a single layer or laminated form.

[0145] The gate insulating layer 402 is preferably formed by sputtering at a substrate heating temperature of room temperature or higher. The film is formed at a temperature of 200°C or less, preferably 50°C to 150°C, in an oxygen gas atmosphere. In addition, a rare gas may be added to oxygen gas, in which case the ratio of oxygen gas should be 30% by volume or more. The content of the gate insulating layer is preferably 50% by volume or more, and more preferably 80% by volume or more. The thickness of 402 is 100 nm or more and 1000 nm or less, preferably 200 nm or more and 700 nm or less. The lower the substrate heating temperature during film formation, the higher the oxygen gas ratio in the film formation atmosphere. However, the thicker the gate insulating layer 402 is, the more oxygen is released when the gate insulating layer 402 is subjected to heat treatment. The sputtering method can reduce the hydrogen concentration in the film compared to the PCVD method. The gate insulating layer 402 may be formed to a thickness exceeding 1000 nm, but this is not recommended for production purposes. The thickness should be such that it does not impair the performance.

[0146] Next, a layer is deposited on the gate insulating layer 402 by sputtering, evaporation, PCVD, or PLD. The oxide semiconductor film 403 is formed by an ALD method, an MBE method, or the like. corresponds to a cross-sectional view after the above steps.

[0147] The thickness of the oxide semiconductor film 403 is greater than or equal to 1 nm and less than or equal to 40 nm. 3 nm to 20 nm. In particular, for transistors with a channel length of 30 nm or less In this case, the short channel effect can be suppressed by setting the thickness of the oxide semiconductor film 403 to about 5 nm. This allows stable electrical characteristics to be obtained.

[0148] In particular, by using an In—Sn—Zn—O-based material for the oxide semiconductor film 403, A transistor with high field effect mobility can be obtained.

[0149] A transistor in which a channel is formed in an oxide semiconductor film containing In, Sn, and Zn as its main components The oxide semiconductor film is formed by heating the substrate or by By performing heat treatment after formation, good characteristics can be obtained. An element that is contained in an amount of 5 atomic % or more.

[0150] Intentionally heating the substrate after forming an oxide semiconductor film containing In, Sn, and Zn as its main components This makes it possible to improve the field effect mobility of the transistor. This makes it possible to shift the threshold voltage of the transistor in a positive direction and make it normally off.

[0151] The oxide semiconductor film 403 has a band gap of 0.1 to 0.2 μm in order to reduce the off-state current of the transistor. A material having an energy of 2.5 eV or more, preferably 2.8 eV or more, and more preferably 3.0 eV or more By using the oxide semiconductor film 403 whose band gap is in the above range, The off-state current of the transistor can be reduced.

[0152] Note that the oxide semiconductor film 403 contains reduced amounts of hydrogen, alkali metals, alkaline earth metals, and the like. The oxide semiconductor film 403 preferably has an extremely low impurity concentration. When 403 contains the above-mentioned impurities, the recombination in the band gap occurs due to the level formed by the impurities. This causes an increase in the off-state current of the transistor.

[0153] The hydrogen concentration in the oxide semiconductor film 403 was measured by secondary ion mass spectrometry (SIMS). ary Ion Mass Spectrometry) is 5×10 19 cm - 3 Less than 5 x 10 18 cm -3 Less than or equal to 1×10 18 cm -3 Below Lower, more preferably 5 × 10 17 cm -3 The following applies.

[0154] The alkali metal concentration in the oxide semiconductor film 403 was measured by SIMS. Concentration is 5 x 10 16 cm -3 Less than 1 × 10 16 cm -3 The following are more preferred: 1×10 15 cm -3 Similarly, the lithium concentration is 5×10 15 cm -3 Less than 1 × 10 15 cm -3Similarly, the potassium concentration is 5 x 10 15 cm -3 Less than 1 × 10 15 cm -3 The following applies.

[0155] In addition, the oxide semiconductor film 403 is c-axis oriented and has an ab-plane, a surface, or an interface. The atomic arrangement is triangular or hexagonal when viewed from the top, and the metal atoms are arranged in layers or In the ab plane, metal atoms and oxygen atoms are arranged in layers, and the a-axis or b-axis is C-Axis Aligned C A CAAC-OS film containing an oxide semiconductor film (also called a C Axis A crystal) ligned Crystalline Oxide Semiconductor membrane and ) can also be applied.

[0156] CAAC is, in a broad sense, a non-single crystal that has a triangular shape when viewed perpendicular to its ab plane. It has an atomic arrangement of a hexagon, an equilateral triangle, or a regular hexagon, and when viewed from a direction perpendicular to the c-axis direction, It refers to a crystal containing a phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. A part of the oxygen constituting the CAAC may be substituted with nitrogen.

[0157] The CAAC-OS film is not a single crystal, but is not formed solely from amorphous material. The CAAC-OS film contains crystallized portions (crystalline portions), but one crystalline portion and another The boundaries of the crystalline portions may not be clearly distinguishable. The c-axes of the individual crystals are aligned in a certain direction (e.g., the surface of the substrate on which the CAAC-OS film is formed, the CA The orientation of the CAAC-OS film may be perpendicular to the surface of the film. The normal to the ab plane of each crystal part constituting the film is in a certain direction (for example, when the CAAC-OS film is formed, The direction may be perpendicular to the surface of the substrate on which the CAAC-OS film is formed, or the surface of the CAAC-OS film. As an example of such a CAAC-OS film, a film is formed on the surface of the film or the substrate on which it is formed. When observed from a perpendicular direction, a triangular or hexagonal atomic arrangement is observed, and the cross section of the film When observed, a layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed. Examples of the oxide film include those that can be used as the base material.

[0158] The oxide semiconductor film 403 is preferably formed by a sputtering method at a substrate heating temperature of 100 ° C. or higher and 600 ° C. or lower, preferably 150 ° C. or higher and 550 ° C. or lower, more preferably 200 ° C. The oxide semiconductor film 403 is formed in an oxygen gas atmosphere at a temperature of 100° C. or higher and 500° C. or lower. The thickness is set to 3 nm or more and 40 nm or less, preferably 3 nm or more and 20 nm or less. The higher the concentration, the lower the impurity concentration of the resulting oxide semiconductor film 403. The atomic arrangement in the conductive film 403 is well-ordered and highly dense, and crystals or CAAC are easily formed. Furthermore, by forming the film in an oxygen gas atmosphere, it is possible to avoid the inclusion of unnecessary atoms such as rare gases. However, in a mixed atmosphere of oxygen gas and rare gas, crystals or CAAC are easily formed. In this case, the oxygen gas content is 30% by volume or more, preferably 50% by volume. The oxide semiconductor film 403 is preferably 80% by volume or more. However, if the thickness is too thin, the effect of interface scattering will increase. This can lead to a decrease in field-effect mobility.

[0159] The oxide semiconductor film 403 is formed by sputtering an In-Sn-Zn-O material. In this case, the atomic ratio is preferably In:Sn:Zn=2:1:3, In:Sn:Zn=1 :2:2, In:Sn:Zn=1:1:1 or In:Sn:Zn=20:45:35 The In-Sn-Zn-O target shown in Fig. 1 was used. The oxide semiconductor film 403 is formed using a Zn—O target, and thus a crystalline or CAA C is more likely to be formed.

[0160] Next, a first heat treatment is performed. The first heat treatment is performed in a reduced pressure atmosphere, an inert atmosphere, or an acid atmosphere. The first heat treatment is performed in a chemical atmosphere. The impurity concentration in the oxide semiconductor film 403 is reduced by the first heat treatment. FIG. 11(B) corresponds to a cross-sectional view after the above steps.

[0161] The first heat treatment is performed in a reduced pressure or inert atmosphere, and then the temperature is maintained. It is preferable to switch to an oxidizing atmosphere while heating, and then perform further heat treatment. Alternatively, when heat treatment is performed in an inert atmosphere, the impurity concentration in the oxide semiconductor film 403 can be effectively reduced. This is because oxygen deficiency occurs at the same time, and The oxygen deficiency can be reduced by heat treatment in an oxidizing atmosphere.

[0162] The oxide semiconductor film 403 is formed by first heat treatment in addition to heating the substrate during film formation. As a result, the field effect of the transistor It is possible to increase the field effect mobility to a level close to the ideal field effect mobility described later.

[0163] Note that oxygen ions are implanted into the oxide semiconductor film 403, and the oxide semiconductor film 404 is formed by heat treatment. The impurities such as hydrogen contained in 03 are released, and the heat treatment is carried out simultaneously with or after the heat treatment. The oxide semiconductor film 403 may be crystallized by the treatment.

[0164] Alternatively, instead of the first heat treatment, the oxide semiconductor film 40 may be selectively irradiated with a laser beam. Alternatively, the first heat treatment may be performed while irradiating the second layer with a laser beam to crystallize the second layer. Alternatively, the oxide semiconductor film 403 may be crystallized. When irradiating with a laser beam, it is performed in an oxidizing atmosphere or a reduced pressure atmosphere. Laser beam (CW laser beam) or pulsed laser beam (pulse laser beam) For example, an Ar laser, a Kr laser, or an excimer laser can be used. Any gas laser, or single or polycrystalline YAG, YVO4, Forsterite ( Mg2SiO4), YAlO3 or GdVO4 with Nd, Yb, Cr as dopants Lasers with a medium doped with one or more of Ti, Ho, Er, Tm, and Ta , or glass laser, ruby ​​laser, alexandrite laser, Ti:sapphire Lasers, or copper vapor lasers or gold vapor lasers. The fundamental wave of such a laser beam, or the fundamental By irradiating a laser beam of any one of the second harmonic, the fifth harmonic, and the third harmonic, the oxide semiconductor The oxide semiconductor film 403 can be crystallized. It is preferable to use a material with a band gap larger than that of 403. For example, K Laser beam emitted from an excimer laser oscillator of rF, ArF, XeCl, or XeF The laser beam may be linear in shape.

[0165] It is also possible to perform laser beam irradiation multiple times under different conditions. The first laser beam irradiation is performed in a rare gas atmosphere or a reduced pressure atmosphere, and the second laser beam irradiation is performed in a rare gas atmosphere or a reduced pressure atmosphere. When the beam irradiation is performed in an oxidizing atmosphere, oxygen vacancies in the oxide semiconductor film 403 are reduced and high crystallinity is obtained. This is preferable because crystallinity can be obtained.

[0166] Next, the oxide semiconductor film 403 is processed into an island shape by a photolithography process or the like. Then, a compound semiconductor film 404 is formed.

[0167] Next, a conductive film is formed over the gate insulating layer 402 and the oxide semiconductor film 404, and then a photo The source electrode 405A and the drain electrode 405B are formed by a lithography process or the like. The conductive film can be formed by sputtering, vapor deposition, PCVD, PLD, or The LD method, MBE method, or the like may be used. B is Al, Ti, Cr, Co, Ni, Cu, Y, Zr, as in the gate electrode layer 401. One or more selected from Mo, Ag, Ta, W, their nitrides, oxides and alloys. It may be used in layers or laminates.

[0168] Next, the insulating film 406 that will become the upper insulating film is formed by sputtering, evaporation, PCVD, or PL The film is formed by the D method, the ALD method, the MBE method, or the like. The insulating film 406 may be formed by a method similar to that for the gate insulating layer 402. .

[0169] A protective insulating film (not shown) may be formed by stacking on the insulating film 406. The film is formed at a temperature in the range of 250°C to 450°C, preferably 150°C to 800°C. In particular, it is preferable that the material has a property of not allowing oxygen to pass through even after heat treatment for, for example, one hour.

[0170] Due to the above-mentioned properties, when the protective insulating film is provided around the insulating film 406, Oxygen released from the insulating film 406 by heat treatment diffuses to the outside of the transistor. In this way, oxygen is held in the insulating film 406, and therefore, the transistor This prevents a decrease in the field-effect mobility of the capacitor, reduces the variation in threshold voltage, and improves reliability. It can be improved.

[0171] The protective insulating film is made of silicon nitride oxide, silicon nitride, aluminum oxide, or aluminum nitride. , hafnium oxide, zirconium oxide, yttrium oxide, lanthanum oxide, cesium oxide One or more of aluminum, tantalum oxide and magnesium oxide are selected and used in a single layer or laminated layer. That's fine.

[0172] After the insulating film 406 is formed, a second heat treatment is performed. The above steps result in the cross section shown in FIG. The second heat treatment is carried out in a reduced pressure atmosphere, an inert atmosphere, or an oxidizing atmosphere. The temperature is 150°C or higher and 550°C or lower, preferably 250°C or higher and 400°C or lower. By performing the heat treatment in step 2, oxygen is released from the gate insulating layer 402 and the insulating film 406. Oxygen vacancies in the oxide semiconductor film 404 can be reduced. and the oxide semiconductor film 404, and the interface state density between the oxide semiconductor film 404 and the insulating film 406. This reduces the interface state density, thereby reducing the variation in the threshold voltage of transistors. This can reduce the noise and improve reliability.

[0173] Transistor using the oxide semiconductor film 404 subjected to the first heat treatment and the second heat treatment Specifically, the field-effect mobility is high and the off-current is small per 1 μm of channel width. Off-state current of 1×10 -18 Below A, 1×10 -21 A or less or 1 x 10 -24 Below A It can be said that:

[0174] The oxide semiconductor film 404 is preferably non-single-crystal. When oxygen vacancies occur in the oxide semiconductor film 404 due to the influence of external light or heat, If the semiconductor film 404 is a perfect single crystal, interstitial oxygen exists to compensate for the oxygen vacancies. Therefore, carriers due to the oxygen vacancies are generated in the oxide semiconductor film 404. Therefore, the threshold voltage of the transistor may shift in the negative direction. Because there is.

[0175] The oxide semiconductor film 404 preferably has crystallinity. As the insulating film, a polycrystalline oxide semiconductor film or a CAAC-OS film is preferably used.

[0176] Through the above steps, the transistor illustrated in FIG. 11D can be manufactured.

[0177] In addition, transistors having structures different from those of the above-described transistors are shown in FIGS. 12(A) to 12(D) are the so-called etching stoppers. The manufacturing process of a channel-stop type (also called a channel-protective type) transistor is shown. Cross-sectional view.

[0178] The transistors shown in FIGS. 12(A) to 12(D) and the transistors shown in FIGS. 11(A) to 11(D) The difference between the transistor and the transistor is whether or not it has an insulating film 408 that serves as an etching stop film. Therefore, in the following, the explanation overlapping with FIGS. 11(A) to 11(D) will be omitted, and the above explanation will be repeated. This document is hereby incorporated by reference.

[0179] By carrying out the above-described steps, the structure shown in the cross-sectional views of FIGS. 12(A) and 12(B) can be obtained. This can be done.

[0180] The insulating film 408 shown in FIG. 12C has the same structure as the gate insulating layer 402 and the insulating film 406. That is, the insulating film 408 can be formed by using an insulating material that releases oxygen by heat treatment. It is preferred to use a membrane.

[0181] Note that the insulating film 408, which functions as an etching stop film, is provided to prevent photolithography. When forming the source electrode 405A and the drain electrode 405B by a lithography process or the like, Therefore, the oxide semiconductor film 404 can be prevented from being etched.

[0182] The insulating film 408 is formed in the same manner as the insulating film 406 shown in FIG. 12(D). Oxygen is released by the second heat treatment later. The effect of reducing oxygen vacancies can be further enhanced. The interface state density with the oxide semiconductor film 404 and the interface between the oxide semiconductor film 404 and the insulating film 408 Since the density of states can be reduced, the variation in the threshold voltage of the transistor can be reduced. This can improve reliability.

[0183] Through the above steps, the transistor illustrated in FIG. 12D can be manufactured.

[0184] The transistors shown in FIGS. 11(D) and 12(D) are used to form the scanning line driver circuit and the pixel. For example, the transistor 11 shown in FIG. A configuration in which a transistor is applied will be described with reference to FIG. 13. Specifically, FIG. 13(A) 11D is a top view of the transistor 11. 13B shows the transistor shown in FIG. 12D as a transistor 1. 13A. In addition, the line segment C1-C2 in FIG. The cross section is shown in FIG. 11(D), which is a cross section taken along line C1-C2 in FIG. 13(B). This is shown in Figure 12(D).

[0185] In the transistors shown in FIGS. 13A and 13B, the signal line 6 shown in FIG. A part of the wiring that functions as a source or drain of the transistor 11 is used as the driving A part of the wiring that functions as the scan line 4 is used as the gate of the transistor 11. In this way, each terminal of the transistor is formed using a part of the wiring provided in the display device. is also possible.

[0186] <Regarding various electronic devices equipped with LCD displays> An example of an electronic device incorporating the liquid crystal display device disclosed in this specification will be described below with reference to FIG. This will be explained with reference to the following.

[0187] FIG. 14(A) shows a notebook-type personal computer, which includes a main body 2201, It is composed of a housing 2202, a display unit 2203, a keyboard 2204, and the like.

[0188] FIG. 14(B) is a diagram showing a personal digital assistant (PDA), and the main body 2211 has a display unit 2 213, an external interface 2215, an operation button 2214, etc. are provided. In addition, a stylus 2212 is provided as an accessory for operation.

[0189] FIG. 14C shows an electronic book 2220 as an example of electronic paper. The book 2220 is made up of two cases, a case 2221 and a case 2223. 2221 and the housing 2223 are integrated by a shaft 2237. With this configuration, the electronic book 2220 can be opened and closed with the opening and closing movement of the arrows. It can be used like a paper book.

[0190] The housing 2221 incorporates a display unit 2225, and the housing 2223 incorporates a display unit 2227. The display unit 2225 and the display unit 2227 are configured to display a continuous screen. Alternatively, a different screen may be displayed. For example, a text is displayed on the right display unit (display unit 2225 in FIG. 14(C)) and An image can be displayed on the display unit (the display unit 2227 in FIG. 14C).

[0191] 14C shows an example in which an operation unit and the like are provided in the housing 2221. For example, The housing 2221 includes a power supply 2231, operation keys 2233, a speaker 2235, etc. The operation keys 2233 can be used to turn pages. The device may be configured to include a keyboard, a pointing device, etc. or on the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and US A terminal that can be connected to various cables such as B cable, etc., and a recording medium insertion section. Furthermore, the electronic book 2220 may be configured to have the function of an electronic dictionary. You may do so.

[0192] The electronic book 2220 may also be configured to be capable of transmitting and receiving information wirelessly. The desired book data can be purchased and downloaded from the electronic book server. It is also possible.

[0193] Electronic paper can be applied to any field as long as it displays information. For example, in addition to e-books, posters, advertisements on trains and other vehicles, credit cards, etc. The present invention can be applied to displays on various cards such as credit cards.

[0194] 14(D) is a diagram showing a mobile phone. The mobile phone has a housing 2240 and The housing 2241 is made up of two housings, a display panel 2242 and a screen. Speaker 2243, microphone 2244, pointing device 2246, camera The housing 2240 is provided with a lens 2247, an external connection terminal 2248, etc. The mobile phone is equipped with a solar cell 2249 for charging the mobile phone, an external memory slot 2250, etc. The antenna is also built into the housing 2241.

[0195] The display panel 2242 has a touch panel function, and the image displayed on the display panel 2242 is shown in FIG. The multiple operation keys 2245 are shown by dotted lines. A boost circuit is implemented to boost the voltage output from module 2249 to the voltage required for each circuit. In addition to the above configuration, a configuration incorporating a non-contact IC chip, a small recording device, etc. It can also be done as follows.

[0196] The display direction of the display panel 2242 changes appropriately depending on the usage mode. The camera lens 2247 is located on the same surface as the lens 2242, allowing video calls. The speaker 2243 and microphone 2244 are not limited to voice calls, but are also used for video calls. Furthermore, the housing 2240 and the housing 2241 can be slid apart. As shown in Figure 14(D), it can be folded from the unfolded state to the overlapped state, making it easy to carry. Suitable miniaturization is possible.

[0197] The external connection terminal 2248 can be connected to various cables such as AC adapters and USB cables. It is capable of charging and data communication. By inserting a recording medium, it is possible to store and transfer a larger amount of data. In addition, it may also be equipped with an infrared communication function, a television receiving function, etc.

[0198] FIG. 14(E) is a diagram showing a digital camera. The digital camera has a main body 226 1, display unit (A) 2267, eyepiece 2263, operation switch 2264, display unit (B) 22 It is composed of a battery 2266, etc.

[0199] FIG. 14(F) is a diagram showing a television device. In the television device 2270, A display unit 2273 is built into the housing 2271. The display unit 2273 displays images. In this case, the housing 2271 is supported by a stand 2275. The figure shows the configuration.

[0200] The television device 2270 can be operated using an operation switch provided on the housing 2271 or a separate remote control. This can be done by the remote control operation device 2280. The channel and volume can be controlled by the -2279, and the information displayed on the display 2273 is In addition, the remote control operation device 2280 can be used to operate the video. A display unit 2277 for displaying information output from the device 2280 may be provided.

[0201] The television device 2270 is preferably configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts. By connecting to a wired or wireless communication network, and two-way (between sender and receiver, or between receivers) information communication. It is possible to do so. [Explanation of symbols]

[0202] 1. Scanning line driving circuit 2. Signal line driver circuit 3 Current source 4 scan lines 5 Inverted Scan Lines 6 Signal Line 7 Power line 10 pixels 11~16 Transistors 17 Capacitor 18 Organic EL element 20 Pulse output circuit Terminals 21-27 31~39 Transistors 50~53 Transistor 60 Inverted pulse output circuit Terminals 61-63 71~74 Transistors 80 Capacitor 81 Transistor 400 boards 401 Gate electrode layer 402 Gate insulating layer 403 Oxide semiconductor film 404 Oxide semiconductor film 405A Source Electrode 405B Drain electrode 406 Insulating film 408 Insulating film 2201 Main unit 2202 Case 2203 Display section 2204 keyboard 2211 Main unit 2212 Stylus 2213 Display section 2214 Operation button 2215 External Interface 2220 e-books 2221 Case 2223 Case 2225 Display section 2227 Display section 2231 Power supply 2233 Operation key 2235 Speaker 2237 Shaft 2240 chassis 2241 Case 2242 Display Panel 2243 Speaker 2244 Microphone 2245 Operation Key 2246 Pointing Device 2247 Camera Lenses 2248 External connection terminal 2249 Solar Cells 2250 external memory slot 2261 Main unit 2263 Eyepiece 2264 Operation switch 2265 Display section (B) 2266 Battery 2267 Display section (A) 2270 Television Equipment 2271 Case 2273 Display section 2275 Stand 2277 Display section 2279 Operation Key 2280 Remote Control Machine

Claims

[Claim 1] a first conductive layer having a region located above the substrate and functioning as a gate electrode layer; a first insulating layer having a region located above the first conductive layer and functioning as a gate insulating layer; an oxide semiconductor film having a region located above the first insulating layer and having a channel formation region; a second insulating layer having a region located above the oxide semiconductor film; a second conductive layer having a region in contact with a top surface of the oxide semiconductor film and a region in contact with a top surface of the second insulating layer, the second conductive layer functioning as a source electrode; a third conductive layer having a region in contact with a top surface of the oxide semiconductor film and a region in contact with a top surface of the second insulating layer and functioning as a drain electrode; The semiconductor device is such that the oxide semiconductor film is In—O.

Images