Data transmission system, transmitter, receiver, and data transmission method

Abstract

To perform clock synchronization with a simple configuration while reducing a transmission delay amount of data in a system for transmitting data included in a packet.SOLUTION: The transmission device operates in accordance with a reference clock, the transmission device transmits a packet to the reception device at a transmission timing in accordance with a transmission cycle, and the reception device reproduces the reference clock based on a pulse signal based on an arrival timing of the packet from the transmission device and the number of pulses of the reference clock in the transmission cycle.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a data transmission system, a transmitting device, a receiving device, and a data transmission method. [Background technology]

[0002] Conventionally, techniques for synchronizing clocks between a transmitting device and a receiving device have been proposed. For example, Patent Document 1 (JP 2011-71830 A) discloses the following clock recovery device. That is, the clock recovery device recovers a clock from a timestamp included in a received packet, and includes counter means that counts based on the recovered clock, and recovery means that recovers the clock based on the difference between the timestamp included in the received packet and the count value of the counter means at the time the packet is received, and the packet is a packet for measuring delay. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-71830 [Patent Document 2] Japanese Patent Application Laid-Open No. 2008-177913 [Patent Document 3] Japanese Patent Application Laid-Open No. 2012-54847 Summary of the Invention [Problem to be solved by the invention]

[0004] Beyond the techniques described in Patent Documents 1 to 3, there is a demand for a technique that can perform clock synchronization with a simple configuration while reducing the amount of data transmission delay in a system that transmits data contained in packets.

[0005] The present disclosure has been made to solve the above-mentioned problems, and its purpose is to provide a data transmission system, a transmitting device, a receiving device, and a data transmission method that are capable of performing clock synchronization with a simple configuration while reducing the amount of data transmission delay in a system that transmits data contained in packets. [Means for solving the problem]

[0006] The data transmission system disclosed herein comprises a transmitting device that transmits transmission data at a predetermined data rate, and a receiving device that receives the transmission data from the transmitting device, wherein the transmitting device transmits packets containing the transmission data to the receiving device using a data clock corresponding to the data rate at transmission timing according to a predetermined transmission clock, and the receiving device regenerates the data clock based on a pulse signal based on the arrival timing of the packet from the transmitting device and the amount of transmission data contained in the packet.

[0007] One aspect of the present disclosure may be realized not only as a transmitting device including such a characteristic processing unit, but also as a transmitting method including steps of such characteristic processing, or as a program for causing a computer to execute such steps. Furthermore, one aspect of the present disclosure may be realized as a semiconductor integrated circuit that realizes part or all of the transmitting device.

[0008] One aspect of the present disclosure may be realized not only as a receiving device including such a characteristic processing unit, but also as a receiving method including steps of such characteristic processing, or as a program for causing a computer to execute such steps. Furthermore, one aspect of the present disclosure may be realized as a semiconductor integrated circuit that realizes part or all of the receiving device. [Effects of the Invention]

[0009] According to the present disclosure, in a system in which data is transmitted in packets, clock synchronization can be performed with a simple configuration while reducing the amount of data transmission delay. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a diagram illustrating a configuration of a data transmission system according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram illustrating a configuration of a transmission device according to the first embodiment of the present disclosure. [Figure 3] FIG. 3 is a timing chart illustrating a packet generation process in the transmission device according to the first embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram illustrating a configuration of a receiving device according to the first embodiment of the present disclosure. [Figure 5] FIG. 5 is a diagram illustrating a configuration of a clock recovery unit in a receiving device according to the first embodiment of the present disclosure. [Figure 6] FIG. 6 is a timing chart showing pulse signals and bit clocks generated in the receiving device according to the first embodiment of the present disclosure. [Figure 7] FIG. 7 is a diagram illustrating an example of a transmission sequence of transmission data in the data transmission system according to the first embodiment of the present disclosure. [Figure 8] FIG. 8 is a diagram illustrating a configuration of a data transmission system according to the second embodiment of the present disclosure. [Figure 9] FIG. 9 is a diagram illustrating a configuration of a transmission device according to the second embodiment of the present disclosure. [Figure 10] FIG. 10 is a diagram illustrating a configuration of a receiving device according to the second embodiment of the present disclosure. [Figure 11] FIG. 11 is a diagram illustrating a configuration of a clock recovery unit in a receiving device according to the second embodiment of the present disclosure. [Figure 12] FIG. 12 is a diagram illustrating a configuration of a data transmission system according to the third embodiment of the present disclosure. [Figure 13] FIG. 13 is a diagram illustrating a configuration of a transmission device according to the third embodiment of the present disclosure. [Figure 14]FIG. 14 is a diagram illustrating a configuration of a receiving device according to the third embodiment of the present disclosure. [Figure 15] FIG. 15 is a diagram illustrating a configuration of a reference clock recovery unit in a receiving device according to the third embodiment of the present disclosure. [Figure 16] FIG. 16 is a timing chart illustrating a pulse signal and a bit clock generated in a receiving device according to the third embodiment of the present disclosure. [Figure 17] FIG. 17 is a diagram illustrating an example of a relationship information generating unit in a transmission device according to the third embodiment of the present disclosure. [Figure 18] FIG. 18 is a diagram illustrating a configuration of a clock recovery unit in a receiving device according to the third embodiment of the present disclosure. [Figure 19] FIG. 19 is a diagram illustrating an example of a relationship information generating unit in a transmission device according to the third embodiment of the present disclosure. [Figure 20] FIG. 20 is a diagram illustrating a configuration of a clock recovery unit in a receiving device according to the third embodiment of the present disclosure. [Figure 21] FIG. 21 is a diagram illustrating an example of a relationship information generating unit in a transmission device according to the third embodiment of the present disclosure. [Figure 22] FIG. 22 is a diagram illustrating a configuration of a clock recovery unit in a receiving device according to the third embodiment of the present disclosure. [Figure 23] FIG. 23 is a diagram illustrating an example of a transmission sequence of transmission data in a data transmission system according to the third embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0011] First, the contents of the embodiments of the present disclosure will be listed and described. (1) A data transmission system according to an embodiment of the present disclosure includes a transmitting device that transmits transmission data at a predetermined data rate and a receiving device that receives the transmission data from the transmitting device, wherein the transmitting device operates according to a reference clock, the transmitting device transmits packets to the receiving device at transmission timings according to a transmission period, and the receiving device regenerates the reference clock based on a pulse signal based on the arrival timing of the packets from the transmitting device and the number of pulses of the reference clock in the transmission period.

[0012] In this way, the receiving device regenerates the reference clock based on a pulse signal based on the arrival timing of packets and the number of pulses of the reference clock in a transmission cycle. This allows the reference clock to be regenerated using the interval between the arrival timings of packets as a common time interval with the transmitting device. This allows clock synchronization to be achieved with a simpler configuration than a configuration in which information about the reference clock is transmitted via a dedicated line separate from the optical signal transmission line. Furthermore, the receiving device regenerates the reference clock based on a packet read cycle adjusted so that the amount of data stored in a buffer that stores received packets is constant. Therefore, in a system that transmits data in packets, clock synchronization can be achieved with a simple configuration while reducing the amount of data transmission delay.

[0013] (2) In the above (1), the receiving device may include a PLL circuit that regenerates the reference clock, and the pulse signal may be provided as a reference signal to a phase comparator in the PLL circuit, and the division number of a divider between the output of a voltage-controlled oscillator in the PLL circuit and the input of the phase comparator may be set to a value corresponding to the number of pulses.

[0014] With this configuration, the pulse signal and the number of pulses can be reflected in the operation of the PLL circuit, and the reference clock can be reproduced with a simple configuration.

[0015] (3) In (1) or (2) above, the reference clock may be a data clock corresponding to the data rate, and the packet may be a data packet in which the transmission data is stored. The transmitting device may use the data clock to transmit to the receiving device at the transmission timing the data packet in which the transmission data is stored, the data packet in which the transmission data has a data amount corresponding to the number of pulses. The receiving device may regenerate the data clock based on a pulse signal based on the arrival timing of the data packet from the transmitting device and the amount of the transmission data included in the data packet.

[0016] With this configuration, the data clock can be recovered by using the interval between the arrival timings of the data packets as a common time interval with the transmitting device.

[0017] (4) In the above (3), the transmitting device may further transmit information indicating the amount of the transmission data included in the data packet to the receiving device.

[0018] With this configuration, the data clock can be more accurately reproduced based on the amount of transmission data actually stored in the data packet in the transmitting device, compared to a configuration in which the data clock is reproduced based on a design value of the amount of transmission data stored in the data packet.

[0019] (5) In (3) above, the transmission period may be a period based on a transmission clock synchronized with the data clock, and the transmitting device may transmit to the receiving device the data packet including the transmission data of a fixed amount of data according to the relationship between the frequency of the data clock and the frequency of the transmission clock.

[0020] With this configuration, the data clock can be accurately recovered in the receiving device without the need to provide the receiving device with information indicating the amount of transmission data stored in the data packets in the transmitting device. Also, since the same amount of transmission data is stored in all data packets, the data clock can be stably recovered in the receiving device.

[0021] (6) In (1) or (2) above, the packet may be a clock packet storing predetermined information, the transmission period may be a period based on the reference clock, the transmitting device may transmit the clock packet to the receiving device at the transmission timing, the transmitting device may transmit relationship information indicating the relationship between the frequency of the reference clock and the frequency of a data clock corresponding to the data rate to the receiving device, and the receiving device may regenerate the reference clock based on a pulse signal based on the arrival timing of the clock packet from the transmitting device and the number of pulses.

[0022] With this configuration, the interval between the arrival timings of the clock packets can be used as a common time interval with the transmitting device to regenerate the reference clock. Also, compared to a configuration that uses the interval between the arrival timings of data packets as a common time interval, a pulse signal based on the arrival timings can be generated with simpler processing.

[0023] (7) In (6) above, the transmitting device may transmit relationship information to the receiving device indicating the relationship between the frequency of the reference clock and the frequency of the data clock corresponding to the data rate, and the receiving device may regenerate the data clock based on the regenerated reference clock and the relationship information received from the transmitting device.

[0024] With this configuration, the reference clock can be used to further recover the data clock.

[0025] (8) A transmitting device according to an embodiment of the present disclosure is a transmitting device that operates according to a reference clock and transmits transmission data at a predetermined data rate to a receiving device, and includes a generating unit that generates packets and a transmitting unit that transmits the packets generated by the generating unit to the receiving device at a transmission timing according to a transmission period.

[0026] In this way, by configuring the system to transmit packets to a receiving device at transmission timings according to a transmission period, the receiving device can, for example, regard the arrival timing of the packets as the transmission timing and use the interval between the arrival timings of the packets as a common time interval with the transmitting device to regenerate a reference clock. Therefore, clock synchronization can be achieved with a simpler configuration than a configuration in which information about the reference clock is transmitted via a dedicated line separate from the optical signal transmission line. Furthermore, packet transmission delay can be reduced compared to a configuration in which the receiving device regenerates a reference clock based on a packet read cycle adjusted so that the amount of data stored in a buffer that stores received packets is constant. Therefore, in a system in which data is transmitted in packets, clock synchronization can be achieved with a simple configuration while reducing data transmission delay.

[0027] (9) A receiving device according to an embodiment of the present disclosure is a receiving device that receives transmission data from a transmitting device that operates according to a reference clock, and includes: a receiving unit that receives packets transmitted from the transmitting device at a transmission timing according to a transmission period; a generating unit that generates a pulse signal based on the arrival timing of the packet; and a regenerating unit that regenerates the reference clock based on the pulse signal generated by the generating unit and the number of pulses of the reference clock in the transmission period.

[0028] In this way, by regenerating the reference clock based on a pulse signal based on the arrival timing of packets and the number of pulses of the reference clock in a transmission cycle, the reference clock can be regenerated using the interval between the arrival timings of packets as a common time interval with the transmitting device. This allows clock synchronization to be achieved with a simpler configuration than a configuration in which information about the reference clock is transmitted via a dedicated line separate from the transmission line for optical signals. Furthermore, packet transmission delays can be reduced compared to a configuration in which the reference clock is regenerated based on a packet read cycle adjusted so that the amount of storage in a buffer that stores received packets is constant. Therefore, in a system that transmits data in packets, clock synchronization can be achieved with a simple configuration while reducing data transmission delays.

[0029] (10) A data transmission method according to an embodiment of the present disclosure is a data transmission method comprising a transmitting device that transmits transmission data at a predetermined data rate and a receiving device that receives the transmission data from the transmitting device, wherein the transmitting device operates according to a reference clock, and includes a step in which the transmitting device transmits a packet to the receiving device at a transmission timing according to a transmission period, and a step in which the receiving device regenerates the reference clock based on a pulse signal based on the arrival timing of the packet from the transmitting device and the number of pulses of the reference clock in the transmission period.

[0030] In this way, in a receiving device, a method for regenerating a reference clock based on a pulse signal based on the arrival timing of packets and the number of pulses of a reference clock in a transmission cycle allows the reference clock to be regenerated using the interval between the arrival timings of packets as a common time interval with the transmitting device, thereby enabling clock synchronization with a simpler configuration than a method for transmitting information about the reference clock via a dedicated line separate from the transmission line for optical signals. Furthermore, in a receiving device, a packet transmission delay can be reduced compared to a method for regenerating a reference clock based on a packet read cycle adjusted so that the amount of data stored in a buffer that stores received packets is constant. Therefore, in a system that transmits data in packets, clock synchronization can be achieved with a simple configuration while reducing the amount of data transmission delay.

[0031] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the drawings, identical or corresponding parts are designated by the same reference numerals, and their description will not be repeated. Furthermore, at least some of the embodiments described below may be combined in any manner.

[0032] First Embodiment [Configuration and basic operation] 1 is a diagram illustrating a configuration of a data transmission system according to a first embodiment of the present disclosure. Referring to FIG. 1, a data transmission system 301 includes a transmitting device 101 and a receiving device 201.

[0033] The transmitting device 101 transmits transmission data Dt at a predetermined data rate Rt to the receiving device 201. More specifically, the transmitting device 101 receives a stream of transmission data Dt, for example, having a nominal data rate Rt of 8 Gbps (Giga bit per second), from a data generating device 111 that generates the transmission data Dt. For example, the stream of transmission data Dt is a stream in which the end of the data is not determined and is transmitted continuously over a long period of time. The transmission data Dt may be video data, audio data, or data other than video data and audio data. The transmitting device 101 generates a fixed-length packet Pt that stores the received transmission data Dt, and transmits a frame Fr1 including the generated packet Pt to the receiving device 201 via the network 151. The data transfer rate between the transmitting device 101 and the receiving device 201 is, for example, 100 Gbps. The packet Pt is an example of a data packet.

[0034] The network 151 is, for example, an all-photonics network conforming to IOWN (Innovative Optical and Wireless Network). An optical signal including a frame Fr1 is transmitted through the network 151. The network 151 is a low-jitter transmission network in which fluctuations in the transmission delay of the frame Fr1 are small.

[0035] The receiving device 201 receives transmission data Dt from the transmitting device 101. More specifically, the receiving device 201 receives a frame Fr1 from the transmitting device 101 via the network 151, and acquires the transmission data Dt from a packet Pt included in the received frame Fr1. The receiving device 201 recovers a bit clock CL1 corresponding to a data rate Rt of the transmission data Dt, and transmits the transmission data Dt to the data processing device 211 using the recovered bit clock CL1. The bit clock CL1 is an example of a data clock and also an example of a reference clock.

[0036] The data transmission system 301 transmits the transmission data Dt with low delay between the data generating device 111 and the data processing device 211. The transmission delay of the transmission data Dt between the data generating device 111 and the data processing device 211 is, for example, 5 milliseconds or less.

[0037] [assignment] In the data transmission system 301, a technique is desired that can perform clock synchronization with a simple configuration while reducing the amount of transmission delay of the transmission data Dt.

[0038] For example, in a system that transmits transmission data Dt without packetizing it, it is possible to provide clock information related to the bit clock CL1 to the transmission destination by encoding or scrambling. On the other hand, since the transmitting device 101 is configured to transmit the transmission data Dt to the receiving device 201 by including it in a packet Pt, it is not easy to provide information related to the bit clock CL1 to the receiving device 201. Furthermore, if the clock information is transmitted using a dedicated line for transmitting clock information separate from the network 151, the configuration of the data transmission system 301 becomes complicated.

[0039] Furthermore, in the receiving device 201, when the amount of transmission data Dt stored in the buffer is monitored and the bit clock CL1 is regenerated based on the read cycle of the transmission data Dt adjusted so that the amount of packets stored in the buffer is constant, it is necessary to store the amount of transmission data Dt required for regeneration in the buffer, which results in a large transmission delay of the transmission data Dt between the data generating device 111 and the data processing device 211.

[0040] Therefore, the data transmission system 301 according to the embodiment of the present disclosure solves the above problem by adopting the following configuration.

[0041] (Transmitting device) 2 is a diagram illustrating a configuration of a transmitting device according to a first embodiment of the present disclosure. Referring to FIG. 2, the transmitting device 101 includes a receiving buffer 11, a clock recovery unit 12, a counter 13, a clock generation unit 14, an instruction unit 15, a frame generation unit 16, a transmission buffer 17, and a transmitting unit 18. The transmitting unit 18 is an example of a second transmitting unit. The frame generation unit 16 is an example of a storing unit. Some or all of the clock recovery unit 12, the counter 13, the clock generation unit 14, the instruction unit 15, the frame generation unit 16, and the transmitting unit 18 are realized by, for example, a processing circuit including one or more processors. The receiving buffer 11 and the transmitting buffer 17 are, for example, FIFO (First-In First-Out) buffers.

[0042] The transmitting device 101 operates in accordance with a bit clock CL1. The transmitting device 101 transmits a packet Pt to the receiving device 201 at a transmission timing according to a transmission cycle Ct1. For example, the transmitting device 101 transmits a packet Pt containing transmission data Dt to the receiving device 201 at a transmission timing according to a predetermined transmission clock CL2, using a bit clock CL1 corresponding to a data rate Rt of the transmission data Dt. The packet Pt stores the transmission data Dt with an amount of data corresponding to the number of pulses of the bit clock CL1 in the transmission cycle Ct1. Details of the processing in the transmitting device 101 will be described below.

[0043] The receiving buffer 11 receives the transmission data Dt having a nominal data rate Rt of 8 Gbps from the data generating device 111, and stores the received transmission data Dt.

[0044] The clock recovery unit 12 recovers a bit clock CL1 corresponding to the data rate Rt of the transmission data Dt. More specifically, the clock recovery unit 12 uses a CDR (Clock Data Recovery) function to extract the bit clock CL1 from the transmission data Dt transmitted from the data generating device 111 to the transmitting device 101. The clock recovery unit 12 outputs the extracted bit clock CL1 to the counter 13. Here, the frequency of the bit clock CL1 is 8000 MHz when the data rate Rt is 8 Gbps.

[0045] Counter 13 counts the pulses of bit clock CL1 received from clock recovery unit 12 and holds the count value.

[0046] The clock generating unit 14 generates a transmission clock CL2. For example, the clock generating unit 14 generates a 50 MHz transmission clock CL2 based on a clock output from a high-precision crystal oscillator (not shown). The clock generating unit 14 outputs the generated transmission clock CL2 to the instruction unit 15.

[0047] Every time the instruction unit 15 detects a rising edge of the transmission clock CL2 received from the clock generation unit 14 and every time the instruction unit 15 detects a falling edge of the transmission clock CL2, the instruction unit 15 outputs a frame generation instruction to the frame generation unit 16 and a transmission instruction to the transmission unit 18. That is, the instruction unit 15 outputs a frame generation instruction and a transmission instruction to the frame generation unit 16 and the transmission unit 18, respectively, at 10 nanosecond intervals.

[0048] The frame generation unit 16 stores the transmission data Dt in the packet Pt using the bit clock CL1. More specifically, the frame generation unit 16 obtains one byte of transmission data Dt from the receive buffer 11 every time the count value of the counter 13 increases by "8" and stores the obtained transmission data Dt in the packet Pt. Until the frame generation unit 16 receives a frame generation instruction from the instruction unit 15, the frame generation unit 16 stores one byte of transmission data Dt in the packet Pt every time the count value of the counter 13 increases by "8".

[0049] Upon receiving a frame generation instruction from the instruction unit 15, the frame generation unit 16 generates status information Sf1 indicating the amount of transmission data Dt stored in the packet Pt. Specifically, the frame generation unit 16 generates status information Sf1 indicating the number of bytes of the transmission data Dt stored in the packet Pt. The frame generation unit 16 then generates a frame Fr1 in which the packet Pt is stored in the payload and the generated status information Sf1 is stored in the header, and accumulates the generated frame Fr1 in the transmission buffer 17. Note that the frame generation unit 16 may store a packet Pt including dummy data in the frame Fr1.

[0050] The transmitter 18 transmits a packet Pt in which transmission data Dt is stored by the frame generator 16 to the receiver 201 at a transmission timing according to the transmission clock CL2. More specifically, the transmitter 18 receives a transmission instruction from the instruction unit 15, obtains one frame Fr1 from the transmission buffer 17, and transmits the obtained frame Fr1 to the receiver 201 via the network 151.

[0051] 3 is a timing chart showing a packet generation process in a transmission device according to the first embodiment of the present disclosure, in which the horizontal axis represents time.

[0052] 3, frame generation unit 16 stores one byte of transmission data Dt in packet Pt every time the count value of counter 13 increases by "8," that is, every one nanosecond. Then, in accordance with a frame generation instruction from instruction unit 15, frame generation unit 16 finishes storing the transmission data Dt in packet Pt at a transmission period Ct1 of 10 nanoseconds and accumulates the packet Pt in transmission buffer 17. Therefore, 10 bytes of transmission data Dt are stored in packet Pt in frame Fr1 transmitted by transmitter 18 to receiving device 201.

[0053] Here, the frequency of the bit clock CL1 generated by the clock recovery unit 12 may deviate from 8000 MHz depending on the actual data rate Rt. Specifically, when the actual data rate Rt is 8.008 Gbps, the frequency of the bit clock CL1 generated by the clock recovery unit 12 is 8008 MHz. Furthermore, the transmission clock CL2 is not synchronized with the bit clock CL1.

[0054] In this case, an average of 10.01 bytes of transmission data Dt is stored in the packets Pt in the frame Fr1 transmitted by the transmitter 18 to the receiving device 201. That is, 99 packets Pt out of 100 packets Pt store 10 bytes of transmission data Dt, and the remaining one packet Pt out of the 100 packets Pt stores 11 bytes of transmission data Dt.

[0055] Therefore, 99 of the 100 frames Fr1 generated by the frame generation unit 16 store status information Sf1 indicating that the data volume of the transmission data Dt is "10 bytes," and the remaining one frame Fr1 of the 100 frames Fr1 stores status information Sf1 indicating that the data volume of the transmission data Dt is "11 bytes."

[0056] (receiving device) 4 is a diagram illustrating a configuration of a receiving device according to the first embodiment of the present disclosure. Referring to FIG. 4, the receiving device 201 includes a receiving unit 21, a signal generating unit 22, a data acquiring unit 23, a clock regenerating unit 24, a transmitting unit 25, and a buffer 26. The signal generating unit 22 is an example of a generating unit. The clock regenerating unit 24 is an example of a regenerating unit. Some or all of the receiving unit 21, the signal generating unit 22, the data acquiring unit 23, the clock regenerating unit 24, and the transmitting unit 25 are realized by, for example, a processing circuit including one or more processors. The buffer 26 is, for example, a FIFO.

[0057] The receiving device 201 recovers the bit clock CL1 based on a pulse signal based on the arrival timing of the packet Pt from the transmitting device 101 and the number of pulses of the bit clock CL1 in the transmission cycle Ct1. For example, the receiving device 201 recovers the bit clock CL1 based on the pulse signal and the amount of transmission data Dt included in the packet Pt. Details of the processing in the receiving device 201 will be described below.

[0058] The receiving unit 21 receives a packet Pt, in which transmission data Dt is stored, from the transmitting device 101 in accordance with the bit clock CL1. More specifically, the receiving unit 21 receives a frame Fr1 from the transmitting device 101 via the network 151. The receiving unit 21 outputs the received frame Fr1 to the signal generating unit 22 and the data acquiring unit 23.

[0059] The signal generating unit 22 generates a pulse signal Sp1 based on the arrival timing of the packet Pt. For example, the signal generating unit 22 generates a 50 MHz pulse signal Sp1 obtained by recovering the transmission clock CL2. More specifically, the signal generating unit 22 detects the end of the frame Fr1 received from the receiving unit 21. The signal generating unit 22 generates a pulse signal Sp1 whose level transitions at the timing when the end of the frame Fr1 is detected, and outputs the pulse signal Sp1 to the clock recovering unit 24.

[0060] The data acquisition unit 23 receives the frame Fr1 from the receiving unit 21 and acquires the packet Pt and the status information Sf1 from the received frame Fr1. The data acquisition unit 23 acquires the transmission data Dt from the acquired packet Pt and stores the data in the buffer 26. For example, if the packet Pt includes dummy data, the data acquisition unit 23 further stores the dummy data in the buffer 26. The data acquisition unit 23 also outputs the acquired status information Sf1 to the clock recovery unit 24.

[0061] The clock recovery unit 24 recovers the bit clock CL1 based on the pulse signal Sp1 generated by the signal generation unit 22 and the amount of transmission data Dt included in the packet Pt received by the reception unit 21.

[0062] 5 is a diagram illustrating a configuration of a clock recovery unit in a receiving device according to a first embodiment of the present disclosure. Referring to FIG. 5, the clock recovery unit 24 includes a PLL circuit 31 and a setting unit 32. The PLL circuit 31 has a phase comparator 31A, a loop filter 31B, a voltage-controlled oscillator 31C, and frequency dividers 31D, 31E, and 31F. The PLL circuit 31 recovers a bit clock CL1. The PLL circuit 31 outputs a bit clock CL3, which is a recovered clock of the bit clock CL1, to the transmitting unit 25.

[0063] The frequency dividers 31D, 31E, and 31F are provided between the output of the voltage-controlled oscillator 31C and the input of the phase comparator 31A. The frequency division number of the frequency divider 31D is set to, for example, "8." The frequency division number of the frequency divider 31F is set to, for example, "2." The frequency division number of the frequency divider 31E is set to a value corresponding to the amount of data of the transmission data Dt included in the packet Pt.

[0064] More specifically, the setting unit 32 sets the frequency division number of the frequency divider 31E to the number of bytes indicated by the status information Sf1 received from the data acquiring unit 23. Specifically, if the amount of data indicated by the status information Sf1 is "10 bytes," the setting unit 32 sets the frequency division number of the frequency divider 31E to "10," and if the amount of data indicated by the status information Sf1 is "11," the setting unit 32 sets the frequency division number of the frequency divider 31E to "11." Every time the setting unit 32 receives the status information Sf1 from the data acquiring unit 23, it sets the frequency division number of the frequency divider 31E to the number of bytes indicated by the status information Sf1.

[0065] Frequency divider 31D divides the output signal of voltage controlled oscillator 31C by eight and outputs the resulting signal to frequency divider 31E. Frequency divider 31E divides the signal received from frequency divider 31D by the division number set by setting unit 32 and outputs the resulting signal to frequency divider 31F. Frequency divider 31F divides the signal received from frequency divider 31E by two and outputs the resulting signal to phase comparator 31A.

[0066] The signal generating unit 22 supplies the pulse signal Sp1 as a reference signal to the phase comparator 31A. The phase comparator 31A compares the phase of the pulse signal Sp1 received from the signal generating unit 22 with the phase of the signal received from the frequency divider 31F, and outputs a phase difference signal indicating the comparison result to the loop filter 31B.

[0067] Loop filter 31B attenuates components of a predetermined frequency or higher among the frequency components of the phase comparison signal received from phase comparator 31A, and outputs the signal as a control voltage for voltage controlled oscillator 31C.

[0068] Voltage controlled oscillator 31C generates a bit clock CL3 which is an oscillation signal having a frequency according to the level of the control voltage received from loop filter 31B, for example, and outputs the generated bit clock CL3 to transmitter 25 and frequency divider 31D.

[0069] 6 is a timing chart showing pulse signals and bit clocks generated in a receiving device according to the first embodiment of the present disclosure, in which the horizontal axis represents time.

[0070] 6, as described above, the signal generating unit 22 generates a pulse signal Sp1 whose level transitions at the timing when the end of the frame Fr1 is detected. Here, since the network 151 is a low-jitter transmission network and the packet Pt has a fixed length, the signal generating unit 22 can generate a 50 MHz pulse signal Sp1 in which the transmission clock CL2 is recovered with high quality.

[0071] The clock recovery unit 24 then sets the division number of the frequency divider 31E in the PLL circuit 31 to the number of bytes indicated by the status information Sf1, thereby generating a bit clock CL3 that is a high-quality recovered version of the bit clock CL1 in the transmitting device 101.

[0072] Referring back to FIG. 4, the transmitter 25 obtains the transmission data Dt bit by bit from the buffer 26 in accordance with the bit clock CL3 received from the clock recovery unit 24, and transmits the obtained transmission data Dt to the data processing device 211.

[0073] [Operation flow] FIG. 7 is a diagram illustrating an example of a transmission sequence of transmission data in the data transmission system according to the first embodiment of the present disclosure.

[0074] Referring to FIG. 7, first, the data generating device 111 transmits a stream of transmission data Dt having a nominal value of a data rate Rt of 8 Gbps to the transmitting device 101 (step S11).

[0075] Next, the transmitting device 101 extracts the bit clock CL1 from the transmission data Dt received from the data generating device 111 (step S12).

[0076] Next, the transmitting device 101 generates a 50 MHz transmission clock CL2 based on a clock output from a high-precision crystal oscillator (not shown) (step S13).

[0077] Next, the transmitting device 101 starts generating a packet Pt. More specifically, every time the count value of the pulses of the bit clock CL1 increases by "8", the transmitting device 101 obtains one byte of transmission data Dt from the receiving buffer 11 and stores it in the packet Pt (step S14).

[0078] Next, the transmitting device 101 generates a frame Fr1 including a packet Pt and status information Sf1 each time it detects a rising edge of the transmitting clock CL2 and each time it detects a falling edge of the transmitting clock CL2, and transmits the generated frame Fr1 to the receiving device 201 via the network 151 (step S15).

[0079] Next, the receiving device 201 generates a pulse signal Sp1 based on the arrival timing of the packet Pt from the transmitting device 101 (step S16).

[0080] Next, the receiving device 201 generates a bit clock CL3 based on the generated pulse signal Sp1 and the status information Sf1 included in the frame Fr1 (step S17).

[0081] Next, the receiving device 201 transmits the transmission data Dt to the data processing device 211 in accordance with the bit clock CL3 (step S18).

[0082] In the transmitting device 101 according to the first embodiment of the present disclosure, the frame generating unit 16 is configured to generate status information Sf1 indicating the number of bytes of transmission data Dt stored in a packet Pt. However, this is not limited to this. The frame generating unit 16 may be configured to generate status information Sf1 indicating the difference between the number of bytes of transmission data Dt stored in a packet Pt during one cycle of the transmission clock CL2 when the data rate Rt is 8 Gbps and the number of bytes of transmission data Dt actually stored in the packet Pt. In other words, the frame generating unit 16 may be configured to generate status information Sf1 indicating the difference between the number of bytes of transmission data Dt actually stored in the packet Pt and 10 bytes. In this case, the setting unit 32 sets the frequency division number of the frequency divider 31E to the sum of the number of bytes indicated by the status information Sf1 and "10."

[0083] Furthermore, in the receiving device 201 according to the first embodiment of the present disclosure, the PLL circuit 31 is configured such that the frequency division number of the frequency divider 31E provided between the voltage-controlled oscillator 31C and the phase comparator 31A is set to a value corresponding to the amount of transmission data Dt included in the packet Pt. However, this is not limiting. The clock recovery unit 24 is not limited to the above-described configuration as long as it can recover the bit clock CL1. Referring again to FIG. 5 , for example, the clock recovery unit 24 may not include the frequency divider 31E, but may instead include a multiplication circuit (not shown) that multiplies the pulse signal Sp1 provided to the phase comparator 31A. The multiplication number of the multiplication circuit is set to a value corresponding to the amount of transmission data Dt included in the packet Pt. That is, if the data amount indicated by the status information Sf1 is "10 bytes," the multiplication number of the multiplication circuit is set to "10." The multiplier circuit then multiplies the 50 MHz pulse signal Sp1 received from signal generator 22 to generate a 500 MHz pulse signal and provides it to phase comparator 31A. Frequency divider 31D divides the output signal of voltage controlled oscillator 31C by eight and outputs the resultant signal to frequency divider 31F. Frequency divider 31F divides the signal received from frequency divider 31D by two and outputs the resultant signal to phase comparator 31A.

[0084] Furthermore, although the transmitting device 101 according to the first embodiment of the present disclosure is configured to receive one stream of transmission data Dt from the data generating device 111, this is not limiting. The transmitting device 101 may be configured to receive multiple streams from the data generating device 111. For example, the transmitting device 101 receives a stream of transmission data DtA, which is the transmission data Dt, a stream of transmission data DtB, which is the transmission data Dt, and a stream of transmission data DtC, which is the transmission data Dt.

[0085] In this case, the transmitting device 101 includes receiving buffers 11A, 11B, and 11C that are receiving buffer 11, clock recovery units 12A, 12B, and 12C that are clock recovery unit 12, and counters 13A, 13B, and 13C that are counter 13. The receiving device 201 also includes clock recovery units 24A, 24B, and 24C that are clock recovery unit 24, transmitting units 25A, 25B, and 25C that are transmitting unit 25, and buffers 26A, 26B, and 26C that are buffer 26.

[0086] In the transmitting device 101, receive buffers 11A, 11B, and 11C store transmit data DtA, DtB, and DtC, respectively. Clock recovery units 12A, 12B, and 12C extract bit clocks CL1A, CL1B, and CL1C, which are bit clocks CL1, from the transmit data DtA, DtB, and DtC, respectively, and output the bit clocks to counters 13A, 13B, and 13C. The counters 13A, 13B, and 13C count pulses of the bit clocks CL1A, CL1B, and CL1C, respectively, and retain the count values. Each time the count value of counter 13A increases by "8," the frame generation unit 16 retrieves one byte of transmit data DtA from the receive buffer 11A and stores it in packet PtA. Each time the count value of counter 13B increases by "8," the frame generation unit 16 retrieves one byte of transmit data DtB from the receive buffer 11B and stores it in packet PtB. Furthermore, every time the count value of the counter 13C is incremented by "8", the frame generation unit 16 obtains one byte of transmission data DtC from the receive buffer 11C and stores it in a packet PtC. Upon receiving a frame generation instruction from the instruction unit 15, the frame generation unit 16 generates a frame Fr1 in which the packets PtA, PtB, and PtC are stored in the payload and the status information Sf1 is stored in the header, and accumulates the generated frame Fr1 in the transmit buffer 17.

[0087] In the receiving device 201, the data acquiring unit 23 acquires packets PtA, PtB, and PtC and status information Sf1 from frame Fr1, acquires transmission data DtA, DtB, and DtC from the acquired packets PtA, PtB, and PtC, and stores them in buffers 26A, 26B, and 26C, respectively. The clock recovering unit 24A generates a bit clock CL3A based on a pulse signal Sp1 and the amount of transmission data DtA included in packet PtA, and outputs the bit clock CL3A to the transmitting unit 25A. The clock recovering unit 24B generates a bit clock CL3B based on the pulse signal Sp1 and the amount of transmission data DtB included in packet PtB, and outputs the bit clock CL3B to the transmitting unit 25B. The clock recovering unit 24C generates a bit clock CL3C based on the pulse signal Sp1 and the amount of transmission data DtC included in packet PtC, and outputs the bit clock CL3C to the transmitting unit 25C. The transmitter 25A obtains transmission data DtA from the buffer 26A in accordance with the bit clock CL3A and transmits it to the data processing device 211. The transmitter 25B obtains transmission data DtB from the buffer 26B in accordance with the bit clock CL3B and transmits it to the data processing device 211. The transmitter 25C obtains transmission data DtC from the buffer 26C in accordance with the bit clock CL3C and transmits it to the data processing device 211.

[0088] Next, other embodiments of the present disclosure will be described with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals and their description will not be repeated.

[0089] <Second embodiment> [Configuration and basic operation] This embodiment relates to a data transmission system 302 that transmits packets Pt each containing a fixed amount of transmission data Dt, as compared with the data transmission system 301 according to the first embodiment. Except for the details described below, the data transmission system 302 is the same as the data transmission system 301 according to the first embodiment.

[0090] 8 is a diagram illustrating a configuration of a data transmission system according to the second embodiment of the present disclosure. Compared to data transmission system 301, data transmission system 302 includes transmitting device 102 instead of transmitting device 101, and includes receiving device 202 instead of receiving device 201.

[0091] (Transmitting device) 9 is a diagram illustrating a configuration of a transmitting device according to the second embodiment of the present disclosure. Compared to transmitting device 101, transmitting device 102 includes clock generating unit 44 instead of clock generating unit 14 and frame generating unit 46 instead of frame generating unit 16.

[0092] The transmitting device 102 transmits packets Pt to the receiving device 202 at transmission timings according to a transmission clock CL2 synchronized with a bit clock CL1, the packets Pt including transmission data Dt whose amount of data corresponds to the relationship between the frequencies of the bit clock CL1 and the transmission clock CL2. That is, the transmission period Ct1 of the packets Pt by the transmitting device 102 is a period based on the transmission clock CL2 synchronized with the bit clock CL1. The processing in the transmitting device 102 will be described in detail below.

[0093] The clock recovery unit 12 extracts a bit clock CL1 from the transmission data Dt transmitted from the data generation unit 111 to the transmission unit 101, and outputs the extracted bit clock CL1 to the counter 13 and the clock generation unit .

[0094] The clock generation unit 44 generates a transmission clock CL2 synchronized with the bit clock CL1 by dividing the frequency of the bit clock CL1 received from the clock recovery unit 12. More specifically, the clock generation unit 44 divides the frequency of the bit clock CL1 by 160 to generate a transmission clock CL2 having a frequency that is 1 / 160 of the frequency of the bit clock CL1. The clock generation unit 44 outputs the generated transmission clock CL2 to the instruction unit 15.

[0095] The instruction unit 15 outputs a frame generation instruction to the frame generation unit 46 and a transmission instruction to the transmission unit 18 every time it detects a rising edge of the transmission clock CL2 received from the clock generation unit 44 and every time it detects a falling edge of the transmission clock CL2.

[0096] The frame generation unit 46 stores the transmission data Dt in the packet Pt using the bit clock CL1. More specifically, the frame generation unit 46 obtains one byte of the transmission data Dt from the receive buffer 11 every time the count value of the counter 13 increases by "8" and stores the obtained transmission data Dt in the packet Pt. The frame generation unit 46 stores one byte of the transmission data Dt in the packet Pt every time the count value of the counter 13 increases by "8" until it receives a frame generation instruction from the instruction unit 15.

[0097] Upon receiving a frame generation instruction from the instruction unit 15, the frame generation unit 46 generates a frame Fr1 in which the packet Pt is stored in the payload without generating the status information Sf1, and stores the generated frame Fr1 in the transmission buffer 17.

[0098] Here, since the frequency of the transmission clock CL2 is 1 / 160 of the frequency of the bit clock CL1, regardless of the actual data rate Rt, a fixed amount of data determined according to the relationship between the frequencies of the bit clock CL1 and the transmission clock CL2, i.e., 10 bytes of transmission data Dt, is stored in every packet Pt generated by the frame generation unit 46. Therefore, the transmitting device 102 does not need to generate and transmit status information Sf1.

[0099] The transmitting unit 18 receives a frame generation instruction from the instruction unit 15, obtains one frame Fr1 from the transmission buffer 17, and transmits the obtained frame Fr1 to the receiving device 202 via the network 151.

[0100] (receiving device) 10 is a diagram illustrating a configuration of a receiving device according to the second embodiment of the present disclosure. Referring to Fig. 10, receiving device 202 includes a clock recovery unit 54 instead of clock recovery unit 24, as compared with receiving device 201.

[0101] The data acquisition unit 23 receives the frame Fr1 from the receiving unit 21 and acquires the packet Pt from the received frame Fr1. The data acquisition unit 23 acquires the transmission data Dt from the acquired packet Pt and stores it in the buffer 26.

[0102] 11 is a diagram illustrating a configuration of a clock recovery unit in a receiving device according to the second embodiment of the present disclosure. Referring to FIG. 11, clock recovery unit 54 does not include setting unit 32, as compared with clock recovery unit 24.

[0103] The frequency division number of the frequency divider 31E is set to a value corresponding to the amount of transmission data Dt included in the packet Pt. More specifically, the frequency division number of the frequency divider 31E is set to the number of bytes of the transmission data Dt included in the packet Pt, i.e., "10."

[0104] Next, other embodiments of the present disclosure will be described with reference to the drawings. In the drawings, the same or corresponding parts are designated by the same reference numerals and their description will not be repeated.

[0105] <Third embodiment> [Configuration and basic operation] This embodiment differs from the data transmission system 301 according to the first embodiment in that it relates to a data transmission system 303 that transmits a predetermined clock packet Pc. Except for the details described below, the data transmission system 303 is the same as the data transmission system 301 according to the first embodiment.

[0106] 12 is a diagram illustrating a configuration of a data transmission system according to the third embodiment of the present disclosure. Compared to data transmission system 301, data transmission system 303 includes a transmitting device 103 instead of transmitting device 101, and a receiving device 203 instead of receiving device 201.

[0107] (Transmitting device) 13 is a diagram illustrating a configuration of a transmitting device according to a third embodiment of the present disclosure. Referring to FIG. 13, transmitting device 103 further includes a reference clock generating unit 61, a related information generating unit 62, a counter 63, an instruction unit 64, a transmission buffer 67, and a transmitting unit 68 compared to transmitting device 101, and includes a frame generating unit 66 instead of frame generating unit 16. Furthermore, transmitting device 103 does not include clock generating unit 14 and instruction unit 15 compared to transmitting device 101. Transmission buffer 67 is, for example, a FIFO. Transmission unit 68 is an example of a first transmitting unit.

[0108] The transmitting device 103 operates in accordance with a predetermined reference clock CL4. The transmitting device 103 transmits a clock packet Pc, which stores predetermined information, to the receiving device 203 at a transmission timing in accordance with a transmission period Ct2 based on the reference clock CL4. For example, the transmitting device 103 further transmits relationship information Sf2 indicating the relationship between the frequency of the reference clock CL4 and the frequency of the bit clock CL1 to the receiving device 203. The processing in the transmitting device 103 will be described in detail below.

[0109] The clock recovery unit 12 extracts a bit clock CL1 from the transmission data Dt transmitted from the data generation device 111 to the transmission device 103, and outputs the extracted bit clock CL1 to the counter 13 and the relationship information generation unit 62.

[0110] The reference clock generating unit 61 generates a reference clock CL4 having a frequency fs. For example, the reference clock generating unit 61 generates the reference clock CL4 having a predetermined frequency based on a clock output from a high-precision crystal oscillator (not shown). The reference clock generating unit 61 outputs the generated reference clock CL4 to the relationship information generating unit 62 and the counter 63.

[0111] Counter 63 counts the pulses of reference clock CL4 received from reference clock generating unit 61 and holds the count value.

[0112] The relationship information generation unit 62 generates relationship information Sf2 indicating the relationship between the frequency of the reference clock CL4 received from the reference clock generation unit 61 and the frequency of the bit clock CL1 received from the clock recovery unit 12, at timing according to a predetermined cycle. The relationship information generation unit 62 may also generate the relationship information Sf2 irregularly. The relationship information generation unit 62 outputs the generated relationship information Sf2 to the frame generation unit 66. Details of the relationship information Sf2 will be described later.

[0113] The frame generation unit 66 receives the relationship information Sf2 from the relationship information generation unit 62 and holds the received relationship information Sf2.

[0114] The instruction unit 64 instructs other units to transmit a clock packet Pc. When the count value of the counter 63 reaches a predetermined value Cnt, the instruction unit 64 resets the count value of the counter 63. Then, the instruction unit 64 outputs a frame generation instruction to the frame generation unit 66 and outputs a transmission instruction to the transmission unit 68. Every time the count value of the counter 63 reaches the predetermined value Cnt, the instruction unit 64 resets the count value and outputs a frame generation instruction and a transmission instruction to the frame generation unit 66 and the transmission unit 68, respectively. That is, the instruction unit 64 outputs a frame generation instruction and a transmission instruction to the frame generation unit 66 and the transmission unit 68, respectively, at a transmission period Ct2 obtained by dividing the predetermined value Cnt by the frequency fs of the reference clock CL4.

[0115] Similar to the frame generation unit 16, the frame generation unit 66 obtains one byte of transmission data Dt from the receive buffer 11 each time the count value of the counter 13 is incremented by "8" and stores the obtained transmission data Dt in a packet Pt. The frame generation unit 66 generates a frame Fr1 in which the packet Pt is stored in the payload and the held relationship information Sf2 is stored in the header, at a timing according to a predetermined period, and stores the generated frame Fr1 in the transmission buffer 17. Note that the frame generation unit 66 may also generate a frame Fr1 and store it in the transmission buffer 17 at irregular intervals.

[0116] Furthermore, the frame generation unit 66 generates a clock packet Pc upon receiving a frame generation instruction from the instruction unit 64. For example, the frame generation unit 66 generates a clock packet Pc that includes a predetermined UDP port number. After generating the clock packet Pc, the frame generation unit 66 generates a frame Fr2 in which the clock packet Pc is stored in the payload, and stores the generated frame Fr2 in the transmission buffer 67.

[0117] The transmitting unit 18 acquires one frame Fr1 from the transmission buffer 17 at a timing according to a predetermined cycle, and transmits the acquired frame Fr1 to the receiving device 203 via the network 151. Note that the transmitting unit 18 may transmit the frame Fr1 to the receiving device 203 at irregular intervals.

[0118] The transmitter 68 transmits the clock packet Pc to the receiver 203 at a transmission timing according to the reference clock CL4. More specifically, upon receiving a transmission instruction from the instruction unit 64, the transmitter 68 obtains one frame Fr2 from the transmission buffer 67 and transmits the obtained frame Fr2 to the receiver 203 via the network 151.

[0119] (receiving device) 14 is a diagram illustrating a configuration of a receiving device according to the third embodiment of the present disclosure. Compared to receiving device 201, receiving device 203 further includes a reference clock recovery unit 75, a signal generation unit 72 instead of signal generation unit 22, a data acquisition unit 73 instead of data acquisition unit 23, and a clock recovery unit 74 instead of clock recovery unit 24.

[0120] The receiving device 203 recovers the reference clock CL4 based on the pulse signal Sp2 based on the arrival timing of the clock packet Pc from the transmitting device 103 and the number of pulses of the reference clock CL4 in the transmission cycle Ct2. For example, the receiving device 203 further recovers the bit clock CL1 based on the recovered reference clock CL4 and relationship information Sf2 received from the transmitting device 103. The processing in the receiving device 203 will be described in detail below.

[0121] The receiving unit 21 receives the frames Fr1 and Fr2 from the transmitting device 103 via the network 151. The receiving unit 21 outputs the received frames Fr1 and Fr2 to the signal generating unit 72 and the data acquiring unit 73.

[0122] The signal generator 72 generates a pulse signal Sp2 based on the arrival timing of the clock packet Pc. More specifically, the signal generator 72 detects the end of frame Fr2 in which the clock packet Pc is stored by referencing the UDP port numbers of the packets in frames Fr1 and Fr2. The signal generator 72 generates a pulse signal Sp2 whose level transitions at the timing when the end of frame Fr2 is detected, and outputs the pulse signal Sp2 to the reference clock recovery unit 75.

[0123] The reference clock recovery unit 75 recovers the reference clock CL4 based on the pulse signal Sp2 received from the signal generation unit 72. The reference clock recovery unit 75 outputs to the clock recovery unit 74 a reference clock CL5 which is a recovered clock of the reference clock CL4.

[0124] 15 is a diagram illustrating a configuration of a reference clock recovery unit in a receiving device according to the third embodiment of the present disclosure. Referring to FIG. 15, reference clock recovery unit 75 includes a PLL circuit 33. PLL circuit 33 has a phase comparator 33A, a loop filter 33B, a voltage-controlled oscillator 33C, and frequency dividers 33D and 33E.

[0125] The division number of the frequency divider 33D is set to the number of pulses of the reference clock CL4 in the transmission period Ct2, i.e., "Cnt." The division number of the frequency divider 33E is set to "2." The frequency divider 33D outputs a signal obtained by dividing the output signal of the voltage-controlled oscillator 33C by Cnt to the frequency divider 33E. The frequency divider 33E outputs a signal obtained by dividing the output signal of the frequency divider 33D by 2 to the phase comparator 33A.

[0126] Phase comparator 33A compares the phase of pulse signal Sp2 received from signal generating unit 72 with the phase of the signal received from frequency divider 33E, and outputs a phase difference signal indicating the comparison result to loop filter 33B.

[0127] Loop filter 33B attenuates components of a predetermined frequency or higher among the frequency components of the phase comparison signal received from phase comparator 33A, and outputs the signal as a control voltage for voltage controlled oscillator 33C.

[0128] Voltage controlled oscillator 33C generates reference clock CL5, which is an oscillation signal having a frequency according to the level of the control voltage received from loop filter 33B, for example, and outputs the generated reference clock CL5 to clock recovery unit 74 and frequency divider 33D.

[0129] 16 is a timing chart showing pulse signals and bit clocks generated in a receiving device according to the third embodiment of the present disclosure, in which the horizontal axis represents time.

[0130] 16, as described above, the signal generation unit 72 generates a pulse signal Sp2 whose level transitions at the timing when the end of frame Fr2 is detected. Here, the network 151 is a low-jitter transmission network, and a clock packet Pc is repeatedly transmitted from the transmitting device 103 every time the count value of pulses of the reference clock CL4 reaches a predetermined value Cnt. Therefore, the reference clock recovery unit 75 can use the pulse signal Sp2 generated by the signal generation unit 72 to generate a reference clock CL5 that is a high-quality recovered version of the reference clock CL4.

[0131] 14 , the data acquisition unit 73 receives a frame Fr1 from the receiving unit 21 and acquires a packet Pt and related information Sf2 from the received frame Fr1. The data acquisition unit 73 acquires transmission data Dt from the acquired packet Pt and stores the data in the buffer 26. The data acquisition unit 73 also outputs the acquired packet Pt and related information Sf2 to the clock recovery unit 74. If packet length information Sf3, which will be described later, is included in the frame Fr1, the data acquisition unit 73 further acquires the packet length information Sf3 and outputs the packet length information Sf3 to the clock recovery unit 74.

[0132] The clock recovery unit 74 recovers the bit clock CL1 based on the reference clock CL5 generated by the reference clock recovery unit 75 based on the pulse signal Sp2 and on the relationship information Sf2 received from the data acquisition unit 73. The clock recovery unit 74 outputs the bit clock CL3, which is a recovered clock of the bit clock CL1, to the transmission unit 25.

[0133] The transmitter 25 obtains the transmission data Dt bit by bit from the buffer 26 in accordance with the bit clock CL3 received from the clock recovery unit 74, and transmits the obtained transmission data Dt to the data processing device 211.

[0134] (Example 1 of relationship information Sf2) 17 is a diagram illustrating an example of a relationship information generation unit in a transmission device according to the third embodiment of the present disclosure. Referring to FIG. 17, relationship information generation unit 62A, which is part of relationship information generation unit 62, includes a frequency divider 81A, a counter 81B, a frequency divider 81C, and a generation unit 81D. Relationship information generation unit 62A generates relationship information Sf2 indicating a comparison result between the frequency of reference clock CL4 and the frequency of bit clock CL1.

[0135] The frequency division number of the frequency divider 81A is set to, for example, "10." The frequency division number of the frequency divider 81C is set to, for example, "fs / (1 mega)."

[0136] The frequency divider 81A receives a bit clock CL1 of approximately 8000 MHz from the clock recovery unit 12, and divides the received bit clock CL1 by 10 to generate a measurement clock Cm1 of approximately 800 MHz, which is output to the counter 81B.

[0137] The counter 81B counts the pulses of the measurement clock Cm1 received from the frequency divider 81A and holds the count value.

[0138] The frequency divider 81C receives a reference clock CL4 of frequency fs from the reference clock generating unit 61, and divides the received reference clock CL4 by (fs / 1 MHz) to generate a 1 MHz measured clock Cm2 and output it to the generating unit 81D.

[0139] The generation unit 81D references the count value of the counter 81B to obtain a measurement value Δc1 of the number of pulses of the measurement clock Cm1 in one cycle of the measurement target clock Cm2 received from the frequency divider 81C. Here, the measurement value Δc1 is "800" if the frequency of the bit clock CL1 is 8000 MHz, and is "799" if the frequency of the bit clock CL1 is, for example, 7990 MHz. The generation unit 81D generates relationship information Sf2 indicating the measurement value Δc1 and outputs the generated relationship information Sf2 to the frame generation unit 66.

[0140] 18 is a diagram illustrating a configuration of a clock recovery unit in a receiving device according to a third embodiment of the present disclosure. Referring to FIG. 18, clock recovery unit 74A, which is clock recovery unit 74, includes PLL circuit 34, setting unit 35, frequency divider 36A, and pulse conversion unit 36B. PLL circuit 34 has phase comparator 34A, loop filter 34B, voltage-controlled oscillator 34C, and frequency dividers 34D and 34E.

[0141] The frequency division number of the frequency divider 36A is set to, for example, "fs / (1 MHz)." The frequency division number of the frequency divider 34D in the PLL circuit 34 is set to, for example, "10" when the transmission data Dt is transmitted in 10-bit units in accordance with the DisplayPort (registered trademark) standard.

[0142] The division number of the frequency divider 34E in the PLL circuit 34 is set to a value corresponding to the relationship between the frequency of the reference clock CL4 and the frequency of the bit clock CL1. More specifically, the setting unit 35 sets the division number of the frequency divider 34E to the measured value Δc1 indicated by the relationship information Sf2 received from the data acquiring unit 73. Every time the setting unit 35 receives the relationship information Sf2 from the data acquiring unit 73, it sets the division number of the frequency divider 34E to the measured value Δc1 indicated by the relationship information Sf2.

[0143] The frequency divider 34D divides the output signal of the voltage-controlled oscillator 34C by 10, and outputs the resultant signal to the frequency divider 34E. The frequency divider 34E divides the output signal of the frequency divider 34D by the division number set by the setting unit 35, and outputs the resultant signal to the phase comparator 34A.

[0144] Frequency divider 36A receives reference clock CL5 of frequency fs from reference clock regeneration unit 75, and divides the received reference clock CL5 by (fs / 1 MHz) to generate a 1 MHz clock signal and output it to pulse conversion unit 36B. Pulse conversion unit 36B generates a reference signal, which is a 1 MHz pulse signal, based on the clock signal received from frequency divider 36A and outputs it to phase comparator 34A.

[0145] Phase comparator 34A compares the phase of the reference signal received from pulse conversion unit 36B with the phase of the signal received from frequency divider 34E, and outputs a phase difference signal indicating the comparison result to loop filter 34B.

[0146] Loop filter 34B attenuates components of a predetermined frequency or higher among the frequency components of the phase comparison signal received from phase comparator 34A, and outputs the signal as a control voltage for voltage controlled oscillator 34C.

[0147] Voltage controlled oscillator 34C generates a bit clock CL3 that is an oscillation signal having a frequency according to the level of the control voltage received from loop filter 34B, for example, and outputs generated bit clock CL3 to transmitter 25 and frequency divider 34D.

[0148] (Specific example 2 of relationship information Sf2) 19 is a diagram illustrating an example of a relationship information generation unit in a transmission device according to the third embodiment of the present disclosure. Referring to FIG. 19, relationship information generation unit 62B, which is part of relationship information generation unit 62, includes a frequency divider 82A, a counter 82B, a frequency divider 82C, and a generation unit 82D. Relationship information generation unit 62B generates relationship information Sf2 indicating a comparison result between the frequency of reference clock CL4 and the frequency of bit clock CL1.

[0149] The frequency division number of the frequency divider 82A is set to, for example, "8000." The frequency division number of the frequency divider 82C is set to, for example, "fs / (900 megabits)."

[0150] The frequency divider 82C receives the reference clock CL4 of frequency fs from the reference clock generating unit 61, and divides the received reference clock CL4 by (fs / 900 MHz) to generate a measurement clock Cm1 of 900 MHz and outputs it to the counter 82B.

[0151] The counter 82B counts the pulses of the measurement clock Cm1 received from the frequency divider 82C and holds the count value.

[0152] The frequency divider 82A receives a bit clock CL1 of approximately 8000 MHz from the clock recovery unit 12, divides the received bit clock CL1 by 8000, and generates a clock Cm2 to be measured of approximately 1 MHz, which is output to the generation unit 82D.

[0153] The generation unit 82D references the count value of the counter 82B to obtain a measurement value Δc2 of the number of pulses of the measurement clock Cm1 in one cycle of the measurement target clock Cm2 received from the frequency divider 82A. Here, when the frequency of the bit clock CL1 is 8000 MHz, the measurement value Δc2 is "900." The generation unit 82D generates relationship information Sf2 indicating the measurement value Δc2 and outputs the generated relationship information Sf2 to the frame generation unit 66.

[0154] 20 is a diagram showing a configuration of a clock recovery unit in a receiving device according to a third embodiment of the present disclosure. Referring to FIG. 20, clock recovery unit 74B, which is part of clock recovery unit 74, includes PLL circuit 37, setting unit 38, down counter 39, and frequency dividers 40A and 40B. PLL circuit 37 includes phase comparator 37A, loop filter 37B, voltage-controlled oscillator 37C, and frequency dividers 37D and 37E.

[0155] The frequency division number of frequency divider 40A is set to, for example, "fs / (900 MHz)". The frequency division number of frequency divider 40B is set to, for example, "2". The frequency division number of frequency divider 37D in PLL circuit 37 is set to, for example, "8000". The frequency division number of frequency divider 37E in PLL circuit 37 is set to, for example, "2".

[0156] The preset value of the down counter 39 is set to a value corresponding to the relationship between the frequency of the reference clock CL4 and the frequency of the bit clock CL1. More specifically, the setting unit 38 sets the count value of the down counter 39 to the measured value Δc2 indicated by the relationship information Sf2 received from the data acquiring unit 73. Every time the setting unit 38 receives relationship information Sf2 from the data acquiring unit 73, it sets the count value of the down counter 39 to the measured value Δc2 indicated by the relationship information Sf2.

[0157] The frequency divider 37D divides the output signal of the voltage controlled oscillator 37C by 8000, and outputs the resultant signal to the frequency divider 37E. The frequency divider 37E divides the output signal of the frequency divider 37D by 2, and outputs the resultant signal to the phase comparator 37A.

[0158] The frequency divider 40A receives the reference clock CL5 of frequency fs from the reference clock recovery unit 75, and divides the received reference clock CL5 by (fs / 900 MHz) to generate a 900 MHz signal and outputs it to the down counter 39.

[0159] Down counter 39 decrements its count by 1 each time it detects a pulse in the signal received from frequency divider 40A, and resets it to the measured value Δc2 when the count reaches zero. Down counter 39 outputs a 1 MHz borrow signal that goes high every time the count reaches zero to frequency divider 40B.

[0160] Frequency divider 40B receives a 1 MHz borrow signal from down counter 39 and divides the frequency of the received borrow signal by two to generate a 500 kHz reference signal with a duty ratio of 50%, which is output to phase comparator 37A.

[0161] Phase comparator 37A compares the phase of the reference signal received from frequency divider 40B with the phase of the signal received from frequency divider 37E, and outputs a phase difference signal indicative of the comparison result to loop filter 37B.

[0162] Loop filter 37B attenuates components of a predetermined frequency or higher among the frequency components of the phase comparison signal received from phase comparator 37A, and outputs the signal as a control voltage for voltage controlled oscillator 37C.

[0163] Voltage controlled oscillator 37C generates a bit clock CL3 which is an oscillation signal having a frequency according to the level of the control voltage received from loop filter 37B, for example, and outputs the generated bit clock CL3 to transmitter 25 and frequency divider 37D.

[0164] (Example 3 of relationship information Sf2) 21 is a diagram illustrating an example of a relationship information generation unit in a transmission device according to the third embodiment of the present disclosure. Referring to FIG. 21, relationship information generation unit 62C, which is part of relationship information generation unit 62, includes a counter 83B and a generation unit 83D. Relationship information generation unit 62C generates relationship information Sf2 indicating the number of pulses of reference clock CL4 during the time required to collect transmission data Dt to be stored in packet Pt from receive buffer 11.

[0165] Counter 83B receives reference clock CL4 having frequency fs from reference clock generating unit 61. Counter 83B counts pulses of reference clock CL4 and holds the count value.

[0166] The generation unit 83D monitors the frame generation unit 66 to obtain the number of bytes of the transmission data Dt stored in the packet Pt by the frame generation unit 66. The generation unit 83D also references the count value of the counter 83B to obtain a measured value Δc3 of the number of pulses of the reference clock CL4 during the period from when the frame generation unit 66 starts storing the transmission data Dt in the packet Pt to when the frame generation unit 66 finishes storing the transmission data Dt in the packet Pt. The generation unit 83D generates packet length information Sf3 indicating the number of bytes of the transmission data Dt stored in the packet Pt and relationship information Sf2 indicating the measured value Δc3, and outputs the generated packet length information Sf3 and relationship information Sf2 to the frame generation unit 66.

[0167] 22 is a diagram illustrating a configuration of a clock recovery unit in a receiving device according to a third embodiment of the present disclosure. Referring to FIG. 22, a clock recovery unit 74C, which is the clock recovery unit 74, includes setting units 90A and 90B, a measurement value FIFO 91, a data FIFO 92, a readout unit 93, latch units 94A and 94B, an up-counter 95, a comparator 96, a loop filter 97, a voltage-controlled oscillator 98, a frequency divider 99, and a down-counter 100. The readout unit 93 may be shared with the transmitting unit 25. The data FIFO 92 may be shared with the buffer 26.

[0168] The clock recovery unit 74C generates a bit clock CL3 based on the result of comparing the number of pulses of the reference clock CL4 during the time required for the transmitting device 103 to store the transmission data Dt in the packet Pt with the number of pulses of the reference clock CL5 during the time required for the receiving device 203 to read the transmission data Dt from the reading unit 93.

[0169] More specifically, the setting unit 90A receives a packet Pt from the data acquiring unit 73 and stores the transmission data Dt included in the received packet Pt in the data FIFO 92. The setting unit 90A assigns a predetermined identifier Id to the first byte of the transmission data Dt in the packet Pt.

[0170] Furthermore, the setting unit 90A receives the relationship information Sf2 from the data acquiring unit 73 and stores the measured value Δc3 indicated by the received relationship information Sf2 in the measured value FIFO 91.

[0171] The frequency divider 99 receives the bit clock CL3 from the voltage controlled oscillator 98, divides the frequency of the received bit clock CL3 by eight to generate a byte clock CL6, and outputs the byte clock CL6 to the readout unit 93 and the down counter 100.

[0172] The read unit 93 receives a byte clock CL6 from the frequency divider 99, and each time it detects a pulse of the byte clock CL6, it reads one byte of transmission data Dt from the data FIFO 92. If the read transmission data Dt has an identifier Id assigned to it, the read unit 93 resets the count value of the up-counter 95 to zero, outputs a latch instruction to the latch unit 94A, and outputs a set instruction to the setting unit 90B.

[0173] The up-counter 95 receives the reference clock CL5 from the reference clock recovery unit 75. The up-counter 95 counts pulses of the reference clock CL5 and holds the count value.

[0174] When receiving a latch instruction from the reading unit 93, the latch unit 94A acquires and holds the measurement value Δc3 from the measurement value FIFO 91. The measurement value Δc3 latched by the latch unit 94A corresponds to the number of pulses of the reference clock CL4 in the time required for the transmitting device 103 to collect, from the receiving buffer 11, the transmission data Dt to be stored in the packet Pt.

[0175] The setting unit 90B receives packet length information Sf3 from the data acquiring unit 73. When the setting unit 90B receives a set instruction from the reading unit 93, it sets the preset value of the down counter 100 to the number of bytes indicated by the received packet length information Sf3. That is, the setting unit 90B sets the count value of the down counter 100 to the number of bytes of the transmission data Dt included in the packet Pt.

[0176] The down counter 100 receives the byte clock CL6 from the frequency divider 99. Each time the down counter 100 detects a pulse of the byte clock CL6, it decrements the count value by "1." When the count value reaches zero, the down counter 100 outputs a latch instruction to the latch unit 94B.

[0177] When receiving a latch instruction from the down counter 100, the latch unit 94B acquires and holds the count value of the up counter 95. The count value latched by the latch unit 94B corresponds to the number of pulses of the reference clock CL5 during the time required for the receiving device 203 to read the transmission data Dt included in the packet Pt from the read unit 93.

[0178] The comparator 96 compares the measurement value Δc3 latched by the latch section 94A with the count value latched by the latch section 94B, and outputs to the loop filter 97 a count comparison signal indicating the comparison result.

[0179] Loop filter 97 attenuates components of a predetermined frequency or higher out of the frequency components of the count comparison signal received from comparator 96 and outputs the signal as a control voltage for voltage controlled oscillator 98 .

[0180] Voltage controlled oscillator 98 generates a bit clock CL3 which is an oscillation signal having a frequency corresponding to the level of the control voltage received from loop filter 97, for example, and outputs generated bit clock CL3 to transmitter 25 and frequency divider 99.

[0181] [Operation flow] FIG. 23 is a diagram illustrating an example of a transmission sequence of transmission data in a data transmission system according to the third embodiment of the present disclosure.

[0182] Referring to FIG. 23, first, the data generating device 111 transmits a stream of transmission data Dt having a nominal value of a data rate Rt of 8 Gbps to the transmitting device 103 (step S21).

[0183] Next, the transmitting device 103 extracts the bit clock CL1 from the transmission data Dt received from the data generating device 111 (step S22).

[0184] Next, the transmitting device 103 generates a 50 MHz transmission clock CL2 based on a clock output from a high-precision crystal oscillator (not shown) (step S23).

[0185] Next, the transmitting device 103 generates a reference clock CL4 based on a clock output from a high-precision crystal oscillator (not shown) (step S24).

[0186] Next, the transmitting device 103 starts generating a packet Pt. For example, every time the count value of the pulses of the bit clock CL1 increases by "8", the transmitting device 103 obtains one byte of transmission data Dt from the receiving buffer 11 and stores it in the packet Pt (step S25).

[0187] Next, the transmitting device 103 generates related information Sf2 each time it detects a rising edge of the transmitting clock CL2 and each time it detects a falling edge of the transmitting clock CL2, generates a frame Fr1 including the packet Pt and the related information Sf2, and transmits the generated frame Fr1 to the receiving device 203 via the network 151 (step S26).

[0188] Furthermore, every time the count value of the pulses of the reference clock CL4 reaches a predetermined value Cnt, the transmitting device 103 resets the count value and transmits a frame Fr2 including a clock packet Pc to the receiving device 203 via the network 151 (step S27).

[0189] Next, the receiving device 203 generates a pulse signal Sp2 based on the arrival timing of the clock packet Pc from the transmitting device 103, and generates a reference clock CL5 based on the pulse signal Sp2 (step S28).

[0190] Next, the receiving device 203 generates a bit clock CL3 based on the reference clock CL5 and the relationship information Sf2 (step S29).

[0191] Next, the receiving device 203 transmits the transmission data Dt to the data processing device 211 in accordance with the bit clock CL3 (step S30).

[0192] In the transmitting device 103 according to the third embodiment of the present disclosure, the frame generating unit 66 is configured to obtain one byte of transmission data Dt from the receiving buffer 11 and store the obtained transmission data Dt in a packet Pt, similar to the frame generating unit 16, each time the count value of the counter 13 increases by "8." However, this is not limited to this. If the transmitting device 103 includes the relationship information generating unit 62A or 62B, the frame generating unit 66 may be configured to obtain a predetermined amount of data, for example, 10 bytes of transmission data Dt, from the receiving buffer 11 in a lump and store the data in a packet Pt without using the count value of the counter 13. In other words, if the transmitting device 103 includes the relationship information generating unit 62A or 62B, the frame generating unit 66 may be configured to store the transmission data Dt in a packet Pt without using the bit clock CL1.

[0193] Furthermore, in the transmitting device 103 according to the third embodiment of the present disclosure, the frame generating unit 66 is configured to store the relationship information Sf2 in the header of the frame Fr1, but this is not limiting. The frame generating unit 66 may also be configured to store the relationship information Sf2 in a frame other than the frame Fr1.

[0194] Furthermore, although the transmitting device 103 according to the third embodiment of the present disclosure is configured to transmit the relationship information Sf2 to the receiving device 203, this is not limiting. The transmitting device 103 may be configured not to transmit the relationship information Sf2. In this case, the receiving device 203 does not recover the bit clock CL1.

[0195] The above-described embodiments should be considered to be illustrative in all respects and not restrictive. The scope of the present invention is defined by the claims, not by the above description, and is intended to include all modifications within the meaning and scope of the claims.

[0196] Each process (each function) in the above-described embodiments is realized by a processing circuit including one or more processors. The processing circuit may be configured as an integrated circuit or the like that combines one or more memories, various analog circuits, and various digital circuits in addition to the one or more processors. The one or more memories store programs (instructions) that cause the one or more processors to execute each of the processes. The one or more processors may execute each of the processes according to the program read from the one or more memories, or according to a logic circuit pre-designed to execute each of the processes. The processor may be various processors suitable for computer control, such as a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a field programmable gate array (FPGA), and an application-specific integrated circuit (ASIC). Note that the physically separate processors may cooperate with each other to execute each of the processes. For example, the processors mounted on a plurality of physically separated computers may cooperate with each other to execute the above processes via a network such as a LAN (Local Area Network), a WAN (Wide Area Network), the Internet, etc. The program may be installed into the memory from an external server device or the like via the network, or may be distributed in a state stored on a recording medium such as a CD-ROM (Compact Disc Read Only Memory), a DVD-ROM (Digital Versatile Disc Read Only Memory), or a semiconductor memory, and installed into the memory from the recording medium.

[0197] The above description includes the following additional features. [Appendix 1] a transmitting device that transmits transmission data at a predetermined data rate; a receiving device that receives the transmission data from the transmitting device, the transmitting device operates according to a reference clock; the transmitting device transmits a packet to the receiving device at a transmission timing according to a transmission period; the receiving device recovers the data clock based on a pulse signal based on the arrival timing of the packet from the transmitting device and the number of pulses of the reference clock in the transmission period; the reference clock is a data clock corresponding to the data rate, the packet is a data packet in which the transmission data is stored, A data transmission system in which the transmitting device transmits the data packet to the receiving device at a transmission timing according to a transmission clock generated by dividing the data clock, the data packet including the transmission data with a data amount corresponding to the relationship between the frequency of the data clock and the frequency of the transmission clock. [Explanation of symbols]

[0198] 11 Receive Buffer 12 Clock recovery section 13 Counter 14,44 Clock generation unit 15 Instruction section 16,46,66 frame generation unit 17 Send Buffer 18 Transmitter 21 Receiving unit 22,72 Signal generation unit 23,73 Data acquisition section 24, 54, 74, 74A, 74B, 74C Clock recovery section 25 Transmitter 26 buffers 31,33,34,37 PLL circuit 31A,33A,34A,37A Phase comparator 31B, 33B, 34B, 37B Loop filters 31C, 33C, 34C, 37C Voltage Controlled Oscillators 31D,33D,34D,37D frequency divider 31E,33E,34E,37E Frequency divider 31F frequency divider 32, 35, 38 Setting section 36A frequency divider 36B Pulse conversion unit 39 Down Counter 40A frequency divider 40B frequency divider 61 Reference clock generation unit 62, 62A, 62B, 62C Relationship information generation unit 63 Counter 64 Instruction section 67 Send Buffer 68 Transmitter 75 Reference clock recovery section 81A,82A frequency divider 81B, 82B, 83B counters 81C,82C frequency divider 81D,82D,83D generation part 90A Setting section 90B Setting section 91 Measurement Value FIFO 92 Data FIFOs 93 Readout section 94A Latch 94B Latch part 95 Up Counter 96 Comparator 97 Loop Filter 98 Voltage Controlled Oscillator 99 frequency divider 100 Down Counter 101, 102, 103 Transmitting device 111 Data generation device 151 Network 201, 202, 203 receiving device 211 Data processing device 301, 302, 303 Data Transmission Systems Pt Packet PC watch packet Fr1, Fr2 frames

Claims

1. a transmitting device that transmits transmission data at a predetermined data rate; a receiving device that receives the transmission data from the transmitting device, the transmitting device operates according to a reference clock; the transmitting device transmits a packet to the receiving device at a transmission timing according to a transmission period; The receiving device regenerates the reference clock based on a pulse signal based on the arrival timing of the packet from the transmitting device and the number of pulses of the reference clock in the transmission period.

2. the receiving device includes a PLL circuit that regenerates the reference clock, and the pulse signal is applied as a reference signal to a phase comparator in the PLL circuit; 2. The data transmission system according to claim 1, wherein a frequency division number of a frequency divider between the output of a voltage-controlled oscillator and the input of said phase comparator in said PLL circuit is set to a value corresponding to said number of pulses.

3. the reference clock is a data clock corresponding to the data rate, the packet is a data packet in which the transmission data is stored, the transmitting device transmits, at the transmission timing, the data packet in which the transmission data is stored using the data clock, the data packet in which the transmission data amount corresponding to the number of pulses is stored, to the receiving device; 3. The data transmission system according to claim 1, wherein the receiving device recovers the data clock based on a pulse signal based on the arrival timing of the data packet from the transmitting device and the amount of transmission data contained in the data packet.

4. 4. The data transmission system according to claim 3, wherein the transmitting device further transmits to the receiving device information indicating the amount of the transmission data contained in the data packet.

5. the transmission cycle is a cycle based on a transmission clock synchronized with the data clock, 4. The data transmission system according to claim 3, wherein the transmitting device transmits to the receiving device the data packet including the transmission data with a fixed amount of data according to the relationship between the frequency of the data clock and the frequency of the transmission clock.

6. the packet is a clock packet in which predetermined information is stored, the transmission period is a period based on the reference clock, the transmitting device transmits the clock packet to the receiving device at the transmission timing; the transmitting device transmits to the receiving device relationship information indicating a relationship between a frequency of the reference clock and a frequency of a data clock corresponding to the data rate; 3. The data transmission system according to claim 1, wherein the receiving device regenerates the reference clock based on a pulse signal based on the arrival timing of the clock packet from the transmitting device and the number of pulses.

7. the transmitting device transmits to the receiving device relationship information indicating a relationship between a frequency of the reference clock and a frequency of a data clock corresponding to the data rate; 7. The data transmission system according to claim 6, wherein the receiving device regenerates the data clock based on the regenerated reference clock and the related information received from the transmitting device.

8. A transmitting device that operates in accordance with a reference clock and transmits transmission data at a predetermined data rate to a receiving device, a generating unit that generates packets; a transmitting unit that transmits the packet generated by the generating unit to the receiving device at a transmission timing according to a transmission period.

9. A receiving device that receives transmission data from a transmitting device that operates according to a reference clock, a receiving unit that receives packets transmitted from the transmitting device at a transmission timing according to a transmission period; a generator for generating a pulse signal based on the arrival timing of the packet; a regenerator that regenerates the reference clock based on the pulse signal generated by the generator and the number of pulses of the reference clock in the transmission period.

10. A data transmission method including a transmitting device that transmits transmission data at a predetermined data rate and a receiving device that receives the transmission data from the transmitting device, the transmitting device operates according to a reference clock; a step of transmitting a packet from the transmitting device to the receiving device at a transmission timing according to a transmission period; A data transmission method comprising the step of the receiving device recovering the reference clock based on a pulse signal based on the arrival timing of the packet from the transmitting device and the number of pulses of the reference clock in the transmission period.

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