Techniques for multi-step current profiles for phase change memory

Abstract

To provide a multi-step current profile for a phase change memory implemented as part of a SET algorithm.SOLUTION: In the logic flow 804, the change from the amorphous state to the crystalline state includes a nucleation stage to create a crystalline seed and a crystal growth stage after the nucleation stage to promote crystal growth to set the crystalline state and the memory cell to a SET logical state, wherein the nucleation stage includes applying at least one second current for a second period of time after applying a first current for a first period of time, and wherein the crystal growth stage includes applying at least one third current and a fourth current for a third period of time and a fourth period of time, respectively.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The examples described herein generally relate to techniques for multi-step current profiles for phase change memories implemented as part of a SET algorithm. [Background technology]

[0002] Memory resources have myriad applications in electronic devices and other computing environments. The continued creation of smaller, more energy-efficient memory devices to provide these resources has led to scaling issues for traditional memory devices based on using electronic charge to store and access data. Phase change materials (PCMs) are based on the property of certain compounds to adopt one of two or more states based on the application of heat to the material. In some examples, PCMs include chalcogenide materials that can exhibit at least two states: a structured crystalline state and a disordered amorphous state. These two states typically depend on the characteristics of the application of heat to the chalcogenide material. PCMs offer potential advantages for use in memory because they are nonvolatile and potentially scalable to relatively small memory cells because data storage and access are based on the structure / state of the material rather than the maintenance of electronic charge. [Brief explanation of the drawings]

[0003] [Figure 1] 1 illustrates an exemplary first system.

[0004] [Figure 2] 1 illustrates an exemplary second system.

[0005] [Figure 3] 1 illustrates a third exemplary system.

[0006] [Figure 4] An exemplary representation is shown.

[0007] [Figure 5] 1 shows an exemplary first current profile.

[0008] [Figure 6] 10 shows an exemplary second current profile.

[0009] [Figure 7] 1 shows an exemplary block diagram of the device.

[0010] [Figure 8] An example of a logic flow is shown below.

[0011] [Figure 9] 1 shows an example of a storage medium.

[0012] [Figure 10] 1 illustrates an exemplary computing platform. DETAILED DESCRIPTION OF THE INVENTION

[0013] Historically, the access performance of memories based on memory cell structures containing PCM has been inferior to that of established memory technologies with memory cell structures arranged to maintain electronic charge. While read latency has improved in recent years to be comparable to these other established memory technologies, write latency remains incomparable. The write latency of PCM is primarily limited by the SET algorithm, which involves a first current pulse to crystallize, or SET, the PCM contained in the memory cell from its RESET or amorphous state. Some SET algorithms may use fixed ramp rates for either a ramp-down method (which initially heats the material to an amorphous state and then attempts to change it to a crystalline state through controlled cooling) or a ramp-up method (which attempts to promote crystallization through controlled temperature increases). These methods for the SET algorithm attempt to ensure that the memory cell experiences an optimal SET temperature to minimize SET latency / duration, which typically results in reduced write latency.

[0014] In some examples, both the ramp-up and ramp-down methods of the SET algorithm work well for memory cells containing unconstrained PCM, but are ineffective for cells containing fully amorphized PCM. In these examples, unconstrained PCM refers to PCM that is not fully amorphized in the RESET state and therefore may contain crystalline nuclei or crystalline regions. Therefore, the ramp-up / ramp-down SET algorithm method may only include a crystal growth step to convert amorphous regions to a crystalline state based on pre-existing crystalline nuclei. However, scaling PCM-based memories with reduced cost and power consumption requires smaller memory cell sizes. Because we have observed that the degree to which a cell becomes fully amorphized correlates with the thickness of the PCM and / or the area of ​​the memory cell, scaling PCM-based memories to smaller geometries results in memory cells that may not be efficiently SET by the ramp-up / ramp-down SET algorithm. Therefore, the ramp-up / ramp-down SET algorithm may require constrained memory cells to grow crystals, and scaling to smaller geometries increases SET latency / duration because the number of crystalline nuclei or the amount of crystalline regions in the PCM contained in these smaller memory cells decreases. The PCM contained in these smaller memory cells may not properly transition to a crystalline state if there are insufficient crystalline nuclei or insufficient crystalline regions to promote subsequent crystal growth. Thus, ramp-up / ramp-down SET algorithms may result in unacceptably long SET latencies / durations, adversely affecting write latency and / or resulting in memory cells that are not effectively SET. The lack of a valid SET state may result in a high bit error rate (BER) for data maintained in or accessed from these smaller memory cells.

[0015] According to some newer approaches to SET algorithms, memory cells containing PCM can be SET using a multi-stage SET algorithm. In these newer methods, logic in the memory device (e.g., in a controller) can heat the PCM contained in the memory cell to a first temperature for a first period of time. The first temperature can be adjusted to promote nucleation of a crystalline state in the PCM. The logic can then raise the PCM temperature to a second temperature for a second period of time. The second temperature can be adjusted to promote crystal growth within the PCM. Nucleation and crystal growth can SET the PCM to a crystalline state. As a result, this exemplary multi-stage SET algorithm includes a two-stage temperature ramp-up, resulting in separate nucleation and growth stages. These types of two-stage, multi-stage SET algorithms can work well when the time allotted at low temperatures is relatively long. However, these newer methods may limit latency reduction because increasingly smaller memory cells contain smaller amounts of PCM and require longer times in the nucleation stage to produce a sufficient amount of crystalline nuclei to produce a valid SET state following the growth stage.

[0016] In some instances, if the nucleation stage is not long enough to result in the formation of a sufficient amount of small crystal nuclei, the second, higher temperature of the growth stage may result in a PCM temperature that is too high during the growth stage. Thus, the combination of insufficient time for the nucleation state and high temperatures during the subsequent growth stage may result in unstable, small crystal nuclei. Unstable, small crystal nuclei may result in memory cells in which the PCM is not effectively SET. In the absence of a valid SET state, the use of two-stage or multi-stage SET algorithms may result in a high bit error rate (BER) for data maintained in or accessed from these smaller memory cells.

[0017] According to some examples, as described in more detail below, an improved SET algorithm may include a multi-step current profile for a crystallization SET process having two distinct stages: a nucleation stage for generating crystal nuclei, and a crystal growth stage for promoting crystal growth from those nuclei generated during the nucleation stage. The nucleation rate, which is typically a stochastic process and occurs at a much slower rate, peaks at lower temperatures compared to the crystal growth temperature, which typically is orders of magnitude faster than the crystal growth peak at higher temperatures. As used herein, a SET algorithm including a multi-step current profile may refer to an algorithm or procedure in which different, discrete temperature levels or temperature ramps are applied (e.g., through controlled application of current and / or light) for a period of time before the temperature level is changed. Thus, in one example, each time a temperature level exceeds a threshold level can be considered a different stage of the SET algorithm. The multi-step application of temperature or heat to a PCM included in a memory cell may result in isothermal conditions that result in different material state changes (nucleation and / or crystal growth).

[0018] In some examples, logic in a memory device having memory cells including a PCM may apply different amounts of current to the PCM to heat the PCM according to a multi-stage current profile, causing the application of different temperature levels through Joule heating. It will be appreciated that the specific value of the current used for Joule heating may vary depending on the type of material used in the PCM and / or based on the relative location of the memory cell within the memory array of the memory device. As described herein, the improved SET algorithm includes a nucleation stage at a lower temperature level to generate crystal nuclei, followed by multiple stages at higher temperature levels to complete crystal growth. With respect to Joule heating through the application of current, the improved SET algorithm may be implemented via lower amplitude current pulses to initiate the crystallization process through the generation of crystal nuclei, followed by current pulses of increasing amplitude to complete the crystallization process and accelerate crystal growth.

[0019] References to memory devices are applicable to different memory types. Memory devices generally refer to volatile memory technologies. Volatile memory is memory whose state (and therefore the data stored therein) is indeterminate when power is removed from the device. Nonvolatile memory is memory whose state is determinate even when power is removed from the device. Dynamic volatile memory requires the data stored in the device to be refreshed to maintain its state. An example of dynamic volatile memory includes dynamic random access memory (DRAM) or some variants such as synchronous DRAM (SDRAM). The memory subsystems described herein may be compatible with a variety of memory technologies. Various memory technologies include DDR3 (Double Data Rate Version 3, JESD79-3, first published by JEDEC (Semiconductor Engineering Association) on June 27, 2007), DDR4 (DDR Version 4, JESD79-4, first published by JEDEC in September 2012), LPDDR3 (Low Power DDR Version 3, JESD209-3B, first published by JEDEC in August 2013), LPDDR4 (Low Power DDR Version 4, JESD209-4, first published by JEDEC in August 2014), WIO2 (Wide I / O 2 (WideIO2), JESD229-2, first published by JEDEC in August 2014), HBM (High Bandwidth Memory DRAM, JESD235, first published by JEDEC in October 2013), LPDDR5 (LPDDR5, first published by JEDEC in February 2019), HBM2 (HBM Version 2, first published by JEDEC in December 2018), DDR5 (DDR Version 5, currently under discussion by JEDEC), combinations of memory technologies, and technologies based on derivatives or extensions of these specifications.

[0020] In addition to or instead of volatile memory, in some examples, references to memory devices may refer to nonvolatile memory devices whose state is determined even when power is removed. Nonvolatile memory devices may include nonvolatile memory. Non-limiting examples of nonvolatile memory may include any one or combination of planar or 3D NAND flash memory or NOR flash memory, 3D cross-point memory, memory devices using chalcogenide phase change materials (e.g., chalcogenide glass), byte-addressable nonvolatile memory devices, ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, polymer memory (e.g., ferroelectric polymer memory), ferroelectric transistor random access memory (Fe-TRAM), ovonic memory, nanowire memory, electrically erasable programmable read-only memory (EEPROM), resistive RAM, various other types of nonvolatile random access memory (RAM), and / or magnetic storage memory.

[0021] FIG. 1 illustrates an exemplary system 100. In some examples, as shown in FIG. 1, system 100 includes a substrate 120 on which a PCM 110 is disposed. In some examples, substrate 120 can be a semiconductor substrate on which a semiconductor PCM is processed as a memory cell. In these examples, substrate 120 can be a plastic or other material on which a chalcogenide glass or other PCM is disposed as a storage medium. As shown in FIG. 1, PCM 110 can have a thickness 114. Thickness 114 can enable memory cell size to be reduced for higher density bit arrays or memory cell arrays.

[0022] According to some examples, due to thickness 114, PCM 110 can be a fully amorphized material in the RESET logic state. Reference to a “fully” amorphized material does not necessarily mean that all bits of the PCM deposited or otherwise processed on substrate 120 are amorphous in the RESET logic state. Rather, a fully amorphized material can refer to all active regions in the PCM being amorphized, as shown by region 112 in FIG. 1 . Region 112 may or may not completely include all phase change material in PCM 110 (as shown by the shaded / patterned region not extending all the way to the corners). Rather, region 112 can be fully amorphized in that it does not contain enough nuclei to promote crystal growth without first seeding the crystal growth. System 100 and other figures herein are not necessarily drawn to scale. The amount of crystal nuclei required to promote growth may vary from PCM to PCM. Generally, crystal growth occurs much faster than nucleation and at significantly higher temperatures. The crystalline state or SET logic state of PCM 110 may be highly ordered and have a relatively low resistance and a relatively high reflectivity compared to the amorphous state or RESET logic state of PCM 110. Thus, the logic state of PCM 110 can be read by calculating the resistance of the PCM or by the refractive index of light. Thus, PCM 110 may be, for example, a PRAM or PCM or optical rotating disk, or other memory.

[0023] In some examples, the heat source 130 may represent a heat source for the PCM 110. The PCM 110 may be integrated on an integrated circuit (I / C). The heat source 130 may include terminals or resistive elements adjacent to memory cells or other components of the I / C that may generate heat when current is applied to the terminals or resistive elements. In some examples, the heat source 130 may be a light source (e.g., a laser) that optically generates heat. In some respects, in certain circuit applications, resistive elements adjacent to memory cells may be optical circuits because they generate more light and more heat as more current is conducted through the resistive elements. Thus, in some examples, the heat source 130 may be integrated adjacent to the PCM 110 and may be local to the PCM 110. In other examples, the heat source 130 may be remote from the PCM 110 and include a laser or other electromagnetic wave source that is transmitted at various intensities on the PCM 110, causing the PCM 110 to heat up.

[0024] According to some examples, set control logic 140 may represent circuitry configured to control the operation of heat source 130. Set control logic 140 may be integrated on a common I / C with PCM 110. For example, set control logic 140 may be integrated on a common substrate 120 with PCM 110. Set control logic 140 may control heat source 130 to heat PCM 110 in multiple distinct stages to first promote nucleation and then promote crystal growth from the generated crystal nuclei. In some examples, set control logic 140 may separate the nucleation and / or growth stages into multiple stages as part of implementing a SET algorithm to transition PCM 110 to the SET logic state.

[0025] FIG. 2 illustrates an exemplary system 200. The system 200 illustrated in FIG. 2 may represent a block diagram of a system that applies a multi-stage phase change set procedure using a current-based heat source. The system 200 may be an example of the system 100 of FIG. 1. In some examples, the system 200 may represent a component of a memory subsystem having a phase change random access memory (PRAM) 220 to store and provide data in response to operations of a processor 210. In these examples, the system 200 may receive memory access requests from a host or processor 210, which may be processing logic that performs operations based on data stored in the PRAM 220 or generates data to store in the PRAM 220. The processor 210 may be or include a host processor, a central processing unit (CPU), a microcontroller or microprocessor, a graphics processor, a peripheral processor, an application-specific processor, or other processor, whether as a single-core processor or a multi-core processor.

[0026] According to some examples, as shown in FIG. 2 , system 200 includes memory controller 230, which represents logic that interfaces with PRAM 220 and manages access to data stored in the memory. In some examples, memory controller 230 may be integrated within processor 210. In other examples, memory controller 230 may be standalone hardware separate from processor 210. In other examples, memory controller 230 may be a separate circuit on a substrate that includes processor 210. In other examples, memory controller 230 may be a separate die or chip integrated on a common substrate with another die that includes processor 210 (e.g., as part of a system on a chip (SoC)). In some examples, at least a portion of PRAM 220 may be included on an SoC with memory controller 230 and / or processor 210.

[0027] In some examples, the memory controller 230 may include read / write logic 234, which includes hardware for interfacing with the PRAM 220. The read / write logic 234 may enable the memory controller 230 to generate read and write commands to process data access requests generated by the execution of instructions by the processor 210. In some examples, as shown in FIG. 2, the memory controller 230 includes a scheduler 232 for scheduling the transmission of access commands to the PRAM 220 based on known timing parameters for read and write accesses to the PRAM 220. The known timing parameters may be preprogrammed or otherwise preset within the system 200, for example. Such parameters may be stored in the PRAM 220 and accessed by the memory controller 230. At least some of the parameters may be determined by a synchronization procedure. The timing parameters may also include timing related to the write latency of the PRAM 220. The write latency of PRAM 220 may be determined by PRAM 220's ability to change the logic state of bits held in PCM memory cells contained in the memory array, for example, by changing the PCM contained in these memory cells from an amorphous RESET logic state (e.g., bit=0) to a crystalline SET logic state (e.g., bit=1) according to any embodiment described herein.

[0028] According to some examples, memory resources or memory arrays or cache lines included in PRAM 220 may be represented by PCM memory cells 226. In these examples, PCM memory cells 226 include PCM, and the PCM for a given one of PCM memory cells 226 is fully amorphized in the RESET logic state. PRAM 220 includes interface logic 224 for controlling access to PCM memory cells 226. Interface logic 224 may include decode logic for addressing a particular row, column, or bit of data stored in PCM memory cells 226. In some examples, interface logic 224 may control the amount of current provided to a particular one of PCM memory cells 226. Accordingly, control of writing to PCM memory cells 226 may be via drivers and / or other access circuitry included in or coupled to interface logic 224.

[0029] In some examples, controller 222 of PRAM 220 may be an on-die controller for controlling the internal operations of PRAM 220 so that PRAM 220 executes commands received from memory controller 230. For example, controller 222 may control timing, addressing, I / O (input / output) margining, scheduling, or error correction of PRAM 220.

[0030] According to some examples, controller 222 may be configured to write data to PCM memory cells 226 according to any of the examples involving separate nucleation and growth stages described herein. In these examples, controller 222 may control operation of interface 224 to supply or pass current to memory cells of PCM memory cells 226 selected to have data written to them. For example, the selected memory cells may be heated in stages to write data to the selected memory cells.

[0031] In some examples, the system 200 includes a power supply 240, as shown in FIG. 2. The power supply 240 can be a voltage source or regulator that provides power to the PRAM 220. The controller 222 and / or the interface logic 224 can use power available from the power supply 240 to heat selected ones of the PCM memory cells 226 to write data. Heating the selected memory cells includes placing the selected memory cells in a crystalline state (SET logic state) according to any example described herein. The controller 222 and the interface logic 224 can be viewed as control circuitry that heats the PCM memory cells 226 to a first temperature for a first period of time, as controlled by the controller 222. The first temperature and first period of time are provided to promote nucleation of the crystalline state of the PCM memory cells 226. The controller 222 can then cause the interface logic 224 to conduct more current, thereby increasing the temperature of the PCM memory cells 226 from the first temperature to subsequent higher temperatures corresponding to multiple steps having respective periods of time. Multiple stages with subsequent higher temperatures and respective durations to promote crystalline growth of the PCM contained in selected memory cells of PCM memory cells 226 to set the PCM to a crystalline state. Controller 222 and interface logic 224 may pass current through selected memory cells of PCM memory cells 226 to heat the PCM contained in the selected memory cells, in addition to potentially passing current through other interface hardware.

[0032] FIG. 3 illustrates an exemplary system 300. In some examples, system 300 may represent a block diagram of a system for applying a multi-step current profile to a phase-change memory SET process that utilizes a light-based heat source. System 300 may be an example of system 100 described above and shown in FIG. 1. In some examples, system 300 shown in FIG. 3 includes memory 320 having PCM memory cells 322 for storing and providing stored data in response to operation of processor 310. Processor 310 may be any processor such as those described above for processor 210 of system 200. Processor 310 may perform operations based on data stored in memory 320 or generate data to store in memory 320.

[0033] 3, system 300 also includes control logic 330 for controlling writing to memory 320. In some examples, control logic 330 is or is part of a memory controller. In some examples, control logic 330 may be integrated with processor 310, integrated on the same substrate as processor 310, or integrated with processor 310 as part of an SoC. In some examples, control logic 330 may control access to memory 320 via laser 340, for example, when memory 320 is being optically written.

[0034] According to some examples, as shown in FIG. 3 , system 300 includes laser 340. In these examples, laser 340 may be capable of optically heating selected ones of PCM memory cells 322. Power from power source 350 may be used to control the intensity (energy per unit area) of light generated by laser 340. For example, based on controlling the intensity of laser 340, control logic 330 may write to selected ones of PCM memory cells 332 according to any example described herein involving separate nucleation and growth stages. Thus, control logic 330 may control laser 340 to irradiate selected ones of PCM memory cells 322 to write data to memory 320 according to any example described herein, including causing the PCM included in the selected memory cell to enter a crystalline state.

[0035] In some examples, the control logic 330 and the laser 340 can be considered a control circuit that heats a selected one of the PCM memory cells 322 to a first temperature for a first period of time under control of the control logic 330. The first temperature and the first period of time promote nucleation of a crystalline state of the PCM contained in the selected one of the PCM memory cells 322. The control logic 330 can then cause the laser 340 to increase the light intensity through a multi-step process to raise the temperature of the selected memory cell from the first temperature to subsequent higher temperatures corresponding to multiple steps having respective durations. A second temperature and a second period of time can promote crystal growth in the PCM memory cell 322 to set the PCM to a crystalline state. To set the PCM to a crystalline state, multiple steps having subsequent higher temperatures and respective durations are used to promote crystal growth of the PCM contained in the selected one of the PCM memory cells 322.

[0036] FIG. 4 illustrates an exemplary representation 400. In some examples, as shown in FIG. 4, representation 400 includes diagram 410 and diagram 430. In these examples, diagrams 410 and 430 provide a basis for separating the heating of the PCM into stages to transition the PCM in selected memory cells to a crystalline state. For example, diagram 410 shows probability density 414 plotted against temperature 412. Diagram 410 includes two curves: curve 422, which shows the probability density of nucleation with temperature change, and curve 424, which shows the probability density of crystal growth with temperature change.

[0037] As previously mentioned, some conventional methods for heating a PCM contained in a memory cell to transition the PCM to a crystalline state as part of a SET algorithm assume that crystalline nuclei are already present in the PCM. Therefore, the SET algorithm initially focuses on crystal growth, ramping the temperature through multiple stages to attempt to reduce the time required to reach an acceptable amount of crystal growth (e.g., maximum crystal growth) by applying an increasing temperature range. As shown in diagram 410, it can be observed that the maximum efficiency of nucleation can be achieved somewhere in the 400°C range for the particular PCM tested to generate diagram 410, while the maximum efficiency of growth occurs somewhere near the 500°C range for that particular PCM. It can also be observed that there is an overlap within the 400-500°C range, which allows both nucleation and growth to occur, but at a much lower efficiency and with a longer time required to set the crystalline state. It will be appreciated that various PCMs may have different temperatures and temperature ranges. For example, another PCM tested may be expected to achieve nucleation somewhere in the range of 250° C., with maximum growth occurring somewhere above 300° C. Thus, this example is merely illustrative and not limiting. Other materials for PCMs with other temperature ranges may also be used according to any example multi-step SET process or procedure described herein.

[0038] 4, diagram 430 shows similar information as diagram 410, but on a logarithmic scale. Thus, in one embodiment, diagram 430 shows log(P) 434, the logarithm of probability density 414, versus temperature 432. Curve 442 shows nucleation occurring most efficiently around the 400° C. range, while curve 444 shows growth occurring most efficiently around the 500° C. range. It can therefore be appreciated that performing a set to a crystalline state can be beneficial due to the improved efficiency achieved by separating the nucleation and growth stages as part of a multi-stage SET process.

[0039] FIG. 5 illustrates an exemplary current profile 500. In some examples, current profile 500 may be a graphical representation of an example multi-step current profile for a crystal growth stage of a crystallization SET process having two distinct stages, shown in FIG. 5 as nucleation 510 and growth 520. In these examples, nucleation 510 may represent a nucleation stage for generating crystal nuclei, and growth 520 may represent a crystal growth stage for promoting crystal growth from the nuclei generated during nucleation 510. Current profile 500 may be an example multi-step current profile diagram of an algorithm or procedure in which distinct and separate temperature levels are applied for a period of time as the process progresses through nucleation stage 510 and growth stage 520, before changing or stepping up to a higher temperature level. Current profile 500 may represent a current profile established or tested to complete a crystallization SET process in a particular PCM structure for a memory architecture or configuration. It will be appreciated that the basic concepts of multi-step current profiles such as those shown in FIG. 5 for current profile 500 are expected to remain the same, although different memory architectures and / or different PCM structures may establish variations compared to the values ​​shown.

[0040] According to some examples, the multiple stages of current profile 500 can be viewed in contrast to conventional SET algorithms, which either melt a crystal and then quench it to allow crystal growth, or sequentially ramp up the current and temperature in a single stage to achieve crystallization, or result in a pulse with a relatively long (e.g., 8-10 times longer) nucleation stage compared to the growth stage. Current profile 500 can be understood as having four distinct stages: initialization 530, nucleation 510, growth 520, and finalization 540.

[0041] In some examples, the current profile 500 begins with an initiating pulse of current at A, which may initially melt the PCM contained in the selected memory cell. The current spike at A may be minimized to the minimum amount of current required to amorphize the PCM, thereby allowing the PCM to cool to a lower temperature more quickly and initiate the nucleation stage. For example, the current pulse at A may be limited to less than 150 microamperes (μA) for approximately 0.1 nanoseconds (ns), allowing the current to dissipate and PCM cooling to occur at B. In this example, the time from the initiating pulse to the start of nucleation (i.e., the time of initialization 530) is expected to be less than 30 ns.

[0042] According to some examples, as shown in FIG. 5, nucleation 510 begins at C, which involves application of a current of approximately 20-30 μA. This 20-30 μA application can occur for approximately 65 ns. In these examples, this 20-30 μA can raise the temperature of the PCM contained in the selected memory cell to a minimum temperature that promotes the formation of crystal nuclei in the PCM. Nucleation 510 then continues at D, where a first step increase in current is performed to approximately 30-40 μA for approximately 35 ns. The first step increase at D can raise the temperature of the PCM to capture the remaining bits in the nucleation distribution and begin to promote crystal growth. Growth 520 then begins at E, where a second step increase in current is performed to approximately 40-50 μA for approximately 35 ns, allowing the PCM to reach an intermediate temperature to enhance crystal growth of the low growth current bits. Growth 520 then continues to F where there is a third step increase in current to about 50-70 μA for about 35 ns. The third step increase at F is the highest temperature, allowing the PCM to further enhance crystal growth and placing the PCM in the SET logic state.

[0043] In some examples, as shown in FIG. 5 , the current profile 500 at G includes a ramp-down of the current during a finalization phase 540 to reach H. In these examples, the current is ramped down to about 20-30 μA and maintained for less than about 30 ns. The finalization phase 540 may include a controlled ramp-down or step-down with a hold at the SET reverse current. It may be appreciated that certain regions of the PCM included in the selected memory cell may be disturbed during the growth 520 and melt back to an amorphous state. The finalization phase 540 may provide a short period of low temperature control to allow the PCM to anneal and “heal” any disturbances in the grown crystal that may result from any overheating in portions of the PCM’s crystalline structure.

[0044] FIG. 6 illustrates an exemplary current profile 600. In some examples, current profile 600 may be a graphical representation similar to current profile 500 illustrated in FIG. 5. For example, current profile 600 may also be a multi-step current profile for the crystal growth stage of a crystallization-SET process, having two distinct stages illustrated in FIG. 6 as nucleation 610 and growth 620. Current profile 600 illustrated in FIG. 6 differs from current profile 500 in that, rather than holding the temperature constant for a period of time to move the PCM from the nucleation stage to the growth stage, a relatively slow ramp of current may be applied to selected memory cells, allowing for a relatively slow sweep from a low temperature to a high temperature. Also, as discussed above for current profile 500, current profile 600 may represent different current profiles established or tested to complete the crystallization-SET process with a particular PCM structure of a memory architecture or configuration. While the basic concepts of the combination of ramp and multi-step current profiles illustrated in FIG. 6 for current profile 600 are expected to remain the same, it will be understood that different memory architectures and / or different PCM structures may establish variations compared to the illustrated values.

[0045] According to some examples, the combination of ramps and multiple current steps in current profile 600 can be viewed in contrast to conventional SET algorithms, which either melt a crystal and then quench it to allow crystal growth, or sequentially ramp up the current and temperature in a single step to achieve crystallization, or result in a pulse with a substantially longer nucleation phase compared to the growth phase (e.g., about 8-10 times longer). Current profile 600 can be understood as having four distinct phases: initialization 630, nucleation 610, growth 620, and finalization 640.

[0046] In some examples, the current profile 600 begins with an initiating pulse of current at A, which initially melts the PCM contained in the selected memory cell. As shown in Figure 6, the current pulse at A may be limited to less than 150 μA for approximately 0.1 ns, allowing the current to dissipate and PCM cooling to occur at B. In this example, the time from the initiating pulse to the start of nucleation (i.e., the time for initialization 630) is expected to be less than 30 ns.

[0047] According to some examples, as shown in FIG. 6 , nucleation 610 begins at C, which includes application of a current of approximately 20-30 μA. This 20-30 μA application can occur for approximately 65 ns. In these examples, this 20-30 μA can raise the temperature of the PCM contained in the selected memory cell to a minimum temperature that promotes the formation of crystalline nuclei in the PCM. Nucleation 610 then continues for a first portion D, which includes a linear ramp that steadily sweeps from 20-30 μA to approximately 40-50 μA over approximately 35 ns to complete nucleation 610. The linear ramp of current for the first portion D can linearly increase the temperature of the PCM to capture the remaining bits of the nucleation distribution and begin to promote crystal growth. Growth 620 then begins with a second portion D, which includes a further ramp of current to a high current of about 70 μA for about 35 ns, steadily raising the PCM to a maximum temperature and continuing to enhance crystal growth of the low growth current bits. Growth 620 then continues to E, which includes maintaining the high current of about 70 μA for about 35 ns to further enhance crystal growth and allow the PCM to enter the SET logic state.

[0048] In some examples, as shown in FIG. 6 , the current profile 600 at F includes a ramp-down of the current during finalization 640 to reach F. In these examples, the current may be ramped to 20-30 μA in less than about 30 ns and then maintained. Finalization 640 may include a controlled ramp-down or step-down with a hold at the SET reverse current. It may be appreciated that certain regions of the PCM included in the selected memory cell may be disturbed during growth 620, melting and returning to an amorphous state. Finalization 640 may provide a short period of low temperature control to allow the PCM to anneal and “recover” any disturbances in the grown crystal that may result from any overheating in portions of the PCM’s crystalline structure.

[0049] Figure 7 shows an example block diagram of an apparatus 700. Although the apparatus 700 shown in Figure 7 has a limited number of elements in a particular topology, it can be understood that the apparatus 700 can include several elements in alternative topologies as desired for a given implementation.

[0050] The device 700 may be supported by circuitry 720, which may be a controller maintained in a memory device or may be a controller with a memory system coupled to a memory array of a memory device via an interface 703, which may also be used to access memory cells (e.g., via read or write operations). The memory device may be coupled to or included in a host computing platform. The circuitry 720 may be configured to execute one or more software- or firmware-implemented logics, components, or modules 722-a (e.g., implemented at least in part by a controller in the memory device). It is worth noting that, as used herein, "a," "b," and "c" and similar designators are intended to be variables representing any positive integer. Thus, for example, if an implementation sets a value of a=3, then the complete set of software or firmware corresponding to the logic, components, or modules 722-a may include logic 722-1, 722-2, or 722-3. Additionally, at least a portion of the "logic" may be software / firmware stored on a computer-readable medium or may be at least partially implemented in hardware; although the logic is shown as separate boxes in FIG. 7, this does not limit the logic to being stored in separate computer-readable media components (e.g., separate memories, etc.) or implemented by separate hardware components (e.g., separate application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs)).

[0051] According to some examples, circuitry 720 may include a processor or processor circuitry, which may be any of a variety of commercially available processors, including, but not limited to, AMD® Athlon®, Duron®, and Opteron® processors, ARM® application, embedded, and secure processors, IBM® and Motorola® DragonBall® and PowerPC® processors, IBM and Sony® Cell processors, Intel® Atom®, Celeron®, Core(2) Duo®, Core i3, Core i5, Core i7, Itanium®, Pentium®, Xeon®, XeonPhi®, and XScale® processors, and the like. According to some examples, circuitry 720 may also include one or more ASICs or FPGAs, and in some examples, at least some of logic 722-a may be implemented as hardware elements of these ASICs or FPGAs.

[0052] According to some examples, device 700 may include selection logic 722-1. Selection logic 722-1 may be logic and / or functionality performed by circuitry 720 that selects a memory cell from among the memory cells of the memory array to implement a SET write operation via interface 703. In these examples, the memory cell includes a phase change material that changes resistivity based on being in a crystalline or amorphous state, where the phase change material has a constrained structure, is fully amorphized in all active regions in the amorphous state, and lacks sufficient crystalline nuclei to promote crystal growth. In these examples, selection logic 722-1 may select the memory cell in response to a write request included in write request 710. For example, write request 710 may be sent from a host CPU or processor (e.g., processor 210 or processor 310) and may cause selection of the memory for the SET write operation. Selection information 730 may also be routed from interface 703 and may include address information used to select the memory cell for the write operation.

[0053] In some examples, the device 700 may also include SET logic 722-2. The SET logic 722-2 may be logic and / or functionality performed by the circuitry 720 that applies currents to terminals of the memory cell to control a change in a phase change material included in the memory cell from an amorphous state to a crystalline state, the change from the amorphous state to a crystalline state including a nucleation stage that creates crystal seeds and a crystal growth stage that follows the nucleation stage and promotes crystal growth to set the crystalline state and place the memory cell in the SET logic state. In these examples, the nucleation stage may include applying a first current for a first period followed by applying at least one second current for a second period, and the crystal growth stage includes applying at least one third current and a fourth current for a third period and a fourth period, respectively. The SET logic 722-2 may route current information 740 through the interface 703 to indicate the respective currents and corresponding periods and cause the currents to be applied to the terminals of the memory cell.

[0054] This specification includes a set of logic flows that represent example methodologies for implementing novel aspects of the disclosed architecture. For ease of explanation, one or more methodologies presented herein are shown and described as a series of operations; however, those skilled in the art will understand and appreciate that the methodologies are not limited by the order of those operations. Some operations may accordingly occur in a different order than and / or concurrently with other operations shown and described herein. For example, those skilled in the art will understand and appreciate that a methodology could alternatively be represented as a series of interrelated states or events, such as in a state diagram. Furthermore, not all operations shown in a methodology are necessarily required for a novel implementation.

[0055] The logic flows may be implemented in software, firmware, and / or hardware. In software and firmware embodiments, the logic flows may be implemented by computer-executable instructions stored on at least one non-transitory computer-readable or machine-readable medium, such as an optical, magnetic, or semiconductor storage device. The embodiments are not limited in this context.

[0056] 8 illustrates an example of a logic flow 800. The logic flow 800 may represent some or all of the operations performed by one or more logic, functions, or devices described herein, such as the apparatus 700. More specifically, the logic flow 800 may be implemented by one or more of the selection logic 722-1 or the SET logic 722-2.

[0057] According to some examples, logic flow 800 can implement a SET write operation at block 802 by selecting a memory cell in a memory array that includes a phase change material that changes resistivity based on being in a crystalline or amorphous state, where the phase change material has a constrained structure, is fully amorphized in all active areas in the amorphous state, and lacks sufficient crystalline nuclei to promote crystal growth. In these examples, the memory cell can be selected by selection logic 722-1.

[0058] In some examples, logic flow 800 can, at block 804, apply a current to a terminal of the memory cell to control a change of a phase change material in the memory cell from an amorphous state to a crystalline state, the change from the amorphous state to the crystalline state including a nucleation stage to create crystal seeds and a crystal growth stage after the nucleation stage to promote crystal growth to set the crystalline state and place the memory cell in a SET logic state, the nucleation stage including applying a first current for a first period followed by applying at least one second current for a second period, and the crystal growth stage including applying at least one third current and a fourth current for a third period and a fourth period, respectively. In these examples, the current can be applied to the terminal by SET logic 722-2.

[0059] FIG. 9 illustrates an example of a storage medium 900. The storage medium 900 may include an article of manufacture. In some examples, the storage medium 900 may include any non-transitory computer-readable or machine-readable medium, such as an optical, magnetic, or semiconductor storage device. The storage medium 900 may store various types of computer-executable instructions, such as instructions for implementing the logic flow 800. Examples of computer-readable or machine-readable storage media may include any tangible medium capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or rewritable memory, etc. Examples of computer-executable instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, etc. These examples are not limiting in this context.

[0060] 10 illustrates an exemplary computing platform 1000. In some examples, as shown in FIG. 10, computing platform 1000 may include a memory system 1030, a processing component 1040, other platform components 1050, or a communication interface 1060. According to some examples, computing platform 1000 may be implemented in a computing device.

[0061] According to some examples, memory system 1030 may include a controller 1032 and a memory device 1034. In these examples, logic and / or functionality resident or located in controller 1032 may perform at least some of the processing operations or logic of apparatus 700 and may include storage media, including storage medium 900. Memory device 1034 may also include non-volatile memory (not shown) of the same type as described above for systems 100, 200, or 300 shown in FIGS. 1-3. In some examples, controller 1032 may be part of the same die as memory device 1034. In other examples, controller 1032 and memory device 1034 may be located on the same die, or may be located on the same substrate or die with a processor (e.g., included in processing component 1040). In still other examples, controller 1032 may be in a separate die or integrated circuit coupled with memory device 1034.

[0062] According to some examples, processing component 1040 may include various hardware elements, software elements, or a combination of both. Examples of hardware elements may include devices, logic devices, components, processors, microprocessors, circuits, processor circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, programmable logic devices (PLDs), digital signal processors (DSPs), FPGAs / programmable logic, memory units, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. Examples of software elements may include software components, programs, applications, computer programs, application programs, system programs, software development programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. The decision whether an example is implemented using hardware and / or software elements may vary according to any number of factors, such as desired computational speed, power level, thermal tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus speed, and other design or performance constraints, as desired for a given example.

[0063] In some examples, other platform components 1050 may include common computing elements such as one or more processors, multi-core processors, co-processors, memory units, chipsets, controllers, peripherals, interfaces, oscillators, timing devices, video cards, audio cards, multimedia I / O components (such as digital displays), power supplies, etc. Examples of memory units associated with either other platform components 1050 or memory system 1030 may include, but are not limited to, various types of computer-readable and machine-readable storage media in the form of one or more faster memory units such as read-only memory (ROM), RAM, DRAM, DDR DRAM, synchronous DRAM (SDRAM), DDR SDRAM, SRAM, programmable ROM (PROM), EPROM, EEPROM, flash memory, ferroelectric memory, polymer memory such as SONOS memory, ferroelectric polymer memory, nanowires, FeTRAM or FeRAM, ovonic memory, phase-change memory, memristors, STT-MRAM, magnetic or optical cards, or other types of storage media suitable for storing information.

[0064] In some examples, communication interface 1060 may include logic and / or functionality to support a communication interface. In these examples, communication interface 1060 may include one or more communication interfaces operating according to various communication protocols or standards for communicating directly or over a network communication link. Direct communication may occur over the direct interface through the use of a communication protocol or standard described in one or more industry standards (including successors and variations), such as those associated with the SMBus specification, PCIe specification, NVMe specification, SATA specification, SAS specification, or USB specification. Network communication may occur over the network interface through the use of a communication protocol or standard such as those described in one or more Ethernet standards promulgated by the IEEE. For example, one such Ethernet standard may include “IEEE 802.3-2018, Carrier sense Multiple access with Collision Detection (CSMA / CD) Access Method and Physical Layer Specifications” (the “IEEE 802.3-2018 specification”), published in August 2018.

[0065] Computing platform 1000 may be part of a computing device, which may be, for example, a user equipment, a computer, a personal computer (PC), a desktop computer, a laptop computer, a notebook computer, a netbook computer, a tablet, a smartphone, an embedded electronic device, a game console, a server, a server array or server farm, a web server, a network server, an internet server, a workstation, a minicomputer, a mainframe computer, a supercomputer, a network appliance, a web appliance, a distributed computing system, a multiprocessor system, a processor-based system, or a combination thereof. Accordingly, functionality and / or specific configurations of computing platform 1000 described herein may be included or omitted in various embodiments of computing platform 1000, as appropriately desired.

[0066] The components and functionality of computing platform 1000 may be implemented using any combination of discrete circuitry, ASICs, logic gates, and / or single-chip architectures. Additionally, the functionality of computing platform 1000 may be implemented using microcontrollers, programmable logic arrays, and / or microprocessors, or any combination of the foregoing, where appropriate. Note that hardware, firmware, and / or software elements may be collectively or individually referred to herein as "logic," "circuitry," or "circuitry."

[0067] Although not shown, any system may include and use a power source such as, but not limited to, a battery, an AC-DC converter for receiving at least AC and providing DC, a renewable energy source (e.g., solar power or motion-based power), etc.

[0068] One or more aspects of at least one example may be implemented by representative instructions, stored on at least one machine-readable medium, representing various logic within a processor, which, when read by a machine, computing device, or system, cause the machine, computing device, or system to create logic that performs the techniques described herein. Such representations may be stored on tangible machine-readable media and supplied to various customers or manufacturing facilities to be loaded into manufacturing machines that actually produce the logic or processor.

[0069] Various examples may be implemented using hardware elements, software elements, or a combination of both. In some examples, hardware elements may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, PLDs, DSPs, FPGAs, memory units, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. In some examples, software elements may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. The decision of whether an example is implemented using hardware and / or software elements may vary according to any number of factors, such as desired computational speed, power level, thermal tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus speed, and other design or performance constraints, as desired for a given implementation.

[0070] Some examples may include an article of manufacture or at least one computer-readable medium. The computer-readable medium may include a non-transitory storage medium for storing logic. In some examples, the non-transitory storage medium may include one or more types of computer-readable storage media capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, etc. In some examples, the logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

[0071] According to some examples, a computer-readable medium may include a non-transitory storage medium for storing or retaining instructions that, when executed by a machine, computing device, or system, cause the machine, computing device, or system to perform methods and / or actions according to described examples. The instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, etc. The instructions may be implemented according to a predefined computer language, manner, or syntax to instruct a machine, computing device, or system to perform a particular function. The instructions may be implemented using any suitable high-level language, low-level language, object-oriented programming language, visual programming language, compiled programming language, and / or interpreted programming language.

[0072] Some examples may be described using the phrase "in one example" or "in one example," along with their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with an example is included in at least one example. The appearances of the phrase "in one example" in various places in this specification are not necessarily all referring to the same example.

[0073] Some examples may be described using the terms "coupled" and "connected," along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, descriptions using the terms "connected" and / or "coupled" may indicate that two or more elements are in direct physical or electrical contact with each other. However, the term "coupled" can also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

[0074] It is emphasized that the Abstract of the Disclosure is provided to comply with 37 C.F.R. Section 1.72(b) requires an Abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Moreover, in the foregoing Detailed Description, various features are grouped together in a single example for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed examples require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed example. Accordingly, the appended claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate example. In the appended claims, the terms "including" and "in which" are used as the plain-English equivalents of the respective terms "comprising" and "wherein," respectively. Moreover, the terms "first," "second," "third," etc. are used merely as labels and are not intended to impose numerical requirements on their objects.

[0075] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the respective claims.

[0076] [Other possible items] (Item 1) A memory cell of a memory array, comprising: a phase change material that changes resistivity based on being in a crystalline or amorphous state, the phase change material having a constrained structure, being completely amorphized in all active areas in the amorphous state, and lacking sufficient crystalline nuclei to promote crystal growth; and a terminal to the memory cell for providing an electric current to control a change of the phase change material from the amorphous state to the crystalline state, wherein the change from the amorphous state to the crystalline state includes a nucleation stage to create crystal seeds, and a crystal growth stage after the nucleation stage to promote crystal growth to set the crystalline state and place the memory cell in a SET logic state, wherein the nucleation stage includes applying a first current for a first period followed by applying at least one second current for a second period, and the crystal growth stage includes applying at least one third current and a fourth current for a third period and a fourth period, respectively. (Item 2) 2. The memory cell of claim 1, further comprising the terminals for providing the current and controlling the change of the phase change material from the amorphous state to the crystalline state through temperature control associated with the first current, the at least one second current, the at least one third current, and the fourth current. (Item 3) 3. The memory cell of claim 2, comprising: the at least one second current including a single second current higher than the first current; and the at least one third current including a single third current higher than the single second current and lower than the fourth current, wherein the single second current changes the phase change material to a second temperature higher than the first temperature caused by the first current, the single third current changes the phase change material to a third temperature higher than the second temperature, and the fourth current changes the phase change material to a fourth temperature higher than the third temperature. (Item 4) 3. The memory cell of claim 2, comprising: the at least one second current including a plurality of currents that increase linearly over the second period; and the at least one third current including a plurality of currents that increase linearly over the third period, wherein the at least one second current linearly raises the phase change material to a second temperature higher than the first temperature produced by the first current, the at least one third current linearly raises the phase change material to a third temperature higher than the second temperature, and the fourth current causes the phase change material to maintain the third temperature. (Item 5) 2. The memory cell of claim 1, further comprising a finalizing step of annealing the phase change material, wherein the phase change material undergoes a change from the amorphous state to the crystalline state. (Item 6) 2. The memory cell of item 1, wherein the first period and the second period when combined are less than 1.5 times the duration of the third period and the fourth period when combined. (Item 7) 2. The memory cell of item 1, wherein the memory array comprises a cross-point memory array. (Item 8) an interface for accessing memory cells of the memory array; Control unit and An apparatus comprising: The control unit has logic, at least a portion of which is implemented as hardware, and the logic includes: Selecting one of the memory cells of the memory array and implementing a SET write operation via the interface, the one memory cell including a phase change material that changes resistivity based on being in a crystalline state or an amorphous state, the phase change material having a constrained structure, being fully amorphized in all active areas in the amorphous state, and lacking sufficient crystalline nuclei to promote crystal growth; applying a current to a terminal of the one memory cell to control a change of a phase change material included in the one memory cell from an amorphous state to the crystalline state, the change from the amorphous state to the crystalline state including a nucleation stage for generating a crystal seed, and a crystal growth stage after the nucleation stage for promoting crystal growth to set the crystalline state and place the memory cell in a SET logic state, the nucleation stage including applying a first current for a first period followed by applying at least one second current for a second period, and the crystal growth stage including applying at least one third current and a fourth current for a third period and a fourth period, respectively; Device. (Item 9) 9. The apparatus of claim 8, further comprising the logic for applying the currents to the terminals to control the change of the phase change material from the amorphous state to the crystalline state via temperature control associated with the first current, the at least one second current, the at least one third current, and the fourth current. (Item 10) 10. The device of claim 9, further comprising: the at least one second current including a single second current higher than the first current; and the at least one third current including a single third current higher than the single second current and lower than the fourth current, wherein the single second current changes the phase change material to a second temperature higher than the first temperature caused by the first current, the single third current changes the phase change material to a third temperature higher than the second temperature, and the fourth current changes the phase change material to a fourth temperature higher than the third temperature. (Item 11) 10. The device of claim 9, further comprising: the at least one second current including a plurality of currents that increase linearly over the second period; and the at least one third current including a plurality of currents that increase linearly over the third period, wherein the at least one second current linearly raises the phase change material to a second temperature that is higher than a first temperature generated by the first current; the at least one third current linearly raises the phase change material to a third temperature that is higher than the second temperature; and the fourth current causes the phase change material to maintain the third temperature. (Item 12) Item 10. The apparatus of item 8, further comprising the logic for effecting a finalization step of annealing the phase change material, comprising the logic for effecting application of a fifth current for a fifth period of time, to effect the change from the amorphous state to the crystalline state of the phase change material. (Item 13) Item 9. The apparatus of item 8, wherein the first period of time and the second period of time when combined are less than 1.5 times the duration of the third period of time and the fourth period of time when combined. (Item 14) one or more processors communicatively coupled to the controller; a network interface communicatively coupled to the device; a battery coupled to said device; or a display communicatively coupled to the device; Item 9. The device according to item 8, comprising one or more of: (Item 15) Selecting a memory cell in a memory array and implementing a SET write operation, the memory cell comprising a phase change material that changes resistivity based on being in a crystalline or amorphous state, the phase change material having a constrained structure, being fully amorphized in all active areas in the amorphous state, and lacking sufficient crystalline nuclei to promote crystal growth; applying currents to terminals of the memory cell to control a change of a phase change material in the memory cell from the amorphous state to the crystalline state, the change from the amorphous state to the crystalline state including a nucleation step to create a crystal seed, and a crystal growth step after the nucleation step to promote crystal growth to set the crystalline state and place the memory cell in a SET logic state, the nucleation step including applying a first current for a first period followed by applying at least one second current for a second period, and the crystal growth step including applying at least one third current and a fourth current for a third period and a fourth period, respectively; A method for providing (Item 16) 16. The method of claim 15, comprising applying the currents to the terminals to control the change of the phase change material from the amorphous state to the crystalline state via temperature control associated with the first current, the at least one second current, the at least one third current, and the fourth current. (Item 17) Item 16. The method of claim 15, further comprising: the at least one second current including a single second current higher than the first current; and the at least one third current including a single third current higher than the single second current and lower than the fourth current, wherein the single second current changes the phase change material to a second temperature higher than a first temperature caused by the first current; the single third current changes the phase change material to a third temperature higher than the second temperature; and the fourth current changes the phase change material to a fourth temperature higher than the third temperature. (Item 18) Item 16. The method of claim 15, further comprising: the at least one second current including a plurality of currents that increase linearly over the second period; and the at least one third current including a plurality of currents that increase linearly over the third period; wherein the at least one second current linearly raises the phase change material to a second temperature that is higher than a first temperature generated by the first current; the at least one third current linearly raises the phase change material to a third temperature that is higher than the second temperature; and the fourth current causes the phase change material to maintain the third temperature. (Item 19) 16. The method of claim 15, further comprising applying a fifth current for a fifth period of time to effect a final step of annealing the phase change material, comprising the transformation from the amorphous state to the crystalline state of the phase change material. (Item 20) Item 16. The method of item 15, wherein the first period of time and the second period of time when combined are less than 1.5 times the duration of the third period of time and the fourth period of time when combined.

Claims

[Claim 1] A memory cell of a memory array, comprising: a phase change material that changes resistivity based on being in a crystalline or amorphous state, the phase change material having a constrained structure, being completely amorphized in all active areas in the amorphous state, and lacking sufficient crystalline nuclei to promote crystal growth; a terminal to the memory cell for providing an electrical current to control a change of the phase change material from the amorphous state to the crystalline state; Equipped with the change from the amorphous state to the crystalline state includes a nucleation step to generate crystalline seeds, and a crystal growth step after the nucleation step to promote crystal growth to set the crystalline state and place the memory cell in a SET logic state, the nucleation step including applying a first current for a first period followed by applying at least one second current for a second period, and the crystal growth step including applying at least one third current and a fourth current for a third period and a fourth period, respectively. A memory cell of a memory array.

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