Semiconductor device

Abstract

To provide a semiconductor device having a large storage capacity per unit area.SOLUTION: The semiconductor device includes a memory cell including a first conductor 122, a first insulator 116 over the first conductor, a first oxide 106 over the first insulator, the first oxide including a first region 109a, a second region 109b, and a third region arranged between the first region and the second region, a second insulator 112 over the first oxide, a second conductor 114 over the second insulator, a third insulator 132 arranged in contact with a side surface of the first region, and a side surface of the third region. And a second oxide 134 arranged with a third insulator interposed therebetween, wherein the first region includes a region overlapping with the first conductor, the third region includes a region overlapping with the second conductor, and the first region and the second region have lower resistance than the third region.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The present invention relates to, for example, a transistor and a semiconductor device. For example, the present invention relates to a method for manufacturing a transistor and a semiconductor device. The present invention relates to a display device, a light-emitting device, a lighting device, a power storage device, a storage device, a processor, and an electronic device. The present invention also relates to a manufacturing method of a display device, a liquid crystal display device, a light emitting device, a storage device, and an electronic device. The present invention also relates to a display device, a liquid crystal display device, a light emitting device, a storage device, and a method for driving electronic equipment.

[0002] Note that one embodiment of the present invention is not limited to the above technical fields. The technical field of one aspect of the present invention relates to an article, a method, or a manufacturing method. One aspect of the invention is a process, machine, manufacture, or composition of matter. It concerns the matter of matter.

[0003] In this specification and the like, a semiconductor device is a device that can function by utilizing semiconductor characteristics. This refers to devices in general, including display devices, light-emitting devices, lighting devices, electro-optical devices, memory devices, semiconductor circuits, and The electronic equipment may include semiconductor devices. [Background technology]

[0004] Silicon (Si)-based transistors and oxide semiconductors (Oxide S) Transistors using OS (semiconductor) as the semiconductor layer (hereafter referred to as OS transistors) A semiconductor device that combines a memory cell (called a memory register) and a memory cell that enables data reading and writing. has been attracting attention (see Patent Document 1).

[0005] In recent years, with the increase in the amount of data handled, semiconductor devices with larger storage capacities have become increasingly popular. To increase the storage capacity per unit area, memory cells must be stacked. It is effective to form the memory cells in layers (see Patent Documents 2 and 3). This makes it possible to increase the storage capacity per unit area in accordance with the number of stacked memory cells. can. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Patent Publication No. 2011-119674 [Patent Document 2] Patent Publication No. 2011-66417 [Patent Document 3] Patent Publication No. 2016-225613 Summary of the Invention [Problem to be solved by the invention]

[0007] An object of the present invention is to provide a semiconductor device having a large storage capacity per unit area. One of the objects of the present invention is to provide a semiconductor device having a novel structure in which memory cells are stacked. Another object is to provide a method for driving a semiconductor device having a novel structure. An object is to provide a highly productive semiconductor device.

[0008] Another object of the present invention is to provide a module having any one of the semiconductor devices described above. Alternatively, an electronic device having any of the above semiconductor devices or modules is provided. Another object of the present invention is to provide a novel semiconductor device. Alternatively, one of the objectives is to provide a new module. One of our goals is to provide

[0009] The description of these problems does not preclude the existence of other problems. It is not necessary for one embodiment to solve all of these problems. The subject matter will be self-evident from the description, drawings, claims, etc. It is possible to extract other issues from the drawings, claims, etc. [Means for solving the problem]

[0010] One embodiment of the present invention is a semiconductor device having a memory cell, the memory cell comprising: a first conductive layer; a first conductor, a first insulator on the first conductor, and a first region and a second region on the first insulator; and a first oxide having a third region disposed between the first region and the second region. a second insulator on the first oxide; a second conductor on the second insulator; and a second conductor on the first region. a third insulator disposed in contact with the surface; and a third insulator disposed on a side surface of the first region via the third insulator. a second oxide formed on the first region, the first region having a region overlapping the first conductor; The third region has a region overlapping with the second conductor, and the first region and the second region are It has lower resistance than area 3.

[0011] One embodiment of the present invention is a semiconductor device having a memory cell, the memory cell comprising: a first conductive layer; a first conductor, a first insulator on the first conductor, and a first region and a second region on the first insulator; and a first oxide having a third region disposed between the first region and the second region. a second insulator on the first oxide; a second conductor on the second insulator; and a second conductor on the first region. a third insulator disposed in contact with the surface; and a third insulator disposed on a side surface of the first region via the third insulator. a second oxide formed on the first region, the first region having a region overlapping the first conductor; The third region has a region overlapping with the second conductor, and the first region and the second region are The first conductor, the first insulator, and the first region have a lower resistance than the third region, and the first conductor, the first insulator, and the first region have a capacitance The first oxide, the second insulator, and the second conductor function as a first transistor. The second oxide, the third insulator, and the first region function as a second transistor. It functions as a register.

[0012] In the above configuration, the first conductor, the second conductor, the first insulator, and the second insulator The insulating layer has an opening, and the second oxide is disposed in the opening via the third insulator.

[0013] In the above structure, the first oxide and the second oxide are made of In and an element M (M is Al , Ga, Y, or Sn) and Zn.

[0014] In the above configuration, the semiconductor device has a base body and a plurality of memory cells on the base body. .

[0015] In the above-mentioned configuration, the semiconductor device has a fourth insulator, and the semiconductor device has a substrate. In the direction horizontal to one of the surfaces, m h pieces(m h is an integer of 2 or more), The fourth insulator is disposed between the first insulator and the second insulator, and has a side surface of the first oxide. and m h The memory cells are isolated from one another by a fourth insulator.

[0016] In the above-described structure, the semiconductor device has m v pieces (m v is an integer of 2 or more).

[0017] In the above structure, the second oxide is m v It is provided in common to the memory cells. [Effects of the Invention]

[0018] It is possible to provide a semiconductor device having a large memory capacity per unit area. It is possible to provide a semiconductor device having a novel structure in which recells are stacked. It is also possible to provide a method for driving the semiconductor device. It can be provided.

[0019] Alternatively, a module including any one of the semiconductor devices described above can be provided. It is possible to provide an electronic device having any of the above semiconductor devices or modules. Alternatively, a novel semiconductor device can be provided. Alternatively, a novel module can be provided. Alternatively, a novel electronic device can be provided.

[0020] The description of these effects does not preclude the existence of other effects. An embodiment does not necessarily have all of these effects. Effects other than these may be included in the description. The above is self-evident from the description, drawings, claims, etc. From the above descriptions, it is possible to extract other effects. [Brief explanation of the drawings]

[0021] [Figure 1]1A and 1B are a circuit diagram and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 2] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 3] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 4] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 5] FIG. 1 is a circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 6] 10 is a timing chart illustrating a method for driving a semiconductor device according to one embodiment of the present invention. [Figure 7] 1A and 1B are schematic diagrams illustrating a semiconductor device according to one embodiment of the present invention. [Figure 8] 1A and 1B are a cross-sectional view and a plan view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 9] FIG. 1 is a plan view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 10] 1A and 1B are a cross-sectional view and a plan view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 11] FIG. 1 is a plan view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 12] FIG. 1 is a plan view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 13] FIG. 1 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 14] 1A and 1B are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 15] 1A and 1B are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 16] 1A and 1B are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 17] 1A and 1B are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 18] 1A and 1B are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 19]1A and 1B are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 20] 1A and 1B are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 21] 1A and 1B are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 22] 1A and 1B are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 23] 1A and 1B are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 24] 1A and 1B are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 25] 1A and 1B are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 26] 1A and 1B are plan views and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. [Figure 27] FIG. 1 is a schematic diagram of a memory device according to one embodiment of the present invention. [Figure 28] FIG. 1 is a block diagram showing an example of the configuration of an AI system according to one embodiment of the present invention. [Figure 29] FIG. 1 is a block diagram illustrating an application example of an AI system according to one embodiment of the present invention. [Figure 30] 1 is a schematic perspective view showing an example of the configuration of an IC incorporating an AI system according to one embodiment of the present invention. [Figure 31] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 32] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. [Figure 33] 1A to 1C are diagrams illustrating electronic devices according to one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0022] The embodiments of the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description, and various modifications in form and details can be easily made by those skilled in the art. Furthermore, the present invention should not be construed as being limited to the description of the following embodiments. In explaining the configuration of the invention using the drawings, the same symbols are used It is used in common among different drawings. When referring to the same thing, the hatch pattern is used in the same way. In some cases, no particular symbol is given.

[0023] The configurations shown in the following embodiments may be applied or combined as appropriate with other configurations shown in the embodiments. Combinations, substitutions, etc. can be made to form one embodiment of the present invention.

[0024] In the drawings, the size, thickness of the film (layer), or area is exaggerated for clarity. This may be the case.

[0025] In this specification, the terms "film" and "layer" are interchangeable. It is possible to do this.

[0026] Also, a voltage is a voltage between a certain potential and a reference potential (for example, ground potential (GND) or source potential). Therefore, voltage can be replaced with potential. Generally, potential (voltage) is relative, and the magnitude is relative to a reference potential. Therefore, even if it is described as "ground potential", The potential is not necessarily 0V. For example, the lowest potential in a circuit may be the "ground potential." Or, the intermediate potential in the circuit may be the "ground potential." In this case, the positive potential and the negative potential are defined based on that potential.

[0027] The ordinal numbers such as 1st and 2nd are used for convenience and do not indicate the order of processes or stacking. It does not indicate the layer order. Therefore, for example, "first" should not be changed to "second" or "third." In addition, the ordinal numbers described in this specification and the like can be replaced with the ordinal numbers The term and the ordinal number used to identify an aspect of the present invention may not match.

[0028] In this specification, "A and B are connected" means that "A and B are directly connected." In addition to the above, it also includes things that are electrically connected. Being connected means that there is an object that has some kind of electrical effect between A and B. A means a device that enables the transmission and reception of electrical signals between A and B.

[0029] In this specification, the source of a transistor is a semiconductor film that functions as an active layer. The source electrode is a part of the semiconductor film. The drain of the transistor is a drain region that is a part of the semiconductor film, or The term "gate" refers to the gate electrode connected to the semiconductor film.

[0030] The source and drain of a transistor are determined by the conductivity type of the transistor and the terminals. The name changes depending on the level of the potential applied. Generally, n-channel transistors In a capacitor, the terminal to which a low potential is applied is called the source, and the terminal to which a high potential is applied is called the drain. In addition, in a p-channel transistor, the terminal to which a low potential is applied is called the drive The terminal to which the high potential is applied is called the drain, and the terminal to which the high potential is applied is called the source. Explain the connection relationship of a transistor, assuming that the source and drain are fixed. However, in reality, the names of source and drain are interchanged according to the above potential relationship. Bad.

[0031] Unless otherwise specified, in this specification, the off-state current refers to the current when a transistor is in an off state. The off-state refers to the drain current when the n-channel transistor is turned on, unless otherwise specified. In a transistor, the potential difference between the gate and source (V GS ) is the threshold voltage (V th ) lower than In the p-channel transistor, V GS V th For example, , the off-state current of an n-channel transistor is V GS V th When lower than The off-state current of a transistor is V GS It may depend on So, the off-state current of the transistor is 10 -21 A or less means that the off-state current of the transistor is Flow is 10 -21 V below A GS It may be said that there exists a value of

[0032] The off-state current of a transistor is determined by the potential difference between the drain and source (V DS ) depends on In this specification, the off-state current is V unless otherwise specified. DS The absolute value of is 0 .1V, 0.8V, 1V, 1.2V, 1.8V, 2.5V, 3V, 3.3V, 10V, 1 It may represent the off-state current at 2V, 16V, or 20V. V that guarantees the reliability of semiconductor devices containing DS , or the transistor V used in semiconductor devices, etc. DS The term "off-state current" may also refer to the off-state current at

[0033] Even when written as "semiconductor," if the conductivity is sufficiently low, it may be called an "insulator." In addition, the boundary between "semiconductors" and "insulators" is unclear and cannot be clearly defined. Therefore, the term "semiconductor" as used herein is not necessarily an "insulator" Similarly, the term "insulator" used in this specification can be interpreted as "semiconductor." It can sometimes be rephrased as "body."

[0034] Also, even if a material is written as a "semiconductor," if the material has a sufficiently high conductivity, it may be written as a "conductor." In addition, the boundary between "semiconductor" and "conductor" is unclear and cannot be clearly defined. Therefore, the term "semiconductor" as used herein is not necessarily a "conductor" Similarly, the term "conductor" used in this specification can be interpreted as "semiconductor." It can sometimes be rephrased as "body."

[0035] In addition, in this specification, the term "insulator" may be replaced with "insulating film" or "insulating layer." The term "conductor" can also be replaced with "conductive film" or "conductive layer." The term "semiconductor" can also be replaced with "semiconductor film" or "semiconductor layer." can.

[0036] The impurities in a semiconductor refer to, for example, anything other than the main component that constitutes the semiconductor. Elements present at concentrations of less than 0.1 atomic percent are considered impurities. The formation of DOS (Density of States) in the conductor and carrier migration The mobility and crystallinity may decrease. In the case of semiconductors, impurities that change the properties of the semiconductor include, for example, Group 1 elements, There are elements from Group 2, Group 13, Group 14, Group 15, and transition metals other than the main component. In particular, for example, hydrogen (which is also contained in water), lithium, sodium, silicon, boron In the case of oxide semiconductors, impurities such as hydrogen can cause Therefore, oxygen vacancies may be formed. Impurities that change the properties include, for example, oxygen, elements of Group 1 except for hydrogen, elements of Group 2, and elements of Group 3. These include the Group 13 elements and Group 15 elements.

[0037] Note that the channel length is, for example, the length of a semiconductor (or transistor) in a top view of a transistor. When the transistor is in the on state, the gate electrode overlaps with the semiconductor (the part where current flows). The source (source region or source The distance between the drain electrode and the drain region is called the distance between the In the transistor, the channel length does not necessarily have the same value in all regions. The channel length of a transistor may not be determined to a single value. In the detailed description, the channel length is any one value, the maximum value, in the region where the channel is formed. , the minimum or average value.

[0038] The channel width is the width of the semiconductor (or transistor) when it is in the on state. The region where the gate electrode overlaps with the electrode (the area where current flows) forms a channel. The length of the region where the source and drain face each other. In a transistor, the channel width does not necessarily have the same value in all regions. The channel width of a transistor may not be determined to a single value. In the detailed description, the channel width is any one value, the maximum value in the region where the channel is formed. , the minimum or average value.

[0039] Depending on the structure of the transistor, the channel in the region where the channel is actually formed may be The effective channel width is shown in the top view of the transistor. The channel width that is actually used (hereinafter referred to as the apparent channel width) may differ from the actual channel width. For example, In a transistor having a three-dimensional structure, the effective channel width is The apparent channel width shown in the figure becomes larger, and the effect becomes non-negligible. For example, in transistors with a fine, three-dimensional structure, the side surface of the semiconductor In this case, the ratio of the channel formation region formed in the top view to the The effective channel width of the channel that is actually formed is larger than the apparent channel width shown by the The width of the rule is larger.

[0040] In a transistor having a three-dimensional structure, the effective channel width is For example, it may be difficult to estimate the effective channel width from the design value. In order for deposition to occur, it is necessary to assume that the shape of the semiconductor is known. It is difficult to accurately measure the effective channel width if the channel conditions are not precisely known. .

[0041] Therefore, in this specification, in a top view of a transistor, a semiconductor and a gate electrode are not mutually connected. The apparent length is the length of the part where the source and drain face each other in the overlapping region. The above channel width is called "Surrounded Channel Width (SCW)". In this specification, it is simply referred to as the channel width. In some cases, it may refer to the enclosed channel width or apparent channel width. In this specification, when simply referring to a channel width, it may refer to an effective channel width. The channel length, channel width, effective channel width, apparent channel width, and The width of the interstitial channel can be determined by acquiring a cross-sectional TEM image and analyzing the image. Thus, the value can be determined.

[0042] The field effect mobility of the transistor and the current value per channel width are calculated. In this case, the effective channel width is calculated using the enclosed channel width. The value may differ from that calculated using the channel width.

[0043] In this specification, "parallel" means that two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it includes the case where the angle is between -5° and 5°. "Parallel" refers to a state in which two lines are arranged at an angle of between -30° and 30°. Also, "perpendicular" means that two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is between 85° and 95°. This refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

[0044] In this specification, when the crystal is a trigonal or rhombohedral crystal, it is represented as a hexagonal crystal system. vinegar.

[0045] In this specification and the like, a silicon oxynitride film is a film containing more oxygen than nitrogen as a component. For example, the oxygen content is preferably 55 atomic % or more and 65 atomic % or less. , nitrogen is 1 atomic % or more and 20 atomic % or less, silicon is 25 atomic % or more and 35 atomic % or less, hydrogen The concentration range of 0.1 atomic % to 10 atomic % is also referred to as nitride oxide. The silicon film has a composition in which the nitrogen content is higher than the oxygen content. Preferably, nitrogen is 55 atomic % or more and 65 atomic % or less, oxygen is 1 atomic % or more and 20 atomic % or less, Silicon concentration is 25 atomic % or more and 35 atomic % or less, and hydrogen concentration is 0.1 atomic % or more and 10 atomic % or less It refers to what is included in the range.

[0046] In this specification, the term "metal oxide" refers to a metal in a broad sense. Metal oxides are oxides of the following: oxide insulators, oxide conductors (including transparent oxide conductors), ), oxide semiconductor (also called oxide semiconductor or simply OS) For example, when a metal oxide is used in the active layer of a transistor, the metal An oxide may be referred to as an oxide semiconductor. In other words, the transistor may be a transistor having a metal oxide or an oxide semiconductor. do.

[0047] In this specification, the expression "In:Ga:Zn=4:2:3 or its vicinity" refers to the atomic ratio of In:Ga:Zn=4:2:3 or its vicinity. In the total number, when In is 4, Ga is 1 to 3 (1≦Ga≦3), and Zn is 2 or more and 4.1 or less (2≦Zn≦4.1). Also, In:Ga:Zn=5:1:6 Or in the vicinity thereof means that, with respect to the total number of atoms, when In is 5, Ga is greater than 0.1. It is less than 2 (0.1 < Ga ≤ 2), and Zn is 5 or more and 7 or less (5 ≤ Zn ≤ 7). Also , In:Ga:Zn = 1:1:1 or in the vicinity thereof means that when In is 1 in terms of the total number of atoms, Ga is greater than 0.1 and less than or equal to 2 (0.1 < Ga ≤ 2), and Zn is greater than 0.1 and less than or equal to 2 (0.1 < Zn ≤ 2).

[0048] (Embodiment 1) In this embodiment, the circuit configuration and operation of a semiconductor device according to an aspect of the disclosed invention will be described with reference to FIGS. 1 to 6.

[0049] <Memory Cell> First, the circuit configuration of the memory cell of the semiconductor device to be described later will be described with reference to FIGS. 1(A) and 1 (B). Here, FIG. 1(A) is an example of a circuit diagram showing the circuit configuration of the memory cell 10 three-dimensionally corresponding to the three-dimensional configuration of the semiconductor device, and FIG. 1(B) is a cross-sectional schematic diagram showing an example of the configuration of the memory cell 10. The memory cell 10 includes a transistor 11, a transistor 12, and a capacitor element 14.

[0050] The memory cell 10 is electrically connected to a wiring WBL, a wiring RWL, a wiring WWL, a wiring SL, and a wiring RBL. In the following description, the transistor 11 and the transistor 12 will be described as n-channel transistors. In the memory cell 10 shown in FIGS. 1(A) and (B), the wiring SL and the source electrode (or drain electrode) of the transistor 11 are electrically connected, and the wiring RBL and the drain electrode (or source electrode) of the transistor 11 are electrically connected. Also, the wiring WBL and the transistor

[0051] In the memory cell 10 shown in FIGS. 1(A) and (B), the wiring SL and the source electrode (or drain electrode) of the transistor 11 are electrically connected, and the wiring RBL and the drain electrode (or source electrode) of the transistor 11 are electrically connected. Also, the wiring WBL and the transistor source electrode (or drain electrode) are electrically connected, and the wiring RBL and the drain electrode (or source electrode) of the transistor 11 are electrically connected. Also, the wiring WBL and the transistor drain electrode (or source electrode) are electrically connected. Also, the wiring WBL and the transistor The source electrode (or drain electrode) of the transistor 12 is electrically connected to the wiring WWL. The gate electrodes of the transistors 12 and 11 are electrically connected. The gate electrode of the transistor 12 and the drain electrode (or source electrode) of the capacitor element 14 The wiring RWL and the other electrode of the capacitance element 14 are electrically connected. It is being done.

[0052] Here, the transistor 12 is preferably an OS transistor. As will be described later, an OS transistor is characterized by an extremely low off-state current. Therefore, when the transistor 12 is turned off, the voltage of the gate electrode of the transistor 11 is The capacitor element 14 can hold the voltage for a very long time. This makes it easier to retain the charge given to the gate electrode of the transistor 11, and , the stored information can be easily read.

[0053] It is also preferable to use an OS transistor as the transistor 11. By using an OS transistor as 11, the through current flowing between the wiring SL and the wiring RBL is reduced. can be reduced.

[0054] In the memory cell 10 shown in FIGS. 1A and 1B, the potential of the gate electrode of the transistor 11 By taking advantage of the feature that information can be stored, it is possible to write, store, and read information as follows: It is possible.

[0055] First, writing and holding of information will be described. First, the potential of the wiring WWL is set as follows: The transistor 12 is turned on by applying a potential that turns the transistor 12 on. As a result, the potential of the wiring WBL is The gate electrode of the transistor 11 and one electrode of the capacitor 14 are electrically connected. Node FN, that is, the gate of transistor 11. A predetermined charge is applied to the electrode (writing). Here, two different potentials are applied. Charge (hereinafter, the charge that gives the low potential is called charge Q L , the charge that gives the high potential is the charge Q H (That is, Any of the three or more different potentials can be applied. Then, the potential of the wiring WWL is applied to the transistor By setting the potential at which the transistor 12 is turned off, the transistor The charge given to the gate electrode of the transistor 11 is held (retained).

[0056] Since the off-state current of the transistor 12 is extremely small, the voltage of the gate electrode of the transistor 11 is The load is held for a long period of time.

[0057] Next, reading of information will be described. When a predetermined potential (constant potential) is applied to the wiring SL, In this state, when an appropriate potential (read potential) is applied to the wiring RWL, the gate of the transistor 11 The wiring RBL has different potentials depending on the amount of charge held in the electrode. Q to the gate electrode H The apparent threshold voltage V th_H is a transition Q is connected to the gate electrode of sta- 11 L The apparent threshold voltage V th_L Yo Here, the apparent threshold voltage is the voltage at which the transistor 11 is turned "off." Wiring R required to change from "ON state" to "ON state" or from "ON state" to "OFF state" Therefore, the potential of the wiring RWL is V th_H and V th_L By setting the potential V0 between these, the charge given to the gate electrode of the transistor 11 can be determined. For example, in writing, H When the potential of the wiring RWL is V 0(>V th_H ), transistor 11 is in the "ON state." Q L is given In this case, the potential of the wiring RWL is V0( <V th_L ), transistor 11 Therefore, by detecting the potential of the wiring RBL, it is possible to The information stored in the memory can be read.

[0058] When memory cells are arranged in a matrix, the information of the desired memory cell is In this way, it is necessary to read only the information of a specific memory cell. To prevent other memory cells from reading information, a transistor is placed between each memory cell. When the memory cells 11 are connected in series, the memory cells that are not the object of reading are For the wiring RWL, the transistor 11 is in the "ON state" regardless of the state of the gate electrode. The potential at which V th_L In this case, the wiring R WL to V th_L When a larger potential is applied, the transistor 11 A potential is applied to the gate electrode of the transistor 11 so that the transistor 11 is in the "on state." The node FN can be turned on independently of the data stored in the node FN.

[0059] Next, the rewriting of information will be explained. That is, the potential of the wiring WWL is changed by turning on the transistor 12. This turns on the transistor 12 by setting the potential of the wiring WBL ( A potential related to new information is applied to the gate electrode of the transistor 11 and the capacitor 14. After that, the potential of the wiring WWL is set to a potential that turns off the transistor 12. By turning off the transistor 12, the gate electrode of the transistor 11 is The charge related to the information is given.

[0060] In this way, the semiconductor device according to the disclosed invention can directly write information again. Therefore, when erasing flash memory, This eliminates the need to extract charge from the floating gate using the high voltage required for This makes it possible to suppress a decrease in the operating speed. In other words, high-speed operation of the semiconductor device is realized. do.

[0061] The drain electrode (or source electrode) of the transistor 12 and the The node FN, to which the gate electrode and one electrode of the capacitor 14 are electrically connected, is a nonvolatile The floating gate of a floating gate transistor used as a memory element When the transistor 12 is off, the node FN is connected to the insulator. The node FN can be considered as being buried, and charge is held in the node FN. The off-state current of the transistor 12 is 100,000 times that of a transistor made of a silicon semiconductor. Because the charge stored in node FN is less than one-fifth of the In other words, the transistor 12 using an oxide semiconductor can store information without power supply. It is possible to realize a storage device capable of long-term retention.

[0062] For example, if the off-state current of the transistor 12 at room temperature (25° C.) is 10 zA (1 zA (zepto)), ampere) is 1 x 10 -21 A) or less, and the capacitance value of the capacitance element 14 is about 10 fF. If so, at least 10 4 It is possible to hold data for more than 10 seconds. It goes without saying that this varies depending on the transistor characteristics and capacitance value.

[0063] In addition, in the memory cell 10 shown in this embodiment, a conventional floating gate type The problem of deterioration of the gate insulating film (tunnel insulating film) that has been pointed out in transistors In other words, there is no problem with injecting electrons into the floating gate, which has been a problem in the past. This solves the problem of deterioration of the gate insulating film during writing. This means that there is no limit to the number of times. The high voltage required for writing and erasing data in a conventional transistor is also unnecessary.

[0064] In the memory cell 10, the node FN is connected to a floating gate of a flash memory or the like. The floating gate of the present embodiment functions in the same way as the floating gate of a gate-type transistor. FN has fundamentally different characteristics from floating gates such as flash memory. In flash memory, the potential applied to the control gate is high, so the potential In order not to affect the floating gates of adjacent cells, the spacing between cells is This is one of the factors that hinders the high integration of semiconductor devices. The reason for this is the flash effect, which generates a tunnel current by applying a high electric field. This is due to the fundamental principles of memory.

[0065] On the other hand, the semiconductor device according to this embodiment has a transistor switch using an oxide semiconductor. It operates by switching and does not use the principle of charge injection by tunnel current as described above. That is, unlike flash memory, a high electric field for injecting charges is not required. This eliminates the need to consider the influence of the high electric field caused by the control gate on adjacent cells. This makes it easier to achieve high integration.

[0066] In order to increase the memory capacity of a semiconductor device, in addition to high integration, a method of multi-level data storage is also required. For example, it is possible to write three or more levels of information into each memory cell. This allows for a larger memory capacity than when writing binary (1-bit) information. For example, the charge Q L , a charge Q that gives a high potential H In addition By applying a charge Q that gives another potential to the gate electrode of the transistor 11, multi-values ​​are realized. Multi-value data can be expressed as, for example, 4-value (2 bits), 8-value (3 bits) It is sufficient to be able to hold data such as 16 values ​​(4 bits), 16 values ​​(4 bits), etc.

[0067] As shown in FIG. 1B, the memory cell 10 includes a transistor 11, a transistor 12, and a capacitor 14. The capacitor 14 functions as either the source or the drain of the transistor 11. The region where the source or drain of the transistor 11 is electrically connected to the wiring RBL. The other region of the transistor 12 is electrically connected to the wiring SL. The conductive layer that functions as a gate is provided extending in the direction of the paper surface, and is formed as wiring WWL. The conductive layer that functions as one of the electrodes of the capacitance element 14 extends in the direction of the depth of the paper. The source or drain of the transistor 12 is also provided as a wiring RWL. The region functioning as one of the gates is electrically connected to the wiring WBL. The region functioning as the other of the two sources or drains functions as a node FN.

[0068] A more specific configuration of the memory cell 10 shown in FIG. 1B will be described in the second embodiment. I will explain.

[0069] In the memory cell array described later, the memory cell 10 is arranged as shown in FIGS. , the channel length direction of the transistor 11, the channel length direction of the transistor 12, the wiring SL The wiring RBL, the wiring WBL, the wiring RWL, and the wiring WWL are arranged to intersect three-dimensionally. It is preferable that:

[0070] The channel length direction of the transistor 11 and the channel length direction of the transistor 12 are approximately perpendicular to each other. It is also preferable that the transistor is disposed on the upper surface of the substrate on which the memory cell 10 is provided. The channel length direction of the transistor 11 is approximately perpendicular, and the channel length direction of the transistor 12 is approximately parallel. It is preferable that there is.

[0071] In addition, the wiring WWL and the wiring RWL are approximately It is preferable that the wiring is perpendicular to the upper surface of the substrate on which the memory cell 10 is provided. RBL, wiring SL and wiring WBL are approximately perpendicular, and wiring WWL and wiring RWL are approximately parallel. It is preferable that there is.

[0072] By configuring the memory cell 10 in this way, as will be described later, a plurality of memory cells 1 0 can be stacked in series with each transistor 11 This increases the storage capacity per unit area according to the number of stacked memory cells 10. It is possible to provide a semiconductor device that can

[0073] As described above, the transistor 11 is arranged so that the channel length direction is perpendicular to the upper surface of the substrate. By configuring the circuit so that the gate electrode surrounds the semiconductor, and the source and drain are Vertical transistors (SGTs) are placed above and below the transistor. ng Gate Transistor) can be easily used. Compared to the core-type transistor, the SGT occupies a very small area. The storage capacity per unit area can be increased.

[0074] <Memory Cell Array> Next, a more specific circuit configuration and operation using the circuit shown in Figure 1 will be explained in Figure 2. The description will be made with reference to FIG.

[0075] A three-dimensional memory cell array 40, a selection transistor array 50, a drive circuit 51, and a read A block circuit of a semiconductor device having a read circuit 52, a drive circuit 53, and a drive circuit 54. An example of the path diagram is shown in Figure 2. In the following, as shown in Figure 2, the x-axis, y-axis, and z-axis For convenience, an orthogonal coordinate system consisting of the following will be set and explained.

[0076] 3 shows an example of a circuit diagram of a three-dimensional memory cell array 40. Also, FIG. An example of a block circuit diagram of a two-dimensional memory cell array 30[1] included in the cell array 40 is shown below. 4 shows an example of a block circuit diagram of a two-dimensional memory cell array 30[1]. Some of the configuration in the x-axis direction is represented in a pseudo-yz plane. 5 shows a selection transistor array 50, a drive circuit 51, a read circuit 52, and a drive 1 shows an example of a block circuit diagram of the operation circuit 54.

[0077] A selection transistor array 50, a drive circuit 51, a read circuit 52, a drive circuit 53, and The drive circuit 54 is formed on a substrate surface that is approximately parallel to the xy plane. A three-dimensional memory cell array 40 is formed on the substrate 50 .

[0078] As shown in FIGS. 2 and 3, the three-dimensional memory cell array 40 has m1×m2×m3 ( The memory cells 10 have m1 memory cells in the x-axis direction and m3 memory cells in the y-axis direction (m1, m2, and m3 are natural numbers). The memory cells 10 are arranged in a rectangular parallelepiped shape, with m2 memory cells in the z-axis direction and m3 memory cells in the z-axis direction. The memory cells 10 are assigned coordinates, and the memory cells 10 (1,1,1) to (m1,m2,m3) It may be shown as follows.

[0079] As shown in FIG. 3, the three-dimensional memory cell array 40 is provided extending in the z-axis direction. The m1 × m2 wires SL, wires RBL and wires WBL are arranged in the y-axis direction. The wiring RWL and the wiring WWL are arranged in a number m1 × m3. The wiring SL is assigned coordinates in the x-axis direction and the y-axis direction, and the wiring SL[1,1] to [m1,m2 Similarly, the wiring RBL[1,1] to [m1,m2], the wiring W It may be expressed as BL[1,1] to [m1,m2]. The lines RWL are assigned coordinates in the x-axis and z-axis directions, and the wiring RWL[1,1] to [m1,m3 Similarly, the wiring WWL[1,1] to [m1,m3] This may be indicated.

[0080] As shown in FIG. 2, the three-dimensional memory cell array 40 includes: It is composed of m1 two-dimensional memory cell arrays 30. Hereinafter, the two-dimensional memory cell array 3 By adding the coordinate in the x-axis direction to 0, the two-dimensional memory cell array 30[1] to [m1] is obtained. This may be indicated.

[0081] As shown in FIG. 2, each two-dimensional memory cell array 30 is arranged in the y-axis direction. The memory cell strings 20 are each made up of m2 memory cell strings 20. The memory cell strings 20 are assigned coordinates in the x-axis and y-axis directions, and are designated as memory cell strings 20[1,1] to Each memory cell string 20 is arranged in the z-axis direction. The memory cells 10 are arranged in a row. Since the array 30 is composed of m2 memory cell strings 20, it is a two-dimensional memory cell In the array 30, m2 memory cells 10 are arranged in a matrix in the y-axis direction and m3 memory cells 10 are arranged in the z-axis direction. The array will be as follows:

[0082] As shown in FIG. 1A, the memory cell 10 includes a transistor 11, a transistor 12, and a and a capacitance element 14, and However, as shown in FIGS. 2 and 4, each memory cell string 20 The memory cells 10 constituting the memory cell array 10 are connected in series in the z-axis direction in the transistor 11. Therefore, memory cell (i1, i2, 1) (i1 is a natural number between 1 and m1, and i2 is 1 ) is connected to the wiring RBL without passing through other memory cells 10. [i1,i2]. Also, only memory cell (i1,i2,m3) is connected to other memory The other memory cells 10 are connected to the wiring SL[i1, i2] without going through the cell 10. , through the other memory cells 10 of the same memory cell string 20, the wiring RBL and the wiring S Electrically connected to L.

[0083] Here, taking the two-dimensional memory cell array 30[1] shown in FIG. 4 as an example, The structure of the two-dimensional memory cell array 30 [1] shown in FIG. The wiring SL[1,1] to [1,m2] and the wiring RBL[1,1] to [1, m2], m2 wirings WBL[1,1] to [1,m2], and m3 wirings RWL[1 ,1] to [1,m3], m3 wires WWL[1,1] to [1,m3], and m2× m3 memory cells 10 (1,1,1) to (1,m2,m3) arranged in a matrix ) and.

[0084] In the following, the matrix wiring and memory cells of the two-dimensional memory cell array 30 are For example, the same two-dimensional memory cell array 30 In this example, a plurality of memory cells 10 having the same z-coordinate are referred to as memory cells 10 in the same row. In the same two-dimensional memory cell array 30, the y coordinates are the same. A plurality of memory cells 10 (which can also be said to constitute the same memory cell string 20) can be expressed as the memory cells 10 in the same column. In the following, the two-dimensional memory cell shown in Fig. 4 etc. In the Array 30, the rows are called the 1st row, the 2nd row, ... the 3rd row from the bottom, and the left column These are called the first row, second row, ... second row.

[0085] The wiring SL[1, i2] is connected to the corresponding transistor of the memory cell 10(1, i2, m3). The wiring RBL[1, i2] is electrically connected to the source electrode of the transistor 11. The drain electrode of the corresponding transistor 11 of the memory cell 10(1,i2,1) is electrically connected to the drain electrode of the corresponding transistor 11. To be continued.

[0086] The wiring WBL[1,i2] is connected to the memory cells 10(1,i2,1) to 10(1 , i2, m3) are electrically connected to the source electrodes of the corresponding transistors 12. In other words, the source electrodes of the transistors 12 of the memory cells 10 in the same column are connected to the wiring WB Electrically connected to L.

[0087] The wiring RWL[1,i3] (i3 is a natural number between 1 and m3) is In addition to the electrodes of the corresponding capacitance elements 14 of the resiliency cells 10(1,1,i3) to (1,m2,i3), In other words, the electrodes of the capacitors 14 of the memory cells 10 in the same row are electrically connected to each other. The other one is electrically connected to the wiring RWL in the same row.

[0088] The wiring WWL[1,i3] is connected to the memory cells 10(1,1,i3) to 10(1,1,i4). , m2, i3) are electrically connected to the gate electrodes of the corresponding transistors 12. In other words, the gate electrodes of the transistors 12 of the memory cells 10 in the same row are connected to the wiring W Electrically connected to L.

[0089] Memory cell 10(1,i2,i 3A )(i 3A denotes a natural number between 1 and m3-1. The source electrode of the transistor 11 of the memory cell 10(1, i2, i 3A +1) Tiger In other words, in the same column, the drain electrodes of the transistors 11 are electrically connected to the drain electrodes of the transistors 11. The memory cells 10 are connected to each other by the source electrode of the transistor 11 and the drain of the transistor 11. The input electrode is electrically connected to the output electrode.

[0090] In this way, between the wiring SL[1,i2] and the wiring RBL[1,i2], transistor 1 1, the memory cells 10 (1, i2, 1) to (1, i2, m3) connected in series Thus, a memory cell string 20[1, i2] is formed.

[0091] In this way, the memory cell string 20 includes a plurality of memory cells 10, The transistors 11 can be stacked so that they are connected in series. The ring 20 has a storage capacity of the memory cell string 20 that varies depending on the number of stacked memory cells 10. Therefore, the number of memory cells 20 can be increased. The dimensional memory cell array 40 has a memory capacity per unit area that varies depending on the number of stacked memory cells 10. The capacity can be increased.

[0092] Here, the structure of the selection transistor array 50 shown in FIG. The transistor array 50 is made up of m1×m2 select transistor cells 6 arranged in a matrix. 0, m2 wires RBL and WBL extending in the x-axis direction, and m2 wires RBL and WBL extending in the y-axis direction The selection transistor has m1 wirings SG1 and SG2 extending in the direction of the arrow. The transistor cells 60 are assigned coordinates on the xy plane, and the select transistor cell 60(1,1) In addition, the wiring RBL and wiring WBL are in the y-axis direction. The coordinates are given as wiring RBL[1] to [m2], wiring WBL[1] to [m2], etc. In addition, the wiring SG1 and wiring SG2 are given coordinates in the x-axis direction, and the wiring S G1[1] to [m1], and wiring SG2[1] to [m1].

[0093] Each select transistor cell 60 includes a transistor 61 and a transistor 62 . In the select transistor cell 60(i1, i2), the wiring RBL[i2] and the transistor The drain electrodes (or source electrodes) of 61 are electrically connected, and the wiring RBL[i1, i2 ] and the source electrode (or drain electrode) of the transistor 61 are electrically connected, and the wiring S G1[i1] and the gate electrode of the transistor 61 are electrically connected. In the transistor cell 60 (i1, i2), the wiring WBL[i2] and the transistor 62 The drain electrode (or source electrode) is electrically connected to the wiring WBL[i1, i2]. The source electrode (or drain electrode) of the transistor 62 is electrically connected to the wiring SG2 [ i1] and the gate electrode of the transistor 62 are electrically connected.

[0094] In this way, each selection transistor cell 60 is set corresponding to each memory cell string 20. The wiring RBL[i2] and the wiring RBL[1,i2] to [m1,i2] are connected. The on state is selected by the transistor 61 of each selection transistor cell 60, and the wiring WBL[i2] and the wiring WBL[1,i2] to [m1,i2] are connected to each of the select transistor cells 6 0 can be selected by transistor 62.

[0095] As shown in FIGS. 2 and 5, a driving circuit is provided around the selection transistor array 50. 51, a read circuit 52, a drive circuit 53 and a drive circuit 54 are provided. 1 is connected to the wiring RBL[1] to [m2] and the wiring WBL[1] to [m2]. The wirings RBL[1] to [m2] are also connected to the read circuit 52. 2, the driving circuit 53 includes wirings RWL[1,1] to [m1,m3] and The wirings WWL[1,1] to [m1,m3] are connected. The wirings SG1[1] to [m1] and the wirings SG2[1] to [m1] are connected to each other.

[0096] 2 and 5, a drive circuit 51, a read circuit 52, a drive circuit 53, and a drive circuit The semiconductor device shown in this embodiment has the above-described circuit 54 provided independently for each function. However, the present invention is not limited to this, and a plurality of circuits may be integrated into one circuit. A driving circuit 51, a readout circuit 52, a driving circuit 53, a driving circuit 54, and circuits connected to each circuit. The layout of the wiring is not limited to the configuration shown in FIG. 2 or FIG. 5, and may be appropriately changed according to the semiconductor device. Just set it.

[0097] In addition, the wirings SL[1,1] to [m1,m2] are connected to the two-dimensional memory cell array 3 in FIG. However, the present invention is not limited to this configuration. For example, multiple The lines SL may be divided into individual sections, or all of the lines SL may be electrically connected. The wirings SL[1,1] to [m1,m2] provide, for example, a ground potential GND or 0V. It is sufficient to connect it to the low power supply potential line that supplies the power.

[0098] In the semiconductor device shown in FIG. 2, a three-dimensional memory cell is provided on the select transistor array 50. The semiconductor device shown in this embodiment is configured to have a memory cell array 40. For example, a selection transistor array may be provided on the three-dimensional memory cell array 40. In this case, the transistor of the select transistor cell 60 The transistor 61 and the transistor 62 are made of, for example, an oxide semiconductor, similar to the transistor 12. It is sufficient to set it up.

[0099] In addition, peripheral circuits such as a drive circuit 51, a read circuit 52, a drive circuit 53, and a drive circuit 54 are A part of the circuit may be provided under the three-dimensional memory cell array 40. For example, A readout circuit may be provided in a matrix corresponding to the ring 20. In this case, the readout circuit and the selection transistor cell 60 are stacked in a matrix. That's fine.

[0100] Data writing, retention, and reading are basically the same as in Figure 1. In the three-dimensional memory cell array 40, first, the two-dimensional memory cell array 30[1] After selecting one of [m1] to [m2], data is written or read. , writing and reading data in the two-dimensional memory cell arrays 30[1] to [m1] This is done at least row by row. In other words, the specific write operation is as follows: In this example, the node FN is set to a potential V2 (a potential lower than the power supply potential VDD). This section explains the case where either the reference potential GND (sometimes expressed as 0V) is applied. However, the relationship of the potential applied to the node FN is not limited to this. When the reference potential GND is applied to the node FN, the data retained is data "1". The data held when this happens is data "0." Also, the reference potential GND is applied to the wiring SL. This shall be the case.

[0101] In writing data, first, one of the two-dimensional memory cell arrays 30 is selected. In selecting the two-dimensional memory cell array 30, the potential of the corresponding wiring SG2 is set to V1 (for example, For example, a transistor 62 electrically connected to the wiring is turned on as a power supply voltage Vdd. Lines WBL[1] to [m2] and the wiring WB included in the selected two-dimensional memory cell array 30 At this time, the potential of the unselected wiring SG2 is set to GND (0V), and the wiring Lines WBL[1] to [m2] and wiring WB included in the unselected two-dimensional memory cell array 30 L is in a non-conductive state.

[0102] Next, in the selected two-dimensional memory cell array 30, the memory cells in the row to be written are The potential of the wiring WWL connected to 10 is set to V3 (a potential higher than V2, for example, VDD). The transistor 12 of the memory cell 10 is turned on. The memory cell 10 stores data "0". When writing, GND is applied to the wiring WBL as a write potential, and When data "1" is written, a potential V2 is applied to the wiring WBL as a write potential. Here, the potential of the wiring WWL is V3, so the potential V2 can be applied to the node FN. It is possible.

[0103] To retain data, the potential of the wiring WWL connected to the memory cell 10 to be retained is set to GND. This is done by turning off the transistor 12 of the memory cell 10. When the potential of WWL is fixed to GND, the potential of node FN is fixed to the potential at the time of writing. That is, when the potential V2, which is data "1", is applied to the node FN, The potential of node FN becomes V2, and if GND, which is data "0", is applied to node FN, The potential of the FN terminal is GND.

[0104] In addition, since GND is given to the wiring WWL, either data "1" or data "0" can be written. Even if a deviation is written, the transistor 12 is in an off state. Since the off-state current is extremely small, the charge in the gate electrode of the transistor 11 remains constant for a long time. In this way, the node FN of the memory cell 10 to be held is set to the write potential. The corresponding data can be retained.

[0105] In reading data, first, one of the two-dimensional memory cell arrays 30 is selected. In selecting the two-dimensional memory cell array 30, the potential of the corresponding wiring SG1 is set to V1 (for example, For example, a transistor 61 electrically connected to the wiring is turned on as a power supply voltage Vdd. Lines RBL[1] to [m2] and the wiring RB included in the selected two-dimensional memory cell array 30 At this time, the potential of the unselected wiring SG1 is set to GND (0V), and the wiring Lines RBL[1] to [m2] and wiring RB included in the unselected two-dimensional memory cell array 30 L is in a non-conductive state.

[0106] Next, in the selected two-dimensional memory cell array 30, the memory cells in the row to be read are The potential of the wiring RWL connected to 10 is set to GND, and the capacitance element The other potential of the electrode 14 is set to GND. The potential of the wiring RWL connected to 0 is V4 (for example, VDD), and The potential of the other electrode of the capacitor 14 is set to V4.

[0107] If the potential of the wiring RWL connected to the memory cell 10 in the row to be read is GND, then A potential V2 representing data "1" is applied to the node FN of the memory cell 10 to be read. On the other hand, when the node FN has data "0", the transistor 11 is turned on. If the GND is applied, the transistor 11 is in an off state.

[0108] In addition, the potential of the wiring RWL connected to the memory cells 10 in the row that is not the target for reading is set to V4 Then, if data "1" is written to the memory cell 10 that is not the target for reading, In both cases where data "0" is written, the transistor 11 is in the ON state.

[0109] After applying a read potential (for example, VDD) to the wiring RBL, it is placed in an electrically floating state. When the transistor 11 of the memory cell 10 to be read is in the ON state, RBL and the wiring SL are electrically connected, and the potential of the wiring RBL drops. When the transistor 11 of the memory cell 10 is in an off state, the wiring RBL and the wiring SL Since the readout potential of the wiring RBL is not turned on, the readout potential of the wiring RBL is maintained. The data of the memory cell to be read can be read from the change in the read potential.

[0110] As a driving method, it is preferable to provide a batch erase operation for data for each block. For example, the two-dimensional memory cell array 30 may be one block. The two-dimensional memory cell array 30 to be erased is selected in the same manner as in the data write. The wiring WWL connected to the two-dimensional memory cell array 30 is connected to the transistor 1. By applying a voltage that turns on 2, it is possible to erase one block of data at once. can.

[0111] FIG. 6 shows an example of a timing chart relating to the detailed operation of the semiconductor device shown in FIG. The timing chart shown in FIG. 6 is for one of the rows of the two-dimensional memory cell array 30[1]. The first row of the two-dimensional memory cell array 30[1] is erased, and the first row of the two-dimensional memory cell array 30[2] is written. This shows the relationship between the potentials of the wirings when reading out the first row of the array 30[1]. The first row of the original memory cell array 30[1] is written to the two-dimensional memory cell array 30[1]. Data "1" is written to the memory cell in the first row and first column of the This is an operation of writing data "0" to the memory cells in the mth to m2th columns. The first row of the array 30[1] is read by writing data to the first row of the two-dimensional memory cell array 30[1]. This is the operation to read the data written in the memory of the first row and first column. The data “1” is stored in the memory cell, and the data “1” is stored in the memory cells of the other columns (the second column to the m2th column) of the first row. It is assumed that "0" is stored.

[0112] [Clear All] In the batch erase of the two-dimensional memory cell array 30[1], first, By applying a potential V1, the transistors of the select transistor cells 60(1,1) to (1,m2) are turned on. The switch 62 is turned on, and the wirings WBL[1] to [m2] are connected to the corresponding wirings WBL[1,1 ] to [1, m2] are connected to GND. Then, the transistors 62 of the select transistor cells 60(2,1) to (m1,m2) are turned on. and the wirings WBL[1] to [m2] are switched to the corresponding wirings WBL[2,1] to [m In this way, the two-dimensional memory is set as the target for the batch erase operation. Select the memory cell array 30[1].

[0113] In the two-dimensional memory cell array 30[1], the wiring WWL[1,1] to the wiring WWL[ A potential V3 is applied to the transistors 12 in the first to m3th rows to turn them on. At the same time, the wirings WBL[1] to [m2] are connected to GND, and the nodes F Set the potential of N to GND.

[0114] The wiring WW electrically connected to the two-dimensional memory cell arrays 30[2] to [m1] L[2,1] to [m1,m3] are GND, and memory cells 10(2,1,1) to ( The potential of the node FN of each of the nodes m1, m2, and m3 is maintained.

[0115] [write] In writing the first row of the two-dimensional memory cell array 30[1], first, The two-dimensional memory is used as the target for the write operation in the same manner as the bulk erase of the cell array 30[1]. The cell array 30[1] is selected.

[0116] In the two-dimensional memory cell array 30[1], a potential V3 is applied to the wiring WWL[1,1]. The transistors 12 in the first row are turned on, and the wirings WWL[1,2] to WWL[1,m3] are turned on. The transistors 12 in the second row to the m3th row are turned off by using GND. A potential V2 is applied to WBL[1], and the wirings WBL[2] to [m2] are set to GND. The wiring RWL[1,1] to [1,m3] can be set to GND.

[0117] As a result, the node of the memory cell 10 in the first row and first column of the two-dimensional memory cell array 30[1] The potential V2 is applied to the node FN, that is, the data "1" is written. In addition, the nodes FN in the first row, second column to the m2th column of the two-dimensional memory cell array 30[1] are set to 0. V is given, that is, data "0" is written.

[0118] As with the collective erasure of the two-dimensional memory cell array 30[1], Wiring WWL[2,1] to [m1,m3] electrically connected to I30[2] to [m1] ] is set to GND, and the nodes F of the memory cells 10(2,1,1) to (m1,m2,m3) The potential of N is maintained.

[0119] [reading] In the first row readout of the two-dimensional memory cell array 30[1], first, the wiring SG1[ 1] is applied with a potential V1 to activate the transistors of the select transistor cells 60(1,1) to (1,m2). The transistor 61 is turned on, and the wirings RBL[1] to [m2] are connected to the corresponding wirings RBL[ 1,1] to [1,m2]. Also, the wiring SG1[2] to [m1] is connected to As ND, the transistors 60(2,1) to (m1,m2) of the select transistor cells 1 is turned off, and the wirings RBL[1] to [m2] are turned on by the corresponding wirings RBL[2,1] to In this way, the two read operations are performed. 3. Select the 3-dimensional memory cell array 30[1].

[0120] In the two-dimensional memory cell array 30[1], the memory cell 10 in the first row to be read The wiring RWL[1,1] connected to is set to GND. A potential V4 is applied to the wiring RWL[1,2] to [1,m3] connected to the cell 10. The transistor 11 of the memory cell 10 is turned on.

[0121] Here, the read circuit 52 supplies VDD to the wiring RBL, and electrically floats the wiring RBL. To make it a state.

[0122] As a result, the memory cell 10 (1,1,1) in which data "1" is written is The wiring RBL[1] connected to the wiring SL[1,1] is electrically connected to the wiring SL[1,1], and the potential drops. , the memory cells 10(1,2,1) to (1) in which data “0” is written , m2,1) are connected to the wirings RBL[2] to [m2]. 1, m2] and is non-conductive, so the potential is VDD.

[0123] The wiring WWL[1,1] to [m1,m3] are connected to GND, and the memory cell 10 (1 , 1, 1) to (m1, m2, m3) hold the potentials of the nodes FN.

[0124] In the above-described method for driving a semiconductor device, binary (1-bit) data is stored in a memory cell. The above explanation was given for the case of writing data, but it is also possible to write three or more levels of information into one memory cell. For example, a memory cell may be configured to store four values ​​(2 bits), eight values ​​(3 bits), or ), 16-value (4-bit) data, etc. may be held.

[0125] In the semiconductor device described in this embodiment, the off-state current of a transistor including an oxide semiconductor is Because it is extremely small, it can be used to retain memory contents for an extremely long period of time. In other words, the refresh operation becomes unnecessary or the refresh operation is shortened. Since the frequency can be reduced to an extremely low level, power consumption can be reduced significantly. In addition, even if there is no power supply (however, it is desirable that the potential is fixed), Even if the memory card is used, it is possible to retain the stored contents for a long period of time.

[0126] In addition, the semiconductor device described in this embodiment does not require a high voltage for writing data. There is no problem of element degradation. For example, unlike conventional non-volatile memory, This eliminates the need to inject electrons into the floating gate or extract electrons from the floating gate. Therefore, the problem of deterioration of the gate insulating layer due to electron extraction does not occur. In the semiconductor device according to the present invention, the rewritable circuit which has been a problem in the conventional nonvolatile memory is There is no limit to the number of transistors, and reliability is dramatically improved. Since information is written depending on the state, high-speed operation can be easily achieved.

[0127] In the semiconductor device described in this embodiment, the memory cells are stacked, so that the number of stacked layers is Therefore, the memory capacity per unit area can be increased according to the In addition, the above-mentioned excellent characteristics can be obtained, and the performance is equivalent to that of conventional memories. Furthermore, it is possible to provide a semiconductor device having a larger storage capacity per unit area.

[0128] As described above, the configurations, methods, etc. shown in this embodiment may be different from the configurations, methods, etc. shown in other embodiments. They can be used in appropriate combinations.

[0129] (Embodiment 2) In this embodiment, the structure of a semiconductor device according to one embodiment of the present invention will be described with reference to FIGS. This will be explained using:

[0130] <Configuration of memory cells and memory cell arrays> A memory cell 10 and a three-dimensional memory cell array 4 in which a plurality of the memory cells 10 are arranged. The configuration of the three-dimensional memory cell array 400 will be described with reference to FIGS. 7 to 9. FIG. 7 shows the three-dimensional memory cell array 400. 8A is a three-dimensional schematic diagram of a three-dimensional memory cell array including a memory cell 10. 8(B), 9(A) and 9(B) are cross-sectional views of a part of the 1-A2. FIG. 8(B) is a plan view of the layer 140 shown in FIG. 8(A). FIG. 9(A) is a plan view of the layer 141 shown in FIG. 8(A). 7 to 9, the x-axis is the same as in FIG. For convenience, an orthogonal coordinate system consisting of y-axis, z-axis, and The upper surface of the substrate on which the array 40 is provided is approximately parallel to the xy plane, and the z axis is 7, the structure of a part of the memory cell 10 (for example, an insulating layer) 116, insulator 112, etc.) are omitted.

[0131] The memory cell arrays shown in FIGS. 8(A) and 8(B) and 9(A) and 9(B) are formed by An insulator 118 is disposed on top, a layer 142 is disposed on top of the insulator 118, and a layer 142 is disposed on top of the layer 142. An insulator 116 is disposed, a layer 140 is disposed on the insulator 116, and an insulator layer 140 is disposed on the layer 140. The insulating layer 112 is disposed on the insulating layer 112, and the layer 141 is disposed on the insulating layer 112. The stack includes at least the layer 142, the insulator 116, the layer 140, the insulator 112, and the layer 141 constitutes the memory cell 10. Here, the insulator 118 is The layer 142 is provided to sandwich the bottom and functions as an interlayer insulating film. 122, insulator 128, and insulator 129. Layer 140 also includes oxide 106 and Layer 141 also includes conductor 114, insulator 126, and insulator 130. It has an edge 127.

[0132] A first opening is provided through the laminate, and an insulator 132 is disposed inside the first opening. An oxide 134 is disposed inside the insulator 132. Also, a third insulating layer 134 is disposed through the stack. A second opening is provided, and a conductor 120 is disposed inside the second opening. A third opening is provided through the insulating material 138, and an insulator 138 is disposed inside the third opening. The first opening and the second opening are vertical hole-shaped openings extending in the z-axis direction. The third opening is a groove-shaped opening extending in the z-axis direction and the y-axis direction. .

[0133] Therefore, the insulator 132 and the oxide 134 extend in the z-axis direction in the same manner as the first opening. The insulator 132 and the oxide 134 are formed in a columnar shape. The insulator 132 and the oxide 134 are formed in the memory cell string 2 shown in FIG. 0, corresponds to a part of a plurality of transistors 11 electrically connected in series.

[0134] Here, the first opening in which the transistor 11 is provided has a circular top surface in FIG. 8(B) and the like. However, the shape is not limited to this. For example, the upper surface may be elliptical. The shape may be a polygon such as a triangle or a rectangle. In the case of a polygonal shape, the corners may be rounded. Alternatively, the insulator 132 and the first opening may be formed in a shape that matches the shape of the top surface of the first opening. The top surface shape of the oxide 134 may also change. The cross-sectional area perpendicular to the z-axis of the opening on the lower side (substrate side) is narrower than the cross-sectional area perpendicular to the z-axis. It may also be in the form of

[0135] The conductor 120 is provided so as to extend in the z-axis direction in the same manner as the second opening. The conductor 120 is shared by the memory cells 10 arranged in the direction. The conductor 120 is formed as the wiring WBL shown in FIG. 8 and 9, the insulator 132 and the oxide 134 The conductors 120 are arranged side by side in the x-axis direction, but are not limited to this. For example, , the insulator 132 and the oxide 134 are arranged next to the conductor 120 at an angle from the x-axis direction. You may do so.

[0136] Here, the second opening in which the conductor 120 is provided has a circular upper surface in FIG. However, the present invention is not limited to this. For example, the upper surface may be elliptical or triangular. The shape may be polygonal, such as rectangular or square. In the case of a polygonal shape, the corners may be rounded. The upper surface of the conductor 120 may be shaped to match the upper surface shape of the second opening. The shape may also vary. Also, the second opening may have a lower ( The cross-sectional area of ​​the opening on the substrate side may be narrower.

[0137] The insulator 138 is provided extending in the z-axis direction and the y-axis direction in the same manner as the third opening. It can also be said that the insulator 138 is formed in a wall shape. It is preferable that 8 has a relatively low relative dielectric constant.

[0138] Here, as shown in FIG. 9(A), in the layer 141, the conductor 114 is The conductors 114 are arranged in the y-axis direction. In the memory cell 10, the wiring WWL shown in FIG. 3 is shared. The conductor 114 is penetrated by the conductor 120, and the conductor 114 and the conductor Between the conductor 120 and the insulator 126, an insulator 126 is formed so as to surround the periphery of the conductor 120. For example, The insulator 126 may be formed by oxidizing the side surface of the conductor 114. 6 is formed, the conductor 114 functions as the wiring WWL and the In addition, the conductor 114 is an insulator. The insulating layer 132 and the oxide 134 are penetrated, and the insulating layer 132 is formed between the conductor 114 and the insulating layer 132. In this case, the insulator 127 is formed so as to surround the insulator 132. For example, the insulator 127 The side surface of the conductor 114 may be oxidized.

[0139] Also, as shown in FIG. 9B, in the layer 142, the conductor 122 is an insulator 138. The conductors 122 are arranged in the y-axis direction. In the memory cell 10, it is shared and has the function of the wiring RWL shown in FIG. In addition, the conductor 122 is penetrated by the conductor 120, and the conductor 122 and the conductor 1 Between the conductor 120 and the insulating material 128, an insulator 128 is formed so as to surround the conductor 120. For example, The insulator 128 may be formed by oxidizing the side surface of the conductor 122. By forming the conductor 122 which functions as the wiring RWL and the conductor 123 which functions as the wiring WBL, This prevents the functional conductor 120 from shorting out. The conductor 122 is penetrated through the insulator 132 and the oxide 134. The insulator 129 is formed so as to surround the insulator 132. For example, the insulator 129 is It can be formed by oxidizing the side surface of the conductor 122 .

[0140] Although not shown, the conductors 114 and 122 are formed such that the lower conductor is connected to the upper conductor. It is preferable that the conductive layer is provided in a stepped manner, extending further in the y-axis direction from the conductive layer. By providing the conductive body 114 and the conductive body 122, a part of the upper surface of the lower conductive body is Since the conductor does not overlap with the conductor in the upper layer, the conductor in the region of each layer and the conductor provided in the form of a plug can be connected.

[0141] As shown in FIG. 8B, in the layer 140, the insulator 130 is divided into the insulator 138. The insulating member 130 and the insulating member 13 are cut and extend in the y-axis direction. The oxide 106 is provided so as to be surrounded by the insulator 130. The insulator 132 and the oxide 134 are arranged in a circular shape with the conductor 120 at the center. The conductor 120 is provided so that at least a part of it penetrates the oxide island 106. , oxide 106, insulator 132 and oxide 134, and conductor 120 form insulator 1 30 and the insulator 138. The oxide 106, the insulator 132, the oxide 134, and the conductor 120 are separated by the insulator 130. The oxide 106 is cut and aligned in the y-axis direction. A region 109a is formed adjacent to the conductive material 120, and a region 109b is formed adjacent to the conductive material 120. a and region 109b are regions of lower resistance than other regions of oxide 106.

[0142] The stacked bodies are repeatedly stacked in the z-axis direction, so that the memory cells 10 are arranged in the z-axis direction. The memory cells 10 are arranged in the z-axis direction, and are the same as the memory cell stack shown in the above embodiment. 8(B), 9(A) and 9(B), The oxide 106, the insulator 132, the oxide 134, and the conductor 1 are surrounded by the insulator 138. 20 and so on are repeatedly arranged in the y-axis direction, so that the memory cells 10 are arranged in the y-axis direction. Similarly, the memory cell strings 20 are also arranged in the y-axis direction. The two-dimensional memory cell array 30 shown in the above embodiment is configured. 1, the blocks sandwiched between the insulators 138 are repeatedly arranged in the x-axis direction, Similarly, the two-dimensional memory cell array 30 is also arranged in the x-axis direction. The two-dimensional memory cell array 30 is similar to the three-dimensional memory cell array 4 shown in the above embodiment. Configure 0.

[0143] The memory cell 10 shown in FIGS. 8(A), 8(B), and 9(A) and 9(B) includes a transistor 11, a transistor It has a transistor 12 and a capacitance element 14 .

[0144] The transistor 12 includes an oxide 106 disposed on an insulator 116 and a gate insulating film 118 formed on the oxide 106. an insulator 112 disposed on the oxide 106 region 106; and a conductor 114 overlapping at least a portion of the region sandwiched between the region 109a and the region 109b. Note that an insulator 118 functioning as an interlayer insulating film is provided over the transistor 12. It is preferable that the insulator 118 has a relatively low dielectric constant.

[0145] Here, the region 109a functions as either the source or the drain of the transistor 12. The region 109b functions as the other of the source and drain of the transistor 12. The region of oxide 106 located between region 109a and region 109b is the region of transistor 12. The insulator 112 functions as a channel forming region. The conductor 114 functions as the gate of the transistor 12. .

[0146] The oxide 106 of the transistor 12 is surrounded by an insulator 130 and an insulator 138. The oxide 106 of the other transistors 12 is isolated from the other transistors 12. The oxides 106 of the transistors 12 connected to the electrodes 114 are prevented from contacting each other. This can be done.

[0147] The oxide 106 is a metal oxide that functions as an oxide semiconductor (hereinafter, also referred to as an oxide semiconductor). It is preferable to use oxide semiconductors, which are superior to semiconductors made of silicon and the like. This is preferable because the transistor has good on-state characteristics and high mobility.

[0148] For example, the oxide 106 may be an In-M-Zn oxide (wherein the element M is aluminum, gallium, etc.). Smoke, yttrium, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium Rumanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, Tantalum, tungsten, magnesium, etc.) In addition, an oxide semiconductor such as In—Ga oxide or I n-Zn oxide may also be used.

[0149] In addition to the elements that make up the oxide semiconductor, the oxide semiconductor also contains aluminum, ruthenium, and By adding metal elements such as aluminum, titanium, tantalum, chromium, and tungsten, Preferably, aluminum, titanium, or tantalum is used to form a metal compound and reduce the resistance. , tungsten, etc. are used.

[0150] To add a metal element to an oxide semiconductor, for example, the metal element is deposited on the oxide semiconductor. a metal film containing a metal element, a nitride film containing a metal element, or an oxide film containing a metal element may be provided. In addition, by providing the film, a metal oxide film can be formed at the interface between the film and the oxide semiconductor or in the vicinity of the interface. A part of the oxygen in the oxide semiconductor located at the boundary is absorbed into the film, etc., forming oxygen vacancies. The resistance near the surface may become low.

[0151] Further, a metal film, a nitride film containing a metal element, or a nitride film containing a metal element may be formed over an oxide semiconductor. After the oxide film is formed, heat treatment may be performed in an atmosphere containing nitrogen. By the heat treatment of the above, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element is formed. , a metal element that is a component of the film is converted into an oxide semiconductor, or a metal that is a component of an oxide semiconductor is converted into an oxide semiconductor. The element diffuses into the film, and the oxide semiconductor and the film form a metal compound, resulting in a low resistance. The metal element added to the oxide semiconductor can be a metal element of the oxide semiconductor and By forming a metal compound, a relatively stable state is created, making it possible to create highly reliable semiconductor devices. can be provided.

[0152] In addition, a metal film, a nitride film containing a metal element, or an oxide film containing a metal element and an oxide semiconductor A compound layer may be formed at the interface with the conductor. The compound layer may be a metal film, a metal A nitride film containing an element or an oxide film containing a metal element and an oxide semiconductor component are mixed. For example, the compound layer may be a layer containing a metal compound containing a metal element of an oxide semiconductor. The added metal element may form an alloy layer. This provides a relatively stable state and a highly reliable semiconductor device.

[0153] Furthermore, hydrogen present in the oxide semiconductor diffuses into the low-resistance region of the oxide semiconductor, When the oxygen enters the oxygen vacancy in the resistive region, it becomes relatively stable. The hydrogen in the oxygen vacancies in the oxide semiconductor is converted into oxygen vacancies by heat treatment at 250°C or higher. The oxide semiconductor is then released from the low-resistance region, diffuses into the low-resistance region, and exists in the low-resistance region. It is known that the oxygen vacancies are contained in the crystals and become relatively stable. Therefore, the region of the oxide semiconductor where the resistance is reduced or the region where the metal compound is formed has a lower resistance. Oxide semiconductors that have become resistive and have not become low-resistive are highly purified (reduced impurities such as water and hydrogen) ) and tends to have a higher resistance.

[0154] In addition, when an impurity element such as hydrogen or nitrogen is present in an oxide semiconductor, the carrier density decreases. The hydrogen in the oxide semiconductor reacts with the oxygen that bonds with the metal atoms to form water, Oxygen vacancies may be formed. When hydrogen enters these oxygen vacancies, the carrier density increases. In addition, some of the hydrogen bonds with oxygen, which bonds with metal atoms, to generate electrons, which act as carriers. That is, the resistance of an oxide semiconductor containing nitrogen or hydrogen is reduced.

[0155] Therefore, a metal element and impurity elements such as hydrogen and nitrogen are added to an oxide semiconductor. By selectively adding the element, it is possible to form a high-resistance region and a low-resistance region in the oxide semiconductor. In other words, by selectively reducing the resistance of the oxide 106, the oxide 106 processed into an island shape can be 06, there is a region that functions as a semiconductor with low carrier density, and a source region or drain region. By providing low resistance regions (regions 109a and 109b) that function as This can be done.

[0156] For example, an oxide film containing a metal element for reducing the resistance of the region 109a, or a metal element The nitride film having the above structure can be used as an interlayer insulating film or a gate insulating film. Specifically, the insulator 132 may be a nitride film containing a metal element, or a gold film. By using an oxide film containing a metal element, the region of the oxide 106 in contact with the insulator 132 The region 109a can be provided by lowering the resistance of the region 109a. Since the resistance can be reduced and the insulator 132 can be formed at the same time, the process can be shortened. can.

[0157] On the other hand, the metal film for reducing the resistance of the region 109a is preferably 0.5 nm or more and 5 nm or less. Preferably, a metal film having a thickness of 1 nm or more and 2 nm or less may be used. When the oxygen is absorbed into the metal film, the metal film is oxidized, and oxygen deficiency occurs in the region 109a. In other words, the metal film becomes highly resistant when oxidized, and the region 109a has oxygen deficiency. This results in a lower resistance.

[0158] In addition, it is preferable to perform a heat treatment in order to completely oxidize the metal film. The treatment is preferably carried out in an oxidizing atmosphere. After the treatment, a heat treatment may be performed in an atmosphere containing oxygen. When there is a structure containing oxygen nearby, the metal film is heated to remove the oxygen contained in the structure. If the metal film is completely oxidized, it will become an insulator. The oxidized metal film can be used as the insulator 132. Therefore, the resistance of the region 109a can be reduced and the insulator 132 can be formed at the same time. , the process can be shortened.

[0159] In addition, for example, a metal film for reducing the resistance of the region 109b, a nitride film containing a metal element, Alternatively, the oxide film containing a metal element may be used as a conductive material for wiring or a plug. Specifically, the conductor 120 may be made of a metal film or a nitride film containing a metal element. Alternatively, by using an oxide film containing a metal element, the conductor 120 in the oxide 106 can be formed. The contact region is made to have a low resistance, so that the region 109b can be provided. The process can be shortened because the resistance of 109b can be reduced and the conductor 120 can be formed at the same time. In this case, the diameter of the second opening where the conductor 120 is provided is set to be sufficiently large, for example. For example, by setting the thickness to about 10 nm or more and 200 nm or less, the region 109b is formed by heat treatment. Even if this occurs, the conductivity of the conductor 120 can be sufficiently maintained.

[0160] The region between the region 109a and the region 109b functions as a channel forming region. The regions are region 109a and region 109b, which function as source and drain regions. The region 109a is a high-resistance region having a higher oxygen concentration and a lower carrier density than the region 109b. The region between the region 109a and the region 109b is composed of metal elements and impurity elements such as hydrogen and nitrogen. It is preferable that at least one of the concentrations is lower than the concentration in the region 109a and the region 109b. As shown in Fig. 1, the region of the oxide 106 that can function as a channel is formed by using a low impurity concentration and a high oxygen concentration. By producing a highly pure intrinsic or substantially highly pure intrinsic oxide semiconductor with a high purity, The off-current of the transistor 12 can be reduced.

[0161] The oxide 106 may be formed by stacking oxides with different energy gaps. For example, as oxide 106, a narrow-gap oxide is formed into two layers of wide-gap oxide. It is sufficient to have a laminated structure sandwiched between the oxides. -gap oxides refer to oxides with a wide energy gap, and narrow-gap oxides refer to oxides with a narrow energy gap. Therefore, wide-gap oxides are relatively The oxide has a wide energy gap. The energy of the conduction band edge can be higher than that of the narrow-gap oxide. In other words, it is preferable that the electron affinity of the wide gap oxide is smaller than that of the narrow gap oxide. It is preferable that the electron affinity is smaller than that of the oxide.

[0162] In addition, wide-gap oxides and narrow-gap oxides have different atomic ratios of each metal atom. Specifically, it is preferable to use a combination of metal oxides that are In the oxide, the atomic ratio of element M among the constituent elements is It is preferable that the atomic ratio of element M in the constituent elements of the oxide is larger than that of element M. In the metal oxide used for the band gap oxide, the atomic ratio of element M to In is narrow. In the metal oxide used for the gap oxide, the atomic ratio of element M to In is larger than that In addition, in the metal oxide used for the narrow gap oxide, the element M is preferably The atomic ratio of In to element M in the metal oxide used for the wide-gap oxide is It is preferable that the atomic ratio of In to Si is larger than that of Si.

[0163] Wide-gap oxides include, for example, In:Ga:Zn=1:3:4, In:Ga:Zn =1:3:2, or In:Ga:Zn=1:1:1 or a composition close to that In addition, narrow gap oxides such as In:G a:Zn=4:2:3 to 4.1, In:Ga:Zn=1:1:1, or In:Ga: Metal oxides having a composition of Zn=5:1:6 or a composition close to that can be used. These wide-gap oxides and narrow-gap oxides are classified into It is preferable to combine them in a manner that satisfies the above requirements. or the atomic ratio in the sputtering target.

[0164] In addition, CAAC-OS, which will be described later, was used as a wide-gap oxide, and narrow-gap It is preferable to use CAC-OS as the oxide.

[0165] Oxide 106 is a narrow-gap oxide sandwiched between two layers of wide-gap oxide. When using a laminated film, carriers mainly flow in the narrow gap portion. , a high current driving force in the on-state of the transistor 12, i.e., a large on-current, and a high High field effect mobility can be obtained.

[0166] Here, at the junction between the wide-gap oxide and the narrow-gap oxide, the conduction band minimum In other words, the junction between the wide-gap oxide and the narrow-gap oxide The conduction band edge at the junction can be said to change continuously or to be a continuous junction. In order to achieve this, at the interface between the wide-gap oxide and the narrow-gap oxide, It is preferable to reduce the defect level density of the mixed layer to be formed.

[0167] Specifically, wide-gap oxides and narrow-gap oxides share common elements other than oxygen. By containing (as a main component), a mixed layer with a low density of defect states can be formed. For example, if the narrow-gap oxide is In-Ga-Zn oxide, the wide-gap oxide As the oxide, In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, etc. may be used. This allows us to determine the defect level at the interface between the wide-gap oxide and the narrow-gap oxide. The density can be reduced, so the effect of interface scattering on carrier conduction is small. As a result, the transistor 12 can obtain a high on-state current.

[0168] For a more detailed description of metal oxides that can be used as the oxide 106, see , as will be described later.

[0169] The side surface of the conductor 114 facing the oxide 134 is the same as the side surface of the conductor 122 facing the oxide 134. Therefore, it is preferable that the conductive material 114 is located on the side of the conductive material 120. The insulator 127 formed on the side of the conductor 122 is thicker than the insulator 129 formed on the side of the conductor 122. Alternatively, the side surface of the conductor 122 facing the oxide 134 may be etched. In this case, the conductor 122 and the conductor 114 are oxidized or etched at the same time, so that the conductor 1 The conductive material 14 is different from the conductive material 122, and the oxidation rate or etching rate of each is different. By doing so, the conductor 114 is This can reduce interference.

[0170] The transistor 11 comprises a region 109a of oxide 106, an insulator 132, and an oxide 134. The insulator 132 and the oxide 134 are formed in a cylindrical opening in the laminate. The insulator 132 is formed in a cylindrical shape in contact with the inside of the opening. The oxide 134 is formed in a cylindrical shape inside the insulator 132. An insulator may be further provided on the side.

[0171] In addition, when an insulator is provided inside the oxide 134, the insulator may be used to prevent oxygen from entering the oxide 134. It is preferable that the material is a material that can supply impurities such as hydrogen and nitrogen. By using oxides that contain as little hydrogen and nitrogen as possible as the insulator, the oxide 134 By supplying oxygen to the oxide 134, Impurities such as hydrogen and water contained in the oxide 134 can be removed, and the oxide 134 becomes highly purified. By using an oxide with as few impurities as possible as the oxide 134, A semiconductor device including the transistor can have high reliability. By using an oxide containing hydrogen or nitrogen as the insulator, the oxide 134 contains hydrogen and nitrogen. By supplying hydrogen or nitrogen to the oxide 134, the oxide 134 The resistance of the oxide 134 may decrease to a level that does not adversely affect the circuit operation. By lowering the voltage, the transistor 11 can be operated at a lower drive voltage. In the on-state of the transistor 11, a high current driving force, i.e., a large on-current, and a high High field effect mobility can be obtained.

[0172] A conductor may be provided inside the insulator. The potential applied to the back gate is applied to the conductor 114 (top gate). By changing the potential applied to the transistor 11 independently of the potential applied to the gate, The threshold voltage can be controlled by applying a negative potential to the back gate. In this case, the threshold voltage of the transistor 11 can be set to be higher than 0 V, thereby reducing the off-state current. do.

[0173] Here, the region 109a of the oxide 106 functions as the gate of the transistor 11. The insulator 132 functions as a gate insulating film of the transistor 11, and the oxide 134 The oxide film functions as a channel forming region, a source, and a drain of the transistor 11. In the object 134, the region overlapping with the region 109a of the oxide 106 in the x-axis direction is the transistor The region 109a of the oxide 106 functions as a channel forming region of the oxide 106, and does not overlap with the region 109a of the oxide 106 in the x-axis direction. (This may be referred to as the region overlapping with the insulator 116 or the insulator 112 in the x-axis direction.) functions as the source or drain of the transistor 11.

[0174] The oxide 134 is preferably formed using an oxide semiconductor similar to that of the oxide 106. Compared to semiconductors made of silicon, etc., semiconductors have better on-state characteristics of transistors. This is preferable because high mobility can be obtained.

[0175] Furthermore, for example, oxide 134 may be a narrow gap oxide, similar to oxide 106. The oxide 13 may be sandwiched between two wide-gap oxide layers. 4, a stacked film in which a narrow-gap oxide is sandwiched between two layers of wide-gap oxide is used. When the gate is narrow, the carriers flow mainly in the narrow gap. In the on-state of the transistor 11, a high current driving force, i.e., a large on-current, and a high field effect transfer You can get mobility.

[0176] Note that, between the region of the oxide 134 that functions as a source or drain and the conductor 114, Since an insulator 127 is provided, the source and drain of the transistor 11 and It is possible to reduce the parasitic capacitance between the conductor 114 functioning as the wiring WWL. The insulating layer 134 is formed between the region of the oxide 134 that functions as a source or drain and the conductor 122. Since the insulator 129 is provided, the source and drain of the transistor 11 and the wiring R It is possible to reduce the parasitic capacitance between the conductor 122 functioning as the WL.

[0177] In this way, the transistor 11 is formed by insulating the oxide 134 at least partially around the oxide 134. A region 109a of oxide 106 that functions as a gate electrode is formed so as to surround the gate electrode 109a via the gate electrode 2. In the oxide 134 of the transistor 11, the channel length is determined by the thickness of the oxide 106. The length of the channel of the transistor 11 is approximately the same as the z-axis direction. As shown in FIG. 8A, the channel length direction of the transistor 11 is parallel to the z-axis. and perpendicularly intersects with the channel length direction of the transistor 12. The channel width is the width of the portion of the circumference of the columnar oxide 134 that is covered by the region 109a. It is roughly the same length as a minute.

[0178] As shown in FIG. 8(A), the insulator 132 and the oxide 134 are formed to extend in the z-axis direction. The memory cells 10 are arranged in the z-axis direction and are shared by the memory cells 10. The region of the compound 134 that functions as the source or drain of the transistor 11 is z It is shared between the transistors 11 adjacent in the axial direction. In the memory cell 10, the transistors 11 are electrically connected in series. do.

[0179] In this manner, the insulator 132 and the oxide 134 form a single memory cell string. 20 are formed together. For example, transistor 1 If 1 is formed using standard planar transistors, plugs and wiring are required for each layer. However, this structure was As a result, the sources and drains of the plurality of transistors 11 are electrically connected in series in a self-aligned manner. A connected structure can be formed.

[0180] Generally, a memory string consists of multiple memory transistors electrically connected in series. Therefore, as the number of memory transistors increases, the on-resistance of each memory transistor increases. This reduces the on-current of the entire memory string. In the semiconductor device shown in the embodiment, an oxide semiconductor having a large on-current and a high field-effect mobility is Since the transistors 11 using the nitride semiconductor are electrically connected in series, the memory cell strip This can reduce the decrease in on-current in the transistor 11 portion of the ring 20.

[0181] In the oxide 134 of the uppermost memory cell 10, the upper surface of the oxide 134 and A conductor electrically connected to the low power supply potential line is formed so as to contact the wiring SL. Also, the oxide 134 of the memory cell 10 at the bottom is formed by the transistor 6. The connection with 1 will be described later.

[0182] 8(A) and 8(B), the first opening is formed so that a part of the first opening penetrates the oxide 106. However, the semiconductor device described in this embodiment is not limited to this. For example, as shown in FIGS. 10(A) and 10(B), the first opening is formed so that the entire first opening penetrates the oxide 106. In this case, the entire periphery of the oxide 134 may be surrounded by the insulator 132. Surrounding this is formed a region 109a of oxide 106 which functions as a gate electrode. In this case, the transistor 11 becomes an SGT, and the channel width of the transistor 11 is a cylindrical The length is approximately the same as the circumference of the oxide 134. This can provide high current and high mobility.

[0183] In a standard planar transistor, the gate electrode, source electrode, and A drain electrode is formed, and in the transistor 11, the inside of the gate electrode is At least a part of the other structure is formed on the side, and the occupied area is very small. In this way, the area occupied by the transistor 11 can be made very small. The area occupied by the memory cell 10 is reduced, and the storage capacity per unit area of ​​the semiconductor device is increased. It is possible to increase

[0184] In addition, as in the case of the transistor 11 in FIG. 8, the source electrode and the drain electrode are not explicitly provided. However, for convenience, such a state may be included in the term "transistor." .

[0185] In addition, the oxide 106 is in contact with the conductor 120 in the region 109b, and the transistor The other of the source or drain of the capacitor 12 is connected to the wiring WBL. In the conductor 120 of the memory cell 10, the upper surface of the conductor 120 functions as the wiring SL. It is preferable to cover it with an insulator to prevent it from coming into contact with other conductive materials. The connection of the conductor 120 of the recell 10 to the transistor 62 will be described later.

[0186] The capacitance element 14 is made up of a conductor 122 disposed on an insulator 118 and a an insulator 116 disposed on the insulating layer 116; and a conductive layer 116 disposed on at least a portion of the region 109a. The region 109a has an oxide 106 that overlaps with the conductor 122. The conductor 122 functions as one of the electrodes of the capacitor 14. The insulator 116 only needs to function as a dielectric of the capacitance element 14, and has a relatively high relative dielectric constant. It is preferable to use a high insulator.

[0187] As mentioned above, region 109a of oxide 106 functions as the gate in transistor 11. However, in the transistor 12, it functions as either a source or a drain, and in the capacitor 14, it functions as a That is, the region 109a of the oxide 106 functions as one of the electrodes shown in FIG. As mentioned above, the off-state current of the transistor 12 is very low, so The charge related to the data held in the node FN can be held for a long period of time.

[0188] In this way, by turning off the transistor 12, data is retained. The gate insulating film (TFT) has been pointed out as a problem in conventional floating gate transistors. In other words, there is no problem of deterioration of the insulating film (channel insulation film) that was previously considered a problem. This solves the problem of gate insulating film deterioration when implanting ions into the floating gate. This means that there is no theoretical limit to the number of times that data can be written.

[0189] The side surface of the conductor 122 facing the conductor 120 is the same as the side surface of the conductor 114 facing the conductor 120. Therefore, it is preferable that the oxide 134 be located on the side of the conductor 122. The insulator 128 formed on the side of the conductor 114 is thicker than the insulator 126 formed on the side of the conductor 114. Alternatively, the side surface of the conductor 122 on the conductor 120 side may be etched. In this case, the conductor 122 and the conductor 114 are oxidized or etched at the same time, so that the conductor 1 The conductive material 22 is different from that of the conductive material 114, and the oxidation rate or etching rate of each is different. In this way, the conductor 122 of the transistor 12 This can reduce interference with

[0190] As shown in FIG. 8B etc., in the above, the insulators 138 are arranged in the y-axis direction between the pair of insulators 138. Although an example in which the memory cells 10 are arranged and the memory cells 10 are not arranged in the x-axis direction has been shown, The semiconductor device described in this embodiment is not limited to this. As shown in the figure, the memory cells 10 are arranged in a grid pattern in the x-axis and y-axis directions between a pair of insulators 138. It may also be configured to be arranged in an array.

[0191] FIG. 11 is a plan view of layer 140, which shows a 3×3 memory cell array between a pair of insulators 138. 5. The circuit of the selection transistor array shown in FIG. The memory cells 10, the wirings RBL[1] to RBL[3], and the wirings WBL[1] to WBL[3] are shown overlapping. [3], wiring SG1[1] to [3], wiring SG2[1] to [3], and selection transistors 11 shows the connection with the resistor cell 60. Note that in FIG. 11, between a pair of insulators 138, Although an example in which 3×3 memory cells 10 are provided is shown, the semiconductor device shown in this embodiment The arrangement is not limited to this, and may be changed according to the circuit configuration and driving method of the memory cell array. The number and arrangement of memory cells, wiring, etc. can be set as appropriate.

[0192] As shown in FIG. 11, each memory cell 10 is connected to a corresponding select transistor cell 60. The oxide 134 of the memory cell 10 is connected to the wiring RBL via the transistor 61. Here, the wiring RBL is extended in the x-axis direction and is arranged in the x-axis direction. The select transistor cell 60 and the memory cell 10 are shared by the same. The conductor 120 of No. 0 is electrically connected to the wiring WBL through the transistor 62. The wiring WBL is extended in the x-axis direction, and the select transistor cells arranged in the x-axis direction 60 and memory cell 10.

[0193] The gate of the transistor 61 is electrically connected to the wiring SG1 extending in the y-axis direction. Here, the wiring SG1 extending in the y-axis direction is connected to the selection transistors arranged in the y-axis direction. The gate of transistor 62 is shared by the first cell 60 and the memory cell 10. The wiring SG2 is electrically connected to the wiring SG1 extending in the y-axis direction. The wiring SG2 is common to the select transistor cells 60 and the memory cells 10 arranged in the y-axis direction. It is owned.

[0194] In FIG. 11, layer 140 is shown, but layers 141 and 142 also have a set of insulating layers at the same intervals. In other words, the 3×3 memory cells 10 shown in FIG. 11. Therefore, the 3×3 metal layers shown in FIG. The memory cell 10 is connected to the same wiring WWL and wiring RWL.

[0195] However, as described above, the wiring RBL and the wiring WBL, the wiring SG1 and the wiring By arranging SG2 and SG3 at right angles to each other, the wiring RBL and wiring WBL are targeted. The y coordinate of the memory cell 10 is selected, and the target memory cell is connected to the wiring SG1 and the wiring SG2. In this way, the x-coordinate of memory cell 10 can be selected as shown in FIG. Even if the 3×3 memory cells 10 are arranged, writing and writing to any memory cell 10 is not possible. and readout can be performed.

[0196] In FIG. 11, the memory cells 10 are arranged in a lattice pattern. For example, as shown in FIG. 12, the memory cells 10 may be arranged in a staggered pattern. It may be placed.

[0197] FIG. 12 is a plan view of layer 140, which shows a 4×4 memory cell array between a pair of insulators 138. 5. The circuit of the selection transistor array shown in FIG. The memory cells 10, the wirings RBL[1] to RBL[4], and the wirings WBL[1] to WBL[4] are shown overlapping. [4], wiring SG1[1] to [4], wiring SG2[1] to [4], and selection transistors 12 shows the connection with the register cell 60. The select transistor cell 60, the wiring RBL, the wiring WBL, the wiring SG1, and the wiring Although the number of lines SG2 is different, the connection relationship is the same as that of the memory cell array shown in FIG. In addition, in FIG. 12, a 4×4 insulator is provided between a pair of insulators 138. 10 memory cells 10 are provided, the semiconductor device shown in this embodiment is However, the present invention is not limited to this, and memory cells may be configured in accordance with the circuit configuration and driving method of the memory cell array. The number and arrangement of cells, wiring, etc. can be set as appropriate.

[0198] Therefore, in the memory cell array shown in FIG. 12, the wiring RBL and the wiring WBL, By providing the wiring SG1 and the wiring SG2 perpendicular to each other, the wiring RBL and the wiring The y coordinate of the target memory cell 10 is selected by the line WBL, and the y coordinate of the target memory cell 10 is selected by the lines SG1 and SG2. The x-coordinate of the target memory cell 10 can be selected. Even if the memory cells 10 are arranged in this manner, any memory cell among the 4×4 memory cells 10 can be It is possible to write to and read from the module 10.

[0199] However, in the memory cell array shown in FIG. 12, when viewed from the y-axis direction, the memory cells 10 The pixels are arranged alternately, that is, shifted in the x-axis direction for each column. The memory cells 10 can be densely arranged, thereby reducing the area occupied by the memory cell array. As a result, the semiconductor device can be highly integrated.

[0200] In the memory cell array shown in FIGS. 11 and 12, the conductor 120 and the insulator Since there are many memory cells 10 in which the distance 138 is sufficiently large, the acid contained in the memory cell In many cases, the top surface of the compound 106 has a substantially circular shape. Among the memory cells, the memory cell 10 closest to the insulator 138 (for example, in FIG. 12, The conductor 120 of the memory cell 10 connected to the wiring SG1[4] and the wiring SG2[4] The distance between the oxide 106 and the insulator 138 is reduced so that the oxide 106 is in contact with the insulator 138. The memory cell array may be integrated.

[0201] <Materials for semiconductor devices> Constituent materials that can be used in the semiconductor device described in this embodiment mode will be described below. do.

[0202] <<Insulators>> Insulators include oxides, nitrides, oxynitrides, nitride oxides, and metal oxides that have insulating properties. The insulator shown in this embodiment has the function of Depending on the function, the insulating material can be selected from the following and formed as a single layer or a laminate.

[0203] For example, as transistors become smaller and more highly integrated, the gate insulator becomes thinner. This can cause problems such as leakage current. By using high-k materials, the voltage required for transistor operation can be reduced while maintaining the physical film thickness. On the other hand, it is possible to use a material with a low relative dielectric constant for the insulator that functions as the interlayer film. This reduces the parasitic capacitance between the wirings. Therefore, materials should be selected accordingly.

[0204] Insulators with high dielectric constants include gallium oxide, hafnium oxide, and zirconium oxide. oxides with aluminum, aluminum and hafnium, oxides with silicon and hafnium, oxides with silicon and hafnium, Examples include oxide nitrides with hafnium or nitrides with silicon and hafnium. For example, such an insulator may be used as the insulator 116.

[0205] Insulators with low dielectric constants include silicon oxide, silicon oxynitride, and silicon nitride oxide. Silicon, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, Examples include silicon oxide doped with carbon and nitrogen, silicon oxide with pores, or resin. do.

[0206] In particular, silicon oxide and silicon oxynitride are thermally stable. For example, by combining it with resin, it is possible to create a laminated structure that is thermally stable and has a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (nylon), Polyimide, polycarbonate, acrylic, etc. For example, silicon oxide and silicon oxynitride can be combined with insulators with high dielectric constants. By doing so, it is possible to obtain a laminated structure that is thermally stable and has a high relative dielectric constant.

[0207] In addition, a transistor using an oxide semiconductor can suppress the permeation of impurities such as hydrogen and oxygen. By surrounding the transistor with an insulator that has the function of suppressing the This can be done.

[0208] Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include: Boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, salt Argon, Gallium, Germanium, Yttrium, Zirconium, Lanthanum, Neo Insulators containing zinc, hafnium or tantalum may be used in single or multilayer configurations. Specifically, as an insulator that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttria oxide ammonium, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide or tungsten oxide Metal oxides such as talc, silicon nitride oxide, silicon nitride, etc. can be used. .

[0209] For example, the insulator 132 may be hafnium, aluminum, gallium, yttrium, Zirconium, tungsten, titanium, tantalum, nickel, germanium, or ma It is possible to use a metal oxide containing one or more metals selected from magnesium, etc. can.

[0210] In particular, aluminum oxide has a high barrier property and is a thin film of 0.5 nm to 3.0 nm. Even if the hafnium oxide is used, it is possible to suppress the diffusion of hydrogen and nitrogen. Although the barrier properties are lower than those of aluminum oxide, the barrier properties can be improved by increasing the film thickness. Therefore, by adjusting the thickness of the hafnium oxide film, it is possible to The amount added can be adjusted appropriately.

[0211] For example, the insulators 112 and 132 that function as part of the gate insulator may be formed by excess It is preferable to use an insulator having an oxygen region. For example, silicon oxide having an excess oxygen region. The silicon or silicon oxynitride is in contact with the oxide 106 or the oxide 134. Thus, the oxygen vacancies in the oxide 106 or the oxide 134 can be compensated for.

[0212] For example, the insulator 112 may be made of silicon oxide or silicon oxynitride, which is stable against heat. It is preferable to use a film that is stable against heat and has a high dielectric constant as the gate insulator. By using a laminated structure with a thin film, the equivalent oxide thickness of the gate insulator can be reduced while maintaining the physical film thickness. (EOT) can be reduced.

[0213] Furthermore, the insulator 112 may have a stacked structure. 12, in addition to the above insulators, aluminum, hafnium, and one type of gallium Alternatively, a plurality of oxides may be laminated. In particular, one or more of aluminum and hafnium may be laminated. Insulators containing oxides of aluminum or hafnium include aluminum oxide, hafnium oxide, and aluminum nitride. It is preferable to use oxides containing hafnium and hafnium (hafnium aluminate). stomach.

[0214] By using the above stacked structure, the on-current can be reduced without weakening the influence of the electric field from the gate electrode. In addition, the physical thickness of the gate insulator allows the gate electrode and By keeping the distance between the gate electrode and the region where the channel is formed, The leakage current between the two electrodes can be suppressed.

[0215] The insulators 118 and 138 preferably have a low dielectric constant. For example, the insulator may be silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, or the like. Silicon, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon and nitrogen It is preferable to use silicon oxide doped with silicon dioxide, silicon oxide having pores, or resin. Alternatively, the insulator may be silicon oxide, silicon oxynitride, silicon nitride oxide, or nitride. silicon dioxide, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, carbon and A laminated structure of silicon oxide to which nitrogen is added or silicon oxide having vacancies and resin. Silicon oxide and silicon oxynitride are thermally stable. By combining it with resin, it is possible to create a thermally stable laminated structure with a low dielectric constant. Examples of resins include polyester, polyolefin, polyamide (nylon, amides, polyimides, polycarbonates or acrylics.

[0216] Additionally, the insulator 130 must function as a sacrificial layer when the oxide 106 is formed. Therefore, in the etching process of the insulator 130 described later, the insulators 118 and 116 , and the etching rate of the insulator 112, etc. is relative to the etching rate of the insulator 130. For example, the insulator 118, the insulator When the body 116, the insulator 112, etc. are made of silicon oxide or silicon oxynitride, the nitride Silicon dioxide can be used instead.

[0217] The insulator 132 has a function of suppressing the permeation of impurities such as hydrogen and oxygen. The insulator 132 may be, for example, aluminum oxide or halogen oxide. Funium, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, acid metal oxides such as zirconium oxide, lanthanum oxide, neodymium oxide or tantalum oxide; Silicon oxide or silicon nitride may be used.

[0218] In addition, the insulators 126 and 127 are made of an insulator obtained by thermally oxidizing the conductor 114. It is also preferable that the insulators 128 and 129 are used to heat the conductor 122. Preferably, an oxidized insulator is used.

[0219] <<Conductors>> Conductors include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, and titanium. Tantalum, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Metal elements selected from sodium, zirconium, beryllium, indium, ruthenium, etc. In addition, a polycrystalline material containing impurity elements such as phosphorus can be used. Semiconductors with high electrical conductivity, such as crystalline silicon, and silicides such as nickel silicide A code may also be used.

[0220] Alternatively, a plurality of conductive layers made of the above materials may be stacked. A laminated structure in which a material containing a metal element and a conductive material containing oxygen are combined may be used. In addition, a laminated layer that combines the material containing the metal element and the conductive material containing nitrogen is also available. In addition, a material containing the above-mentioned metal element, a conductive material containing oxygen, and a material containing nitrogen may be used. A laminated structure may be formed by combining a conductive material containing a silicon dioxide.

[0221] When an oxide is used for the channel formation region of a transistor, The conductor that functions as a conductive material is a material containing the above-mentioned metal element and a conductive material containing oxygen. In this case, it is preferable to use a laminated structure in which a conductive material containing oxygen is used. It is preferable to provide the conductive material containing oxygen on the channel forming region side. This makes it easier for oxygen released from the conductive material to be supplied to the channel formation region.

[0222] In particular, the metal oxide in which the channel is formed is used as a conductor that functions as a gate electrode. It is preferable to use a conductive material containing a metal element and oxygen. Conductive materials containing metal elements and nitrogen may also be used, such as titanium nitride and tantalum nitride. Alternatively, a conductive material containing nitrogen, such as indium tin oxide or tungsten oxide, may be used. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, titanium oxide Indium oxide containing titanium dioxide, indium tin oxide, indium zinc oxide Indium tin oxide containing nitrogen may also be used. Mugallium zinc oxide may also be used. By using such a material, the channel is formed. In some cases, hydrogen contained in the metal oxides surrounding the outer insulating layer can be captured. It may be possible to capture hydrogen that is mixed in from the surroundings.

[0223] The conductors 120, 122, and 114 may be made of aluminum, chromium, Copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium Aluminum, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium Materials containing one or more metal elements selected from the group consisting of tungsten, ruthenium, and the like can be used. In addition, silicon with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, Semiconductors and silicides such as nickel silicide may also be used.

[0224] It is preferable that the conductor 114 and the conductor 122 are made of different conductive materials. By using different conductive materials for the conductor 114 and the conductor 122, the oxidation rates of the two materials can be Alternatively, since the etching rates are different, the positions of the side surfaces of the conductor 114 and the conductor 122 are shifted. It is possible.

[0225] <<Metal oxides>> The following describes metal oxides applicable to the oxide 106 and oxide 134 according to the present invention. and explain.

[0226] The metal oxide preferably contains at least indium or zinc. In addition to these, aluminum, gallium, It is preferable that yttrium or tin is contained. Also, boron, titanium, iron, etc. , nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium , hafnium, tantalum, tungsten, magnesium, or One or more types may be included.

[0227] Here, the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. The element M is aluminum, gallium, yttrium, or Other elements that can be used for element M include boron, titanium, iron, and nickel. Nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, Examples include fluorine, tantalum, tungsten, and magnesium. However, the element M is: In some cases, a combination of the aforementioned elements may be used.

[0228] In this specification, metal oxides containing nitrogen are also referred to as metal oxides (metal oxides). Metal oxides containing nitrogen are sometimes collectively called metal oxynitrides (metal oxynitrides). It may also be called tal oxynitride.

[0229] [Metal oxide composition] Hereinafter, a CAC (C This paper explains the structure of the Cloud-Aligned Composite OS.

[0230] In this specification, CAAC (c-axis aligned crystal) l), and CAC (Cloud-Aligned Composite) CAAC represents an example of a crystal structure, and CAC represents a function or a material configuration. An example is shown below.

[0231] CAC-OS or CAC-metal oxide is a material that has a conductive function in some parts. The material has insulating properties in some parts and semiconductor properties in the whole material. Note that CAC-OS or CAC-metal oxide is used as the active material for the transistor. When used in a layer, the conductive function is to allow electrons (or holes) to flow as carriers. The insulating function is to prevent the flow of electrons, which act as carriers. By making these functions work in a complementary manner, the switching function (On / Off) The function of making the CAC-OS or CAC-metal oxide In CAC-OS or CAC-metal oxide, the respective functions By separating the two, the functions of both can be maximized.

[0232] In addition, CAC-OS or CAC-metal oxide is a conductive area and an insulating area. The conductive region has the above-mentioned conductive function, and the insulating region has the above-mentioned insulating function. In addition, the conductive and insulating regions in the material are formed by nanoparticles. The conductive region and the insulating region may be separated by different materials. In addition, the conductive area may be observed as a cloud-like connected area with a blurred periphery. This may be the case.

[0233] In addition, in the CAC-OS or CAC-metal oxide, a conductive region and The insulating regions are each 0.5 nm to 10 nm, preferably 0.5 nm to 3 nm. They may be dispersed in the material at sizes of less than 1 m.

[0234] In addition, CAC-OS or CAC-metal oxide has different band gaps For example, CAC-OS or CAC-metal ox The ide consists of a wide-gap component due to the insulating region and a conductive component due to the conductive region. In this configuration, when carriers flow, In addition, carriers mainly flow in the narrow gap component. The component with a narrow gap acts complementary to the component with a wide gap. Carriers also flow into the wide-gap component in conjunction with the component that has a wide gap. CAC-OS or CAC-metal oxide is used as the channel formation region of the transistor. When used in a transistor, it has a high current driving force in the on-state, i.e., a large on-current. , and high field-effect mobility can be obtained.

[0235] That is, CAC-OS or CAC-metal oxide is a matrix composite. matrix composite, or metal matrix composite It can also be called a matrix composite.

[0236] [Metal oxide structures] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single-crystal oxide semiconductor, for example, CAAC-OS (c- axis aligned crystalline oxide semiconductor ctor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline ox ide semiconductor), pseudo-amorphous oxide semiconductor (a-like OS : amorphous-like oxide semiconductor) and non crystalline oxide semiconductors.

[0237] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The crystal structure is distorted by the connection of multiple nanocrystals. In the region, the lattice arrangement is changed between a region with a uniform lattice arrangement and another region with a uniform lattice arrangement. This refers to the point where the direction of the

[0238] Nanocrystals are basically hexagonal, but are not limited to regular hexagonal shapes. They may also have non-regular hexagonal shapes. In addition, the distortion may have lattice arrangements such as pentagons and heptagons. In addition, in CAAC-OS, clear grain boundaries (grain bows) are not observed even near the strain. It is difficult to confirm the lattice distortion. This is because the CAAC-OS crystals are grown in the ab-plane direction. In the case of the SiO2, the arrangement of oxygen atoms is not dense, and the bond distance between atoms is reduced by the substitution of metal elements. This is because distortion can be tolerated due to changes in the distance, etc.

[0239] In addition, the CAAC-OS has a layer containing indium and oxygen (hereinafter referred to as an In layer) and an elemental A layered crystal consisting of layers containing element M, zinc, and oxygen (hereinafter referred to as the (M,Zn) layer). It is noted that indium and element M tend to have a structure (also called a layered structure). When the element M in the (M,Zn) layer is replaced with indium, the (In,M,Zn) ) layer. Also, when indium in the In layer is replaced with element M, it can be expressed as (In, It can also be expressed as the M layer.

[0240] CAAC-OS is a highly crystalline metal oxide. Since it is difficult to identify grain boundaries, the decrease in electron mobility caused by grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides can be reduced by the incorporation of impurities or the generation of defects. Therefore, CAAC-OS should be free from impurities and defects (oxygen vacancies (V O :oxygen v Therefore, CAAC- Metal oxides with OS have stable physical properties. Metal oxides are heat resistant and highly reliable.

[0241] nc-OS is a material that can be used in microscopic areas (e.g., areas between 1 nm and 10 nm, especially areas between 1 nm and 10 nm). The atomic arrangement is periodic in the region of 3 nm or less. There is no regularity in the crystal orientation between the crystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, nc-OS may be classified as a-like OS or amorphous oxide semiconductor. It may be indistinguishable from the body.

[0242] The a-like OS is a metal oxide semiconductor with a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has pores or low density regions. The ke-OS has lower crystallinity than the nc-OS and CAAC-OS.

[0243] Oxide semiconductors (metal oxides) have a variety of structures, each with different properties. The oxide semiconductor of one embodiment of the present invention may be an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-li The ke-OS, nc-OS, and CAAC-OS may have two or more of them.

[0244] [Transistors with metal oxides] Next, the case where the above metal oxide is used for a channel formation region of a transistor will be described. do.

[0245] Note that by using the above metal oxide for the channel formation region of a transistor, a high field efficiency can be achieved. It is possible to realize a transistor with high mobility. It can be realized.

[0246] Here, an example of a hypothesis regarding electrical conduction in metal oxides will be described.

[0247] Electrical conduction in solids is hindered by scattering sources called scattering centers. For example, in single crystals, In the case of silicon, lattice scattering and ionized impurity scattering are known to be the main scattering centers. In other words, when there are few lattice defects or impurities, the electrical conduction in the solid There are no blocking factors and carrier mobility is high.

[0248] The above is also assumed to be true for metal oxides. In metal oxides containing less oxygen than the oxygen that fills the composition, oxygen vacancies V O There are many It is thought that the atoms around this oxygen vacancy are in a distorted position rather than in their essential state. It is possible that the distortion caused by this oxygen vacancy is the scattering center.

[0249] For example, in a metal compound containing more oxygen than the stoichiometric composition, Excess oxygen is present. Excess oxygen, which exists in a free state in the metal compound, accepts electrons. By doing so, O - Ya O 2- It becomes. - Ya O 2- The excess oxygen may become a scattering center. There is.

[0250] From the above, it is clear that metal oxides have an essential state in which oxygen is contained in a stoichiometric composition. In this case, the carrier mobility is considered to be high.

[0251] Indium-, a type of metal oxide containing indium, gallium, and zinc, Gallium zinc oxide (IGZO) tends to have difficulty growing crystals in the atmosphere. Therefore, smaller crystals are more likely to be formed than larger crystals (here, crystals of several mm or several cm). In some cases, crystals (such as the nanocrystals mentioned above) are structurally more stable. The strain energy is relieved more easily when small crystals are connected to each other than when large crystals are formed. This is thought to be because

[0252] In addition, in the region where small crystals are connected to each other, the strain energy of the region is relaxed. Therefore, defects may be formed in the region. By relaxing the strain energy, the mobility of carriers can be increased.

[0253] It is also preferable to use a metal oxide with a low carrier density for the transistor. When the carrier density of the metal oxide film is reduced, the impurity concentration in the metal oxide film is reduced. In this specification and the like, the impurity concentration is low and the defect level density is low. A low level density is called high purity intrinsic or substantially high purity intrinsic. For example, metal oxides , the carrier density is 8×10 11 / cm 3 Less than 1 x 10 11 / cm 3 Less than, More preferably, 1×10 10 / cm 3 Less than 1 x 10 -9 / cm 3 That's all. stomach.

[0254] Furthermore, a highly pure intrinsic or substantially highly pure intrinsic metal oxide film has a low density of defect states. Therefore, the trap level density may also be low.

[0255] In addition, the charges trapped in the trap levels of metal oxides take a long time to disappear. Therefore, the trap level density is high. A transistor having a metal oxide in a channel formation region may have unstable electrical characteristics. be.

[0256] Therefore, in order to stabilize the electrical characteristics of the transistor, the impurity concentration in the metal oxide must be kept low. In order to reduce the impurity concentration in the metal oxide, It is preferable to reduce the impurity concentration in the adjacent film. These include alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0257] [impurities] Here, the influence of each impurity in the metal oxide will be described.

[0258] When metal oxides contain silicon or carbon, which are elements of Group 14, they become metal oxides. Defect levels are formed in the oxides. This leads to the formation of silicon and carbon concentrations in the metal oxides. The concentration of silicon and carbon near the metal-oxide interface was measured by secondary ion mass spectrometry (SIMS). : Secondary Ion Mass Spectrometry) concentration) to 2 x 10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0259] In addition, when alkali metals or alkaline earth metals are contained in metal oxides, defect levels are formed. Therefore, alkali metals or alkaline earth metals A transistor that uses a metal oxide containing metals in the channel formation region is normally on. Therefore, the concentration of alkali metals or alkaline earth metals in metal oxides It is preferable to reduce the degree of Al in the metal oxide obtained by SIMS. The concentration of potassium metal or alkaline earth metal is 1×10 18 atoms / cm 3 Below, I prefer Or 2 x 10 16 atoms / cm 3 Do the following:

[0260] In addition, when nitrogen is contained in a metal oxide, electrons that act as carriers are generated, and the carriers As a result, the density increases and it becomes easier to make the metal oxide containing nitrogen into a channel type. The transistors used in the metal-doped region tend to be normally-on. In the oxide, it is preferable that the nitrogen content in the channel formation region is reduced as much as possible. For example, the nitrogen concentration in metal oxides is 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 The following .

[0261] In addition, hydrogen contained in metal oxides reacts with oxygen that bonds with metal atoms to form water. When hydrogen enters the oxygen vacancy, the electrons acting as carriers are released. In addition, some of the hydrogen may combine with the oxygen that is bonded to the metal atom, forming a carrier. Therefore, metal oxides containing hydrogen can be used The transistor tends to be normally on. Therefore, hydrogen in the metal oxide is not formed. Specifically, in the case of metal oxides, the The resulting hydrogen concentration is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 Less than, more Preferably 1 x 10 18 atoms / cm 3 Less than.

[0262] Use of metal oxide with sufficiently reduced impurities in the channel formation region of a transistor Therefore, the off-state current of the transistor can be reduced and stable electrical characteristics can be provided.

[0263] <Configuration of selection transistor array> Next, one of the configurations of the transistors included in the select transistor array shown in the above embodiment will be described. An example will be described with reference to FIG.

[0264] 13A and 13B show the transistors provided in the selection transistor array 50 shown in FIG. 13A is a cross-sectional view of the transistor 61. The cross-section C1-C2 shown in FIG. 13B is a cross-sectional view of the transistor 61. The figure shows a cross section in the channel width direction.

[0265] The transistor 61 shown in FIGS. 13A and 13B is a transistor using a semiconductor substrate 150. The transistor 61 is formed by a region 172a in the semiconductor substrate 150 and a region 172b in the semiconductor substrate 150. 0, an area 172b, an insulator 162a, and a conductor 154a. Although not shown, a configuration in which a sidewall insulator is provided in contact with the side surface of the conductor 154a is also possible. In addition, when a sidewall insulator is provided in contact with the side surface of the conductor 154a, the region In the region 172a and the region 172b, the sidewall insulator is overlapped with the region This can result in regions with lower impurity concentrations than regions that do not overlap with the sidewall insulator. .

[0266] In transistor 61, regions 172a and 172b are the source and drain regions. The insulator 162a functions as a gate insulator. The conductor 154a also functions as a gate electrode. The resistance of the channel formation region can be controlled by the potential applied to the conductive material 154a. That is, the potential applied to the conductor 154a causes a voltage between the region 172a and the region 172b. Conduction and non-conduction can be controlled.

[0267] In the semiconductor device shown in FIGS. 13A and 13B, a transistor 61 is configured as a fin type. By making the transistor 61 a fin type, the effective channel width increases. This improves the on-state characteristics of the transistor 61. Since the contribution of the magnetic field can be increased, the off characteristics of the transistor 61 can be improved. can.

[0268] The semiconductor substrate 150 may be, for example, a semiconductor substrate such as silicon or germanium, or are silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, A semiconductor substrate such as gallium oxide may be used. A single crystal silicon substrate is used.

[0269] The semiconductor substrate 150 is a semiconductor substrate containing impurities that impart p-type conductivity. However, a semiconductor substrate containing impurities that impart n-type conductivity is used as the semiconductor substrate 150. In this case, the region that will become the transistor 61 is given a p-type conductivity. Alternatively, the semiconductor substrate 150 may be an i-type. No.

[0270] Note that the substrate used for the semiconductor device shown in this embodiment mode is not limited to a semiconductor substrate. For example, when forming an active layer such as a transistor 61 by film formation, an insulating substrate Alternatively, a conductive substrate or the like can be used. An example of an insulating substrate is a glass substrate. , quartz substrate, sapphire substrate, stabilized zirconia substrate (yttria stabilized zirconia substrate In addition, there are semiconductor substrates that have an insulating region inside the semiconductor substrate. Even if a substrate, such as an SOI (Silicon On Insulator) substrate, is used, Conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, there are substrates having metal nitrides, substrates having metal oxides, etc. , a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a semiconductor substrate in which a conductor or an insulator is provided and a substrate in which a semiconductor or an insulator is provided on a conductive substrate. The substrate may have elements mounted thereon. The elements include capacitance elements, resistance elements, switch elements, light emitting elements, memory elements, etc. It may also be called a substrate.

[0271] In addition, a flexible substrate that can withstand the heat treatment during transistor fabrication can be used as the substrate. As a method for providing a transistor on a flexible substrate, a method for providing a transistor on a non-flexible substrate is also available. There is also a method in which a transistor is fabricated on a substrate, and then the transistor is peeled off and transferred to a flexible substrate. In that case, a peeling layer may be provided between the non-flexible substrate and the transistor. The substrate may be a sheet, film, or foil containing woven fibers. The substrate may be stretchable. The substrate may also be designed to retain its original shape when the bending or pulling is stopped. Alternatively, the substrate may have a property of not returning to its original shape. The thickness is, for example, 5 μm or more and 700 μm or less, preferably 10 μm or more and 500 μm or less. More preferably, the thickness is 15 μm or more and 300 μm or less. Furthermore, by making the substrate thinner, it is possible to reduce the extension even when glass is used. If the material has shrinkage or the property of returning to its original shape when bending or pulling is stopped, Therefore, in order to reduce the impact that may be applied to the semiconductor device on the board when it is dropped, etc. That is, a robust semiconductor device can be provided.

[0272] The regions 172a and 172b are regions containing impurities that impart n-type conductivity. In this way, the transistor 61 constitutes an n-channel transistor.

[0273] The transistor 61 is separated from adjacent transistors by a region 160 or the like. The region 160 is an insulating region.

[0274] The semiconductor device shown in FIGS. 13A and 13B includes an insulator 132, an oxide 134, and an insulator 135. 64, insulator 165, insulator 166, insulator 168, insulator 170, and conductor 1 80a, conductor 180b, conductor 178a, conductor 178b, conductor 176a, , and the conductor 174a. Here, the insulator 132 and the oxide 134 are the same as those described above. The memory cells are formed in a three-dimensional memory cell array 40.

[0275] The insulator 164 is formed to bury the transistor 61. is formed on the insulator 164. Insulator 166 is formed on insulator 165. In addition, the insulator 168 is formed on the insulator 166. In addition, the insulator 170 is formed on the insulator Formed on 168.

[0276] The insulators 164, 165, 166, 168, and 170 are in the region The insulating layer 132 and the oxide layer 172a are disposed in the cylindrical opening. The insulator 132 is formed in a cylindrical shape in contact with the inner wall of the opening. The oxide 134 is formed in a cylindrical shape inside the insulator 132. The object 134 is formed to extend substantially perpendicular to the upper surface of the semiconductor substrate 150 .

[0277] An opening is formed in at least a part of the bottom surface of the insulator 132, and the oxide is exposed through the opening. The oxide 134 is in contact with the region 172a. corresponds to one of the wirings RBL[1,1] to [m1,m2] shown in FIG. The region 172a functions as the source region or the drain region of the transistor 61. By adopting the above-mentioned configuration, the wiring RBL at the bottom of the memory cell string The source region or drain region of the transistor 61 of the selected transistor cell 60 is electrically connected to the can be effectively connected.

[0278] Furthermore, the insulators 164 and 165 have openings that reach the region 172b and the conductor 1 The openings have openings that reach the conductors 180a and 154a. 80b and 80b are embedded in the insulator 166. Furthermore, the insulator 166 has an opening that reaches the conductor 180a. and an opening that reaches the conductor 178a. The insulator 168 is embedded with the conductor 178a and the conductor 178b. The opening has an opening that reaches the insulating layer 176. The opening is filled with a conductor 176a. The conductive material 70 has an opening that reaches the conductive material 176a. The conductive material 174a is embedded in the opening. It is being eaten.

[0279] Here, the conductor 174a functions as the source region or the drain region of the transistor 61. 5 and the like. ]. The conductor 178b functions as the gate of the transistor 61. It is electrically connected to the conductor 154a that functions as the wiring SG1 shown in FIG. When reading data, the wiring SG1 and the transistor 61 thus formed are connected to each other. , and one of the two-dimensional memory cell arrays 30[1] to [m1] can be selected via can.

[0280] one or more of insulator 164, insulator 165, insulator 166, insulator 168, and insulator 170 It is preferable that the insulating material has a function of blocking impurities such as hydrogen and oxygen. The three-dimensional memory cell array 40 includes a transistor 12 and a layer below the transistor 12. By placing an insulator that has the function of blocking impurities and oxygen, The electrical characteristics of the star 12 can be stabilized.

[0281] Examples of insulators that have the function of blocking impurities such as hydrogen and oxygen include fluorine, Uron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine , argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium Insulators containing titanium, hafnium or tantalum may be used in single or multilayer configurations.

[0282] Conductor 180a, Conductor 180b, Conductor 178a, Conductor 178b, Conductor 176a The conductor 174a may be, for example, boron, nitrogen, oxygen, fluorine, silicon, phosphorus, Aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, Yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum Conductors containing one or more of zinc and tungsten may be used in a single layer or a multilayer. For example, the conductor may be an alloy or compound, such as an aluminum-containing conductor, a copper-containing conductor, or a titanium-containing conductor. Conductors, conductors containing copper and manganese, conductors containing indium, tin and oxygen, Conductors containing titanium and nitrogen may also be used.

[0283] 13(C) and 13(D) show the transistors provided in the selection transistor array 50 shown in FIG. 13C is a cross-sectional view of the transistor 62. The cross-section C5-C6 shown in FIG. 13(D) is a cross section of the transistor 6. 2 shows a cross section in the channel width direction.

[0284] The structure of the semiconductor device shown in FIGS. 13(C) and 13(D) is formed of an insulator 132 and an oxide 134. 13(A)(B) except that conductor 120 is formed instead of the The transistor 62 is formed in a region in a semiconductor substrate 150. 172c, region 172d in semiconductor substrate 150, insulator 162b, and conductor 154b. However, the regions 172c and 172d have the same structure as the regions 172a and 172b. The insulator 162b has the same structure as the insulator 162a, and the conductor 154b has the same structure as the conductor 154a. The structure of the above can be taken into consideration.

[0285] In addition, the conductor 180c, the conductor 180d, the conductor 178c, the conductor 178d, and the conductor 1 76b and conductor 174b are conductors 180a, 180b, 178a, and conductor The structures of the conductor 178b, the conductor 176a, and the conductor 174a can be taken into consideration.

[0286] The insulators 164, 165, 166, 168, and 170 are in the region The conductive member 120 is disposed inside the cylindrical opening that reaches the conductive member 172c. The conductor 120 is formed in a cylindrical shape in contact with the inner wall of the opening. The substrate 150 is formed to extend substantially perpendicularly to the upper surface of the substrate 150. ) is one of the wirings WBL[1,1] to [m1,m2] shown in FIG. 3 and the like. The region 172c corresponds to either the source region or the drain region of the transistor 62. By adopting the above-described configuration, the memory cell 10 The wiring WBL electrically connected to the transistor 12 is connected to the transistor of the selection transistor cell 60. The source or drain region of the transistor 62 can be electrically connected.

[0287] Additionally, the conductor 174b functions as the source or drain region of the transistor 62. 5 and the wiring WBL[1] to [m2] shown in FIG. Conductor 178d also functions as the gate of transistor 62. The wiring SG2 shown in FIG. 5 is electrically connected to the conductor 154b. When writing data, the wiring SG2 and the transistor 62 thus formed are , one of the two-dimensional memory cell arrays 30[1] to [m1] can be selected. Cut.

[0288] <Method for fabricating memory cell array> Next, a manufacturing method of the semiconductor device will be described with reference to FIGS. 4 to 26 show memory cells 10 in a part of the three-dimensional memory cell array 40 of the semiconductor device. 14A to 26A are diagrams showing the manufacturing process of layer 14 of memory cell 10. 14(B) to 26(B) are cross-sectional views of the memory cell 10. 14(A) to 26(A) correspond to the dashed line A1-A2 shown in FIG. 14(B) to 26(C) correspond to the plan view shown in FIG. 8(B), and FIGS. 14(B) to 26(D) correspond to the plan view shown in FIG. B) corresponds to the cross-sectional view shown in FIG. 8(A).

[0289] In the manufacturing method described below, the film formation process is performed by sputtering, chemical vapor deposition (CVD), Chemical Vapor Deposition (CVD), Molecular Beam Epitaxy (MBE) BE: Molecular Beam Epitaxy, Pulsed Laser Deposition (PLD) Pulsed Laser Deposition (ALD) or Atomic Layer Deposition (ALD) This can be done using a method such as atomic layer deposition.

[0290] The CVD method is a plasma CVD (PECVD) method that uses plasma. Enhanced CVD (TCVD) method, and thermal CVD (TCVD) method. These methods can be further classified into the VD method, which uses light, and the Photo CVD method. Depending on the source gas, metal CVD (MCVD) and metal organic CVD are used. (MOCVD: Metal Organic CVD) method.

[0291] The plasma CVD method can produce high-quality films at relatively low temperatures. This is a film formation method that can suppress plasma damage to the processed object because it does not use a plasma. For example, wiring, electrodes, elements (transistors, capacitors, etc.) included in a semiconductor device These may become charged up by receiving electric charges from the plasma. The accumulated charge can destroy the wiring, electrodes, elements, etc. contained in the semiconductor device. On the other hand, in the case of thermal CVD methods that do not use plasma, such plasma damage does not occur. In addition, the thermal CVD method does not require the use of a metal oxide film, which increases the yield of semiconductor devices. Since no plasma damage occurs inside the film, a film with few defects can be obtained.

[0292] The ALD method is also a film formation method that can suppress plasma damage to the workpiece. Therefore, a film with few defects can be obtained. For this reason, films formed by ALD are more susceptible to impurities than those formed by other film formation methods. In some cases, the film contains more impurities such as carbon than the film formed by the method described above. The quantitative determination of This can be done using endoscopic imaging.

[0293] The CVD and ALD methods are film formation methods in which particles emitted from a target are deposited. It is a film forming method in which a film is formed by a reaction on the surface of the object to be treated. Therefore, this is a film forming method that is less affected by the shape of the workpiece and has good step coverage. In addition, the ALD method has excellent step coverage and thickness uniformity, making it suitable for forming thin films with high aspect ratios. However, the ALD method is relatively slow in forming films. Because the deposition rate is slow, it should be used in combination with other deposition methods such as CVD, which has a high deposition rate. may be preferable.

[0294] In the CVD and ALD methods, the composition of the resulting film is controlled by the flow rate ratio of the source gases. For example, in the CVD and ALD methods, the flow rate ratio of the source gases can be adjusted to any value. In addition, for example, in the CVD method and the ALD method, it is possible to form a film having the following composition. By changing the flow rate ratio of the source gases while oxidizing, a film with a continuously changing composition can be formed. When forming a film while changing the flow rate ratio of the source gases, multiple film forming chambers can be used. Compared to forming a film using a vacuum, the time required for film formation is shorter because there is no time required for transport or pressure adjustment. Therefore, the productivity of the semiconductor device can be improved. There is.

[0295] In addition, the deposited conductors, insulators, and semiconductors are processed using lithography. In addition, the processing can be performed by using a dry etching method or a wet etching method. Dry etching is suitable for microfabrication.

[0296] In the lithography method, first, the resist is exposed to light through a mask. The areas are removed or left behind using a developer to form a resist mask. By etching through a resist mask, conductors, semiconductors, insulators, etc. can be formed as desired. For example, KrF excimer laser light, ArF excimer laser light, The resist is removed using ultraviolet light, EUV (Extreme Ultraviolet) light, etc. A resist mask can be formed by exposing the substrate to light. It is also possible to use a liquid immersion technique in which the substrate is exposed to light by filling it with liquid (for example, water). Alternatively, an electron beam or an ion beam may be used. In this case, the pattern is written directly on the resist, so the above-mentioned resist exposure mask is not required. The resist mask can be used for dry etching such as ashing, or for wet etching. Etching is performed, dry etching is performed followed by wet etching, or can be removed by wet etching followed by dry etching, etc. Cut.

[0297] Moreover, instead of the resist mask, a hard mask made of an insulator or a conductor may be used. When a hard mask is used, an insulating layer that will become the hard mask material is formed on the constituent material to be etched. An insulating film or a conductive film is formed, a resist mask is formed on it, and a hard mask material is etched. By etching the material, a hard mask of the desired shape can be formed. The etching can be performed after removing the resist mask, or with the resist mask left in place. In the latter case, the resist mask may be lost during etching. After etching the composition material, the hard mask may be removed by etching. If the mask material does not affect the subsequent process or can be used in the subsequent process, it is not necessarily hard There is no need to remove the mask.

[0298] The dry etching equipment is a capacitively coupled plasma (CCP) device with parallel plate electrodes. (Capacitively Coupled Plasma) etching equipment is used. The capacitively coupled plasma etching apparatus having parallel plate electrodes can Alternatively, a high frequency power supply may be applied to one of the parallel plate type electrodes. Alternatively, a parallel plate electrode may be used. Alternatively, a parallel plate electrode may be used. Alternatively, a high-density plasma source may be provided. A dry etching apparatus having a high density plasma source can be used. The plasma processing device is, for example, an inductively coupled plasma (ICP) type. A plasma etching device or the like can be used.

[0299] First, an insulator 118A, a Conductor 122A, insulator 116A, insulator 130A, insulator 112A, and conductor 11 4A are laminated in this order (see FIGS. 14(A) and (B)). This laminate is repeatedly formed according to the number of layers of the stack. The conductor 122A is an insulating film that will become the insulator 118 in a subsequent process. Insulator 116A is an insulating film that will become insulator 116 in a later process. The insulator 130A is an insulating film that will become the insulator 130 in a later process. The conductive material 112A is an insulating film that will become the insulator 112 in a later process. The conductive film will become the conductor 114 in the process. The insulating film and the conductive film are formed by the following methods: Sputtering, CVD, MBE, PLD, ALD, etc. can be done.

[0300] However, the top layer in FIG. 14(B) is conveniently shown as the top layer of the three-dimensional memory cell array. Although the uppermost layer of the three-dimensional memory cell array is an edge layer 118, the present invention is not limited to this. The layer may be an insulating film, a conductive film, a semiconductor film, or the like, as appropriate depending on the circuit configuration or the like.

[0301] The insulator 130A is formed by joining the insulators 118A, 116A, and It is necessary to perform etching selectively with respect to the insulator 112A. In the etching process, the etching rate of the insulator 130A is higher than that of the insulators 118A and 116A. , and is preferably significantly greater than the etching rate of the insulator 112A. If the etching rates of the insulator 118A, the insulator 116A, and the insulator 112A are 1, The etching rate of the insulator 130A is preferably 5 or more, and more preferably 10 or more. Therefore, the insulators 130A, 118A, 116A, and 112A are The insulating material used must be selected to suit the etching conditions so as to satisfy the above etching rate. It is preferable to select the appropriate amount in accordance with the above.

[0302] Here, the ends of the conductor 122A and the conductor 114A extending in the y-axis direction are stepped. It is preferable to provide a step-like portion of the conductor 122 and the conductor 114. This forms a contact portion with the connected wiring. can easily make contact with the plug connected to the wiring.

[0303] Next, using a mask, the insulator 118A, the conductor 122A, the insulator 116A, and the insulator 1 The laminate including the insulating material 112A, the conductive material 114A, and the insulating material 112B is cut into pieces. 18B, conductor 122B, insulator 116B, insulator 130B, insulator 112B, and conductor A laminate including an insulator 118B and a conductor 114B is formed (see FIGS. 15(A) and 15(B)). Conductor 122B, insulator 116B, insulator 130B, insulator 112B, and conductor 114 The laminate including B is divided by a third opening into which an insulator 138 is filled in a later process. The third opening is a groove-shaped opening extending in the y-axis direction. B, conductor 122B, insulator 116B, insulator 130B, insulator 112B, and conductor The third opening 114B has a plate-like shape extending in the y-axis direction. This can be achieved by performing a highly anisotropic etching process such as a dry etching process.

[0304] Next, the insulator 118B, the conductor 122B, the insulator 116B, the insulator 130B, and the insulator 1 12B, and the third opening between the laminate including the conductor 114B. The insulator 138 is formed by using a CVD method or an ALD method (see FIGS. 16(A) and 16(B)). In particular, the ALD method allows for the formation of grooves with a large aspect ratio and This is preferable because it allows a film of uniform thickness to be formed even in the opening. The insulator 138 may be formed by combining the LD method and the CVD method. It is preferable that the planarization process is performed using the MP method or the reflow method. When performing the planarization process, the insulator 138 is polished until the surface of the insulator 118B is exposed. Alternatively, the insulator 118B and the insulator 138 may be polished together.

[0305] Next, using a mask, the insulator 118B, the conductor 122B, the insulator 116B, and the insulator 1 forming a vertical hole-shaped opening in a laminate including the insulating material 30B, the insulating material 112B, and the conductive material 114B; Insulator 118C, conductor 122C, insulator 116C, insulator 130C, insulator 112C, and a conductor 114C are formed (see FIGS. 17(A) and 17(B)). 8C, conductor 122C, insulator 116C, insulator 130C, insulator 112C, and conductor The laminate including the body 114C has a second opening formed therein in which the conductor 120 is to be embedded in a later step. The second opening is formed by anisotropic etching such as dry etching. All that is required is to perform a chipping process.

[0306] Next, the surfaces of the conductors 114C and 122C facing the second opening are oxidized to form conductive layers. An insulator 126 is formed on the side of the conductor 114C, and an insulator 128 is formed on the side of the conductor 122C ( 18(A)(B). The formation of the insulators 126 and 128 is achieved by, for example, Here, the conductor 114C and the conductor 122C are subjected to a heat treatment in an atmosphere containing different By using a conductive material, the speed at which the insulators 126 and 128 are formed can be made different. Therefore, the thickness of the insulator 126 can be increased.

[0307] Before forming the insulators 126 and 128, an etching process is performed to form conductive The conductive body 122C may be selectively removed. By using a conductive material, the etching rates of the conductor 114C and the conductor 122C can be made different. Therefore, the side surface of the conductor 122C can be positioned closer to the A1 side than the side surface of the conductor 114C. Cut.

[0308] Next, an isotropic etch is performed to selectively remove the insulator 130C provided on the layer 140. The insulating layer 130 is formed by removing the insulating layer 130 (FIGS. 19A and 19B). For example, wet etching or etching using a reactive gas may be used. In etching using reactive gases, the substrate is intentionally not biased. In addition, when etching using reactive gas, the reactive gas is The reactivity of the etching gas is increased by increasing the temperature or by converting the reactive gas into plasma. It may be improved.

[0309] In this etching process, the etching rate of the insulator 130C is higher than that of the insulator 118C. , significantly higher than the etching rates of the insulators 116C, 112C, and 138. It is preferable that the insulator 118C, the insulator 116C, the insulator 112C, and If the etching rate of the insulator 130C is 1, the etching rate of the insulator 130C is 5 or more. The etching rate is preferably 10 or more, and more preferably 10 or more. In this way, etching conditions can be selected appropriately.

[0310] For example, the insulator 130C is made of silicon nitride, and the insulators 118C and 116C are made of silicon nitride. When the insulators 112C and 138 are made of silicon oxide, an aqueous solution of phosphoric acid is used. Wet etching using

[0311] At this time, as shown in FIG. 19(A), the etching area of ​​the insulator 130 in the layer 140 is The top surface of the region may have a generally circular shape, as if cut by the insulator 138.

[0312] Next, the insulator 118C, the conductor 122C, the insulator 116C, the insulator 130, the insulator 11 2C, and forming an oxide 106A in an opening formed in the stack including the conductor 114C. (See FIGS. 20(A) and 20(B)). Here, the oxide 106A will be replaced by the oxide 106 in a later step. Therefore, the oxide 106A may be formed by a CVD method or the like. It can be formed by the ALD method. In particular, by using the ALD method, it is possible to This is preferable because it can form a film of uniform thickness even on large grooves and openings. Alternatively, the oxide 106A may be formed by combining the ALD method and the CVD method. When a CVD method is used, either an MOCVD method or an MCVD method may be used. When A is a laminated film, it may be formed in the same film forming apparatus or in different film forming apparatuses. That's fine.

[0313] In each layer 140, the oxide 106A is surrounded by the insulators 130 and 138. As a result, the oxide 106A is formed in an island shape in each layer 140. , it is possible to prevent the oxides 106A from coming into contact with each other.

[0314] Here, the oxide 106A formed on the top surface of the memory cell array is formed by using a CMP method or the like. It is preferable that the oxidized material is removed by the addition of the oxidized material.

[0315] Next, the oxide 106A formed in the second opening is selectively removed, and the oxide 106B is formed. As a result, the oxide 106B is divided into layers 140. The oxide 106A in the second opening can be selectively removed by, for example, dry etching. This can be achieved by performing an anisotropic etching process such as etching.

[0316] Next, the insulator 118C, the conductor 122C, the insulator 116C, the insulator 130, the oxide 10 6B, insulator 112C, and conductor 114C. The conductor 120 is formed on the substrate (see FIGS. 22A and 22B). It can be formed by using the LD method. In particular, by using the ALD method, it is possible to This is preferable because it allows a film of uniform thickness to be formed even in large grooves or openings. Alternatively, the conductor 120 may be formed by combining the ALD method and the CVD method. When the VD method is used, the MOCVD method or the MCVD method may be used.

[0317] Here, the bottom of the conductor 120 is in the region 1 of the transistor 62 as shown in FIG. 72c.

[0318] In the layer 140, the oxide 106B is in contact with the side surfaces of the conductor 120 so as to surround the periphery. The oxide 106B is in contact with the conductor 120 in the vicinity of the region where the oxide 106B is in contact with the conductor 120. The metal element is added to the oxide 106B, and the resistance of the region is reduced to form a region 109b. In addition, by performing a heat treatment after forming the conductor 120, the conductor 120 may be The contained metal element is added to the oxide 106, and the region 109b can be formed more reliably. Here, the diameter of the second opening where the conductor 120 is provided is set to be sufficiently large, for example, 10 nm or more. By setting the thickness to about 200 nm or less, even if the region 109b is formed by heat treatment, the conductive material The electrical conductivity of 120 can be sufficiently maintained.

[0319] Next, using a mask, the insulator 118C, the conductor 122C, the insulator 116C, and the insulator 1 30, a vertical hole-shaped layer is formed in a laminate including an oxide 106B, an insulator 112C, and a conductor 114C. An opening is formed, and the insulating material 118, the conductor 122, the insulating material 116, the insulating material 130, and the insulating material 11 are stacked. 2 and a conductor 114 (see FIGS. 23(A) and 23(B)). 18, conductor 122, insulator 116, insulator 130, insulator 112, and conductor 114 The stack of layers includes a first opening that will be filled with an insulator 132 and an oxide 134 in a later step. The first opening is formed by a different method such as dry etching. A cyclotropic etching process can be performed.

[0320] Next, the surfaces of the conductors 114 and 122 facing the first opening are oxidized, and the conductors 114 and 122 are oxidized. An insulator 127 is formed on the side of the conductor 124, and an insulator 129 is formed on the side of the conductor 122 (FIG. 23( The insulators 127 and 129 are formed in an atmosphere containing oxygen, for example. Here, the conductor 114 and the conductor 122 are made of different conductive materials. By using this, the speed at which the insulators 127 and 129 are formed is made different, and the speed at which the insulators 127 and 129 are formed is made different. The thickness of the film 27 can be increased.

[0321] Furthermore, before forming the insulators 127 and 129, an etching process is performed to form conductive The conductive body 114 may be selectively removed. The conductive body 114 and the conductive body 122 may be made of different conductive materials. By using the above, the etching rates of the conductor 114 and the conductor 122 are made different, and the conductor The side of 114 can be positioned closer to the A2 side than the side of the conductor 122.

[0322] Next, the insulator 118, the conductor 122, the insulator 116, the insulator 130, the insulator 112, and and depositing an insulator 132A in the first opening formed in the stack including the conductive material 114. (See FIGS. 24(A) and 24(B)). Here, the insulator 132A will become the insulator 132 in a later process. Therefore, the insulator described in this embodiment may be used. In particular, the ALD method allows for the formation of a large aspect ratio. This is preferable because it allows a film of uniform thickness to be formed even in large grooves and openings. Alternatively, the insulator 132A may be formed by a combination of the ALD method and the CVD method.

[0323] Here, the insulator 132A is in contact with the inside of the first opening and has a cylindrical shape with a space inside. It is preferable that a stator be provided.

[0324] The insulator 132A does not necessarily have to be an insulator immediately after being formed. Thin metal films such as aluminum, ruthenium, titanium, tantalum, chromium, and tungsten can be The metal film is then formed into a thin film, and oxygen is supplied to the metal film by heat treatment or the like to form an insulating metal oxide. In this case, the thickness of the metal film may be, for example, 0. The thickness may be 0.5 nm or more and 5 nm or less, preferably 1 nm or more and 2 nm or less. By performing the treatment in an atmosphere containing oxygen, the insulator 132A can be formed more reliably. In the above heat treatment, the heat treatment is once performed in an atmosphere containing nitrogen, and then The heat treatment may be performed in an atmosphere containing oxygen.

[0325] Here, in the layer 140, the oxide 106 surrounds the metal film that becomes the insulator 132A. Therefore, the oxide 10 is formed in parallel with the formation of the insulator 132A. In the vicinity of the region in contact with the metal film that will become the insulator 132A of No. 6, The metal element contained in the oxide 106 is added to the oxide 106. As a result, a region 109a is formed (see FIGS. 24(A) and 24(B)).

[0326] Next, the insulator 132A formed at the bottom of the first opening is selectively removed, and the insulator 132 (See FIGS. 25(A) and 25(B)). The insulator 132A is removed by anisotropic etching. In this case, the insulators 118 and 138 are preferably used. 132A is also removed, so that the insulator 132 is only provided on the sidewalls of the first opening.

[0327] Next, the insulator 118, the conductor 122, the insulator 116, the insulator 130, the insulator 112, and and forming an oxide 134 in a first opening formed in the stack including the conductor 114 ( 26(A)(B)). Here, the oxide 134 is the oxide described in this embodiment. The oxide 134 may be formed by using a CVD method, an ALD method, or a sputtering method. In particular, the ALD method allows for the formation of grooves and openings with large aspect ratios. This method is preferable because it can form a film with a uniform thickness. The oxide 134 may be formed by combining the CVD method. In the case where the oxide 134 is a laminated film, the MOCVD method or the MCVD method may be used. They may be formed in the same film forming apparatus or in different film forming apparatuses.

[0328] Here, the bottom of the oxide 134 is in the region 1 of the transistor 61 as shown in FIG. 72a.

[0329] The oxide 134 formed on the top surface of the memory cell array is formed by using a CMP method or the like. Preferably, it is removed.

[0330] By fabricating the memory cell array in this manner, the memory cells 10 are fabricated for each layer. The memory cells 10 of a plurality of layers can be fabricated at once without patterning for the purpose of forming the layers. Furthermore, when a memory cell array is fabricated by the above method, the memory cells 10 Increasing the number of layers also increases the number of steps in the patterning and etching process of the memory cell 10. In this way, the process of manufacturing the memory cell array can be shortened, and productivity can be improved. Therefore, a high-quality semiconductor device can be provided.

[0331] With the above-described configuration, the memory cells 10 are stacked in a direction perpendicular to the upper surface of the substrate. In this way, a three-dimensional memory cell array can be provided. By providing the layers in this way, the storage capacity per unit area can be increased according to the number of layers. The memory cell includes two transistors and one capacitance element, By using the semiconductor device described in this embodiment, In addition to its excellent characteristics, it has a memory capacity per unit area equal to or greater than that of conventional memory. Therefore, a semiconductor device with a large capacitance can be provided.

[0332] Note that the structure of the semiconductor device described in this embodiment mode is an example, and the present invention is not limited to this embodiment mode. The number and arrangement of circuit elements, wiring, etc. shown in the drawings are not limited to those shown in the drawings. The number and arrangement of circuit elements, wirings, etc., included in the semiconductor device according to this embodiment etc. can be set appropriately in accordance with the circuit configuration and driving method.

[0333] As described above, the configurations, methods, etc. shown in this embodiment may be different from the configurations, methods, etc. shown in other embodiments. They can be used in appropriate combinations.

[0334] (Embodiment 3) This embodiment mode will describe an application example of a memory device using the semiconductor device described in the above embodiment. The semiconductor device described in the above embodiment can be used in various electronic devices (for example, Terminals, computers, smartphones, e-book readers, digital cameras (including video cameras) The present invention can be applied to storage devices such as video recorders, video playback devices, and navigation systems. Here, the computer refers to a tablet computer, a notebook computer, or This includes desktop computers as well as large computers such as server systems. Alternatively, the semiconductor device according to the above embodiment may be used in a memory card (for example, D card), USB memory, SSD (Solid State Drive) and other removable media This is applied to removable storage devices. Figure 27 shows some configuration examples of removable storage devices. For example, the semiconductor device shown in the above embodiment is a packaged memory chip. It is processed into a format and used in various storage devices and removable memory.

[0335] 27A is a schematic diagram of a USB memory. The USB memory 1100 is a housing 1101. 1102, a USB connector 1103, and a substrate 1104. 4 is housed in a housing 1101. For example, the substrate 1104 includes a memory chip 110 5, controller chip 1106 is attached. The semiconductor device described in the above embodiment can be incorporated into the semiconductor device 105 or the like.

[0336] Figure 27(B) is a schematic diagram of the external appearance of an SD card, and Figure 27(C) is a schematic diagram of the internal structure of an SD card. The SD card 1110 is a schematic diagram of the structure. The SD card 1110 comprises a housing 1111, a connector 1112, and a base. The substrate 1113 is housed in a housing 1111. For example, 13 has a memory chip 1114 and a controller chip 1115 attached thereto. By providing a memory chip 1114 on the back side of the substrate 1113, the SD card 1110 The capacity can be increased. In addition, a wireless chip having a wireless communication function can be installed on the substrate 1113. This allows the host device and the SD card 1110 to communicate wirelessly. This allows data to be read from and written to the memory chip 1114. The semiconductor device described in the above embodiment can be incorporated into the chip 1114 or the like.

[0337] FIG. 27(D) is a schematic diagram of the external appearance of the SSD, and FIG. 27(E) is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a board 1153. The substrate 1153 is housed in the housing 1151. For example, the substrate 1153 has a memory The memory chip 1154, memory chip 1155, and controller chip 1156 are installed. The memory chip 1155 is a working memory for the controller chip 1156. For example, a DRAM chip may be used. A memory chip 1154 is also provided on the back side of the substrate 1153. By providing the memory chip 1153, the capacity of the SSD 1150 can be increased. The semiconductor device described in the above embodiment can be incorporated into the chip 1154 or the like.

[0338] (Fourth embodiment) In this embodiment mode, a semiconductor device according to the above embodiment mode is applied to a semiconductor device A. I will explain the system.

[0339] FIG. 28 is a block diagram showing an example of the configuration of the AI ​​system 4041. 1 includes a calculation unit 4010, a control unit 4020, and an input / output unit 4030.

[0340] The calculation unit 4010 includes an analog calculation circuit 4011, a DOSRAM 4012, and a NOSR. It has AM4013, FPGA4014, and 3D-NAND4015.

[0341] Here, DOSRAM (registered trademark) is a trademark of Dynamic Oxide Semiconductor It is an abbreviation for "Inductor RAM" and is a 1T (transistor) 1C (capacitance) type memory. Refers to RAM with a resettable register.

[0342] NOSRAM (registered trademark) stands for "Nonvolatile Oxide Semiconductor It is an abbreviation for "Semiconductor RAM" and is a memory of the gain cell type (2T type, 3T type). DOSRAM and NOSRAM refer to RAM with OS transistors. This is a memory that utilizes the low off-state current.

[0343] The control unit 4020 includes a CPU (Central Processing Unit) 40 21, GPU (Graphics Processing Unit) 4022, and P LL (Phase Locked Loop) 4023 and SRAM (Static R andom Access Memory) 4024 and PROM (Programma ble Read Only Memory) 4025 and memory controller 4026 , a power supply circuit 4027, and a PMU (Power Management Unit) 40 28 and has.

[0344] The input / output unit 4030 includes an external storage control circuit 4031, an audio codec 4032, and a video a codec 4033, a general-purpose input / output module 4034, and a communication module 4035; It has.

[0345] The calculation unit 4010 can perform learning or inference using a neural network. Cut.

[0346] The analog arithmetic circuit 4011 is an A / D (analog / digital) conversion circuit, a D / A (digital It has a digital / analog conversion circuit and a multiply-and-accumulate circuit.

[0347] The analog arithmetic circuit 4011 is preferably formed using an OS transistor. The analog arithmetic circuit 4011 using a transistor has an analog memory and performs learning or This makes it possible to perform the multiply-and-accumulate operations required for inference with low power consumption.

[0348] The DOSRAM4012 is a DRAM formed using OS transistors. The SRAM4012 temporarily stores digital data sent from the CPU4021. The DOSRAM4012 is a memory that uses memory cells that include OS transistors and Si The memory cell and the read circuit unit are stacked. Since the DOSRAM4012 can be placed on different layers, the total circuit area can be reduced It can be made smaller.

[0349] Calculations using neural networks can involve more than 1,000 pieces of input data. When storing the above input data in SRAM, the SRAM has a limited circuit area and memory capacity. Since the size of the memory is small, the input data must be divided into smaller pieces and stored. 2 allows memory cells to be highly integrated even in a limited circuit area, and SRA The memory capacity is larger than that of the M. Therefore, the DOSRAM4012 can efficiently store the above input data. It can be stored efficiently.

[0350] NOSRAM4013 is a non-volatile memory that uses OS transistors. The M4013 is a memory card that can be used with flash memory and ReRAM (Resistive Random Access Memory). Access Memory), MRAM (Magnetoresistive Ran Compared to other non-volatile memories such as DDR Memory (DDR3), data can be written to the It consumes less power when writing data. The elements do not deteriorate when writing, and there is no limit to the number of times data can be written.

[0351] In addition to 1-bit binary data, the NOSRAM4013 can also handle multi-level data of 2 or more bits. NOSRAM4013 can store multi-value data. The memory cell area per bit can be reduced.

[0352] In addition, NOSRAM4013 can store analog data in addition to digital data. Therefore, the analog arithmetic circuit 4011 converts the NOSRAM 4013 into an analog memory. The NOSRAM4013 can also be used as a memory. Therefore, D / A conversion circuits and A / D conversion circuits are not required. The RAM 4013 can reduce the area of ​​the peripheral circuits. Analog data refers to data with a resolution of 3 bits (8 values) or more. In some cases, multi-valued data is included in the analog data.

[0353] The data and parameters used in the neural network calculations are stored in NOSRA. The above data and parameters can be stored in the M4013 via the CPU4021. The data may be stored in a memory provided outside the AI ​​system 4041, but may also be stored in a memory provided inside the AI ​​system 4041. The NOSRAM4013, which is equipped with the DDR3 RAM, stores the above data and parameters at higher speeds and with lower power consumption. The NOSRAM4013 also has a higher bit rate than the DOSRAM4012. Since the bit lines can be made longer, the storage capacity can be increased.

[0354] The FPGA 4014 is an FPGA using OS transistors (OS-FPGA). The AI ​​system 4041 uses the FPGA 4014 to perform deep learning, which will be described later. Neural Networks (DNN), Convolutional Neural Networks (CNN), Recursion Neural Networks (RNNs), Autoencoders, Deep Boltzmann Machines (DBMs) , Deep Belief Networks (DBNs), etc., are used to connect neural networks in hardware. The above neural network connections can be configured in hardware. This allows for faster execution.

[0355] The OS-FPGA can reduce the memory area compared to FPGAs that are configured with SRAM. Therefore, even if a context switching function is added, the area increase is small. OS-FPGA can transmit data and parameters at high speed by boosting. do.

[0356] 3D-NAND4015 is a non-volatile memory that uses OS transistors. AND4015 is a highly integrated memory with a large storage capacity per unit area.

[0357] In addition to 1-bit binary data, 3D-NAND4015 can also handle multi-value data of 2 or more bits. 3D-NAND4015 can store multi-level data. Therefore, the memory cell area per bit can be further reduced.

[0358] In addition, as the 3D-NAND 4015, for example, the semiconductor device shown in the above embodiment is used. This allows the area occupied by the memory cells to be reduced, The semiconductor device having the memory circuit according to the embodiment can be further highly integrated. As a result, the storage capacity per unit area of ​​the storage device according to this embodiment can be increased. do.

[0359] The AI ​​system 4041 is composed of an analog arithmetic circuit 4011, a DOSRAM 4012, and an NOS The RAM4013 and FPGA4014 can be mounted on a single die (chip). Therefore, the AI ​​system 4041 is designed to be fast and low power consumption, and to use neural networks. In addition, the analog arithmetic circuit 4011 and the DOSRAM4 The 012, NOSRAM4013, and FPGA4014 are manufactured using the same manufacturing process. Therefore, the AI ​​system 4041 can be manufactured at low cost. .

[0360] The calculation unit 4010 includes a DOSRAM 4012, a NOSRAM 4013, and an FP It is not necessary to have all of GA4014. Depending on the problem that AI system 4041 wants to solve, DOSRAM4012, NOSRAM4013, and FPGA4014. A plurality of the above may be selected and provided.

[0361] AI System 4041 uses deep neural networks to solve various problems. (DNN), Convolutional Neural Network (CNN), Recurrent Neural Network RNN, autoencoder, deep Boltzmann machine (DBM), deep belief network The PROM4025 can implement techniques such as DBN. It is possible to store a program for executing at least one program. Some or all of the program may be stored in NOSRAM 4013.

[0362] Existing programs that exist as libraries are based on GPU processing. Therefore, it is preferable that the AI ​​system 4041 has a GPU 4022. The system 4041 performs the multiply-and-accumulate operation, which is the rate-limiting operation used in learning and inference. The multiplication and accumulation operations can be executed by the calculation unit 4010, and other multiplication and accumulation operations can be executed by the GPU 4022. This allows for faster learning and inference.

[0363] The power supply circuit 4027 not only generates a low power supply potential for the logic circuit but also The power supply circuit 4027 may also use an OS memory. 27 can reduce power consumption by storing the reference potential in the OS memory.

[0364] PMU4028 has the function of temporarily turning off the power supply to AI System 4041. do.

[0365] The CPU 4021 and the GPU 4022 preferably have OS memory as a register. The CPU 4021 and the GPU 4022 have OS memory, so the power supply is Even when the power is turned off, the data (logical values) can still be stored in the OS memory. As a result, the AI ​​system 4041 can save power.

[0366] The PLL 4023 has the function of generating a clock. It operates based on the clock generated by PLL4023. PLL4023 has OS memory. It is preferable that the PLL4023 has an OS memory, which allows the clock oscillation period to be adjusted. The analog potential to be controlled can be held.

[0367] The AI ​​system 4041 may store data in external memory such as DRAM. Therefore, the AI ​​System 4041 uses memory that acts as an interface with external DRAM. It is preferable that the memory controller 4026 is included. It is preferable to place it near the CPU 4021 or the GPU 4022. This allows for high-speed data exchange.

[0368] Some or all of the circuits shown in the control unit 4020 are formed on the same die as the operation unit 4010. By doing so, the AI ​​system 4041 can achieve high speed and low power consumption. Neural network calculations can be performed.

[0369] The data used for neural network calculations is stored in an external storage device (HDD). Hard Disk Drive, SSD (Solid State Drive), etc.) Therefore, the AI ​​system 4041 does not have an interface with an external storage device. It is preferable that the external memory control circuit 4031 functions as an interface.

[0370] Learning and inference using neural networks often involves audio and video, so The I system 4041 has an audio codec 4032 and a video codec 4033 . The audio codec 4032 encodes and decodes audio data. The video codec 4033 encodes and decodes the video data.

[0371] The AI ​​system 4041 performs learning or inference using data obtained from external sensors. Therefore, the AI ​​system 4041 has a general-purpose input / output module 4034. The general-purpose input / output module 4034 is, for example, a USB (Universal Ser ial Bus) and I2C (Inter-Integrated Circuit), etc. Includes.

[0372] The AI system 4041 can learn or perform inference using data obtained via the Internet. Therefore, the AI system 4041 preferably has a communication module 403 5.

[0373] The analog arithmetic circuit 4011 may use a multi-valued flash memory as an analog memory. However, the flash memory has a limited number of rewritable times. Also, it is very difficult to form a multi-valued flash memory embedded (forming the arithmetic circuit and the memory on the same die).

[0374] Also, the analog arithmetic circuit 4011 may use ReRAM as an analog memory. However, ReRAM has a limited number of rewritable times and also has problems in terms of storage accuracy. Furthermore, since it is a two-terminal element, the circuit design for separating data writing and reading becomes complicated.

[0375] Also, the analog arithmetic circuit 4011 may use MRAM as an analog memory. However, MRAM has a low resistance change rate and has problems in terms of storage accuracy.

[0376] In view of the above, it is preferable for the analog arithmetic circuit 4011 to use the OS memory as an analog memory.

[0377] The configuration shown in this embodiment can be used in appropriate combination with the configuration shown in other embodiments.

[0378] (Embodiment 5) <Application Examples of AI System> In this embodiment, application examples of the AI system shown in the above embodiment will be described using FIG. 29. ​

[0379] FIG. 29(A) shows the AI ​​system 4041 described in FIG. 28 arranged in parallel and connected via a bus line. This is AI system 4041A, which enables signals to be sent and received between systems.

[0380] The AI ​​system 4041A shown in FIG. 29(A) includes a plurality of AI systems 4041_1 to AI system 4041_n (n is a natural number of 2 or more). The AI ​​systems 4041_1 to 4041_n are connected to each other via a bus line 4098.

[0381] 29(B) shows the AI ​​system 4041 described in FIG. 28 in the same manner as in FIG. 29(A). AI systems are arranged in parallel, enabling signals to be sent and received between systems via a network. The stem is 4041B.

[0382] The AI ​​system 4041B shown in FIG. 29(B) is a system including a plurality of AI systems 4041_1 The AI ​​systems 4041_1 to 4041_n are 041_n are connected to each other via a network 4099.

[0383] The network 4099 is a network of the AI ​​systems 4041_1 to 4041_n. Each of them may be provided with a communication module, and configured to perform wireless or wired communication. The communication module can communicate via an antenna. For example, World Wi The Internet, intranets, and extranets that form the foundation of the World Wide Web (WWW) PAN (Personal Area Network), LAN (Local A rea Network), CAN (Campus Area Network), MA N (Metropolitan Area Network), WAN (Wide Ar Network), GAN (Global Area Network), etc. Each AI system can be connected to a computer network and communicate with each other. When carrying out this, LTE (Long Term Evolution) is used as the communication protocol or communication technology. lution), GSM (Global System for Mobile Com) communication: registered trademark), EDGE (Enhanced Data Rate s for GSM Evolution), CDMA2000 (Code Divis ion Multiple Access 2000), W-CDMA (registered trademark), etc. communication standard, or Wi-Fi (registered trademark), Bluetooth (registered trademark), Zig Specifications standardized by IEEE such as Bee (registered trademark) can be used.

[0384] By using the configuration shown in Figures 29(A) and 29(B), analog signals obtained from external sensors etc. can be It can be processed by separate AI systems. For example, biometric information such as brain waves, pulse, Information such as blood pressure and body temperature is transmitted via a brain wave sensor, pulse wave sensor, blood pressure sensor, and temperature sensor. It is possible to acquire data from various sensors and process the analog signals with separate AI systems. Each AI system processes signals or learns, creating a single AI system. Therefore, the amount of information processing required for signal processing or learning can be reduced. As a result, recognition accuracy can be improved. The system can instantly and comprehensively grasp complex changes in biological information. It is expected that this will be possible.

[0385] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0386] (Embodiment 6) This embodiment shows an example of an IC incorporating the AI ​​system shown in the above embodiment. .

[0387] The AI ​​system shown in the above embodiment is a digital processor such as a CPU that is made up of Si transistors. logic circuits, analog arithmetic circuits using OS transistors, OS-FPGA and DOSR OS memory such as AM and NOSRAM can be integrated onto a single die.

[0388] Figure 30 shows an example of an IC incorporating an AI system. The IC7000 has leads 7001 and a circuit section 7003. For example, the IC chip is mounted on a printed circuit board 7002. These are electrically connected to each other on the printed circuit board 7002, and electronic components are mounted on them. The circuit portion 7003 has the same structure as that shown in the above embodiment mode. The circuit section 7003 is similar to the circuit section 7001 shown in the previous embodiment. As shown, it has a laminated structure, and includes a Si transistor layer 7031, a wiring layer 7032, an OS transistor The OS transistor layer 7033 is divided into a Si transistor layer 7031 and a Since the ICs can be stacked on top of each other, it is easy to miniaturize the AI ​​system IC7000.

[0389] In Figure 30, the AI ​​system IC7000 is packaged in a QFP (Quad Flat Packaging) However, the form of the package is not limited to this.

[0390] Digital processing circuits such as CPUs and analog arithmetic circuits using OS transistors, FPGAs and OS memories such as DOSRAM and NOSRAM are all made of Si transistors. layer 7031, a wiring layer 7032, and an OS transistor layer 7033. In other words, the elements that make up the AI ​​system can be formed in the same manufacturing process. Therefore, the IC shown in this embodiment can be manufactured in a simple manner even if the number of constituent elements increases. There is no need to increase the number of servers, and the AI ​​system can be incorporated at low cost.

[0391] The structure described in this embodiment mode may be used in appropriate combination with structures described in other embodiments. can be done.

[0392] (Embodiment 7) <Electronic equipment> The semiconductor device according to one embodiment of the present invention can be used in a variety of electronic devices. 33A to 33C illustrate specific examples of electronic devices using a semiconductor device according to one embodiment of the present invention.

[0393] The robot 2100 shown in FIG. 31(A) includes a computing device 2110, an illuminance sensor 2101, a Microphone 2102, upper camera 2103, speaker 2104, display 2105 , a lower camera 2106, an obstacle sensor 2107, and a movement mechanism 2108.

[0394] The microphone 2102 has a function of detecting the user's voice and environmental sounds. The speaker 2104 has a function of emitting sound. The phone 2102 and the speaker 2104 are used to communicate with the user. is possible.

[0395] The display 2105 has the function of displaying various information. The information desired by the user can be displayed on the display 2105. The device 2105 may be equipped with a touch panel.

[0396] The upper camera 2103 and the lower camera 2106 capture images of the surroundings of the robot 2100. The obstacle sensor 2107 also detects the obstacles of the robot 21 by using the moving mechanism 2108. Robot 2 can detect the presence or absence of obstacles in its path as it moves forward. 100 uses an upper camera 2103, a lower camera 2106, and an obstacle sensor 2107. This allows the robot to recognize its surroundings and move safely.

[0397] The flying object 2120 shown in FIG. 31(B) includes a computing device 2121, a propeller 2123, and a camera. It has a Mera 2122 and has the ability to fly autonomously.

[0398] In the flying object 2120, the above semiconductor device is provided in the computing device 2121 and the camera 2122. It can be used.

[0399] 31(C) is an external view showing an example of an automobile. The automobile 2980 is equipped with a camera 298 1st place. In addition, the car 2980 is equipped with infrared radar, millimeter wave radar, laser radar, The car 2980 is equipped with various sensors such as a camera 2981. The system analyzes the surrounding traffic conditions, such as whether there are pedestrians, and can then drive autonomously.

[0400] Figure 31(D) shows a case where two or more people communicate in different languages. 2 shows a situation in which a portable electronic device 2130 is used for simultaneous interpretation.

[0401] The portable electronic device 2130 has a microphone and a speaker, etc., and can pick up the user's voice. It has the ability to recognize and translate into the language spoken by the person you are speaking to.

[0402] In FIG. 31(D), the user uses a portable microphone 2131. The microphone 2131 has a wireless communication function and transmits the detected sound to the portable electronic device 213. It has the ability to send to 0.

[0403] FIG. 32(A) is a schematic cross-sectional view showing an example of a pacemaker.

[0404] The pacemaker main body 5300 includes batteries 5301a and 5301b, a regulator, and , a control circuit, an antenna 5304, a wire 5302 to the right atrium, a wire 5303 to the right ventricle 03 and at least.

[0405] The pacemaker body 5300 is placed inside the body by surgery, and two wires are inserted into the clavicle of the human body. The wire is passed through the inferior vena cava 5305 and the superior vena cava 5306, and one end of the wire is inserted into the right ventricle and the other end into the right ventricle. The tip of the wire is placed in the right atrium.

[0406] In addition, the antenna 5304 can receive power, and the power is supplied to multiple batteries 5301a, 5301b, which can reduce the frequency of pacemaker replacement. The 5300 camera body has multiple batteries, making it highly safe and allowing you to continue using it even if one of them fails. Even if one power supply is turned on, the other power supply can still function, so it can also function as an auxiliary power source.

[0407] In addition to the antenna 5304 that can receive power, an antenna that can transmit physiological signals is also provided. For example, physiological signals such as pulse, respiratory rate, heart rate, and temperature may be monitored externally. A system may be configured to monitor cardiac activity as seen by the device.

[0408] The sensor 5900 shown in FIG. 32(B) is attached to the human body using an adhesive pad or the like. The sensor 5900 transmits a signal to electrodes 5931 attached to the human body via wiring 5932. The acquired information is transmitted as a wireless signal and read out. The information is transmitted to a terminal such as a reading device.

[0409] FIG. 33 is a schematic diagram showing an example of a cleaning robot.

[0410] The cleaning robot 5100 has a display 5101 on the top surface and a It has a plurality of cameras 5102, a brush 5103, and an operation button 5104. Although not shown, the cleaning robot 5100 is provided with tires, a suction port, etc. on its underside. The cleaning robot 5100 also has infrared sensors, ultrasonic sensors, acceleration sensors, and piezo sensors. It is equipped with various sensors such as sensors, light sensors, and gyro sensors. The 5100 is equipped with wireless communication means.

[0411] The cleaning robot 5100 moves by itself, detects the dust 5120, and sucks it out from the suction port on the bottom. It can suck up dirt from

[0412] In addition, the cleaning robot 5100 analyzes the image captured by the camera 5102 and detects the walls, furniture, or It can also detect obstacles such as steps and other obstacles by analyzing images. If an object that may become entangled in the brush 5103 is detected, the rotation of the brush 5103 will be stopped. can be done.

[0413] The display 5101 can display the remaining battery level and the amount of dust that has been sucked up. The route traveled by the cleaning robot 5100 can be displayed on the display 5101. Also, the display 5101 may be a touch panel, and the operation buttons 5104 may be It may be provided in the play 5101.

[0414] The cleaning robot 5100 can communicate with a mobile electronic device 5140 such as a smartphone. The image captured by the camera 5102 can be displayed on the portable electronic device 5140. Therefore, the owner of the Cleaning Robot 5100 can check the status of the room even when they are away from home. In addition, the display on the display 5101 can be displayed on a portable electronic device such as a smartphone. You can also check it with a device.

[0415] For example, a memory device using the semiconductor device of one embodiment of the present invention can be used for the control information of the above-described electronic devices. The semiconductor device according to one aspect of the present invention can store information, control programs, and the like for a long period of time. By using the device, highly reliable electronic equipment can be realized.

[0416] In addition, for example, the AI ​​system is incorporated into the arithmetic unit of the electronic device. Therefore, the electronic device described in this embodiment can be implemented as an AI system. This allows for appropriate operation according to the situation to be performed with low power consumption.

[0417] This embodiment mode can be implemented by being appropriately combined with the configurations described in other embodiment modes. It is Noh. [Explanation of symbols]

[0418] 10: memory cell, 11: transistor, 12: transistor, 14: capacitance element, 20: Memory cell string, 30:dimensional memory cell array, 40:dimensional memory cell array, 5 0: selection transistor array, 51: drive circuit, 52: readout circuit, 53: drive circuit, 54: drive circuit, 60: selection transistor cell, 61: transistor, 62: transistor 106: oxide, 106A: oxide, 106B: oxide, 109a: region, 109b : Area, 112: Insulator, 112A: Insulator, 112B: Insulator, 112C: Insulator, 1 14: conductor, 114A: conductor, 114B: conductor, 114C: conductor, 116: insulator body, 116A: insulator, 116B: insulator, 116C: insulator, 118: insulator, 118 A: insulator, 118B: insulator, 118C: insulator, 120: conductor, 122: conductor, 122A: conductor, 122B: conductor, 122C: conductor, 126: insulator, 127: insulator Insulator, 128: Insulator, 129: Insulator, 130: Insulator, 130A: Insulator, 130B : insulator, 130C: insulator, 132: insulator, 132A: insulator, 134: oxide, 1 38: insulator, 140: layer, 141: layer, 142: layer, 150: semiconductor substrate, 154a: Conductor, 154b: Conductor, 160: Region, 162a: Insulator, 162b: Insulator, 16 4: Insulator, 165: Insulator, 166: Insulator, 168: Insulator, 170: Insulator, 17 2a: area, 172b: area, 172c: area, 172d: area, 174a: conductor, 1 74b: conductor, 176a: conductor, 176b: conductor, 178a: conductor, 178b: conductor, 178c: conductor, 178d: conductor, 180a: conductor, 180b: conductor, 180c: conductor, 180d: conductor, 1100: USB memory, 1101: housing, 11 02: Cap, 1103: USB connector, 1104: Board, 1105: Memory chip ,1106: Controller chip, 1110: SD card, 1111: Housing, 1112: Connector, 1113: Board, 1114: Memory chip, 1115: Controller chip, 1150: SSD, 1151: housing, 1152: connector, 1153: board, 1154: Memory chip, 1155: Memory chip, 1156: Controller chip, 2100: Bot, 2101: Illumination sensor, 2102: Microphone, 2103: Upper camera, 2 104: Speaker, 2105: Display, 2106: Lower camera, 2107: Obstacle Sensor, 2108: moving mechanism, 2110: computing device, 2120: flying object, 2121: computing device, 2122: camera, 2123: propeller, 2130: portable electronic device, 2131: portable Belt-type microphone, 2980: automobile, 2981: camera, 4010: computing unit, 401 1: Analog arithmetic circuit, 4012: DOSRAM, 4013: NOSRAM, 4014: FPGA, 4015: 3D-NAND, 4020: Control unit, 4021: CPU, 4022 :GPU, 4023:PLL, 4024:SRAM, 4025:PROM, 4026: Memory controller, 4027: power supply circuit, 4028: PMU, 4030: input / output unit, 40 31: external memory control circuit, 4032: audio codec, 4033: video codec, 40 34: General-purpose input / output module, 4035: Communication module, 4041: AI system, 4 041_1: AI system, 4041_n: AI system, 4041A: AI system, 4041B: AI system, 4098: Bus line, 4099: Network, 5100: Sweeping Robot, 5101: Display, 5102: Camera, 5103: Brush, 5104 :Operation buttons, 5120:Garbage, 5140:Portable electronic devices, 5300:Pacemaker body , 5301a: Battery, 5301b: Battery, 5302: Wire, 5303: Wire Ear, 5304: Antenna, 5305: Subclavian vein, 5306: Superior vena cava, 5900: Sensor, 5931: Electrode, 5932: Wiring, 7000: AI system IC, 7001: Lead 7002: Printed circuit board, 7003: Circuit section, 7004: Mounting board, 7031: Si Transistor layer, 7032: Wiring layer, 7033: OS transistor layer

Claims

1. A semiconductor device having a memory cell, the memory cell includes a first transistor, a second transistor, and a capacitance element; one of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the first transistor is electrically connected to one of the electrodes of the capacitor element; In a cross-sectional view of the first transistor in a channel length direction, the channel length direction of the first transistor has a region extending in a first direction, In the cross-sectional view, the channel length direction of the second transistor has a region extending in a second direction intersecting the first direction.

2. A semiconductor device having a memory cell, the memory cell includes a first transistor, a second transistor, and a capacitance element; one of the source and the drain of the first transistor is electrically connected to the gate of the second transistor; one of a source and a drain of the first transistor is electrically connected to one of the electrodes of the capacitor element; In a cross-sectional view of the first transistor in a channel length direction, the channel length direction of the first transistor has a region extending in a first direction, In the cross-sectional view, the channel length direction of the second transistor has a region extending in a second direction intersecting the first direction, the second transistor includes an oxide semiconductor; the oxide semiconductor has a first region, a second region, and a third region having a region disposed between the first region and the second region; the first region functions as one of a source and a drain of the first transistor, one of electrodes of the capacitor, and a gate of the second transistor; the second region functions as the other of the source and the drain of the first transistor, The third region functions as a channel formation region of the first transistor.

Images