Photoelectric conversion device and apparatus

Abstract

Some embodiments of the present invention provide a technique advantageous in improving the image capturing performance of a photoelectric conversion apparatus having a voltage holding type global electronic shutter function.SOLUTION: According to an embodiment of the present disclosure, there is provided a photoelectric conversion apparatus including a plurality of pixels and a processing circuit configured to process signals read out from the plurality of pixels, wherein each of the plurality of pixels includes a photoelectric conversion element, a first amplification unit including an input node to which a signal from the photoelectric conversion element is input and configured to output a signal obtained by amplifying a signal level of the input node, and a holding unit configured to hold an output signal of the first amplification unit, and a second amplification unit including a second input node to which a signal output from the holding capacitance unit is input and configured to output a signal obtained by amplifying a signal level of the second input node, in which a capacitance value of the holding capacitance unit is changed according to a change in a driving force of at least one of the first amplification unit and the second amplification unit.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to photoelectric conversion devices and equipment. [Background technology]

[0002] It has been proposed that a photoelectric conversion device perform a global electronic shutter operation that simultaneously resets the photoelectric conversion units arranged in each of multiple pixels and reads out charges from the photoelectric conversion units. Patent Document 1 discloses an imaging device equipped with a voltage-holding global electronic shutter function that converts signal charges into voltage and holds them. The imaging device described in Patent Document 1 achieves the global electronic shutter operation by simultaneously holding the signal voltage generated in the photoelectric conversion units in capacitive elements for all pixels and then sequentially reading out the held voltages. Patent Document 1 also discloses that the size of the capacitive element for R pixels, which are provided with red optical filters and receive a relatively small amount of incident light, is made larger than the size of the capacitive element for G pixels, which are provided with green optical filters and receive a relatively large amount of incident light. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2023-83030 Summary of the Invention [Problem to be solved by the invention]

[0004] In Patent Document 1, the relationship between the setting of the size of the capacitance element and the signal settling time is not considered, and there is room for further improvement in the accuracy of the signal held by the capacitance element and imaging performance. [Means for solving the problem]

[0005] According to one disclosure of this specification, there is provided a photoelectric conversion device comprising a plurality of pixels and a processing circuit that processes signals read out from the plurality of pixels, wherein each of the plurality of pixels comprises a photoelectric conversion element, a first amplifier unit having an input node to which a signal from the photoelectric conversion element is input and that outputs a signal obtained by amplifying the signal level of the input node, a holding capacitor unit that holds the output signal of the first amplifier unit and has a variable capacitance value, and a second amplifier unit having a second input node to which a signal output from the holding capacitor unit is input and that outputs a signal obtained by amplifying the signal level of the second input node, and wherein the photoelectric conversion device is characterized in that the capacitance value of the holding capacitor unit is changed in response to a change in the driving power of at least one of the first amplifier unit and the second amplifier unit.

[0006] According to another disclosure of the present specification, there is provided a photoelectric conversion device comprising a plurality of pixels and a processing circuit that processes signals read out from the plurality of pixels, wherein each of the plurality of pixels comprises a photoelectric conversion element, a first amplifier unit that has an input node to which a signal from the photoelectric conversion element is input and outputs a signal that is an amplified signal level of the input node, and a storage capacitor unit that holds the output signal of the first amplifier unit and has a variable capacitance value, and wherein the capacitance value of the storage capacitor unit is changed in response to a change in the driving power of the first amplifier unit.

[0007] According to another disclosure of the present specification, there is provided a photoelectric conversion device comprising a plurality of pixels and a processing circuit that processes signals read out from the plurality of pixels, wherein each of the plurality of pixels comprises a photoelectric conversion element, a first amplifier unit having an input node to which a signal from the photoelectric conversion element is input and that outputs a signal obtained by amplifying the signal level of the input node, and a holding capacitor unit that is connected to the first amplifier unit via a switch, holds the output signal of the first amplifier unit, and has a variable capacitance value, and wherein the photoelectric conversion device changes the capacitance value of the holding capacitor unit in response to a change in the on period of the switch. [Effects of the Invention]

[0008] An object of the present invention is to provide a technique that is advantageous for improving imaging performance in a photoelectric conversion device having a voltage holding type global electronic shutter function. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a block diagram illustrating a photoelectric conversion device according to a first embodiment. [Figure 2] Schematic diagram illustrating a photoelectric conversion device according to a first embodiment. [Figure 3] 1 is a circuit diagram illustrating a photoelectric conversion device according to a first embodiment; [Figure 4] 1 is a circuit diagram of a current source of a photoelectric conversion device according to a first embodiment; [Figure 5] Circuit diagram of a signal retention memory of a photoelectric conversion device according to a first embodiment [Figure 6] 1 is a timing chart showing a driving timing of a photoelectric conversion device according to a first embodiment; [Figure 7] 1 is a cross-sectional view illustrating a photoelectric conversion device according to a first embodiment; [Figure 8] FIG. 10 is a cross-sectional view illustrating another example of the photoelectric conversion device according to the first embodiment. [Figure 9] 1 is a plan view of a signal retention memory of a photoelectric conversion device according to a first embodiment; [Figure 10] FIG. 10 is a schematic plan view of a signal retention memory showing another example of the photoelectric conversion device according to the first embodiment; [Figure 11] Circuit diagram of a signal retention memory of a photoelectric conversion device according to a second embodiment [Figure 12] 10 is a timing chart showing a driving timing of a photoelectric conversion device according to a second embodiment; [Figure 13] 10 is a plan view of a signal retention memory of a photoelectric conversion device according to a second embodiment; [Figure 14] Circuit diagram of a signal retention memory of a photoelectric conversion device according to a third embodiment [Figure 15] 10 is a plan view of a signal retention memory of a photoelectric conversion device according to a third embodiment; [Figure 16] FIG. 10 is a schematic diagram illustrating a device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] The embodiments described below are intended to embody the technical ideas of the present disclosure and are not intended to limit the present disclosure. The sizes and positional relationships of components shown in each drawing may be exaggerated for clarity. In the following description, the same components may be designated by the same reference numerals and their description may be omitted.

[0011] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following description, terms indicating specific directions or positions (e.g., "upper," "lower," "right," "left," and other terms including these terms) will be used as necessary. The use of these terms is intended to facilitate understanding of the embodiments with reference to the drawings, and the meanings of these terms do not limit the technical scope of the present disclosure.

[0012] In this specification, the term "plane" refers to a surface parallel to the main surface of a substrate. The main surface of a substrate may be the light incident surface of a substrate including a photoelectric conversion element, a surface on which multiple ADCs are repeatedly arranged, or a bonding surface between substrates in a stacked photoelectric conversion device. The term "planar view" refers to a view perpendicular to the light incident surface of a semiconductor layer. The term "cross section" refers to a surface perpendicular to the light incident surface of a semiconductor layer. The term "cross section" refers to a view perpendicular to the light incident surface of a semiconductor layer. When the light incident surface of a semiconductor layer is rough when viewed microscopically, the planar view is defined based on the light incident surface of the semiconductor layer when viewed macroscopically.

[0013] In the following embodiments, an image pickup device will be mainly described as an example of a photoelectric conversion device. However, the embodiments are not limited to image pickup devices and can be applied to other examples of photoelectric conversion devices. For example, a distance measurement device (a device that measures distance using focus detection or TOF (Time Of Flight)) or a photometry device (a device that measures the amount of incident light) can be used.

[0014] Metallic components such as wiring and pads described herein may be composed of a single metal element or a mixture (alloy). For example, wiring described as copper wiring may be composed of copper alone or may be composed primarily of copper with other components. Furthermore, for example, pads connected to external terminals may be composed of aluminum alone or may be composed primarily of aluminum with other components. The copper wiring and aluminum pads shown here are merely examples and can be replaced with various metals. Furthermore, the wiring and pads shown here are merely examples of metallic components used in photoelectric conversion devices and may also be applied to other metallic components.

[0015] In the following description, it is assumed that the charges accumulated by the photoelectric conversion unit in a pixel are electrons. Also, it is assumed that all transistors provided in a pixel are N-channel MOS transistors (hereinafter abbreviated as NMOS transistors). However, the charges accumulated by the photoelectric conversion unit may be holes, in which case the transistors of the pixel may be P-channel MOS transistors (hereinafter abbreviated as PMOS transistors). In other words, the conductivity type of transistors etc. can be changed as appropriate depending on the polarity of the charges handled as signals.

[0016] In the following embodiments, the connection between elements of a circuit may be described. In this case, even if another element is interposed between the elements of interest, the elements of interest are treated as being connected to each other unless otherwise specified. For example, assume that element A is connected to one node of a capacitive element C having multiple nodes, and element B is connected to the other node. Even in such a case, element A and element B are treated as being connected to each other unless otherwise specified.

[0017] (First embodiment) A photoelectric conversion device according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 10. FIG.

[0018] FIG. 1 is a schematic diagram of an example of a photoelectric conversion device according to this embodiment.

[0019] As shown in FIG. 1, the photoelectric conversion device 10 includes three substrates: a first substrate 100, a second substrate 200, and a third substrate 300. The photoelectric conversion device 10 has a three-dimensional structure formed by bonding these three substrates together. The first substrate 100, the second substrate 200, and the third substrate 300 are stacked in this order. However, more substrates may be stacked. In the following, a photoelectric conversion device in which multiple substrates are stacked will be described as an example. However, a single substrate in which the components included in the first substrate 100, the second substrate 200, and the third substrate 300 are arranged may also be used as the photoelectric conversion device.

[0020] The first substrate 100 includes a pixel region 110 in which a plurality of pixels are arranged in a two-dimensional array in a planar view. The second substrate 200 includes a memory region 210 in which a plurality of pixel memories are arranged in a two-dimensional array in a planar view. The third substrate 300 includes a signal processing unit 310 in which a plurality of signal processing circuits are arranged.

[0021] The first substrate 100, the second substrate 200, and the third substrate 300 may each be a semiconductor layer such as a silicon substrate. The first substrate 100, the second substrate 200, and the third substrate 300 may each include a semiconductor layer and a wiring structure. Each substrate may be a chip or a wafer. The photoelectric conversion device 10 has a plurality of metal junctions formed by bonding a metal member of a top layer (first bonding layer), which is the wiring layer of the first substrate's wiring structure closest to the second substrate, to a metal member of a top layer (second bonding layer), which is the wiring layer of the second substrate's wiring structure closest to the first substrate. The bonding surfaces on which the plurality of metal junctions are formed also include an insulating junction formed by bonding an insulating member of the first bonding layer to an insulating member of the second bonding layer. The second substrate and the third substrate are also bonded using a bonding structure similar to that of the first substrate and the second substrate. In this manner, bonding the metal members provided on each substrate allows signals to be exchanged between the respective components.

[0022] FIG. 2 is an example of a block diagram of the photoelectric conversion device according to this embodiment.

[0023] The first substrate 100 includes a pixel region 110, a vertical scanning circuit 120, and a pixel control circuit 20. The pixel region 110 has a plurality of pixels 30 that perform photoelectric conversion. The plurality of pixels 30 are arranged in an array across a plurality of rows and a plurality of columns within the pixel region 110. The pixels 30 include photoelectric conversion elements such as photodiodes. The photoelectric conversion elements may be photoelectric conversion films. The photoelectric conversion elements generate and accumulate signal charges according to incident light. The pixels 30 output pixel signals according to the amount of this signal charge. The pixel signals output from the pixels 30 are analog signals.

[0024] In addition to effective pixels that output pixel signals according to the amount of incident light, optical black pixels in which photoelectric conversion elements are shielded, dummy pixels that do not output signals, etc. may be arranged in the pixel region 110. Furthermore, in this specification, the horizontal direction in the drawings is referred to as the row direction, and the vertical direction is referred to as the column direction, and the number of rows and columns of the pixel array arranged in the pixel region 110 is not particularly limited.

[0025] The pixel control circuit 20 is a logic circuit that generates timing for operating the pixels 30, and outputs drive pulses for the pixels 30 to the vertical scanning circuit 120. The vertical scanning circuit 120 has a driver that drives the pixels 30 row by row. The voltage SVDD, which is the power supply voltage, and the voltage SGND, which is the reference voltage, supplied to the pixels 30 may be supplied via a pad, a metal junction, or the like, or may be supplied via the pixel control circuit 20.

[0026] The second substrate 200 includes a memory region 210, a memory vertical scanning circuit 220, a current source 230, and a memory control circuit 21. The pixel memories 40 are arranged in an array across multiple rows and multiple columns in the memory region 210. The pixel memories 40 have the function of holding pixel signals output from the pixels 30. Note that the number of pixels 30 included in the pixel region 110 does not need to be the same as the number of pixel memories 40 included in the memory region 210. For example, pixel memories 40 do not need to be arranged for dummy pixels that do not output signals. Furthermore, dummy pixel memories that do not output signals may be arranged corresponding to the dummy pixels.

[0027] The current source 230 supplies a reference current to the pixel memory 40. The memory control circuit 21 has a logic circuit that generates timing for operating the pixel memory 40 and controls circuits arranged around the pixel, such as the current source 230. The drive pulses output from the memory control circuit 21 are input to the memory vertical scanning circuit 220. The memory vertical scanning circuit 220 has a driver that drives the pixel memory 40 row by row. The voltage MVDD, which is the power supply voltage supplied to the memory 40, and the voltage MGND, which is the reference voltage, may be supplied via a pad, a metal junction, or the like, or may be supplied via the memory control circuit 21.

[0028] The third substrate 300 includes a signal processing unit 310, a column control circuit 320, a ramp generator 340, a current source 330, and a signal processing control circuit 22. The signal processing unit 310 includes column signal processing circuits 50 arranged in an array in the column direction. The column signal processing circuit 50 performs analog-to-digital (AD) conversion on the signal voltage output from the pixel memory 40 based on a reference voltage generated by the ramp generator 340. The AD-converted signal is then output to the outside of the third substrate 300 as image data. In this embodiment, ramp-type AD conversion is described as an example of the AD conversion method. However, the AD conversion method is not limited to ramp-type AD conversion. For example, the AD conversion method can be successive approximation AD conversion, cyclic AD conversion, ΔΣ AD conversion, or other AD conversion methods. The column signal processing circuit 50 may also perform digital processing such as noise reduction on the image data.

[0029] The current source 330 supplies a reference current to the column signal processing circuit 50. The signal processing control circuit 22 has a logic circuit that generates timing for operating the column signal processing circuit 50 and sets the functions of the ramp generator 340 and the current source 330. A drive pulse output from the signal processing control circuit 22 is input to the column control circuit 320. The column control circuit 320 has a drive driver that outputs a drive pulse to the column signal processing circuit 50. The voltage AVDD, which is a power supply voltage, and the voltage AGND, which is a reference voltage, supplied to the column signal processing circuit 50 may be supplied via a pad, a metal junction, or the like, or may be supplied via the signal processing control circuit 22.

[0030] The photoelectric conversion device according to this embodiment is a photoelectric conversion device that performs a so-called voltage domain global electronic shutter operation. Readout of the pixel 30 in the photoelectric conversion device according to this embodiment will be described with reference to FIGS.

[0031] FIG. 3 is an example of a circuit diagram of the pixel 30, pixel memory 40, and column signal processing circuit 50 included in the photoelectric conversion device according to this embodiment.

[0032] Each pixel 30 includes a photoelectric conversion element (PD) 115, a PD 116, a transfer transistor 113 (pixel transfer transistor), a transfer transistor 114 (pixel transfer transistor), and a reset transistor 112 (pixel reset transistor). The pixel 30 also includes an amplification transistor 111 (first amplification unit, pixel amplification transistor), a selection transistor 117 (pixel selection transistor), and a floating diffusion capacitance unit (FD capacitance unit). The FD capacitance unit is the input node of the amplification transistor 111, which is the first amplification unit. Signals from the PDs 115 and 116 are input to the amplification transistor 111. The amplification transistor 111 outputs a signal obtained by amplifying the signal level of this input node. Note that, in this specification, "amplification" includes both gains of 1x or greater and gains of less than 1x. The amplification transistor 111 operates as a source follower circuit. Typically, the amplification factor of the amplification transistor 111 is in the range of 0.8x to 1x.

[0033] The photoelectric conversion device according to this embodiment includes PD115 and PD116 in one pixel. The signals from PD115 and PD116 are used for phase difference detection, making this a so-called image-plane phase difference detection photoelectric conversion device. The anode terminal of PD115 is connected to a reference power supply SGND, and the cathode terminal is connected to the source of the transfer transistor 113. The anode terminal of PD116 is connected to a reference power supply SGND, and the cathode terminal is connected to the source of the transfer transistor 114. The drains of the transfer transistor 113 and 114 are connected to the gate of the amplifier transistor 111 and the source of the reset transistor 112, respectively. An FD capacitance unit is connected to the gate of the amplifier transistor 111, with the reference power supply SGND as a reference. The FD capacitance unit temporarily stores signal charges generated by PD115 and PD116 and functions as a charge-voltage converter that converts the stored signal charges into a voltage signal. The drains of the reset transistor 112 and the amplifier transistor 111 are connected to the power supply wiring for voltage SVDD. The source of the amplification transistor 111 is connected to the drain of the selection transistor 117 .

[0034] 3 is just an example, and the pixel 110 may further include a transistor. For example, a transistor that changes the capacitance value of the FD 114 or a transistor that discharges signal charge from the photoelectric conversion element 115 may further be provided. Alternatively, the pixel 110 may be configured not to include the selection transistor 117, but rather to change the selected or unselected state of the pixel 110 depending on the voltage input from the reset transistor 112 to the FD 114.

[0035] The pixel memory 40 includes a storage capacitor 240. The storage capacitor 240 may be configured with a plurality of capacitance elements and a plurality of write transistors. In this embodiment, the storage capacitor 240 includes a signal storage memory Nmem (first capacitance element), a signal storage memory Smem-A (second capacitance element), and a signal storage memory Smem-AB (third capacitance element) as a combination of a plurality of capacitance elements. Hereinafter, the plurality of signal storage memories may be collectively referred to as the signal storage memory mem (storage capacitor 240). The signal storage memory Nmem is connected to a memory write transistor 213, the signal storage memory Smem-A is connected to a memory write transistor 214, and the signal storage memory Smem-AB is connected to a memory write transistor 215. The pixel memory 40 further includes a reset transistor 212, an amplification transistor 211, a current source transistor 216 (first current source transistor), a switch transistor 217, and a selection transistor 218. The reset transistor 212 is a memory reset transistor, the amplifying transistor 211 is a memory amplifying transistor, and the selecting transistor 218 is a memory selecting transistor.

[0036] The source of the selection transistor 117 of the pixel 30 is connected to the drain of the current source transistor 216 of the pixel memory 40 via a metal junction 400. The source of the current source transistor 216 is connected to the drain of the switch transistor 217. At this time, a control signal VBIAS1 is supplied to the gate of the current source transistor 216 from a current source 230, and the current source transistor 216 is controlled so that a current based on the control signal VBIAS1 flows. The configuration of the current source 230 will be described later.

[0037] The source of the selection transistor 218 is connected to the drain of a current source transistor 313 (second current source transistor) of the column signal processing circuit 50 via a metal junction 401. The source of the current source transistor 313 is connected to the drain of the switch transistor 314. At this time, a control signal VBIAS2 is supplied from a current source 330 to the current source transistor 313, and the current source transistor 313 is controlled so that a current based on the control signal VBIAS2 flows.

[0038] Cu-Cu bonding (Cu to Cu Bonding, CCB) can be used as the metal joints 400, 410. However, the method for electrically connecting the first substrate 100 and the second substrate 200, and the second substrate 200 and the third substrate 300 may be configured by TSV (Through Silicon Via) or the like.

[0039] The signal retention memory Nmem has one terminal connected to a power supply wiring that supplies a reference power supply MGND, and the other terminal connected to the source of the memory write transistor 213. The drain of the memory write transistor 213 is connected to the gate of the amplifier transistor 211 (second amplifier section). Similarly, the signal retention memory Smem-A has one terminal connected to a power supply wiring that supplies a reference power supply MGND, and the other terminal connected to the source of the memory write transistor 214. The drain of the memory write transistor 214 is connected to the gate of the amplifier transistor 211. The signal retention memory Smem-AB has one terminal connected to a power supply wiring that supplies a reference power supply MGND, and the other terminal connected to the source of the memory write transistor 215. The drain of the memory write transistor 215 is connected to the gate of the amplifier transistor 211. In this case, the signal retention memory (capacitive element) may be any element that has the function of retaining a signal.

[0040] The capacitive element may be, for example, a capacitor formed in a wiring structure, or a capacitor formed in a semiconductor layer such as a silicon substrate. The capacitor formed in the wiring structure is, for example, a DRAM (Dynamic Random Access Memory) or an MIM (Metal-Insulator-Metal) capacitor structure formed in the wiring structure. Furthermore, the capacitor formed in a semiconductor substrate such as a silicon substrate is, for example, an MIS (Metal-Insulator-Semiconductor) capacitor structure formed from a diffusion layer and polysilicon on a silicon substrate. The amplifier transistor 211 operates as a source follower circuit. Typically, the amplification factor of the amplifier transistor 211 is in the range of 0.8 to 1.

[0041] Furthermore, each of the memory write transistors 213, 214, and 215 is typically formed on a semiconductor substrate such as a silicon substrate. When the signal retention memory (capacitive element) is formed of a DRAM provided in a wiring structure, the sources of the memory write transistors 213, 214, and 215 are connected to the DRAM via contact plugs and wiring in the wiring structure.

[0042] The column signal processing circuit 50 includes an ADC 311 , a current source transistor 313 , and a switch transistor 314 .

[0043] The source of the current source transistor 313 is connected to the drain of the switch transistor 314, and the source of the switch transistor 314 is connected to a power supply wiring that supplies a reference power supply AGND. At this time, a control signal VBIAS2 is supplied to the gate of the current source transistor 313 from the current source 330, and a current based on the control signal VBIAS2 flows through the current source transistor 313. The drain of the current source transistor 313 is connected to the input of the ADC 311 via a signal line VLOUT, and the ADC 311 is connected to a power supply wiring that supplies a voltage AVDD and a power supply wiring that supplies a reference power supply AGND.

[0044] 4 shows an example of the configuration of the current source 230 and the current source 330. In FIG. 4, the switch transistor 217 and the switch transistor 314 shown in FIG.

[0045] The current source 230 configures a current mirror circuit with a reference current source 232 and a bias generation transistor 231. The reference current source 232, which generates a reference current, is connected between a power supply wiring that supplies a voltage MVDD and the drain of the bias generation transistor 231. The source of the bias generation transistor 231 is connected to a power supply wiring that supplies a reference voltage AGND. A control signal VBIAS1, which is generated by connecting the gate of the bias generation transistor 231 to the drain of the bias generation transistor 231, is supplied to each pixel memory 40.

[0046] The current source 330 configures a current mirror circuit with a reference current source 332 and a bias generation transistor 331. The reference current source 332, which generates a reference current, is connected between a power supply wiring that supplies a voltage MVDD and the drain of the bias generation transistor 331. The source of the bias generation transistor 331 is connected to a power supply wiring that supplies a reference voltage AGND. A control signal VBIAS2, which is generated by connecting the gate of the bias generation transistor 331 to the drain of the bias generation transistor 331, is supplied to each column signal processing circuit 50.

[0047] FIG. 5 is a diagram showing a detailed configuration of the storage capacitor section 240. As shown in FIG.

[0048] 3 is composed of a plurality of signal retention memories Nmem1 to 3, as shown in FIG. 5. The memory write transistor 213 is composed of memory write transistors 213-1 to 4. The source of the memory write transistor 213-1 is connected to the drains of the memory write transistors 213-2 to 4. The drain of the memory write transistor 213-1 is connected to the gate of the amplification transistor 211. One terminal of each of the plurality of signal retention memories Nmem1 to 3 is connected to a power supply wiring that supplies a reference power supply MGND, and the other terminal is connected to the source of the memory write transistors 213-2 to 4, respectively.

[0049] Similarly, the signal retention memory Smem-A is composed of a plurality of signal retention memories Smem-A1 to A3. The memory write transistor 214 is composed of memory write transistors 214-1 to 214-4. The source of the memory write transistor 214-1 is connected to the drains of the memory write transistors 214-2 to 214-4. The drain of the memory write transistor 214-1 is connected to the gate of the amplification transistor 211. One terminal of each of the plurality of signal retention memories Smem-A1 to A3 is connected to the power supply wiring that supplies the reference power supply MGND, and the other terminal is connected to the source of the memory write transistors 214-2 to 214-4, respectively.

[0050] The signal retention memory Smem-AB is composed of a plurality of signal retention memories Smem-AB1 to AB3. The memory write transistor 215 is composed of memory write transistors 215-1 to 215-4. The source of the memory write transistor 215-1 is connected to the drains of the memory write transistors 215-2 to 215-4. The drain of the memory write transistor 215-1 is connected to the gate of the amplification transistor 211. One terminal of each of the plurality of signal retention memories Smem-AB1 to AB3 is connected to the power supply wiring that supplies the reference power supply MGND, and the other terminal is connected to the source of the memory write transistors 215-2 to 215-4, respectively.

[0051] The connection relationship of each reference power supply is not limited to the configuration described in this embodiment. For example, the reference power supplies SGND and MGND may be common, or the reference power supplies MGND and AGND may be common. Here, "common" refers to a configuration in which multiple reference power supplies share a single pad connected to the outside of the photoelectric conversion device, or a configuration in which two power supply wirings transmitting the reference power supplies are connected to each other to transmit a common power supply voltage. Furthermore, the substrates on which the control circuits, scanning circuits, and current sources are arranged are not limited to the configuration described in this embodiment. For example, the memory control circuit 21 and current source 230 arranged on the second substrate may be arranged on a third substrate, or the current source 330 may be shared by the second and third substrates. Furthermore, the second and third substrates may be combined into a single fourth substrate, and the first and fourth substrates may be stacked.

[0052] Fig. 6 is an example of a driving timing chart of the photoelectric conversion device according to this embodiment. Fig. 6 illustrates a period T1 during which signal voltages based on signal charges generated by PD 115 and PD 116 are stored in the signal storage memory mem, and a period T2 during which the signal voltages stored in the signal storage memory mem are AD converted by the column signal processing circuit 50.

[0053] In Fig. 6, when the control signal supplied from each control circuit is high, each transistor is turned on (conducting), and when the control signal is low, each transistor is turned off (non-conducting). In Fig. 6, a high level is written as Hi and a low level is written as Lo. This notation method is the same in other drawings.

[0054] The relationship between each control signal shown in Fig. 6 and the transistors that operate in response to each control signal will be described with reference to Fig. 3 and Fig. 5. The signal charges generated by PD 115 and PD 116 and the signal voltages held in the holding capacitors may be collectively referred to as pixel signals.

[0055] During period T1, the control signals PSEL and PCSW go high, turning on the selection transistor 117 and the switch transistor 217. This allows the outputs from PD 115 and PD 116 to be supplied to node CH (second input node) via a source follower (SF) circuit formed by the amplifier transistor 111 and current source transistor 216, which function as an amplifier. First, during the period from time t0 to time t1, the control signal PRST goes high, turning on the reset transistor 112, and resetting the FD capacitance section to a potential level based on the voltage SVDD. This is referred to as the first reset period.

[0056] After the first reset period is completed, during the period from time t2 to t3, the control signal TX_A goes high and the transfer transistor 113 is turned on. As a result, the FD capacitance section holds signal charge generated based on incident light by one photoelectric conversion element (PD115) of the multiple photoelectric conversion elements. As a result, the signal charge of PD115 is supplied to node CH via the SF circuit configured by the amplification transistor 111 and the current source transistor 216. This is referred to as the first transfer period.

[0057] Similarly, during the period from time t4 to time t5, the control signal TX_B goes high, turning on the transfer transistor 114. As a result, the FD capacitance section holds a signal charge obtained by adding together the signal charges generated by one of the multiple photoelectric conversion elements and the other photoelectric conversion element (PD116) based on incident light. A signal corresponding to this added signal charge is supplied to the node CH via an SF circuit configured by the amplifier transistor 111 and the current source transistor 216. This is referred to as a second transfer period. Note that this is not a limitation, and the control signal PRST may be set high again and then low between time t3 and time t4. In this case, similarly, during the period from time t4 to time t5, the control signal TX_B goes high, causing the FD capacitance section to hold the signal charge generated by the PD116 based on incident light. A signal corresponding to this signal charge is supplied to the node CH via an SF circuit configured by the amplifier transistor 111 and the current source transistor 216.

[0058] Next, the control of the memory write transistors 213 to 215 and the voltage signals held in the signal holding memory mem will be described.

[0059] During the period from time t6 to time t7 after the end of the first reset period and before the start of the first transfer period, the node CH is supplied with a reset state potential (hereinafter sometimes referred to as the N level) of the FD capacitance section via an SF circuit configured with the amplifier transistor 111 and the current source transistor 216. This N level signal is a signal mainly composed of noise components. At time t6, the control signal WR_N-1 is set high to turn on the memory write transistor 213-1, thereby sampling the N level in the signal retention memory Nmem. Then, at time t7, the control signal WR_N-1 is set low to hold the N level. In the example of FIG. 6, the control signals WR_N-2 and WR_N-3 are set high and the control signal WR_N-4 is set low, and the N level is held in the signal retention memories Nmem-1 and Nmem-2. In other words, during the period when the signal retention memories Nmem1 and Nmem-2 are selected, the signal retention memory Nmem3 is in an unselected state. At this time, a fixed potential is supplied to the unselected signal retention memories Nmem. By switching the control of the control signals WR_N-2 to WR_N-4, the selection of the signal retention memories Nmem-1 to 3 can be switched. That is, the capacitance value of the signal retention memory Nmem can be adjusted and changed.

[0060] The period from time t8 to time t9 is the first transfer period, during which a potential (hereinafter sometimes referred to as the SA level) based on the signal charge of the PD 115 is supplied to the node CH via an SF circuit configured with the amplifier transistor 111 and the current source transistor 216 in the FD capacitance section. At time t8, the control signal WR_SA-1 is set high to turn on the memory write transistor 214-1, thereby sampling the SA level to the signal retention memory Smem-A. Then, at time t9, the control signal WR_SA-1 is set low to hold the SA level. In the example of FIG. 6, the control signals WR_SA-2 and WR_SA-3 are set high and the control signal WR_SA-4 is set low, and the SA level is held in the signal retention memories Smem-A1 and Smem-A2. By switching the control of the control signals WR_SA-2 to WR_SA-4, the selection of the signal retention memories Smem-A1 to Smem-A3 can be switched. In other words, the capacitance value of the signal retention memory Smem-A can be adjusted to change the capacitance value.

[0061] Similarly, the period from time t10 to time t11 is the second transfer period, during which a potential (hereinafter sometimes referred to as the SAB level) based on the signal charge of the PD 116 is connected to the node CH via an SF circuit composed of the amplifier transistor 111 and the current source transistor 216. At time t10, the control signal WR_SAB-1 is set high to turn on the memory write transistor 215-1, thereby sampling the SAB level to the signal retention memory Smem-AB. Then, at time t11, the control signal WR_SAB-1 is set low to hold the SAB level. In the example of FIG. 6, the control signals WR_SAB-2 and WR_SAB-3 are set high and the control signal WR_SAB-4 is set low, so that the SAB level is held in the signal retention memories Smem-AB1 and 2. By switching the control of the control signals WR_SAB-2 to WR_SAB-4, the selection of the signal retention memories Smem-AB1 to 3 can be switched. In other words, the capacitance value of the signal retention memory Smem-AB can be adjusted to change the capacitance value. It is preferable that the capacitance value of each signal holding memory be changed based on the possible range of the signal amplitude of the signal output from the pixel 30 .

[0062] By these operations, the N level, SA level, and SAB level are held as signal voltages in the signal holding memory mem. Here, the period during which the signal voltage is sampled and held in the signal holding memory mem is referred to as a voltage holding operation period.

[0063] This series of operations from the start of the first reset period to the end of the second transfer period is called the pixel signal voltage retention operation. By simultaneously performing the pixel signal voltage retention operation on all pixels, a global electronic shutter operation can be realized. Of the multiple pixels 30 and multiple pixel memories 40, the pixel signal voltage retention operation may be performed on all pixels 30 and all pixel memories 40, or on some pixels 30 and some pixel memories 40. For example, the pixel signal voltage retention operation may be performed sequentially in units of multiple pixel rows or multiple pixel columns. Alternatively, the pixel signal voltage retention operation may be performed row by row.

[0064] After the pixel signal voltage holding operation, the signal voltage held in the signal holding memory mem is read out to the column signal processing circuit 50.

[0065] During period T2 shown in FIG. 6, the selection transistor 117 is turned off. This disconnects the pixel 30 from the pixel memory 40. Furthermore, the switch transistor 217 is turned off, cutting off the current supplied by the current source transistor 216, and the SF circuit formed by the amplifier transistor 111 and the current source transistor 216 is turned off. This causes the node CH to float. After time t11, at time t12, the control signal MSEL goes high, turning on the selection transistor 218. Furthermore, at time t13, the control signal MCSW goes high, turning on the switch transistor 314. This connects the pixel 30 to the ADC 311 via the SF circuit formed by the amplifier transistor 211 and the current source transistor 313, which functions as an amplifier for amplifying a signal read from the signal retention memory mem. Note that time t12 and time t13 may occur at the same time.

[0066] During the period from time t14 to time t15, the control signal MRST goes high, the reset transistor 212 is turned on, and the node CH is reset to a potential level based on the voltage MVDD. This is referred to as a second reset period.

[0067] After the second reset period, during the period from time t16 to time t17, the control signal WR_N-1 is set high to turn on the memory write transistor 213-1, thereby outputting the signal voltages held in the signal retention memories Nmem-1 to Nmem-2 to the node CH. The ADC 311 performs AD conversion on the signal voltages held in the signal retention memories Nmem-1 to Nmem-2 that are read via the SF circuit formed by the amplification transistor 211 and the current source transistor 313, i.e., the voltages based on the N level. This is referred to as the first AD conversion period.

[0068] The potential of node CH is determined according to the ratio of the capacitance of node CH, the diffusion capacitance of wiring and memory write transistors 213-1, 214-1, and 215-1, the capacitance of the gate electrode of amplifier transistor 211, etc. to the capacitance of the signal retention memory, and the potential difference between each node. Therefore, in the operation shown in Fig. 6, in order to reset node CH to a constant potential before reading out the voltages retained in each signal retention memory mem, a second reset period is provided in which reset transistor 212 is turned on and then turned off.

[0069] After the first AD conversion period, a second reset period is provided between time t18 and time t19, during which the reset transistor 212 is turned on and then turned off.

[0070] After the second reset period from time t18 to time t19, during the period from time t20 to time t21, the control signal WR_SA-1 is set high, turning on the memory write transistor 214-1. As a result, the signal voltage held in the signal retention memories Smem-A1 to Smem-A2 is output to the node CH. The ADC 311 performs AD conversion on the signal voltage held in the signal retention memories Smem-A1 to Smem-A2, i.e., the voltage based on the SA level, which is read via the SF circuit formed by the amplification transistor 211 and the current source transistor 313. This is referred to as the second AD conversion period.

[0071] After the second AD conversion period, a second reset period is provided between time t22 and time t23, during which the reset transistor 212 is turned on and then turned off.

[0072] After the second reset period from time t22 to time t23, during the period from time t24 to time t25, the control signal WR_SAB-1 is set high, turning on the memory write transistor 215-1. As a result, the signal voltage held in the signal retention memories Smem-AB1-2 is output to the node CH. The ADC 311 performs AD conversion on the voltage signal held in the signal retention memories Smem-AB1-2, i.e., the voltage based on the SAB level, read via the SF circuit formed by the amplification transistor 211 and the current source transistor 313. This is referred to as the third AD conversion period.

[0073] After the third AD conversion period, period T2 ends, and the selection transistor 218 and the switch transistor 314 are turned off. This disconnects the pixel memory 40 from the column signal processing circuit 50. Furthermore, the switch transistor 314 being turned off cuts off the current supplied by the current source transistor 313, and the SF circuit having the amplifier transistor 211 and the current source transistor 313 is turned off.

[0074] 6 does not explicitly state the reset operation of PD115 and PD116, but the accumulation start time may be set to, for example, after the first transfer period or the second transfer period. Furthermore, the transfer transistor 113, the transfer transistor 114, and the reset transistor 112 may be turned on during period T2 or at a timing other than periods T1 and T2. As a result, PD115 and PD116 may be reset to a potential based on the voltage SVDD. Furthermore, a reset transistor may be provided between PD115 and PD116 and the voltage SVDD, separate from the reset transistor 112, to perform the reset operation.

[0075] 7 is a cross-sectional view including the metal bonding portions of the first substrate 100, the second substrate 200, and the third substrate 300 according to this embodiment. Note that FIG. 7 shows some of the elements and wiring connections in the configuration described in FIG.

[0076] The first substrate 100 includes a semiconductor substrate 1100 (first semiconductor layer) and an interconnect structure 1110 (first interconnect structure). The semiconductor substrate 1100 is, for example, a silicon semiconductor substrate, and is a first semiconductor layer in which a photoelectric conversion element and a readout circuit for reading out a signal based on the photoelectric conversion of the photoelectric conversion element are formed. If the photoelectric conversion element is a photoelectric conversion film instead of a photodiode, this photoelectric conversion film can be provided on top of the first semiconductor layer. The semiconductor substrate 1100 may be made of a material other than silicon, and may be a compound semiconductor substrate such as a gallium arsenide substrate. Here, the description will be continued assuming that the semiconductor substrate 1100 is a silicon single crystal substrate.

[0077] 7 shows PD 115, PD 116, and selection transistor 117 as examples of elements provided on the semiconductor substrate 1100. A microlens 103 and a color filter 102 are formed on the light incident surface side of the semiconductor substrate 1100. The color filter 102 has the function of limiting the wavelength band of incident light. For example, it can transmit light in wavelength bands corresponding to the red, green, and blue colors of visible light.

[0078] The microlens 103 has the function of focusing incident light onto the PDs 115 and 116. The first main surface F1 of the semiconductor substrate 1100 is the surface onto which the incident light is incident. The second main surface F2 of the semiconductor substrate 1100 is the surface on which the gates of the transistors are provided. The second main surface F2 is located between the first main surface F1 and the wiring structure 1110 (first wiring structure) of the first substrate 100.

[0079] Metal wiring 105 connecting each circuit is arranged in multiple layers in the wiring structure 1110. Contact vias 104 connecting each component are provided between the metal wiring 105 in each layer, between the metal wiring 105 and the semiconductor substrate 1100, and between the metal wiring 105 and the transistors formed on the semiconductor substrate 1100. For example, in the select transistor 117, the contact via 104 is connected to the source region.

[0080] The gate electrode 107 is made of polysilicon that constitutes the gate electrode of a transistor. The wiring structure 1110 is a first wiring structure that electrically connects the PD 115, the PD 116, the readout circuit included in the semiconductor substrate 1100, and the readout circuit included in the second substrate 200.

[0081] The second substrate 200 includes a semiconductor substrate 1200 and an interconnect structure 1210 (second interconnect structure) of the second substrate 200. The semiconductor substrate 1200 is, for example, a silicon semiconductor substrate, and is a second semiconductor layer having a memory and an output circuit that outputs a voltage held by the memory. The semiconductor substrate 1200 may be made of a material other than silicon, for example, a compound semiconductor substrate such as a gallium arsenide substrate. Here, the description will be continued assuming that the semiconductor substrate 1200 is a silicon single crystal substrate. As shown in FIG. 7, the thickness of the semiconductor substrate 1100 and the thickness of the semiconductor substrate 1200 may be different or the same. If the thicknesses are different, for example, the thickness of the semiconductor substrate 1100 may be smaller than the thickness of the semiconductor substrate 1200, as shown in FIG. 7.

[0082] As an example of elements provided on the semiconductor substrate 1200, a current source transistor 216, a switch transistor 217, an amplifier transistor 211, and a selection transistor 218 are shown in FIG.

[0083] The wiring structure 1210 of the second substrate 200 is a wiring structure formed of metal wiring 105, contact vias 104, and gate electrodes 107, similar to the wiring structure 1110 of the first substrate 100. The signal retention memories Nmem1 to Nmem3, signal retention memories Smem-A1 to Nmem-A3, and signal retention memories Smem-AB1 to Nmem-AB3 described with reference to FIGS.

[0084] In FIG. 7, each signal retention memory is represented as *mem*1 to *mem*3, and indicates a plurality of signal retention memories with separate electrodes. Wiring structure 1210 electrically connects each signal retention memory mem to the output circuit. Here, it is sufficient for the signal retention memory mem to have the function of retaining a signal voltage, and as mentioned above, it may be configured to retain a signal by forming a capacitance within semiconductor substrate 1200. This configuration will be described later.

[0085] The third substrate 300 includes a semiconductor substrate 1300 and an interconnect structure 1310 (third interconnect structure). The semiconductor substrate 1300 is, for example, a silicon semiconductor substrate, and is a third semiconductor layer having a second read circuit that reads out a signal corresponding to the voltage held in the memory. As examples of elements provided on the semiconductor substrate 1300, a current source transistor 313 and a switch transistor 314 are shown in FIG. 7.

[0086] The wiring structure 1310 is a third wiring structure formed of metal wiring 105, contact vias 104, and gate electrodes 107, similar to the wiring structure 1110, and electrically connected to the second readout circuit.

[0087] As shown in Fig. 7, the wiring structure 1110 of the first substrate 100 and the wiring structure 1210 of the second substrate 200 are bonded together so as to face each other, and a metal junction 400 is formed at the electrically connected location. The metal junction 400 in Fig. 7 is a CCB. The metal junction 400 is formed by bonding and connecting a Cu pad (metal member) formed on the lower surface (first layer) of the wiring structure 1110 to a Cu pad (metal member) formed on the upper surface (second layer) of the wiring structure 1210. An insulating junction is also formed by bonding the insulating member of the first layer and the insulating member of the second layer together.

[0088] Furthermore, the wiring structure 1210 of the second substrate 200 and the wiring structure 1310 of the third substrate 300 are connected via the semiconductor substrate 1200. A TSV 106 is formed in the semiconductor substrate 1200 and connected to a Cu pad prepared on the underside of the semiconductor substrate 1200. This Cu pad is joined to a Cu pad formed on the upper surface of the wiring structure 1310 to form a metal junction 401 of the CCB.

[0089] The selection transistor 117 is connected to the current source transistor 216 via a metal junction 400. The selection transistor 218 is connected to the column signal processing circuit 50 and the current source transistor 313 via a metal junction 401.

[0090] 3 and 5, one of the two terminals of the signal retention memory mem is connected to the memory write transistor, and the other is connected to the voltage MGND. In Fig. 7, a plurality of wiring patterns separated by an insulating member are provided on the third layer L1. A portion of the signal retention memory mem (first capacitance portion) is provided on the plurality of wiring patterns on the third layer L1, and the plurality of signal retention memories mem are each separated by an insulating member.

[0091] In Fig. 7, a fourth layer L2 is provided with a plurality of wiring patterns separated by insulating members. The plurality of wiring patterns on the fourth layer L2 are provided with portions of signal retention memories (second capacitance portions), and the plurality of signal retention memories (mem) are each separated by insulating members. In Fig. 7, as described in Figs. 3 and 5, each second capacitance portion is configured to be connected to the power supply wiring of voltage MGND, but each second capacitance portion may be connected to a power supply wiring that supplies a different voltage.

[0092] FIG. 8 is a cross-sectional schematic diagram of a first substrate 100, a second substrate 200, and a third substrate 300 in an example different from that of FIG.

[0093] Similar to the configuration in FIG. 7, signal retention memories Nmem1-3, signal retention memories Smem-A1-3, and signal retention memories Smem-AB1-3 are formed within wiring structure 1210. As in FIG. 7, the signal retention memories are denoted as *mem*1-3. FIG. 8 differs from FIG. 7 in that the electrode connected to the power supply wiring for voltage MGND is shared by multiple signal retention memories. In FIG. 8, as in FIG. 7, the capacitance value of each signal retention memory mem can be changed. Furthermore, by sharing the capacitance portion on the fourth layer L2 as in FIG. 8, the signal retention memories can be connected to the same power supply wiring with low resistance. This reduces variations in voltage MGND, which serves as a reference for voltage retention between signal retention memories, improving the quality of the retained signals.

[0094] Fig. 9 is a plan view schematically illustrating the arrangement of signal retention memories Nmem1-3, signal retention memories Smem-A1-A3, and signal retention memories Smem-AB1-AB3 in a wiring structure 1210 for pixel memory 40. Fig. 9 illustrates the third layer L1 shown in Fig. 7 as viewed from above with respect to the semiconductor substrate 1100. It can also be said that Fig. 9 illustrates a plurality of wiring patterns in the third layer L1.

[0095] The connection between the signal retention memories and the control signals is represented by arrows, which include the write transistors, and each control signal controls each signal retention memory. The control here refers to controlling the signal retention memory to either select or deselect, for example. Note that the control signals WR_N-1, WR_SA-1, and WR_SAB-1 that control the write transistors 213-1, 214-1, and 215-1 are omitted.

[0096] On the third layer L1, the multiple wiring patterns are electrically separated by an insulating member DF. The schematic plan view of the fourth layer L2 may also be similar to that shown in FIG. 9. In FIG. 9, the signal retention memories Nmem1-3 are arranged vertically, the signal retention memories Smem-A1-A3 are arranged vertically, and the signal retention memories Smem-AB1-AB3 are arranged vertically. Furthermore, the control signal lines are arranged such that the control signals WR_N-2, WR_SA-2, and WR_SAB-2 are adjacent to each other. Similarly, the control signals WR_N-3, WR_SA-3, and WR_SAB-3 are arranged adjacent to each other, and the control signals WR_N-4, WR_SA-4, and WR_SAB-4 are arranged adjacent to each other, but the present invention is not limited to this arrangement.

[0097] 10 is a plan view schematic diagram illustrating the arrangement of signal retention memories Nmem1-3, signal retention memories Smem-A1-A3, and signal retention memories Smem-AB1-AB3 in an interconnect structure 1210 in another example of pixel memory 40 different from that in FIG. 9. The signal retention memories Nmem1-3, signal retention memories Smem-A1-A3, and signal retention memories Smem-AB1-AB3 may be arranged irregularly. FIG. 10 differs from FIG. 9 in that the signal retention memories Nmem1-3 are arranged adjacent to each other in a diagonal direction. Similarly, the signal retention memories Smem-A1-A3 and signal retention memories Smem-AB1-AB3 are also arranged diagonally, and the control signal lines are arranged in the same manner as in FIG. 9.

[0098] As shown in FIG. 6 , the signal retention memories Nmem, Smem-A, and Smem-AB retain the voltage signal N level, SA level, and SAB level through sample-and-hold operation. For example, the period from time t6 to time t7 during which the N level is sampled in the signal retention memory Nmem (sampling period N) is roughly determined by the driving force of the SF circuit configured by the amplifier transistor 111 and the current source transistor 216 and the capacitance value of the signal retention memory Nmem. The driving force of the SF circuit is, for example, the amount of current flowing from the current source transistor 216. The amount of current flowing from the current source transistor 216 can be varied by adjusting the size of the bias generation transistor 231 described in FIG. 4 and the current mirror ratio. The amount of current flowing from the current source transistor 216 can also be varied by adjusting the current of the reference current source 232. The amount of current flowing from the current source transistor 216 can also be varied by changing the voltage applied to the gate of the current source transistor 216. The same applies to the period from time t8 to time t9 (sampling period SA) when the SA level is sampled in the signal retention memories Smem-A1 to A2, and the same applies to the period from time t10 to time t11 (sampling period SAB) when the SAB level is sampled in the signal retention memories Smem-AB1 to AB2.

[0099] As described in FIG. 6, one frame period is determined by periods T1 and T2. In other words, to increase the frame rate of a photoelectric conversion device, at least one of periods T1 and T2 must be shortened. Period T1 is roughly determined by sampling period N, sampling period SA, and sampling period SAB. For example, shortening period T1 requires increasing the driving force of the SF circuit composed of the amplifier transistor 111 and current source transistor 216. For example, it is necessary to increase the current flowing through the current source transistor 216. In this case, the current in each pixel must be increased, potentially resulting in an increase in power consumption. On the other hand, reducing the capacitance value of the signal retention memory mem shortens each sampling period and period T1. However, reducing the signal retention memory mem may change the noise frequency band, resulting in, for example, deterioration of noise performance, increased accuracy of the absolute value of capacitance, and increased variation between capacitances, which may result in degradation of image quality and imaging performance, such as reduced accuracy of retention voltage and phase difference detection. To adjust the period T2, the driving force of the SF circuit composed of the amplifier transistor 211 and the current source transistor 313 can be changed according to the capacitance value of the signal retention memory mem, but this may also result in an increase in power consumption. Also, increasing the number of column signal processing circuits 50 and increasing the number of parallel signal processes may increase the speed, but this may result in an increase in area and power consumption.

[0100] In this embodiment, it is possible to appropriately set the capacitance value of the signal retention memory mem, the driving force of the amplification transistor 111, and the driving force of the amplification transistor 211. Therefore, in a photoelectric conversion device equipped with a voltage retention type global electronic shutter function, it is possible to set the capacitance value and the driving force of the SF circuit in consideration of the size of the capacitance element, the signal settling time, etc., which may further improve imaging performance.

[0101] From another perspective, if the sampling period N, sampling period SA, and sampling period SAB are long, the device may be more susceptible to low-frequency noise, for example. Alternatively, a longer capacitance retention period can lead to a decrease in the accuracy of the retention voltage due to leakage current from the signal retention memory, which can cause degradation in image quality. In other words, a longer period T1 can have a significant impact on image quality performance. Furthermore, the degree of these effects varies depending on the capacitance value of the signal retention memory.

[0102] In this embodiment, as described with reference to FIGS. 5 and 6, the capacitance values ​​of the signal retention memories Nmem, Smem-A, and Smem-AB can be selected using the control signals WR_N-2 to WR_N-4, WR_SA-2 to WR_SA-4, and WR_SAB-2 to WR_SAB-4. For example, when capturing a single still image, with a slow readout speed and high image quality, the signal retention memories Nmem1 to Nmem3, Smem-A1 to Smem-A3, and Smem-AB1 to Smem-AB3 are all selected. This reduces noise and the effects of leakage. Meanwhile, by suppressing the driving force of the SF circuit formed by the amplifier transistor 111 and the current source transistor 216, the period T1 is lengthened, but power consumption can be suppressed. Alternatively, when capturing a video at a high frame rate and image quality degradation is acceptable, the signal retention memories Nmem1, Smem-A1, and Smem-AB1 are selected, allowing for increased noise and the effects of leakage. Furthermore, it is possible to increase the driving force of the SF circuit formed by the amplifier transistor 111 and the current source transistor 216, thereby increasing power, while shortening the period T1. In this case, in the arrangement shown in Figure 9, memories that are not physically adjacent to each other, such as signal retention memory Nmem1, signal retention memory Smem-A2, and signal retention memory Smem-AB3, may be selected. This allows for a configuration that reduces crosstalk between the signal retention memories.

[0103] The gate width of the current source transistor 216 may be different from the gate width of the current source transistor 313. For example, the gate width of the current source transistor 216 may be larger than the gate width of the current source transistor 313. This allows the driving power of the first amplifying unit to be larger than the driving power of the second amplifying unit.

[0104] According to the photoelectric conversion device of this embodiment, the number of signal retention memories to be selected, i.e., the capacitance value, can be selected and made variable. For example, the capacitance value of the retention capacitor 240 can be changed in response to a change in the on-period of the memory write transistor. Furthermore, the driving force of the SF circuit configured by the amplifier transistor 111 and the current source transistor 216 can be adjusted. Similarly, the driving force of the SF circuit configured by the amplifier transistor 211 and the current source transistor 313 can be adjusted. The capacitance value of the retention capacitor 240 can be changed in response to a change in at least one of the driving forces of the amplifier transistor 111 and the amplifier transistor 211. This allows for appropriate selection and adjustment in response to the required image quality and imaging performance.

[0105] The operation of the reset transistor 212 may be adjusted or the size of the reset transistor 212 may be adjusted depending on the capacitance value of the signal retention memory mem. Here, the size may be, for example, the gate width or the gate length of the gate electrode. When the signal retention memory mem is reset by the reset transistor 212, the reset period is adjusted or the size of the reset transistor 212 is changed depending on the capacitance value of the signal retention memory mem. For example, if the capacitance value of the signal retention memory mem is large, the reset period can be lengthened or the size of the reset transistor 212 can be increased to improve the accuracy of resetting the signal retention memory mem.

[0106] From another perspective, if any of the signal retention memories Nmem1-3, signal retention memories Smem-A1-A3, or signal retention memories Smem-AB1-AB3 has a defect (such as a characteristic defect or failure), the corresponding memory may not be used. For example, in the schematic plan view of pixel memories 40 shown in FIG. 9, if signal retention memory Smem-A2 of a certain pixel memory 40 has a defect, the signal retention memory Smem-A2 of that pixel memory 40 may not be used. This may reduce image quality degradation by controlling not to use the corresponding signal retention memory even if a defect exists in any of the signal retention memories. Alternatively, a spare signal retention memory may be provided, and if a certain signal retention memory has a defect, the spare signal retention memory may be used by switching the connection.

[0107] The layout, layout distance, shape, and size of the signal retention memories (MEM) are not limited to the configuration described in this embodiment. For example, as described in some embodiments, the sizes of the signal retention memories (MEM) may be the same or different. The shapes of the signal retention memories may be the same or different. The layout distances between the signal retention memories (MEM) may also be different.

[0108] As described above, according to this embodiment, the memory that holds the pixel signals generated by the photoelectric conversion elements is configured and controlled using a plurality of capacitive elements, thereby making it possible to optimally set the image quality performance and imaging performance.

[0109] (Second embodiment) A photoelectric conversion device according to a second embodiment of the present invention will be described with reference to FIGS.

[0110] 11 is a circuit diagram of the signal retention memory (retention capacitor unit 240) of the photoelectric conversion device according to the second embodiment. The same reference numerals as in FIG. 5 are used for the memory write transistor and the signal retention memory, but the configuration and connection relationship in FIG. 5 differs from that of the first embodiment. Other than this point and the points described below, the configuration can be substantially the same as that of the first embodiment, and therefore, the description may be omitted.

[0111] The signal retention memory Nmem is composed of a plurality of signal retention memories Nmem1 to 3. The memory write transistor 213 is composed of memory write transistors 213-1 to 3. The drains of the memory write transistors 213-1 to 3 are connected to the gate of the amplification transistor 211. One terminal of each of the plurality of signal retention memories Nmem1 to 3 is connected to a power supply wiring that supplies a reference voltage MGND, and the other terminal is connected to the source of the memory write transistors 213-1 to 3, respectively. Similarly, the signal retention memory Smem-A is composed of a plurality of signal retention memories Smem-A1 to 3. The memory write transistor 214 is composed of memory write transistors 214-1 to 3. The drains of the memory write transistors 214-1 to 3 are connected to the gate of the amplification transistor 211. One terminal of each of the plurality of signal retention memories Smem-A1 to 3 is connected to a power supply wiring that supplies a reference voltage MGND, and the other terminal is connected to the sources of the memory write transistors 214-1 to 214-3, respectively. The signal retention memory Smem-AB is made up of a plurality of signal retention memories Smem-AB1 to 3. The memory write transistor 215 is made up of memory write transistors 215-1 to 215-3. The drains of the memory write transistors 215-1 to 215-3 are connected to the gate of the amplification transistor 211. One terminal of each of the plurality of signal retention memories Smem-AB1 to 3 is connected to a power supply wiring that supplies a reference voltage MGND, and the other terminal is connected to the sources of the memory write transistors 215-1 to 215-3, respectively.

[0112] Fig. 12 is an example of a drive timing chart for the photoelectric conversion device according to this embodiment. That is, it is a diagram illustrating the operation timing of the readout circuit in Fig. 3 and Fig. 11. Explanation of parts that overlap with the operation explained in Fig. 6 will be omitted.

[0113] In the operation timing of FIG. 12, during sampling period N from time t6 to time t7, control signals WR_N-1 to WR_N-3 are set high, and N level is held in signal retention memories Nmem1 to Nmem3. Meanwhile, during period T2, control signals WR_N-1 to WR_N-2 are set high, and the signal voltages held in signal retention memories Nmem1 to Nmem2 are read out. Similarly, during sampling period SA from time t8 to time t9, control signals WR_SA-1 to WR_SA-3 are set high, and SA level is held in signal retention memories Smem-A1 to Smem-A3. Meanwhile, during period T2, control signals WR_SA-1 to WR_SA-2 are set high, and the signal voltages held in signal retention memories Smem-A1 to Smem-A2 are read out. During sampling period SAB from time t10 to time t11, control signals WR_SAB-1 to WR_SAB-3 are set high, and SAB level is held in signal retention memories Smem-AB1 to Smem-AB3. On the other hand, in period T2, the control signals WR_SAB-1 and WR_SAB-2 are set high to read out the signal voltages held in the signal holding memories Smem-AB1 and AB2. In this way, the capacitance value of the holding capacitor is changed depending on the read mode.

[0114] In this embodiment, when reading the output of the SF circuit composed of the amplification transistor 111 and the current source transistor 216 during period T1, the signal holding memory serving as the load capacitance of the SF circuit output is increased. In this way, the capacitance value of the signal holding memory (holding capacitor unit 240) can be changed according to the gain processing. This reduces the high-frequency components of the SF circuit noise. On the other hand, when reading the signal voltage held in the signal holding memory during period T2, the number of signal holding memories is reduced from that during period T1. This reduces the effects of switching noise that may occur when each signal holding memory holds the signal voltage during period T1 and switching noise that may occur during selection during period T2.

[0115] 5, for example, during period T1, the control signals WR_SA-2 to WR_SA-4 are set high to select signal retention memories Smem-A1 to Smem-A3, and during period T2, the control signal WR_SA-4 is set low to select and read out signal retention memories Smem-A1 to Smem-A2. However, since switching the control signal WR_SA-4 from high to low during period T1 to T2 can cause superimposed switching noise, which can degrade image quality, the configuration shown in FIG. 11 is preferable. Note that, as explained in FIG. 6, when reading out each signal retention memory during period T2, the potential of node CH changes depending on the capacitance value of the signal retention memory. Therefore, a configuration in which a signal retention memory is selected to adjust the potential of node CH may be used.

[0116] Fig. 13 is an example of a plan view schematic diagram of the retention capacitor unit 240 of Fig. 11 for the pixel memory 40. In Fig. 13, dummy capacitance elements Dmem (not shown in Fig. 11) are arranged between the signal retention memories Nmem and Smem-A, between the signal retention memories Smem-A and Smem-AB, and between the pixel memories 40.

[0117] As explained in Figures 3 and 6, the signal retention memories Nmem, Smem-A, and Smem-AB perform retention and read operations at different times for the voltage signals N level, SA level, and SAB level. For example, if parasitic capacitance exists between the signal retention memories mem, the voltage signals retained between each signal retention memory mem will change due to crosstalk. For example, let the capacitance value of signal retention memory Nmem be CN, the capacitance value of signal retention memory Smem-A be CA, and the capacitance value of signal retention memory Smem-AB be CAB, and let us assume that a parasitic capacitance Cp exists between each signal retention memory. As explained in Figure 6, if the voltage on signal retention memory Smem-AB changes by ΔV during the period from time t10 to time t11, a voltage change of equation (1) will occur in signal retention memory Nmem, and equation (2) will occur in signal retention memory Smem-A. ΔV x Cp / (Cp+CN) (1) ΔV x Cp / (Cp+CA) (2) Furthermore, during period T2, when the voltage signal of each signal retention memory (mem) is read out to the column signal processing circuit 50, the voltage on each signal retention memory (mem) changes according to the reset level of node CH. This causes crosstalk due to the parasitic capacitance Cp between each signal retention memory (mem). Similarly, if parasitic capacitance exists between multiple pixel memories 40, crosstalk also occurs between the pixel memories 40. These can cause errors in the signal charge generated by PD 115 and PD 116. For example, this can cause linearity errors and offset errors in the pixel output signal relative to incident light. Furthermore, crosstalk between signal retention memories Smem-A and Smem-AB can cause phase difference detection errors. Furthermore, crosstalk between pixels can cause color mixing between pixels of different colors, degrading image quality.

[0118] In this embodiment, as in the first embodiment, the capacitance value and the driving force of the SF circuit can be appropriately selected and adjusted according to the required image quality and imaging performance. Also, as shown in Fig. 13, by arranging a dummy capacitance element Dmem, crosstalk between signal retention memories can be reduced.

[0119] The capacitance element Dmem may be connected to a power supply line of the power supply voltage VDD, the reference voltage GND, or other reference voltages. It may also be connected to a write transistor so that it can be used as a signal retention memory.

[0120] (Third embodiment) A photoelectric conversion device according to a third embodiment of the present invention will be described with reference to FIGS.

[0121] 14 is a circuit diagram of a signal retention memory (retention capacitor section 240) of a photoelectric conversion device according to the third embodiment. The same reference numerals as in FIG. 5 are used for the memory write transistors and signal retention memories, but the number of memory write transistors and their connection relationships differ from those of the first and second embodiments. Other than this point and the points described below, the configuration can be substantially the same as that of the first embodiment, and therefore, description thereof may be omitted.

[0122] The signal retention memory Nmem is composed of a plurality of signal retention memories Nmem1 to 3. The memory write transistor 213 is composed of memory write transistors 213-1 to 2. The drains of the memory write transistors 213-1 to 2 are connected to the gate of the amplification transistor 211. One terminal of each of the plurality of signal retention memories Nmem1 to 3 is connected to a power supply wiring that supplies a reference voltage MGND. The other terminal of the signal retention memory Nmem1 is connected to the source of the memory write transistor 213-1, and the other terminal of the signal retention memories Nmem2 to 3 is connected to the source of the memory write transistor 213-2.

[0123] The signal retention memory Smem-A is composed of a plurality of signal retention memories Smem-A1 to A3. The memory write transistor 214 is composed of memory write transistors 214-1 to 2. The drains of the memory write transistors 214-1 to 2 are connected to the gate of the amplification transistor 211. One terminal of each of the plurality of signal retention memories Smem-A1 to A3 is connected to a power supply wiring that supplies a reference voltage MGND. The other terminal of the signal retention memory Smem-A1 is connected to the source of the memory write transistor 214-1, and the other terminal of the signal retention memory Smem-A2 to A3 is connected to the source of the memory write transistor 214-2.

[0124] The signal retention memory Smem-AB is composed of a plurality of signal retention memories Smem-AB1 to AB3. The memory write transistor 215 is composed of memory write transistors 215-1 to 2. The drains of the memory write transistors 215-1 to 2 are connected to the gate of the amplification transistor 211. One terminal of each of the plurality of signal retention memories Smem-AB1 to AB3 is connected to a power supply wiring that supplies a reference voltage MGND. The other terminal of the signal retention memory Smem-AB1 is connected to the source of the memory write transistor 215-1, and the other terminal of the signal retention memory Smem-AB2 to AB3 is connected to the source of the memory write transistor 215-2.

[0125] In this embodiment, the signal retention memories mem selected by the write transistors 213-1, 214-1, and 215-1 and the signal retention memories mem selected by the write transistors 213-2, 214-2, and 215-2 have explicitly different capacitance values. In Figure 14, the signal retention memories Nmem2 and Nmem3, signal retention memories Smem-A2 and Smem-A3, and signal retention memories Smem-AB2 and Smem-AB3 are connected in parallel to show the difference in capacitance value. This may also be a configuration in which one signal retention memory with a different capacitance value is provided.

[0126] In this embodiment as well, a configuration may be adopted in which a capacitance of either size can be selected depending on the image quality performance and imaging performance as described in FIG. 6, or the control of the write transistor may be switched between periods T1 and T2 as described in FIG. 12.

[0127] Fig. 15 is a plan view of the configuration of pixel memory 40 in Fig. 14. Fig. 14 is a circuit diagram in which signal retention memories Nmem2 and Nmem3, signal retention memories Smem-A2 and Smem-A3, and signal retention memories Smem-AB2 and Smem-AB3 are arranged in parallel. However, since they are essentially treated as a single signal retention memory, Fig. 15 shows them as a single signal retention memory.

[0128] In this embodiment, as in the first embodiment, the capacitance value and the driving force of the SF circuit can be appropriately selected and adjusted according to the required image quality performance and imaging performance.

[0129] (Fourth embodiment) The fourth embodiment is applicable to the first to third embodiments. FIG. 16(a) is a schematic diagram illustrating an apparatus 9191 including a semiconductor device 930 according to this embodiment. The photoelectric conversion device according to each of the above-described embodiments can be used for the semiconductor device 930. The apparatus 9191 including the semiconductor device 930 will be described in detail. The semiconductor device 930 may include a semiconductor device 910. The semiconductor device 930 may include, in addition to the semiconductor device 910, a package 920 that houses the semiconductor device 910. The package 920 may include a base to which the semiconductor device 910 is fixed, and a lid such as glass that faces the semiconductor device 910. The package 920 may further include bonding members such as bonding wires or bumps that connect terminals provided on the base to terminals provided on the semiconductor device 910.

[0130] The equipment 9191 can include at least one of an optical device 940, a control device 950, a processing device 960, a display device 970, a storage device 980, and a mechanical device 990. The optical device 940 corresponds to the semiconductor device 930. The optical device 940 is, for example, a lens, a shutter, or a mirror, and includes an optical system that guides light to the semiconductor device 930. The control device 950 controls the semiconductor device 930. The control device 950 is, for example, a semiconductor device such as an ASIC.

[0131] The processing device 960 processes the signal output from the semiconductor device 930. The processing device 960 is a semiconductor device such as a CPU or ASIC for configuring an AFE (analog front end) or a DFE (digital front end). The display device 970 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor device 930. The storage device 980 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor device 930. The storage device 980 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0132] The mechanical device 990 has a moving part or a propulsion part such as a motor or an engine. In the device 9191, the signal output from the semiconductor device 930 is displayed on the display device 970, or transmitted to the outside by a communication device (not shown) provided in the device 9191. For this purpose, the device 9191 preferably further includes a memory device 980 and a processing device 960 in addition to the memory circuit and arithmetic circuit provided in the semiconductor device 930. The mechanical device 990 may be controlled based on the signal output from the semiconductor device 930.

[0133] The device 9191 is also suitable for electronic devices such as information terminals with a photographing function (for example, smartphones and wearable devices) and cameras (for example, interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 990 in the camera can drive components of the optical device 940 for zooming, focusing, and shutter operations. Alternatively, the mechanical device 990 in the camera can move the semiconductor device 930 for vibration isolation operations.

[0134] Furthermore, the device 9191 may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 990 in the transportation equipment may be used as a moving device. The device 9191 as transportation equipment is suitable for transporting the semiconductor device 930 or for assisting and / or automating driving (piloting) using an imaging function. The processing device 960 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 990 as a moving device based on information obtained by the semiconductor device 930. Alternatively, the device 9191 may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot.

[0135] According to the above-described embodiment, it is possible to obtain good pixel characteristics. Therefore, the value of the semiconductor device can be increased. In this case, increasing the value corresponds to at least one of adding functions, improving performance, improving characteristics, improving reliability, improving manufacturing yield, reducing environmental impact, reducing costs, reducing size, and reducing weight.

[0136] Therefore, if the semiconductor device 930 according to this embodiment is used in the equipment 9191, the value of the equipment can also be improved. For example, by installing the semiconductor device 930 in a transport equipment, excellent performance can be obtained when photographing the exterior of the transport equipment or measuring the external environment. Therefore, when manufacturing and selling transport equipment, deciding to install the semiconductor device according to this embodiment in the transport equipment is advantageous in terms of improving the performance of the transport equipment itself. In particular, the semiconductor device 930 is suitable for transport equipment that performs driving assistance and / or automatic driving of the transport equipment using information obtained by the semiconductor device.

[0137] The photoelectric conversion system and the moving object of this embodiment will be described with reference to FIGS. 16(b) and 16(c).

[0138] FIG. 16(b) shows an example of a photoelectric conversion system related to an in-vehicle camera. The photoelectric conversion system 8 includes a photoelectric conversion device 1. The photoelectric conversion device 1 is the photoelectric conversion device (imaging device) described in any of the above embodiments. The photoelectric conversion system 8 includes an image processing unit 801 that performs image processing on multiple pieces of image data acquired by the photoelectric conversion device 1, and a parallax acquisition unit 802 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the photoelectric conversion system 8. Here, the photoelectric conversion system 8 may include an optical system (not shown) that guides light to the photoelectric conversion device 10, such as a lens, shutter, or mirror. Furthermore, multiple photoelectric conversion units that are approximately conjugate with the pupil of the optical system may be arranged in pixels of the photoelectric conversion device 10. For example, the multiple photoelectric conversion units that are approximately conjugate with the pupil are arranged corresponding to one microlens. The multiple photoelectric conversion units receive light beams that have passed through different positions on the pupil of the optical system, and the photoelectric conversion device 10 outputs image data corresponding to the light beams that have passed through the different positions. The parallax acquisition unit 802 may then calculate the parallax using the output image data. The photoelectric conversion system 8 also includes a distance acquisition unit 803 that calculates the distance to the object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 802 and the distance acquisition unit 803 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information is information about the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 804 may determine the possibility of a collision using any of this distance information. The distance information may be acquired using ToF (Time of Flight). The distance information acquisition means may be realized by dedicated hardware or a software module. It may also be realized by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit), or the like, or a combination thereof.

[0139] The photoelectric conversion system 8 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The photoelectric conversion system 8 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the determination result of the collision determination unit 804. The photoelectric conversion system 8 is also connected to an alarm device 830 that issues an alarm to the driver based on the determination result of the collision determination unit 804. For example, if the determination result of the collision determination unit 804 indicates a high possibility of a collision, the control ECU 820 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0140] In this embodiment, the photoelectric conversion system 8 captures an image of the surroundings of the vehicle, for example, the front or rear. Fig. 16(c) shows the photoelectric conversion system 8 when capturing an image of the area in front of the vehicle (imaging range 850). The vehicle information acquisition device 810 sends instructions to the photoelectric conversion system 8 or the photoelectric conversion device 1. This configuration can further improve the accuracy of distance measurement.

[0141] While the above describes an example of control to prevent collisions with other vehicles, the present invention can also be applied to other applications, such as autonomous driving control to follow other vehicles and autonomous driving control to prevent vehicles from drifting out of their lanes. Furthermore, the photoelectric conversion system 8 can be applied not only to automobiles and other vehicles, but also to moving bodies (mobile devices) such as ships, aircraft, and industrial robots. The moving body includes one or both of a driving force generating unit that generates a driving force primarily used to move the moving body and a rotating body primarily used to move the moving body. The driving force generating unit can be an engine, a motor, or the like. The rotating body can be a tire, a wheel, a ship's screw, a propeller, or the like. In addition to moving bodies, the present invention can be applied to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0142] (Modified embodiment) The present disclosure is not limited to the above-described embodiment, and various modifications are possible.

[0143] For example, an example in which part of the configuration of any one embodiment is added to another embodiment, or an example in which part of the configuration of another embodiment is replaced with another embodiment, is also included in the embodiments of the present disclosure.

[0144] Furthermore, the equipment shown in the second embodiment above is an example of a photoelectric conversion system to which the photoelectric conversion device can be applied, and the equipment and photoelectric conversion system to which the photoelectric conversion device of the present disclosure can be applied are not limited to the configuration shown in Figure 16.

[0145] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present disclosure, and the technical scope of the present disclosure should not be construed as being limited by these embodiments. In other words, the present disclosure can be carried out in various forms without departing from its technical concept or main features.

[0146] The above-described embodiments can be modified as appropriate without departing from the spirit of the present invention. The disclosure of this specification includes not only what is described herein but also all matters that can be understood from the specification and the accompanying drawings. The disclosure of this specification also includes the complement of the concepts described herein. In other words, if the specification contains a statement that "A is greater than B," even if the statement that "A is not greater than B" is omitted, the specification can still be said to disclose that "A is not greater than B." This is because the statement that "A is greater than B" presupposes that the case in which "A is not greater than B" is taken into consideration.

[0147] The matters described in this disclosure have the following configuration.

[0148] (Configuration 1) A photoelectric conversion device comprising a plurality of pixels and a processing circuit that processes signals read out from the plurality of pixels, each of the plurality of pixels includes a photoelectric conversion element; a first amplifier unit having an input node to which a signal from the photoelectric conversion element is input and which outputs a signal obtained by amplifying the signal level of the input node; a storage capacitor unit having a variable capacitance value which stores the output signal of the first amplifier unit; and a second amplifier unit having a second input node to which a signal output from the storage capacitor unit is input and which outputs a signal obtained by amplifying the signal level of the second input node; A photoelectric conversion device, characterized in that the capacitance value of the storage capacitor is changed in response to a change in the driving power of at least one of the first amplifier and the second amplifier.

[0149] (Configuration 2) A photoelectric conversion device comprising a plurality of pixels and a processing circuit that processes signals read out from the plurality of pixels, each of the plurality of pixels includes a photoelectric conversion element; a first amplifier unit having an input node to which a signal from the photoelectric conversion element is input and which outputs a signal obtained by amplifying a signal level of the input node; and a storage capacitor unit which stores an output signal of the first amplifier unit and has a variable capacitance value; A photoelectric conversion device, characterized in that the capacitance value of the storage capacitor is changed in response to a change in the driving power of the first amplifier.

[0150] (Configuration 3) A photoelectric conversion device comprising a plurality of pixels and a processing circuit that processes signals read out from the plurality of pixels, each of the plurality of pixels includes a photoelectric conversion element; a first amplifier unit having an input node to which a signal from the photoelectric conversion element is input and which outputs a signal obtained by amplifying the signal level of the input node; and a storage capacitor unit connected to the first amplifier unit via a switch, which stores the output signal of the first amplifier unit, and has a variable capacitance value; A photoelectric conversion device, characterized in that the capacitance value of the storage capacitor is changed in response to a change in the ON period of the switch.

[0151] (Configuration 4) The photoelectric conversion device according to configuration 3, wherein each of the plurality of pixels includes a second input node to which a signal output from the storage capacitor is input, and a second amplifier unit that outputs a signal obtained by amplifying the signal level of the second input node.

[0152] (Configuration 5) 5. The photoelectric conversion device according to configuration 1 or 4, wherein the driving force of the first amplifier unit is smaller than the driving force of the second amplifier unit.

[0153] (Configuration 6) the photoelectric conversion element is disposed on a first substrate, and the storage capacitor is disposed on a second substrate; 6. The photoelectric conversion device according to any one of configurations 1 to 5, wherein the first substrate and the second substrate are stacked.

[0154] (Configuration 7) 7. The photoelectric conversion device according to any one of configurations 1 to 6, wherein the storage capacitor section is configured by combining a plurality of capacitance elements.

[0155] (Configuration 8) The photoelectric conversion device according to configuration 7, wherein the plurality of capacitive elements are capacitors formed in a wiring structure.

[0156] (Configuration 9) 8. The photoelectric conversion device according to configuration 7, wherein the plurality of capacitive elements are capacitors formed on a silicon substrate.

[0157] (Configuration 10) 10. The photoelectric conversion device according to any one of configurations 7 to 9, wherein the plurality of capacitive elements have the same capacitance value.

[0158] (Configuration 11) 10. The photoelectric conversion device according to any one of configurations 7 to 9, wherein the plurality of capacitive elements have different capacitance values.

[0159] (Configuration 12) The photoelectric conversion device according to configuration 11, wherein a storage capacitor is formed by selecting and connecting the capacitive elements having different capacitance values.

[0160] (Configuration 13) The photoelectric conversion device according to any one of configurations 7 to 12, wherein the plurality of capacitive elements include some capacitive elements that are in a non-selected state during a period in which some of the capacitive elements are selected.

[0161] (Configuration 14) 14. The photoelectric conversion device according to configuration 13, wherein a fixed potential is supplied to the other part of the capacitance elements.

[0162] (Configuration 15) 15. The photoelectric conversion device according to configuration 13 or 14, wherein the other part of the capacitance elements is disposed between a plurality of the storage capacitance sections in plan view.

[0163] (Configuration 16) 16. The photoelectric conversion device according to any one of configurations 7 to 15, wherein the plurality of capacitive elements are arranged irregularly.

[0164] (Configuration 17) 17. The photoelectric conversion device according to any one of configurations 7 to 16, wherein a storage capacitor section is formed of the plurality of non-adjacent capacitor elements.

[0165] (Configuration 18) The photoelectric conversion device according to any one of configurations 1 to 17, characterized in that the capacitance value of the holding capacitor when holding the signal of the first amplifier is different from the capacitance value when outputting the signal held in the holding capacitor.

[0166] (Configuration 19) The processing circuit performs gain processing, 19. The photoelectric conversion device according to any one of configurations 1 to 18, wherein the capacitance value of the storage capacitor is changed in accordance with the gain processing.

[0167] (Configuration 20) 19. The photoelectric conversion device according to any one of configurations 1 to 18, wherein the capacitance value of the storage capacitor section is changed depending on the readout mode.

[0168] (Configuration 21) the storage capacitor includes at least a first capacitor and a second capacitor, 21. The photoelectric conversion device according to any one of configurations 1 to 20, wherein the first capacitance section and the second capacitance section hold the signal output from the first amplification section for different periods.

[0169] (Configuration 22) 22. The photoelectric conversion device according to configuration 21, wherein the first capacitance section is configured by combining a plurality of capacitance elements.

[0170] (Configuration 23) 23. The photoelectric conversion device according to any one of configurations 1 to 22, wherein the driving force of the first amplifying section is variable.

[0171] (Configuration 24) a switch for resetting the storage capacitor unit; 24. The photoelectric conversion device according to any one of configurations 1 to 23, wherein at least one of the size of the switch and the time for which the switch is turned on is changed according to the capacitance value of the storage capacitor section.

[0172] (Configuration 25) 4. The photoelectric conversion device according to configuration 3, wherein the capacitance value of the storage capacitor is changed based on the range of possible signal amplitudes.

[0173] (Configuration 26) 26. The photoelectric conversion device according to any one of configurations 1 to 25, wherein the capacitance value is increased when the driving force of at least one of the first amplifying section and the second amplifying section is large.

[0174] (Configuration 27) 3. The photoelectric conversion device according to configuration 2, wherein the capacitance value is increased when the driving force is large.

[0175] (Configuration 28) 4. The photoelectric conversion device according to configuration 3, wherein the capacitance value is increased when the on-period of the switch is increased.

[0176] (Configuration 29) a current source is connected to the first amplifier unit via a transistor; 2. The photoelectric conversion device according to configuration 1, wherein the driving force of the first amplifier section is changed by changing the voltage applied to the gate of the transistor.

[0177] (Configuration 30) a current source is connected to the first amplifier unit via a current source transistor; 3. The photoelectric conversion device according to configuration 2, wherein the driving force of the first amplifier section is changed by changing the voltage applied to the gate of the current source transistor.

[0178] (Configuration 31) a plurality of current sources are connected in parallel to the first amplifier; The photoelectric conversion device according to configuration 1, wherein the driving force of the first amplifier section is changed by changing the number of connected current sources among the plurality of current sources.

[0179] (Configuration 32) a plurality of current sources are connected in parallel to the first amplifier; The photoelectric conversion device according to configuration 2, wherein the driving force of the first amplifier section is changed by changing the number of connected current sources among the plurality of current sources.

[0180] (Configuration 33) a first current source transistor and a second current source transistor are connected to the first amplifier section; 33. The photoelectric conversion device according to any one of configurations 1 to 32, wherein the gate width of the first current source transistor is larger than the gate width of the second current source transistor.

[0181] (Configuration 34) a first current source transistor and a second current source transistor are connected to the first amplifier section; 3. The photoelectric conversion device according to configuration 2, wherein the gate width of the first current source transistor is larger than the gate width of the second current source transistor.

[0182] (Configuration 35) An apparatus including the photoelectric conversion device according to any one of configurations 1 to 34, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device. [Explanation of symbols]

[0183] 10 Photoelectric conversion device 20 Pixel control circuit 21 Memory control circuit 22 Signal processing control circuit 30 pixels 40 pixel memory 50 Column signal processing circuit 111 First Amplifier 211 Second Amplifier 240 Holding capacity section

Claims

1. A photoelectric conversion device comprising a plurality of pixels and a processing circuit that processes signals read out from the plurality of pixels, each of the plurality of pixels includes a photoelectric conversion element; a first amplifier unit having an input node to which a signal from the photoelectric conversion element is input and which outputs a signal obtained by amplifying the signal level of the input node; a storage capacitor unit having a variable capacitance value which stores the output signal of the first amplifier unit; and a second amplifier unit having a second input node to which a signal output from the storage capacitor unit is input and which outputs a signal obtained by amplifying the signal level of the second input node; A photoelectric conversion device, characterized in that a capacitance value of the storage capacitor is changed in response to a change in the driving power of at least one of the first amplifier and the second amplifier.

2. A photoelectric conversion device comprising a plurality of pixels and a processing circuit that processes signals read out from the plurality of pixels, each of the plurality of pixels includes a photoelectric conversion element; a first amplifier unit having an input node to which a signal from the photoelectric conversion element is input and which outputs a signal obtained by amplifying a signal level of the input node; and a storage capacitor unit which stores the output signal of the first amplifier unit and has a variable capacitance value; A photoelectric conversion device, characterized in that the capacitance value of the storage capacitor is changed in response to a change in the driving power of the first amplifier.

3. A photoelectric conversion device comprising a plurality of pixels and a processing circuit that processes signals read out from the plurality of pixels, each of the plurality of pixels includes a photoelectric conversion element; a first amplifier unit having an input node to which a signal from the photoelectric conversion element is input and which outputs a signal obtained by amplifying the signal level of the input node; and a storage capacitor unit connected to the first amplifier unit via a switch, which stores the output signal of the first amplifier unit, and has a variable capacitance value; A photoelectric conversion device, characterized in that the capacitance value of the storage capacitor is changed in response to a change in the ON period of the switch.

4. The photoelectric conversion device according to claim 3, characterized in that each of the plurality of pixels has a second input node to which a signal output from the storage capacitor section is input, and includes a second amplifier section that outputs a signal obtained by amplifying the signal level of the second input node.

5. 2. The photoelectric conversion device according to claim 1, wherein the driving force of the first amplifier unit is smaller than the driving force of the second amplifier unit.

6. the photoelectric conversion element is disposed on a first substrate, and the storage capacitor is disposed on a second substrate; 2. The photoelectric conversion device according to claim 1, wherein the first substrate and the second substrate are stacked.

7. the photoelectric conversion element is disposed on a first substrate, and the storage capacitor is disposed on a second substrate; 3. The photoelectric conversion device according to claim 2, wherein the first substrate and the second substrate are stacked.

8. the photoelectric conversion element is disposed on a first substrate, and the storage capacitor is disposed on a second substrate; 4. The photoelectric conversion device according to claim 3, wherein the first substrate and the second substrate are stacked.

9. 2. The photoelectric conversion device according to claim 1, wherein the storage capacitor section is configured by combining a plurality of capacitance elements.

10. 10. The photoelectric conversion device according to claim 9, wherein the plurality of capacitive elements are capacitors formed in a wiring structure.

11. 10. The photoelectric conversion device according to claim 9, wherein the plurality of capacitive elements are capacitors formed on a silicon substrate.

12. 10. The photoelectric conversion device according to claim 9, wherein the plurality of capacitive elements have the same capacitance value.

13. 10. The photoelectric conversion device according to claim 9, wherein the plurality of capacitive elements have different capacitance values.

14. 14. The photoelectric conversion device according to claim 13, wherein the storage capacitor is formed by selecting and connecting the capacitor elements having different capacitance values.

15. 10. The photoelectric conversion device according to claim 9, wherein the plurality of capacitive elements include some capacitive elements that are in a non-selected state during a period in which some of the capacitive elements are selected.

16. 16. The photoelectric conversion device according to claim 15, wherein a fixed potential is supplied to the other part of the capacitance elements.

17. 16. The photoelectric conversion device according to claim 15, wherein the other part of the capacitance elements is arranged between a plurality of the storage capacitance sections in a plan view.

18. The photoelectric conversion device according to claim 9 , wherein the plurality of capacitance elements are arranged irregularly.

19. 10. The photoelectric conversion device according to claim 9, wherein a storage capacitor section is formed by the plurality of non-adjacent capacitor elements.

20. 2. The photoelectric conversion device according to claim 1, wherein the capacitance value of the holding capacitor when holding the signal of the first amplifier is different from the capacitance value when outputting the signal held in the holding capacitor.

21. The processing circuit performs gain processing, 2. The photoelectric conversion device according to claim 1, wherein the capacitance value of the storage capacitor is changed in accordance with the gain processing.

22. 2. The photoelectric conversion device according to claim 1, wherein the capacitance value of the storage capacitor is changed depending on a read mode.

23. the storage capacitor includes at least a first capacitor and a second capacitor, 2. The photoelectric conversion device according to claim 1, wherein the first capacitance section and the second capacitance section hold the signal output from the first amplification section for different periods.

24. 24. The photoelectric conversion device according to claim 23, wherein the first capacitance section is configured by combining a plurality of capacitance elements.

25. 2. The photoelectric conversion device according to claim 1, wherein the driving power of the first amplifier is variable.

26. a switch for resetting the storage capacitor unit; 2. The photoelectric conversion device according to claim 1, wherein at least one of the size of the switch and the time for which the switch is turned on is changed according to the capacitance value of the storage capacitor section.

27. 4. The photoelectric conversion device according to claim 3, wherein the capacitance value of the storage capacitor is changed based on a range of possible signal amplitudes.

28. 2. The photoelectric conversion device according to claim 1, wherein the capacitance value is increased when the driving force of at least one of the first amplifying section and the second amplifying section is large.

29. 3. The photoelectric conversion device according to claim 2, wherein the capacitance value is increased when the driving force is large.

30. 4. The photoelectric conversion device according to claim 3, wherein the capacitance value is increased when the ON period of the switch is increased.

31. a current source is connected to the first amplifier unit via a transistor; 2. The photoelectric conversion device according to claim 1, wherein the driving force of the first amplifier section is changed by changing the voltage applied to the gate of the transistor.

32. a current source is connected to the first amplifier unit via a current source transistor; 3. The photoelectric conversion device according to claim 2, wherein the driving force of the first amplifier section is changed by changing the voltage applied to the gate of the current source transistor.

33. a plurality of current sources are connected in parallel to the first amplifier; 2. The photoelectric conversion device according to claim 1, wherein the driving power of the first amplifier section is changed by changing the number of connected current sources among the plurality of current sources.

34. a plurality of current sources are connected in parallel to the first amplifier; 3. The photoelectric conversion device according to claim 2, wherein the driving power of the first amplifier section is changed by changing the number of connected current sources among the plurality of current sources.

35. a first current source transistor and a second current source transistor are connected to the first amplifier section; 2. The photoelectric conversion device according to claim 1, wherein the gate width of the first current source transistor is larger than the gate width of the second current source transistor.

36. a first current source transistor and a second current source transistor are connected to the first amplifier section; 3. The photoelectric conversion device according to claim 2, wherein the gate width of the first current source transistor is larger than the gate width of the second current source transistor.

37. An apparatus comprising the photoelectric conversion device according to any one of claims 1 to 36, an optical device corresponding to the photoelectric conversion device; a control device that controls the photoelectric conversion device; a processing device that processes a signal output from the photoelectric conversion device; a display device that displays information obtained by the photoelectric conversion device; a storage device that stores information obtained by the photoelectric conversion device; and and a mechanical device that operates based on information obtained by the photoelectric conversion device.

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