Split double gate transistor and method of manufacturing the same

Abstract

To provide a split double gate transistor and a method of manufacturing the same.SOLUTION: The method includes forming a first fin on a substrate, partially removing a sacrificial layer from the first fin, sequentially forming a first gate insulating layer, a channel layer, and a protection layer on an exposed portion of each gate metal layer, patterning to form a second fin, patterning the second fin to form a plurality of first concave portions and a plurality of second concave portions, forming a plurality of inner isolation layers, forming a first gate member, a drain member, and a source member, removing each protection layer, and sequentially forming a second gate insulating layer, a plurality of gate connection members, and a second gate member.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a transistor and a method for manufacturing the same, and more particularly to a split double gate transistor and a method for manufacturing the same. [Background technology]

[0002] Stacked nanowire / nanosheet is a new type of transistor structure that is currently undergoing rapid development at the 3nm node and more advanced nodes (e.g., 2nm, 1.4nm, and even sub-1nm). The technology aims to further reduce the size of transistors, increasing circuit density and providing better circuit driving capability while reducing power consumption characteristics.

[0003] Among stacked nanowire / nanosheet structures, gate-all-around (GAA) is one of the most representative architectures. GAA transistors achieve stronger electric field control by completely surrounding the nanowire or nanosheet on all four sides with the gate material, significantly reducing short channel effects (SCE) and improving switching characteristics (On / Off ratio).

[0004] However, in the GAA fabrication process, the channel layers are deposited sequentially, meaning that each nanowire or nanosheet channel must be constructed layer by layer. During this multi-step fabrication process, temperature fluctuations, gas flow rate changes, non-uniform material supply, or poor etch selectivity can all lead to significant differences in thickness, crystal quality, stress distribution, and doping concentration between different channel layers. These process variations directly impact the consistency of the electron mobility (carrier mobility) and threshold voltage (Vt) of the channel layer and the electrical performance stability of the entire transistor, resulting in significantly reduced fabrication yields and unpredictable product performance.

[0005] Another major challenge in existing GAA architectures is the lack of a back gate. In conventional field-effect transistors (FETs), a back gate is typically used to dynamically control the carrier concentration in the channel, allowing for flexible adjustment of the critical voltage. However, in GAA transistors, the channel is completely covered by the gate material, leaving no extra space for a back gate inside. This prevents existing GAA architectures from precisely controlling the critical voltage using back biasing techniques. Summary of the Invention [Problem to be solved by the invention]

[0006] The technical problem that the present invention aims to solve is to provide a split double gate transistor and a manufacturing method thereof in response to the shortcomings of the prior art. [Means for solving the problem]

[0007] In order to solve the above technical problems, one technical solution adopted by the present invention provides a method for manufacturing a split double-gate transistor, which includes the steps of forming a first fin on a substrate, the first fin including a plurality of gate metal layers and a plurality of sacrificial layers stacked alternately; partially removing the plurality of sacrificial layers from the first fin; forming a first gate insulating layer, a channel layer, and a protective layer in this order on the exposed portions of each gate metal layer; patterning the first fin, each of the first gate insulating layers, each of the channel layers, and each of the protective layers to form a second fin; and patterning the second fin to form a plurality of first recesses on a first side and a second side, and a plurality of first recesses on a third side and a fourth side. forming a plurality of internal isolation layers filling the plurality of first recesses and the plurality of second recesses; forming a first gate member electrically connected to the plurality of gate metal layers on the first side, and forming a drain member and a source member electrically connected to each channel layer on the third side and the fourth side, respectively; removing a part of the plurality of internal isolation layers and each protection layer from the second side to expose each gate metal layer, each first gate insulating layer, each channel layer, and each internal isolation layer that has not been removed; and forming a second gate insulating layer and a second gate member in this order on each exposed gate metal layer, each first gate insulating layer, each channel layer, and each internal isolation layer that has not been removed.

[0008] To solve the above technical problems, another technical solution adopted by the present invention provides a split double-gate transistor, which includes a substrate, a fin-shaped structure, a second gate insulating layer, a first gate member, a drain member, a source member, and a second gate member. The fin-shaped structure is disposed on the substrate and includes a plurality of stacked structures, a plurality of gate connection members, a plurality of inner spacers, and a second gate insulating layer. The plurality of stacked structures are disposed at intervals along the vertical direction, and each includes a gate metal layer, a first gate insulating layer, and a channel layer. The plurality of gate connection members are disposed alternately with the plurality of stacked structures along the vertical direction, and each gate connection member extends along the first direction. The plurality of inner spacers are disposed at intervals along the vertical direction, and each surrounds the plurality of gate connection members and contacts each of the first gate insulating layer and the channel layer. A second gate insulating layer is disposed between the inner spacers and the gate connection members and between the gate connection members and the stacked structures. A first gate member is disposed on a first side of the fin-shaped structure and is electrically connected to each gate metal layer. A drain member and a source member are disposed on a third side and a fourth side of the fin-shaped structure, respectively, facing each other along a second direction, with the drain member electrically connected to the drain region of each channel layer and the source member electrically connected to the source region of each channel layer. A second gate member is disposed on a second side of the fin-shaped structure and is electrically connected to each gate connection member. [Brief explanation of the drawings]

[0009] [Figure 1] 2 is a flowchart of a method for manufacturing a split double-gate transistor according to an embodiment of the present invention. [Figure 2] FIG. 1 is a top view of the process of step S10 according to an embodiment of the present invention. [Figure 3] FIG. 1 is a first cross-sectional view of the process of step S10 according to an embodiment of the present invention. [Figure 4] FIG. 10 is a second cross-sectional view of the process of step S10 according to an embodiment of the present invention. [Figure 5] FIG. 10 is a top view of the process of step S11 according to an embodiment of the present invention. [Figure 6] FIG. 10 is a first cross-sectional view of the process of step S11 according to an embodiment of the present invention. [Figure 7] FIG. 10 is a second cross-sectional view of the process of step S11 according to an embodiment of the present invention. [Figure 8] FIG. 10 is a first top view of the process of step S12 according to one embodiment of the present invention. [Figure 9] FIG. 10 is a first cross-sectional view of the process of step S12 according to an embodiment of the present invention. [Figure 10] FIG. 10 is a second cross-sectional view of the process of step S12 according to an embodiment of the present invention. [Figure 11] FIG. 10 is a second top view of the process of step S12 according to an embodiment of the present invention. [Figure 12] FIG. 10 is a third cross-sectional view of the process of step S12 according to an embodiment of the present invention. [Figure 13] FIG. 4 is a fourth cross-sectional view of the process of step S12 according to an embodiment of the present invention. [Figure 14] FIG. 10 is a top view of the process of step S13 according to an embodiment of the present invention. [Figure 15] FIG. 10 is a first cross-sectional view of the process of step S13 according to an embodiment of the present invention. [Figure 16] FIG. 10 is a second cross-sectional view of the process of step S13 according to an embodiment of the present invention. [Figure 17] 10 is a detailed flowchart of step S14. [Figure 18] FIG. 10 is a top view of the process of step S14 according to an embodiment of the present invention. [Figure 19] FIG. 10 is a first cross-sectional view of the process of step S14 according to an embodiment of the present invention. [Figure 20] FIG. 10 is a second cross-sectional view of the process of step S14 according to an embodiment of the present invention. [Figure 21] FIG. 10 is a top view of the process of step S15 according to an embodiment of the present invention. [Figure 22] FIG. 10 is a first cross-sectional view of the process of step S15 according to an embodiment of the present invention. [Figure 23]FIG. 10 is a second cross-sectional view of the process of step S15 according to an embodiment of the present invention. [Figure 24] FIG. 10 is a top view of the process of step S16 according to an embodiment of the present invention. [Figure 25] FIG. 10 is a first cross-sectional view of the process of step S16 according to an embodiment of the present invention. [Figure 26] FIG. 10 is a second cross-sectional view of the process of step S16 according to an embodiment of the present invention. [Figure 27] FIG. 10 is a top view of the process of steps S17 and S18 according to an embodiment of the present invention. [Figure 28] FIG. 10 is a first cross-sectional view of the process of steps S17 and S18 according to an embodiment of the present invention. [Figure 29] FIG. 10 is a second cross-sectional view of the process of steps S17 and S18 according to an embodiment of the present invention. [Figure 30] FIG. 10 is a top view of the process of step S19 according to an embodiment of the present invention. [Figure 31] FIG. 10 is a first cross-sectional view of the process of step S19 according to an embodiment of the present invention. [Figure 32] FIG. 10 is a second cross-sectional view of the process of step S19 according to an embodiment of the present invention. [Figure 33] FIG. 10 is a top view of the process of step S20 according to one embodiment of the present invention. [Figure 34] FIG. 10 is a first cross-sectional view of the process of step S20 according to an embodiment of the present invention. [Figure 35] FIG. 10 is a second cross-sectional view of the process of step S20 according to an embodiment of the present invention. [Figure 36] FIG. 2 is a perspective view of a split double-gate transistor according to another embodiment of the present invention. [Figure 37] FIG. 2 is a perspective view of a split double-gate transistor according to another embodiment of the present invention after removing the second gate member. DETAILED DESCRIPTION OF THE INVENTION

[0010] To better understand the features and technical contents of the present invention, please refer to the following detailed description of the present invention and the accompanying drawings, which are provided for reference and explanation only and do not limit the scope of the present invention.

[0011] The following describes the implementation of the "split double-gate transistor and its manufacturing method" according to the present invention through specific examples. Those skilled in the art can understand the advantages and benefits of the present invention based on the disclosure herein. The present invention can be implemented or applied through other different specific examples, and various modifications and changes can be made to the details herein based on different perspectives and applications without departing from the concept of the present invention. Please note that the accompanying drawings are for simple schematic illustrations and are not drawn to scale. The technical content of the present invention will be described in more detail based on the following examples, but the disclosed content does not limit the scope of protection of the present invention. The term "or" used in this specification may include any one or more combinations of the related listed items depending on the actual situation.

[0012] The main objective of the present invention is to provide a split double gate transistor and a manufacturing method thereof, which can reduce process variations by simultaneously depositing all channel layers through a design process, and can control the critical voltage of the formed transistor by a back gate.

[0013] 1 is a flow chart of a method for fabricating a split double-gate transistor according to one embodiment of the present invention. The method of FIG. 1 is for illustrative purposes only, and other steps may be performed before, during, or after the method.

[0014] Referring to FIG. 1, a first embodiment of the present invention provides a method for fabricating a split double-gate transistor, which includes the following steps.

[0015] Step S10: A first fin is formed on the substrate. 2, 3, and 4 are a top view, a first cross-sectional view, and a second cross-sectional view, respectively, of step S10 of an embodiment of the present invention. Here, FIG. 3 is a cross-sectional view taken along the cross-sectional line CS1, and FIG. 4 is a cross-sectional view taken along the cross-sectional line CS2. Unless otherwise specified, the other cross-sectional views are uniformly taken along the cross-sectional lines CS1 and CS2, and are not separately described. As shown in FIGS. 2, 3, and 4, the substrate 10 can be made of a material such as silicon, germanium, or glass. A first region A1 and two adjacent excess regions Ar are defined on the substrate 10. The first fin 12 extends in the vertical direction DN, simultaneously covering the first region A1 and the two adjacent excess regions Ar of the substrate 10. As shown in the figure, the first direction DR1, the second direction DR2, and the vertical direction DN are perpendicular to each other, and the first area A1 and the excess areas Ar on both sides thereof are arranged along the first direction DR1, and the first area A1 is, for example, rectangular, and its width in the second direction DR2 is shorter than its length in the first direction DR1.

[0016] The first fin 12 includes multiple gate metal layers 120 and multiple sacrificial layers 122 stacked alternately along the vertical direction DN. For example, a first gate metal layer 120 is disposed on the substrate 10, a first sacrificial layer 122 is disposed on the first gate metal layer 120, and a second gate metal layer 120 is disposed on the first sacrificial layer 122. In the following example, three gate metal layers 120 and three sacrificial layers 122 are stacked alternately. In one embodiment, the gate metal layers 120 and the sacrificial layers 122 have different thicknesses. In addition, the thicknesses of one gate metal layer 120 and another gate metal layer 120 may be different from each other, and the thicknesses of one sacrificial layer 122 and another sacrificial layer 122 may be different from each other.

[0017] The gate metal layer 120 can be made of titanium nitride (TiN), tungsten, aluminum, or titanium, with a thickness ranging from 1 nm to 1000 nm, and can be formed by atomic layer deposition (ALD) or physical vapor deposition (PVD). The material of the sacrificial layer 122 can include one or more of titanium nitride, titanium, tungsten, silicon nitride, and silicon dioxide, with a thickness ranging from 1 nm to 1 μm, and can be deposited by ALD, sputtering, plasma-enhanced chemical vapor deposition (PECVD), or epitaxy.

[0018] In step S10, three gate metal layers 120 and three sacrificial layers 122 are formed in this order on the substrate 10 (e.g., by ALD or sputtering techniques), and then a mask defining a fin pattern is formed on the top surface of the stack (e.g., by e-beam lithography), followed by removing portions of the stack not covered by the mask (e.g., using reactive ion etching (RIE)), and finally removing the mask to form the fin structure.

[0019] Step S11: Partially remove the sacrificial layer from the first fin portion. 5, 6, and 7 are a top view, a first cross-sectional view, and a second cross-sectional view, respectively, of the process of step S11 according to one embodiment of the present invention. In step S11, a portion of the sacrificial layer 122 overlapping with the first region A1 may be removed from the first fin 12 to expose a portion of each gate metal layer 120.

[0020] For example, by selective etching, a portion of the sacrificial layer 122 overlapping with the first region A1 can be removed to expose a portion of the gate metal layer 120 overlapping with the first region A1. Here, the second gate metal layer 120 and the third gate metal layer 120 are supported by the sacrificial layer 122 that has not been removed in the excess area Ar, and portions of them in the first region A1 float above the substrate 10.

[0021] Step S12: A first gate insulating layer, a channel layer, and a protective layer are formed in this order on the exposed portions of each gate metal layer. 8, 9, and 10 are a first top view, a first cross-sectional view, and a second cross-sectional view, respectively, of step S12 according to an embodiment of the present invention. As shown in FIGS. 8, 9, and 10, the material of the first gate insulating layer 13 may be a dielectric material with a high k value (dielectric constant), such as aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconia (ZrO2), or hafnium zirconium oxide (HZO), and its thickness may be in the range of 1 nm to 1000 nm. The deposition method of the first gate insulating layer 13 may employ a technique such as atomic layer deposition (ALD).

[0022] The material of the channel layer 14 may be selected from a variety of materials, including oxide semiconductor materials, II-VI, III-V, IV, and 2D materials. The deposition method of the channel layer 14 may employ techniques such as atomic layer deposition (ALD), and applicable oxide semiconductor materials include InO, IZO, ITO, IWO, IGZO, IGZTO, etc. In some circumstances, the material of the sacrificial layer 122 (e.g., SiO2, SiN, TiN, W, Ti) should be different from the material of the channel layer 14 (e.g., IGZO) to achieve etching selectivity.

[0023] As can be seen from Figure 9, the first gate insulating layer 13 and the channel layer 14 cover, in this order, the substrate 10, the top surface of the top sacrificial layer 122, and the exposed portion of the top gate metal layer 120. As can be seen from Figure 10, the first gate insulating layer 13 and the channel layer 14 are formed in this order to cover the bottom gate metal layer 120 and to surround the floating gate metal layer 120 (particularly the top, side, and bottom surfaces of the second and third gate metal layers 120). Note that, as can be seen from Figure 9, the first gate insulating layer 13 and the channel layer 14 also cover the inner surface of the sacrificial layer 122 exposed after step S11. Therefore, a two-layer rectangular structure with a hollow portion is formed between the first and second gate metal layers 120, and a corresponding recess is formed on the third gate metal layer 120.

[0024] 11, 12, and 13 are a second top view, a third cross-sectional view, and a fourth cross-sectional view, respectively, of step S12 of the process according to one embodiment of the present invention. As shown in FIGS. 11, 12, and 13, after forming the first gate insulating layer 13 and the channel layer 14, a protective layer 15 may be further formed. The protective layer 15 may be, for example, silicon oxide (SiOx), and may be deposited by PECVD, thermal oxidation, or ALD techniques. As can be seen from FIGS. 11 and 12, the protective layer 15 completely covers and surrounds the entire stack structure of the channel layer 14, the first gate insulating layer 13, and the gate metal layer 120. 12, the protective layer 15 covers the stacked structure of the channel layer 14-first gate insulating layer 13 above the third gate metal layer 120 and the third sacrificial layer 122, filling the hollow portion of the rectangular structure consisting of two layers shown in FIG. 9 and also filling the recessed portion formed corresponding to the third gate metal layer 120. In one embodiment, the thickness of the protective layer 15 in the second direction DR2 is different from the thickness of the protective layer 15 in the vertical direction DN.

[0025] In step S12, the design process allows all channel layers 15 to be formed simultaneously in a single step, thus minimizing process variations between different channel layers 14 of the present invention compared to multiple channel layers grown sequentially in conventional stacked nanowire / nanosheet structures, and maintaining consistency in electron mobility, critical voltage, and overall transistor electrical performance.

[0026] Step S13: The first fin, the first gate insulating layers, the channel layers, and the protective layers are patterned to form a second fin. 14, 15, and 16 are a top view, a first cross-sectional view, and a second cross-sectional view, respectively, of the process of step S13 according to one embodiment of the present invention. More specifically, in step S13, portions of the first fin 12, the first gate insulating layer 13, the channel layer 14, and the protective layer 15 that do not overlap the second region A2 of the substrate 10 are removed to form a second fin 16 in the second region A2 of the substrate 10. For example, the second region A2 may be rectangular and partially overlap the first region A1. The length of the second region A2 in the first direction DR1 is smaller than the length of the first region A1 in the first direction DR1. More specifically, the length of the second region A2 in the first direction DR1 is equal to or smaller than the length of the first region A1 in the first direction DR1 minus twice the thickness of the first gate insulating layer 13 and twice the thickness of the channel layer 14. The width of the second region A2 in the second direction DR2 is greater than the width of the first region A1 in the second direction DR2. More specifically, the width of the second region A2 in the second direction DR2 is equal to or greater than the width of the first region A1 in the second direction DR2 plus twice the thickness of the first gate insulating layer 13, twice the thickness of the channel layer 14, and twice the thickness of the protective layer 15 in the first direction DR1.

[0027] As can be seen from the definitions of the sizes of the first region A1 and the second region A2 above, after removing the portions of the first fin 12, the first gate insulating layer 13, the channel layer 14, and the protective layer 15 that do not overlap with the second region A2 of the substrate 10, the side surfaces of the gate metal layer 120, the first gate insulating layer 13, and the channel layer 14 in the first direction DR1 are exposed, but the side surfaces of the gate metal layer 120, the first gate insulating layer 13, and the channel layer 14 in the second direction DR2 are still covered by the protective layer 15. Taking this embodiment as an example, the formed second fin 16 includes, from bottom to top, a gate metal layer 120, a first gate insulating layer 13, a channel layer 14, a protective layer 15, a channel layer 14, a first gate insulating layer 13, a gate metal layer 120, a first gate insulating layer 13, a channel layer 14, a protective layer 15, a channel layer 14, a first gate insulating layer 13, a gate metal layer 120, a first gate insulating layer 13, a channel layer 14, and a protective layer 15. Note that the opposite sides of the second fin 16 along the first direction DR1 are defined as a first side and a second side, and the opposite sides along the second direction DR2 are defined as a third side and a fourth side.

[0028] Step S14: The second fin is patterned to form a plurality of first recesses on the first side and the second side, and a plurality of second recesses on the third side and the fourth side. FIG. 17 is a detailed flowchart of step S14, and FIGS. 18, 19, and 20 are a top view, a first cross-sectional view, and a second cross-sectional view, respectively, of the process of step S14 according to one embodiment of the present invention. In one embodiment, step S14 may include the following steps:

[0029] Step S140: A portion of the gate insulating layer, a portion of the channel layer, and a portion of the protective layer are removed from the second fin along a first direction, and the gate insulating layer, the channel layer, and the protective layer are recessed relative to the plurality of gate metal layers to form the plurality of first recesses. As shown in FIGS. 18 to 20 , the second region A2 may include an inner region A21 and an outer region A22 surrounding it, and in step S140, a selective etching technique (e.g., reactive ion etching (RIE), plasma etching, atomic layer etching (ALE), and / or wet etching) may be employed to remove portions of the first gate insulating layer 13, the channel layer 14, and the protective layer 15 from the second fin 16 that overlap with the outer region A22 along the first direction DR1, thereby recessing the first gate insulating layer 13, the channel layer 14, and the protective layer 15 relative to the gate metal layer 120 to form a plurality of first recesses R1. That is, both the top and bottom surfaces of each gate metal layer 120 are partially exposed, and the surfaces on both sides of each gate metal layer 120 in the first direction DR1 protrude relative to the stacked structure of the adjacent first gate insulating layer 13, channel layer 14, and protective layer 15.

[0030] Step S141: Remove another portion of the protective layer from the second fin along a second direction to recess the protective layer relative to the plurality of gate metal layers, the gate insulating layer, and the channel layer to form the plurality of second recesses. As shown in Figures 18 to 20, in step S141, another selective etching technique (e.g., reactive ion etching (RIE), plasma etching, atomic layer etching (ALE), and / or wet etching, etc.) can be adopted to remove a portion of the protective layer 15 that overlaps with the outer region A22 from the second fin 16 along the second direction DR2, thereby recessing the protective layer 15 relative to the gate metal layer 120, the first gate insulating layer 13, and the channel layer 14 to form a plurality of second recesses R2.

[0031] That is, the outer surface of each channel layer 14 formed to surround the gate metal layer 120 is partially exposed, and the outer surfaces on both sides of each channel layer 14 in the second direction DR2 protrude from the adjacent protective layer 15. Note that the outer surfaces on both sides of each first gate insulating layer 13 formed to surround the gate metal layer 120 in the second direction DR2 also protrude from the adjacent protective layer 15.

[0032] Step S15: A plurality of inner isolation layers are formed to fill the plurality of first recesses and the plurality of second recesses. 21, 22, and 23 are a top view, a first cross-sectional view, and a second cross-sectional view, respectively, of step S15 of one embodiment of the present invention. As can be seen from FIGS. 21 and 22, the inner isolation layer 17 surrounds all of the first gate insulating layers 13, channel layers 14, and protective layers 15, while both surfaces of each gate metal layer 120 in the first direction DR1 are exposed, and all of the first recesses R1 are filled evenly. As can be seen from FIGS. 21 and 23, the inner isolation layer 17 surrounds all of the protective layers 15, while both outer surfaces of each channel layer 14 in the second direction DR2 are exposed, and all of the second recesses R2 are filled evenly.

[0033] In this process, the material of the inner isolation layer 17 can be selected as silicon nitride (Si3N4), silicon oxide (SiO2), silicon oxynitride (SiON), etc. The deposition method of the inner isolation layer 17 can include techniques such as ALD, sputtering, and PECVD.

[0034] Step S16: Forming a first gate member electrically connected to the plurality of gate metal layers on the first side, and forming a drain member and a source member electrically connected to each channel layer on the third side and the fourth side, respectively. 24, 25, and 26 are a top view, a first cross-sectional view, and a second cross-sectional view, respectively, of step S16 according to one embodiment of the present invention. Before performing step S16, n-type or p-type doping may be performed on the exposed outer surfaces of each channel layer 14 (i.e., the surfaces on the third and fourth sides of each channel layer 14) along the second direction DR2 to form n+ or p+ regions at the positions where the drain and source of the channel layer 14 are to be formed (i.e., the drain and source regions). The method for forming the n+ or p+ regions may include highly selective ion implantation (HiSIDE). Subsequently, drain members D1 and source members S1 electrically connected to each channel layer 14 may be formed on the third and fourth sides, respectively. The drain member D1 and the source member S1 can be made of TiN, Al, Ti, W, indium tin oxide (ITO), or indium oxide (InO), and can have a thickness ranging from 1 nm to 1000 nm. They can be deposited by ALD or sputtering. As shown in FIG. 26, the drain member D1 and the source member S1 can be formed as two elongated metal sheets extending along the vertical direction DN and electrically connecting to the respective channel layers 14. Their heights are slightly higher than those of the protective layer 15 and the inner isolation layer 17. The contact areas between the drain member D1 and the source member S1 and the outer surfaces of the exposed sides of the channel layers 14 are relatively large, which can reduce the series resistance and improve the device performance.

[0035] Meanwhile, a first gate member G1 can be formed on the first side, electrically connected to each gate metal layer 120. Similarly, the material of the first gate member G1 can be selected from TiN, Al, Ti, W, indium tin oxide (ITO), or indium oxide (InO), and the thickness can range from 1 nm to 1000 nm, and can be deposited by ALD or sputtering techniques. As shown in FIG. 25 , the first gate member G1 can be formed as a long metal sheet extending along the vertical direction DN and electrically connected to each gate metal layer 120.

[0036] In one embodiment, steps S17 and S18 may be performed first after forming the first gate member G1, the drain member D1, and the source member S1.

[0037] Step S17: A dielectric layer is formed to cover the first gate member, the drain member and the source member, and the inner isolation layer on the first side of the second fin. 27, 28, and 29 are a top view, a first cross-sectional view, and a second cross-sectional view, respectively, of steps S17 and S18 according to an embodiment of the present invention. Referring to FIGS. 27, 28, and 29, step S17 can use chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD) techniques to uniformly form a dielectric layer 18 on the structure surface. Materials such as silicon dioxide (SiO), silicon nitride (SiN), or hafnium dioxide (HfO) are typically selected for the dielectric layer, which can provide good insulating performance.

[0038] Step S18: Partially remove the dielectric layer, the protective layer, the inner isolation layer, the first gate member, the drain member, and the source member in a vertical direction by a polishing process. 27, 28, and 29, in step S18, for example, a chemical mechanical polishing (CMP) technique can be employed to precisely remove excess material in the vertical direction DN. The CMP process can achieve a surface planarization effect on the dielectric layer 18, the protective layer 15, the inner isolation layer 17, the first gate member G1, the drain member D1, and the source member S1 by combining mechanical polishing and chemical etching. After the CMP process is completed, unnecessary portions on the tops of the dielectric layer 18, the protective layer 15, the inner isolation layer 17, the first gate member G1, the drain member D1, and the source member S1 are removed, preparing them for subsequent processes.

[0039] Step S19: Remove some of the internal isolation layers and the protective layers from the second side to expose the gate metal layers, the first gate insulating layers, the channel layers, and any remaining internal isolation layers. For example, in step S19, an etching process can be performed to remove the internal isolation layer 17 and the portion of the dielectric layer 18 located on the second side, all of the protective layer 15, a portion of the drain member D1, and a portion of the source member S1. Referring to Figures 30, 31, and 32, a top view, a first cross-sectional view, and a second cross-sectional view of step S19 according to one embodiment of the present invention are shown.

[0040] In step S19, reactive ion etching (RIE) and / or wet etching techniques can be employed to precisely remove material in the target areas. For example, due to the highly anisotropic properties of RIE, fluoride gases (e.g., SF6, CF4) can be injected to etch the dielectric layer 18, and chlorine gases (e.g., Cl2, BCl3) can be employed to etch metal materials during the manufacturing process.

[0041] In some embodiments, a hydrofluoric acid (HF) solution may be used to remove the inner isolation layer 17, or a mixture of aqueous ammonia and hydrogen peroxide (SC-1) may be used to remove portions of specific metal components. Wet etching has good selectivity when processing complex structures.

[0042] In the above etching process, a photoresist or a hard mask may be provided as required for the process to accurately and selectively remove the inner isolation layer 17 and the portions of the dielectric layer 18 located on the second side, and the drain member D1 and the source member S1 may be partially removed to expose the portion of the gate metal layer 120 facing the second side, the portion of the first gate insulating layer 13 facing the second side, a portion of the surface of the channel layer 14, and the inner isolation layer 17. Specifically, the main purpose of this step is to open the channel layer 14 and, at the same time, to open a specific surface on the gate metal layer 120 to install a back gate as a body contact.

[0043] Step S20: A second gate insulating layer, a plurality of gate connecting members, and a second gate member are formed in this order on the exposed gate metal layers, the first gate insulating layers, the channel layers, and the unremoved isolation layers. 33, 34 and 35, there are shown a top view, a first cross-sectional view and a second cross-sectional view, respectively, of the process of step S20 according to one embodiment of the present invention.

[0044] Similar to the first gate insulating layer 13, the second gate insulating layer 19 may be made of a dielectric material with a high k value (dielectric constant), such as aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconia (ZrO2), or hafnium zirconium oxide (HZO). Its thickness may be in the range of 1 nm to 1000 nm, and a deposition method such as atomic layer deposition (ALD) may be employed. The second gate insulating layer 19 may be formed on the exposed second surfaces of the gate metal layers 120, the first gate insulating layers 13, the channel layers 14, and the remaining inner isolation layers 17, as shown in the figure. Since the substrate 10 is partially exposed by removing the dielectric layer 18 and the first gate metal layer 120 in step S19, the second gate insulating layer 19 also covers the exposed portions. As can be seen from the first cross-sectional view, the second gate insulating layer 19 has a comb-like structure.

[0045] Meanwhile, a plurality of gate connection members G21 and a second gate member G22 can be formed on the second side, electrically connected to each gate metal layer 120. Similarly, the materials for the gate connection member G21 and the second gate member G22 can be selected from TiN, Al, Ti, W, indium tin oxide (ITO), or indium oxide (InO), and can be deposited using ALD or sputtering techniques. As shown in FIG. 34, the second gate member G22 extends along the vertical direction, and a plurality of gate connection members G21 branch out from the second gate member G22, and each gate connection member G21 extends along the first direction DR1. Therefore, the plurality of gate connection members G21 and the second gate member G22 collectively form a comb-shaped conductive member electrically connected to each gate metal layer 120. Each comb structure (gate connection member G21) is disposed between two adjacent channel layers 14, between two adjacent first gate insulating layers 13, and between two adjacent gate metal layers 120. Here, the gate connection member G21 and the second gate member G22 function as body contacts to control the threshold voltage.

[0046] After step S20, the dielectric layer can be removed by etching or polishing process according to the electrode configuration needs, to form the split double gate transistor provided by the present invention.

[0047] 36 and 37, there are shown perspective views and perspective views after removing the second gate member, respectively, of a split double gate transistor according to another embodiment of the present invention.

[0048] As shown in Figures 36 and 37, an embodiment of the present invention provides a split double-gate transistor 2 including a substrate 20, a fin-like structure 22, a first gate member G1', a drain member D1', a source member D2', and a second gate member G22'.

[0049] The fin-like structure 22 is disposed on the substrate 20 and includes a plurality of stacked structures 220, a plurality of gate connecting members G21', a plurality of inner spacers 222, and a second gate insulating layer 224.

[0050] The plurality of stacked structures 220 are spaced apart along the vertical direction DN, and each includes a gate metal layer 2200, a first gate insulating layer 2202, and a channel layer 2204.

[0051] The gate connection members G21' are arranged alternately with the stacked structures 220 along the vertical direction DN, and each gate connection member G21' extends along the first direction DR1.

[0052] The inner spacers 222 are spaced apart along the vertical direction DN, each surrounding the gate connecting members G21′ and contacting each first gate insulating layer 2202 and each channel layer 2204.

[0053] A second gate insulating layer 224 is provided between each inner spacer 222 and the gate connecting member G21′ it surrounds, and a second gate insulating layer 224 is also provided between each gate connecting member G21′ and an adjacent stacked structure 220. The second gate insulating layer 224 has, in a first portion provided along the first direction DR1 and the second direction DR2, a first sub-portion in contact with the channel layer 2204 and a second sub-portion in contact with the substrate 20. The second portion of the second gate insulating layer 224 provided along the vertical direction DN has a third sub-portion in contact with each inner spacer 222 and a fourth sub-portion in contact with each stacked structure 22.

[0054] The first gate member G1′ is disposed on the first side of the fin-like structure 22 and is electrically connected to each gate metal layer 2200.

[0055] The drain member D1' and the source member S1' are respectively disposed on the third and fourth sides of the fin-shaped structure 22 facing each other along the second direction DR2, and the drain member D1' is electrically connected to the drain region of each channel layer 2204, and the source member S1' is electrically connected to the source region of each channel layer 2204.

[0056] The second gate member G22' is disposed on the second side of the fin-like structure 22 and is electrically connected to each gate connecting member G21'.

[0057] Here, for the specific appearances and materials used of the substrate 20, the fin-shaped structure 22, the gate connecting member G21′, the inner spacer 222, the second gate insulating layer 224, the gate metal layer 2200, the first gate insulating layer 2202, the channel layer 2204, the first gate member G1′, the drain member D1′, the source member D2′, and the second gate member G22′, reference may be made to Figures 31, 32, 33, and related depictions, and detailed descriptions will not be provided again here.

[0058] The split double-gate transistor provided by the present invention has a back gate that can be used to control the threshold voltage, thereby improving the performance of electronic devices that employ it. For example, when the split double-gate transistor provided by the present invention is applied to an existing 2T0C memory architecture, the bulk voltage applied to the second gate element can be adjusted to the operating voltage (VDD) to increase the conduction current and improve the write speed. Alternatively, the bulk voltage applied to the second gate element can be adjusted to the negative operating voltage (-VDD) to reduce the leakage current when the switch is turned off, thereby improving the retention time for data stored in the node. [Industrial Applicability]

[0059] [Beneficial Effects of Examples] One of the beneficial effects of the present invention is that the split double gate transistor and the manufacturing method thereof provided by the present invention can simultaneously deposit all channel layers by design process, thereby reducing process variations, and the critical voltage of the formed transistor can be controlled by the back gate.

[0060] Furthermore, when the split double-gate transistor provided by the present invention is applied to an existing memory architecture, the bulk voltage applied to the second gate member can be adjusted to the operating voltage (VDD) to increase the current flow and improve the write speed, or the bulk voltage applied to the second gate member can be adjusted to a negative operating voltage to reduce the leakage current when the switch is turned off and improve the retention time of data stored in the node.

[0061] The above disclosure is merely a preferred embodiment of the present invention, and the scope of the claims of the present invention is not limited thereto. Therefore, any equivalent technical modifications made by utilizing the specification and drawings of the present invention are included in the scope of the claims of the present invention. [Explanation of symbols]

[0062] 10,20...board 12...First fin 22...Fin-like structure 220...Laminated structure 16...Second fin 120,2200...gate metal layer 122...Sacrificial layer 13,2202...First gate insulating layer 14,2204...Channel layer 15...protective layer 17...Inner separation layer 222...Inner spacer 18...Dielectric layer 19,224...Second gate insulating layer G1, G1'...first gate member D1, D1'...Drain member D2, D2'...Source material G21, G21'...Gate connecting members G22, G22'...Second gate member S1, S1'...Source material A1...first area A2...Second Area A21...Inner area A22...outer area DR1...first direction DR2...Second direction DN...vertical direction R1...first recess R2...Second recess S10~S20,S140,S141...process CS1, CS2...section line Ar...surplus area

Claims

1. forming a first fin over a substrate, the first fin including a plurality of gate metal layers and a plurality of sacrificial layers stacked in alternating order; partially removing the plurality of sacrificial layers from the first fin; forming a first gate insulating layer, a channel layer, and a protection layer in this order on the exposed portions of each of the gate metal layers; patterning the first fin, each of the first gate insulating layers, each of the channel layers, and each of the protection layers to form a second fin; patterning the second fin to form a plurality of first recesses on a first side and a second side and a plurality of second recesses on a third side and a fourth side; forming a plurality of inner isolation layers filling the plurality of first recesses and the plurality of second recesses; forming a first gate member electrically connected to the plurality of gate metal layers on the first side, and forming a drain member and a source member electrically connected to each of the channel layers on the third side and the fourth side, respectively; removing a portion of the plurality of internal isolation layers and each of the protection layers from the second side to expose each of the gate metal layers, each of the first gate insulating layers, each of the channel layers, and each of the internal isolation layers that is not removed; forming a second gate insulating layer, a plurality of gate connection members, and a second gate member in this order on the exposed gate metal layers, the exposed first gate insulating layers, the exposed channel layers, and the exposed inner isolation layers.

2. 2. The method of claim 1, wherein the first fin extends in a vertical direction while covering a first region of the substrate, and the first gate member, the second gate member, the drain member, and the source member extend along the vertical direction.

3. 2. The method of claim 1, wherein partially removing the plurality of sacrificial layers from the first fin comprises removing portions of the plurality of sacrificial layers from the first fin that overlap with a first region of the substrate to expose portions of the plurality of gate metal layers.

4. The step of patterning the first fin, the first gate insulating layer, the channel layer, and the protection layer to form the second fin includes:

2. The method for manufacturing a split double-gate transistor of claim 1, further comprising removing portions of the first fin, the gate insulating layer, the channel layer, and the protection layer that do not overlap with the second region of the substrate to form the second fin in the second region of the substrate, wherein the first region and the second region of the substrate partially overlap.

5. The step of patterning the second fin to form the plurality of first recesses and the plurality of second recesses includes: removing a portion of the gate insulating layer, a portion of the channel layer, and a portion of the protection layer from the second fin along a first direction to recess the gate insulating layer, the channel layer, and the protection layer relative to the plurality of gate metal layers to form the plurality of first recesses; and removing another portion of the protective layer from the second fin along a second direction to recess the protective layer relative to the plurality of gate metal layers, the gate insulating layer, and the channel layer to form the plurality of second recesses.

6. The method for fabricating a split double-gate transistor according to claim 5 , wherein the first direction and the second direction are both perpendicular to a vertical direction.

7. forming a dielectric layer after forming the first gate member, the drain member, and the source member to cover the first gate member, the drain member, the source member, and the plurality of inner isolation layers on the first side of the second fin; partially removing the dielectric layer, the protective layer, the inner isolation layer, the first gate member, the drain member, and the source member in a vertical direction by a polishing process; and removing the plurality of inner isolation layers, the portions of the dielectric layer located on the second side, the protective layer, portions of the drain member, and portions of the source member by an etching process.

8. 3. The method of claim 2, wherein the first gate member is electrically connected to the plurality of gate metal layers at a plurality of positions in the vertical direction, respectively.

9. 9. The method for manufacturing a split double-gate transistor according to claim 8, wherein the channel layer and the first gate insulating layer are provided between each of the gate metal layers and the drain member or the source member.

10. 2. The method for manufacturing a split double-gate transistor according to claim 1, wherein the first gate insulating layer, the channel layer, the second gate insulating layer, the second gate member, the second gate insulating layer, the channel layer, and the first gate insulating layer are arranged in this order between two adjacent gate metal layers.

11. A substrate; a fin structure disposed on the substrate; a first gate member; a drain member and a source member; a second gate member; The fin-like structure is a plurality of vertically spaced stacked structures, each including a gate metal layer, a first gate insulating layer, and a channel layer; a plurality of gate connection members disposed alternately with the plurality of stacked structures along the vertical direction, each extending along a first direction; a plurality of inner spacers spaced apart along the vertical direction, each spacer surrounding the plurality of gate connection members and contacting each of the first gate insulating layers and the channel layer; a second gate insulating layer disposed between the inner spacers and the gate connecting members, and between the gate connecting members and the stacked structures; the first gate member is disposed on a first side of the fin-like structure and is electrically connected to each of the gate metal layers; the drain member and the source member are respectively disposed on a third side and a fourth side of the fin-shaped structure facing each other along the second direction, the drain member is electrically connected to a drain region of each of the channel layers, and the source member is electrically connected to a source region of each of the channel layers; the second gate member is disposed on a second side of the fin-like structure and is electrically connected to the gate connection member;

12. 12. The split double-gate transistor of claim 11, wherein the first gate member, the second gate member, the drain member, and the source member extend along the vertical direction.

13. 13. The split double-gate transistor of claim 12, wherein the first gate insulating layer, the channel layer, and the protection layer are recessed relative to the plurality of gate metal layers in the first direction.

14. The split double-gate transistor of claim 11 , wherein the first direction, the second direction, and the vertical direction are perpendicular to each other.

15. 12. The split double-gate transistor of claim 11, wherein the first gate member is electrically connected to the plurality of gate metal layers at a plurality of positions in the vertical direction, respectively.

16. 12. The split double-gate transistor of claim 11, wherein the channel layer and the first gate insulating layer are disposed between each of the gate metal layers and the drain member or the source member.

17. 12. The split double-gate transistor according to claim 11, wherein the first gate insulating layer, the channel layer, the second gate insulating layer, the second gate member, the second gate insulating layer, the channel layer, and the first gate insulating layer are arranged in this order between two adjacent gate metal layers.

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