Pixel circuit and display device including the same

Abstract

An object of the present invention is to provide a pixel circuit for low area and high PPI.SOLUTION: The pixel circuit includes: a first transistor including a first gate electrode connected to a first node, a first electrode receiving the first power supply voltage, a second electrode connected to a second node, and a second gate electrode connected to a third node; a second transistor connecting a data line to the first node in response to a data write gate signal; and a second transistor connected to the first node in response to a compensation gate signal. And a light emitting element including a third transistor configured to provide a reference voltage to the third node, a first capacitor including a first electrode connected to the first node and a second electrode connected to the second node, a second capacitor including a first electrode connected to the second node and a second electrode connected to the third node, an anode electrode connected to the second node, and a cathode electrode configured to receive a second power supply voltage.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a pixel circuit and a display device including the pixel circuit. [Background technology]

[0002] In general, a display device includes a display panel and a display panel driver. The display panel includes gate lines, data lines, and pixel circuits. The display panel driver includes a gate driver that provides gate signals to the gate lines, a data driver that provides data voltages to the data lines, and a driver controller that controls the gate driver and the data driver.

[0003] Recently, display devices that provide virtual reality (VR) or augmented reality (AR) have become popular. To achieve this, the display devices are required to have a small area and high pixels per inch (PPI). In this case, the pitch occupied by pixel circuits becomes narrow, which imposes restrictions on the number of transistors constituting the pixel circuits and the signals applied to the pixel circuits. Summary of the Invention [Problem to be solved by the invention]

[0004] An object of the present invention is to provide a pixel circuit for low area and high PPI.

[0005] Another object of the present invention is to provide a display device including the pixel circuit. [Means for solving the problem]

[0006] In order to achieve the object of the present invention, a pixel circuit according to the present invention is characterized by including: a first transistor including a first gate electrode connected to a first node, a first electrode for receiving a first power supply voltage, a second electrode connected to a second node, and a second gate electrode connected to a third node; a second transistor for connecting a data line and the first node in response to a data write gate signal; a third transistor for providing a reference voltage to the third node in response to a compensation gate signal; a first capacitor including a first electrode connected to the first node and a second electrode connected to the second node; a second capacitor including a first electrode connected to the second node and a second electrode connected to the third node; and a light-emitting element including an anode electrode connected to the second node and a cathode electrode for receiving a second power supply voltage.

[0007] The first to third transistors are NMOS transistors.

[0008] The second transistor includes a gate electrode that receives the data write gate signal, a first electrode that is connected to the data line, and a second electrode that is connected to the first node.

[0009] The third transistor includes a gate electrode that receives the compensation gate signal, a first electrode that receives the reference voltage, and a second electrode that is coupled to the third node.

[0010] The first gate electrode of the first transistor is a gate electrode, and the second gate electrode of the first transistor is a back gate electrode.

[0011] The first gate electrode of the first transistor is a back gate electrode, and the second gate electrode of the first transistor is a gate electrode.

[0012] The pixel circuit further includes a fourth transistor that connects the first node and the second node in response to a second compensation gate signal.

[0013] The fourth transistor includes a gate electrode that receives the second compensation gate signal, a first electrode that is coupled to the first node, and a second electrode that is coupled to the second node.

[0014] The pixel circuit further includes a fifth transistor responsive to an initialization gate signal to provide an initialization voltage to the second node.

[0015] The fifth transistor includes a gate electrode that receives the initialization gate signal, a first electrode that receives the initialization voltage, and a second electrode that is coupled to the second node.

[0016] In order to achieve the object of the present invention, a pixel circuit according to the present invention includes: a first transistor including a first gate electrode connected to a first node, a first electrode for receiving a first power supply voltage, a second electrode connected to a second node, and a second gate electrode connected to the second node; a first capacitor including a first electrode connected to the first node and a second electrode connected to a third node; a second transistor connecting a data line and the third node in response to a data write gate signal; a third transistor providing a reference voltage to the first node in response to a compensation gate signal; a fourth transistor connecting the second node and the third node in response to the compensation gate signal; a second capacitor including a first electrode connected to the second node and a second electrode connected to the third node; and a light-emitting element including an anode electrode connected to the second node and a cathode electrode for receiving a second power supply voltage.

[0017] The first to fourth transistors are NMOS transistors.

[0018] The second transistor includes a gate electrode that receives the data write gate signal, a first electrode that is connected to the data line, and a second electrode that is connected to the third node.

[0019] The third transistor includes a gate electrode that receives the compensation gate signal, a first electrode that receives the reference voltage, and a second electrode that is coupled to the first node.

[0020] The fourth transistor includes a gate electrode that receives the compensation gate signal, a first electrode that is coupled to the second node, and a second electrode that is coupled to the third node.

[0021] In order to achieve another object of the present invention, a display device according to the present invention includes a display panel including a pixel circuit; a gate driver for providing a gate signal to the pixel circuit; a data driver for providing a data voltage to the pixel circuit; and a drive controller for controlling the gate driver and the data driver, wherein the pixel circuit includes: a first transistor including a first gate electrode connected to a first node, a first electrode for receiving a first power supply voltage, a second electrode connected to a second node, and a second gate electrode connected to a third node; a second transistor for connecting a data line to the first node in response to a data write gate signal; a third transistor for providing a reference voltage to the third node in response to a compensation gate signal; a first capacitor including a first electrode connected to the first node and a second electrode connected to the second node; a second capacitor including a first electrode connected to the second node and a second electrode connected to the third node; and a light emitting element including an anode electrode connected to the second node and a cathode electrode for receiving a second power supply voltage.

[0022] The first to third transistors are NMOS transistors.

[0023] The second transistor includes a gate electrode that receives the data write gate signal, a first electrode that is connected to the data line, and a second electrode that is connected to the first node.

[0024] The third transistor includes a gate electrode that receives the compensation gate signal, a first electrode that receives the reference voltage, and a second electrode that is coupled to the third node.

[0025] The first gate electrode of the first transistor is a gate electrode, and the second gate electrode of the first transistor is a back gate electrode. [Effects of the Invention]

[0026] In the pixel circuit and the display device including the pixel circuit according to the present invention, the pixel circuit includes a small number of transistors and capacitors, which allows the pixel circuit to have a small area and a high PPI.

[0027] However, the effects of the present invention are not limited to the effects mentioned above, and can be expanded in various ways without departing from the spirit and scope of the present invention. [Brief explanation of the drawings]

[0028] [Figure 1] FIG. 1 is a block diagram showing a display device according to an embodiment of the present invention. [Figure 2] FIG. 2 is a circuit diagram showing an example of a pixel circuit in FIG. [Figure 3] FIG. 3 is a timing chart showing an example of the operation of the pixel circuit in FIG. [Figure 4] FIG. 4 is a circuit diagram showing an example in which the pixel circuit of FIG. 2 operates in the first section of FIG. [Figure 5] FIG. 5 is a circuit diagram showing an example in which the pixel circuit of FIG. 2 operates in the second interval of FIG. [Figure 6] FIG. 6 is a circuit diagram showing an example in which the pixel circuit of FIG. 2 operates in the third interval of FIG. [Figure 7] FIG. 7 is a circuit diagram showing an example in which the pixel circuit of FIG. 2 operates in the fourth interval of FIG. [Figure 8] FIG. 8 is a circuit diagram showing an example of the pixel circuit of FIG. [Figure 9] FIG. 9 is a circuit diagram showing an example of the pixel circuit of FIG. [Figure 10] FIG. 10 is a timing chart showing an example of the operation of the pixel circuit of FIG. [Figure 11] FIG. 11 is a circuit diagram showing an example in which the pixel circuit of FIG. 9 operates in the first interval of FIG. [Figure 12] FIG. 12 is a circuit diagram showing an example in which the pixel circuit of FIG. 9 operates in the second interval of FIG. [Figure 13] FIG. 13 is a circuit diagram showing an example in which the pixel circuit of FIG. 9 operates in the third interval of FIG. [Figure 14] FIG. 14 is a circuit diagram showing an example in which the pixel circuit of FIG. 9 operates in the fourth interval of FIG. [Figure 15] FIG. 15 is a circuit diagram showing an example of the pixel circuit of FIG. [Figure 16] FIG. 16 is a timing chart showing an example of the operation of the pixel circuit of FIG. [Figure 17] FIG. 17 is a circuit diagram showing an example in which the pixel circuit of FIG. 15 operates in the first interval of FIG. [Figure 18] FIG. 18 is a circuit diagram showing an example in which the pixel circuit of FIG. 15 operates in the second interval of FIG. [Figure 19] FIG. 19 is a circuit diagram showing an example in which the pixel circuit of FIG. 15 operates in the third interval of FIG. [Figure 20] FIG. 20 is a circuit diagram showing an example in which the pixel circuit of FIG. 15 operates in the fourth interval of FIG. [Figure 21] FIG. 21 is a circuit diagram showing an example of the pixel circuit of FIG. [Figure 22] FIG. 22 is a timing chart showing an example of the operation of the pixel circuit of FIG. [Figure 23] FIG. 23 is a circuit diagram showing an example in which the pixel circuit of FIG. 21 operates in the first interval of FIG. [Figure 24] FIG. 24 is a circuit diagram showing an example in which the pixel circuit of FIG. 21 operates in the second interval of FIG. [Figure 25]FIG. 25 is a circuit diagram showing an example in which the pixel circuit of FIG. 21 operates in the third interval of FIG. [Figure 26] FIG. 26 is a circuit diagram showing an example in which the pixel circuit of FIG. 21 operates in the fourth interval of FIG. [Figure 27] FIG. 27 is a block diagram illustrating an electronic device according to an embodiment of the present invention. [Figure 28] FIG. 28 is a diagram illustrating an example in which the electronic device of FIG. 27 is implemented as a VR device. [Figure 29] FIG. 29 is a block diagram illustrating an electronic device according to an embodiment of the present invention. [Figure 30] FIG. 30 is a schematic diagram of the electronic device of FIG. DETAILED DESCRIPTION OF THE INVENTION

[0029] The present invention will now be described in more detail with reference to the accompanying drawings.

[0030] FIG. 1 is a block diagram showing a display device according to an embodiment of the present invention.

[0031] 1, the display device includes a display panel 100 and a display panel driver. The display panel driver includes a drive controller 200, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0032] For example, the drive control unit 200 and the data driver 500 are integrally formed. For example, the drive control unit 200, the gamma reference voltage generator 400, and the data driver 500 are integrally formed. For example, the drive control unit 200, the gate driver 300, the gamma reference voltage generator 400, and the data driver 500 are integrally formed. Meanwhile, a driver module in which at least the drive control unit 200 and the data driver 500 are integrally formed is called a timing controller embedded data driver (TED).

[0033] The display panel 100 includes a display section for displaying an image and a peripheral section disposed adjacent to the display section.

[0034] For example, the display panel 100 may be an organic light-emitting diode display panel including organic light-emitting diodes, a quantum dot organic light-emitting diode display panel including organic light-emitting diodes and quantum dot color filters, a quantum dot nano light-emitting diode display panel including nano light-emitting diodes and quantum dot color filters, or a liquid crystal display panel including a liquid crystal layer.

[0035] The display panel 100 includes gate lines GL, data lines DL, and pixel circuits PX electrically connected to the gate lines GL and the data lines DL. The gate lines GL extend in a first direction, and the data lines DL extend in a second direction intersecting the first direction.

[0036] The drive control unit 200 receives input image data IMG and an input control signal CONT from an external device. For example, the input image data IMG includes red image data, green image data, and blue image data. According to an embodiment, the input image data IMG may further include white image data. For example, the input image data IMG includes magenta image data, yellow image data, and cyan image data. The input control signal CONT includes a master clock signal and a data enable signal. The input control signal CONT further includes a vertical synchronization signal and a horizontal synchronization signal.

[0037] The drive control unit 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0038] The driving control unit 200 generates the first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT and outputs the first control signal CONT1 to the gate driver 300. The first control signal CONT1 includes a vertical start signal and a gate clock signal.

[0039] The driving control unit 200 generates the second control signal CONT2 for controlling the operation of the data driver 500 based on the input control signal CONT and outputs the second control signal CONT2 to the data driver 500. The second control signal CONT2 includes a horizontal start signal and a load signal.

[0040] The driving control unit 200 generates the data signal DATA based on the input image data IMG and outputs the data signal DATA to the data driver 500.

[0041] The driving control unit 200 generates the third control signal CONT3 for controlling the operation of the gamma reference voltage generating unit 400 based on the input control signal CONT, and outputs the third control signal CONT3 to the gamma reference voltage generating unit 400.

[0042] The gate driver 300 generates gate signals for driving the gate lines GL in response to the first control signal CONT1 input from the driving controller 200. The gate driver 300 outputs the gate signals to the gate lines GL.

[0043] In one embodiment, the gate driver 300 is integrated on the periphery of the display panel 100 .

[0044] The gamma reference voltage generator 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 input from the driving control unit 200. The gamma reference voltage generator 400 provides the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF has a value corresponding to each of the data signals DATA.

[0045] In one embodiment, the gamma reference voltage generator 400 is disposed in the driving control unit 200 or the data driver 500 .

[0046] The data driver 500 receives the second control signal CONT2 and the data signal DATA from the drive control unit 200 and the gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 converts the data signal DATA and the gamma reference voltage VGREF into an analog data voltage VDATA. The data driver 500 outputs the data voltage VDATA to the data line DL.

[0047] FIG. 2 is a circuit diagram showing an example PXa of the pixel circuit PX in FIG.

[0048] 2, the pixel circuit PXa includes a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1, a second capacitor C2, and a light-emitting element EL. In one embodiment, the first to third transistors T1 to T3 are NMOS transistors. In another embodiment, the first transistor T1 is the NMOS transistor, and the second and third transistors T2 to T3 are PMOS transistors.

[0049] The NMOS transistor is turned on in response to a gate signal having a high level and turned off in response to a gate signal having a low level, and the PMOS transistor is turned on in response to a gate signal having the low level and turned off in response to a gate signal having the high level.

[0050] The first transistor T1 includes a first gate electrode connected to a first node N1, a first electrode receiving a first power supply voltage ELVDD, a second electrode connected to a second node N2, and a second gate electrode connected to a third node N3. In one embodiment, the first gate electrode of the first transistor T1 is a gate electrode, and the second gate electrode of the first transistor T1 is a back gate electrode. The first transistor T1 generates a driving current based on the voltage of the first node N1 and the voltage of the second node N2, and provides the driving current to the light-emitting element EL.

[0051] The second transistor T2 connects a data line DL and the first node N1 in response to a data write gate signal GW[N]. The data line DL transmits a reference voltage VREF or a data voltage VDATA. The second transistor T2 includes a gate electrode that receives the data write gate signal GW[N], a first electrode connected to the data line DL, and a second electrode connected to the first node N1.

[0052] The third transistor T3 provides the reference voltage VREF to the third node N3 in response to a compensation gate signal GC. The third transistor T3 includes a gate electrode receiving the compensation gate signal GC, a first electrode receiving the reference voltage VREF, and a second electrode connected to the third node N3. However, the present invention is not limited thereto. In another embodiment, the reference voltage VREF received by the first electrode of the third transistor T3 is different from the reference voltage VREF transmitted by the data line DL.

[0053] The first capacitor C1 includes a first electrode connected to the first node N1 and a second electrode connected to the second node N2.

[0054] The second capacitor C2 includes a first electrode connected to the second node N2 and a second electrode connected to the third node N3.

[0055] Thus, the pixel circuit PXa includes three transistors T1, T2, T3 and two capacitors C1, C2, which allows the pixel circuit PXa to have a small area and a high PPI.

[0056] Fig. 3 is a timing diagram showing an example of operation of the pixel circuit PXa of Fig. 2. Fig. 4 is a circuit diagram showing an example of operation of the pixel circuit PXa of Fig. 2 in the first interval DU1 of Fig. 3. Fig. 5 is a circuit diagram showing an example of operation of the pixel circuit PXa of Fig. 2 in the second interval DU2 of Fig. 3. Fig. 6 is a circuit diagram showing an example of operation of the pixel circuit PXa of Fig. 2 in the third interval DU3 of Fig. 3. Fig. 7 is a circuit diagram showing an example of operation of the pixel circuit PXa of Fig. 2 in the fourth interval DU4 of Fig. 3.

[0057] 3 and 4, in the first period DU1, the first power supply voltage ELVDD has the low level L, the second power supply voltage ELVSS has the high level H, the compensation gate signal GC has the high level H, the data write gate signal GW[N] has the high level H, and the data line DL transmits the reference voltage VREF. The first power supply voltage ELVDD, the second power supply voltage ELVSS, the compensation gate signal GC, and the data write gate signal GW[N] may be simultaneously applied to the pixel circuit PXa.

[0058] The second transistor T2 is turned on in response to the data write gate signal GW[N] having the high level H, and connects the data line DL transmitting the reference voltage VREF to the first node N1. Therefore, the second transistor T2 provides the reference voltage VREF to the first node N1, and the voltage of the first node N1 has the reference voltage VREF.

[0059] The third transistor T3 is turned on in response to the compensation gate signal GC having the high level H to provide the reference voltage VREF to the third node N3, so that the voltage of the third node N3 has the reference voltage VREF.

[0060] Since the voltage at the first node N1 has the reference voltage VREF and the voltage at the third node N3 has the reference voltage VREF, the voltage at the second node N2 can have the reference voltage VREF.

[0061] As described above, in the first period DU1, the voltage of the first node N1 and the voltage of the second node N2 are initialized to the reference voltage VREF, and therefore the first period DU1 is referred to as an initialization period.

[0062] 3 and 5, in the second interval DU2, the first power supply voltage ELVDD has the high level H, the second power supply voltage ELVSS has the high level H, the compensation gate signal GC has the high level H, the data write gate signal GW[N] has the high level H, and the data line DL transmits the reference voltage VREF. The first power supply voltage ELVDD, the second power supply voltage ELVSS, the compensation gate signal GC, and the data write gate signal GW[N] may be simultaneously applied to the pixel circuit PXa.

[0063] The second transistor T2 is turned on in response to the data write gate signal GW[N] having the high level H, and connects the data line DL transmitting the reference voltage VREF to the first node N1. Therefore, the second transistor T2 provides the reference voltage VREF to the first node N1, and the voltage of the first node N1 has the reference voltage VREF.

[0064] The third transistor T3 is turned on in response to the compensation gate signal GC having the high level H to provide the reference voltage VREF to the third node N3, so that the voltage of the third node N3 has the reference voltage VREF.

[0065] When the first power supply voltage ELVDD changes from the low level L to the high level H, the first transistor T1 is turned on. As a result, the voltage of the second node N2 can be changed from the reference voltage VREF to a value obtained by subtracting the threshold voltage of the first transistor T1 from the reference voltage VREF. As a result, the first capacitor C1 and the second capacitor C2 can store the threshold voltage of the first transistor T1, and the threshold voltage of the first transistor T1 is compensated.

[0066] In this way, the threshold voltage of the first transistor T1 is compensated in the second section DU2, and therefore the second section DU2 is referred to as a compensation section.

[0067] 3 and 6, in the third interval DU3, the first power supply voltage ELVDD has the low level L, the second power supply voltage ELVSS has the high level H, the compensation gate signal GC has the low level L, the data write gate signal GW[N] has the high level H, and the data line DL transmits the data voltage VDATA. The first power supply voltage ELVDD, the second power supply voltage ELVSS, and the compensation gate signal GC are simultaneously applied to the pixel circuit PXa, and the data write gate signal GW[N] is sequentially applied to the pixel circuit PXa.

[0068] The second transistor T2 is turned on in response to the data write gate signal GW[N] having the high level H to connect the data line DL transmitting the data voltage VDATA to the first node N1, so that the second transistor T2 provides the data voltage VDATA to the first node N1, and the voltage of the first node N1 has the data voltage VDATA.

[0069] In this manner, the data voltage VDATA is applied to the pixel circuit PXa in the third interval DU3, and therefore the third interval DU3 is referred to as a data writing interval.

[0070] 3 and 7, in the fourth interval DU4, the first power supply voltage ELVDD has the high level H, the second power supply voltage ELVSS has the low level L, the compensation gate signal GC has the low level L, the data write gate signal GW[N] has the low level L, and the data line DL transmits the reference voltage VREF. The first power supply voltage ELVDD, the second power supply voltage ELVSS, the compensation gate signal GC, and the data write gate signal GW[N] may be simultaneously applied to the pixel circuit PXa.

[0071] The first power supply voltage ELVDD has the high level H, and the second power supply voltage ELVSS has the low level L, so that the first transistor T1 can generate the driving current based on the voltage of the first node N1 and the voltage of the second node N2 and provide it to the light-emitting element EL. The light-emitting element EL can emit light based on the driving current. The luminance of the light-emitting element EL is determined based on the strength of the driving current, and the strength of the driving current is determined based on the level of the data voltage VDATA. That is, the luminance of the light-emitting element EL is determined based on the level of the data voltage VDATA.

[0072] In this manner, the light emitting element EL emits light in the fourth section DU4, and therefore the fourth section DU4 is referred to as a light emitting section.

[0073] Figure 8 is a circuit diagram showing an example PXb of the pixel circuit PX of Figure 1. The pixel circuit PXb of Figure 8 is substantially the same as the pixel circuit PXa of Figure 2, except for the first transistor T1. Therefore, the same reference numerals are used for the same or similar components, and redundant explanations will be omitted.

[0074] 1 and 8, the pixel circuit PXb includes a first transistor T1, a second transistor T2, a third transistor T3, a first capacitor C1, a second capacitor C2, and a light-emitting element EL. In one embodiment, the first to third transistors T1 to T3 are NMOS transistors. In another embodiment, the first transistor T1 is the NMOS transistor, and the second and third transistors T2 to T3 are PMOS transistors.

[0075] The NMOS transistor is turned on in response to a gate signal having a high level and turned off in response to a gate signal having a low level, and the PMOS transistor is turned on in response to a gate signal having the low level and turned off in response to a gate signal having the high level.

[0076] The first transistor T1 includes a first gate electrode connected to a first node N1, a first electrode receiving a first power supply voltage ELVDD, a second electrode connected to a second node N2, and a second gate electrode connected to a third node N3. In one embodiment, the first gate electrode of the first transistor T1 is a back gate electrode, and the second gate electrode of the first transistor T1 is a gate electrode. The first transistor T1 generates a driving current based on the voltage of the second node N2 and the voltage of the third node N3, and provides the driving current to the light-emitting element EL.

[0077] The second transistor T2 connects a data line DL and the first node N1 in response to a data write gate signal GW[N]. The data line DL transmits a reference voltage VREF or a data voltage VDATA. The second transistor T2 includes a gate electrode that receives the data write gate signal GW[N], a first electrode connected to the data line DL, and a second electrode connected to the first node N1.

[0078] The third transistor T3 provides the reference voltage VREF to the third node N3 in response to a compensation gate signal GC. The third transistor T3 includes a gate electrode receiving the compensation gate signal GC, a first electrode receiving the reference voltage VREF, and a second electrode connected to the third node N3. However, the present invention is not limited thereto. In another embodiment, the reference voltage VREF received by the first electrode of the third transistor T3 is different from the reference voltage VREF transmitted by the data line DL.

[0079] The first capacitor C1 includes a first electrode connected to the first node N1 and a second electrode connected to the second node N2.

[0080] The second capacitor C2 includes a first electrode connected to the second node N2 and a second electrode connected to the third node N3.

[0081] Thus, the pixel circuit PXb includes three transistors T1, T2, T3 and two capacitors C1, C2, which allows the pixel circuit PXb to have a small area and a high PPI.

[0082] FIG. 9 is a circuit diagram showing an example PXc of the pixel circuit PX in FIG.

[0083] The pixel circuit PXc in Fig. 9 is substantially the same as the pixel circuit PXa in Fig. 2 except for the fourth transistor T4. Therefore, the same or similar components are denoted by the same reference numerals, and redundant explanations will be omitted.

[0084] 1 and 9, the pixel circuit PXc includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor C1, a second capacitor C2, and a light-emitting element EL. In one embodiment, the first to fourth transistors T1 to T4 are NMOS transistors. In another embodiment, the first transistor T1 is the NMOS transistor, and the second to fourth transistors T2 to T4 are PMOS transistors.

[0085] The NMOS transistor is turned on in response to a gate signal having a high level and turned off in response to a gate signal having a low level, and the PMOS transistor is turned on in response to a gate signal having the low level and turned off in response to a gate signal having the high level.

[0086] The first transistor T1 includes a first gate electrode connected to a first node N1, a first electrode receiving a first power supply voltage ELVDD, a second electrode connected to a second node N2, and a second gate electrode connected to a third node N3. In one embodiment, the first gate electrode of the first transistor T1 is a gate electrode, and the second gate electrode of the first transistor T1 is a back gate electrode. The first transistor T1 generates a driving current based on the voltage of the first node N1 and the voltage of the second node N2, and provides the driving current to the light-emitting element EL.

[0087] The second transistor T2 connects a data line DL and the first node N1 in response to a data write gate signal GW[N]. The data line DL transmits a reference voltage VREF or a data voltage VDATA. The second transistor T2 includes a gate electrode that receives the data write gate signal GW[N], a first electrode connected to the data line DL, and a second electrode connected to the first node N1.

[0088] The third transistor T3 provides the reference voltage VREF to the third node N3 in response to a compensation gate signal GC. The third transistor T3 includes a gate electrode receiving the compensation gate signal GC, a first electrode receiving the reference voltage VREF, and a second electrode connected to the third node N3. However, the present invention is not limited thereto. In another embodiment, the reference voltage VREF received by the first electrode of the third transistor T3 is different from the reference voltage VREF transmitted by the data line DL.

[0089] The fourth transistor T4 connects the first node N1 and the second node N2 in response to a second compensation gate signal GC2, so that the voltage at the first node N1 is the same as the voltage at the second node N2. The fourth transistor T4 includes a gate electrode receiving the second compensation gate signal GC2, a first electrode connected to the first node N1, and a second electrode connected to the second node N2.

[0090] The first capacitor C1 includes a first electrode connected to the first node N1 and a second electrode connected to the second node N2.

[0091] The second capacitor C2 includes a first electrode connected to the second node N2 and a second electrode connected to the third node N3.

[0092] Thus, the pixel circuit PXc includes four transistors T1, T2, T3, and T4 and two capacitors C1 and C2, which allows the pixel circuit PXc to have a small area and a high PPI.

[0093] Fig. 10 is a timing diagram showing an example of operation of the pixel circuit PXc of Fig. 9. Fig. 11 is a circuit diagram showing an example of operation of the pixel circuit PXc of Fig. 9 in the first interval DU1 of Fig. 10. Fig. 12 is a circuit diagram showing an example of operation of the pixel circuit PXc of Fig. 9 in the second interval DU2 of Fig. 10. Fig. 13 is a circuit diagram showing an example of operation of the pixel circuit PXc of Fig. 9 in the third interval DU3 of Fig. 10. Fig. 14 is a circuit diagram showing an example of operation of the pixel circuit PXc of Fig. 9 in the fourth interval DU4 of Fig. 10.

[0094] 10 and 11, in a first interval DU1, the first power supply voltage ELVDD has the low level L, the second power supply voltage ELVSS has the high level H, the compensation gate signal GC has the high level H, the second compensation gate signal GC2 has the low level L, the data write gate signal GW[N] has the high level H, and the data line DL transmits the reference voltage VREF. The first power supply voltage ELVDD, the second power supply voltage ELVSS, the compensation gate signal GC, the second compensation gate signal GC2, and the data write gate signal GW[N] may be simultaneously applied to the pixel circuit PXc.

[0095] The second transistor T2 is turned on in response to the data write gate signal GW[N] having the high level H, and connects the data line DL transmitting the reference voltage VREF to the first node N1. Therefore, the second transistor T2 provides the reference voltage VREF to the first node N1, and the voltage of the first node N1 has the reference voltage VREF.

[0096] The third transistor T3 is turned on in response to the compensation gate signal GC having the high level H to provide the reference voltage VREF to the third node N3, so that the voltage of the third node N3 has the reference voltage VREF.

[0097] Since the voltage at the first node N1 has the reference voltage VREF and the voltage at the third node N3 has the reference voltage VREF, the voltage at the second node N2 has the reference voltage VREF.

[0098] In this manner, in the first period DU1, the voltage of the first node N1 and the voltage of the second node N2 are initialized to the reference voltage VREF, and therefore the first period DU1 is referred to as an initialization period.

[0099] 10 and 12, in the second interval DU2, the first power supply voltage ELVDD has the high level H, the second power supply voltage ELVSS has the high level H, the compensation gate signal GC has the high level H, the second compensation gate signal GC2 has the high level H, the data write gate signal GW[N] has the low level L, and the data line DL transmits the reference voltage VREF. The first power supply voltage ELVDD, the second power supply voltage ELVSS, the compensation gate signal GC, the second compensation gate signal GC2, and the data write gate signal GW[N] may be simultaneously applied to the pixel circuit PXc.

[0100] The third transistor T3 is turned on in response to the compensation gate signal GC having the high level H to provide the reference voltage VREF to the third node N3, so that the voltage of the third node N3 has the reference voltage VREF.

[0101] When the first power supply voltage ELVDD is changed from the low level L to the high level H, the fourth transistor T4 is turned on in response to the second compensation gate signal GC2 having the high level H, and the first transistor T1 is turned on. As a result, the first transistor T1 is diode-connected and the threshold voltage of the first transistor T1 is compensated.

[0102] In this way, the threshold voltage of the first transistor T1 is compensated in the second section DU2, and therefore the second section DU2 is referred to as a compensation section.

[0103] 10 and 13, in the third interval DU3, the first power supply voltage ELVDD has the low level L, the second power supply voltage ELVSS has the high level H, the compensation gate signal GC has the low level L, the second compensation gate signal GC2 has the low level L, the data write gate signal GW[N] has the high level H, and the data line DL transmits the data voltage VDATA. The first power supply voltage ELVDD, the second power supply voltage ELVSS, the compensation gate signal GC, and the second compensation gate signal GC2 are simultaneously applied to the pixel circuit PXc, and the data write gate signal GW[N] is sequentially applied to the pixel circuit PXc.

[0104] The second transistor T2 is turned on in response to the data write gate signal GW[N] having the high level H to connect the data line DL transmitting the data voltage VDATA to the first node N1, so that the second transistor T2 provides the data voltage VDATA to the first node N1, and the voltage of the first node N1 has the data voltage VDATA.

[0105] In this manner, the data voltage VDATA is applied to the pixel circuit PXc in the third interval DU3, and therefore the third interval DU3 is referred to as a data write interval.

[0106] 10 and 14, in a fourth interval DU4, the first power supply voltage ELVDD has the high level H, the second power supply voltage ELVSS has the low level L, the compensation gate signal GC has the low level L, the second compensation gate signal GC2 has the low level L, the data write gate signal GW[N] has the low level L, and the data line DL transmits the reference voltage VREF. The first power supply voltage ELVDD, the second power supply voltage ELVSS, the compensation gate signal GC, the second compensation gate signal GC2, and the data write gate signal GW[N] may be simultaneously applied to the pixel circuit PXc.

[0107] The first power supply voltage ELVDD has the high level H, and the second power supply voltage ELVSS has the low level L, so that the first transistor T1 can generate the driving current based on the voltage of the first node N1 and the voltage of the second node N2 and provide it to the light-emitting element EL. The light-emitting element EL can emit light based on the driving current. The luminance of the light-emitting element EL is determined based on the strength of the driving current, and the strength of the driving current is determined based on the level of the data voltage VDATA. That is, the luminance of the light-emitting element EL is determined based on the level of the data voltage VDATA.

[0108] In this manner, the light emitting element EL emits light in the fourth section DU4, and therefore the fourth section DU4 is referred to as a light emitting section.

[0109] Fig. 15 is a circuit diagram showing an example PXd of the pixel circuit PX of Fig. 1. Except for the fifth transistor T5, the pixel circuit PXd of Fig. 15 is substantially the same as the pixel circuit PXc of Fig. 9. Therefore, the same reference numerals are used for the same or similar components, and redundant explanations will be omitted.

[0110] 1 and 15, the pixel circuit PXd includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a first capacitor C1, a second capacitor C2, and a light-emitting element EL. In one embodiment, the first to fifth transistors T1 to T5 are NMOS transistors. In another embodiment, the first transistor T1 is the NMOS transistor, and the second to fifth transistors T2 to T5 are PMOS transistors.

[0111] The NMOS transistor is turned on in response to a gate signal having a high level and turned off in response to a gate signal having a low level, and the PMOS transistor is turned on in response to a gate signal having the low level and turned off in response to a gate signal having the high level.

[0112] The first transistor T1 includes a first gate electrode connected to a first node N1, a first electrode receiving a first power supply voltage ELVDD, a second electrode connected to a second node N2, and a second gate electrode connected to a third node N3. In one embodiment, the first gate electrode of the first transistor T1 is a gate electrode, and the second gate electrode of the first transistor T1 is a back gate electrode. The first transistor T1 generates a driving current based on the voltage of the first node N1 and the voltage of the second node N2, and provides the driving current to the light-emitting element EL.

[0113] The second transistor T2 connects a data line DL and the first node N1 in response to a data write gate signal GW[N]. The data line DL transmits a reference voltage VREF or a data voltage VDATA. The second transistor T2 includes a gate electrode that receives the data write gate signal GW[N], a first electrode connected to the data line DL, and a second electrode connected to the first node N1.

[0114] The third transistor T3 provides the reference voltage VREF to the third node N3 in response to a compensation gate signal GC. The third transistor T3 includes a gate electrode receiving the compensation gate signal GC, a first electrode receiving the reference voltage VREF, and a second electrode connected to the third node N3. However, the present invention is not limited thereto. In another embodiment, the reference voltage VREF received by the first electrode of the third transistor T3 is different from the reference voltage VREF transmitted by the data line DL.

[0115] The fourth transistor T4 connects the first node N1 and the second node N2 in response to a second compensation gate signal GC2, so that the voltage at the first node N1 is the same as the voltage at the second node N2. The fourth transistor T4 includes a gate electrode receiving the second compensation gate signal GC2, a first electrode connected to the first node N1, and a second electrode connected to the second node N2.

[0116] The fifth transistor T5 provides an initialization voltage VINT to the second node N2 in response to an initialization gate signal GI, so that the voltage at the second node N2 is initialized to the initialization voltage VINT. The fifth transistor T5 includes a gate electrode receiving the initialization gate signal GI, a first electrode receiving the initialization voltage VINT, and a second electrode connected to the second node N2.

[0117] The first capacitor C1 includes a first electrode connected to the first node N1 and a second electrode connected to the second node N2.

[0118] The second capacitor C2 includes a first electrode connected to the second node N2 and a second electrode connected to the third node N3.

[0119] Thus, the pixel circuit PXd includes five transistors T1, T2, T3, T4, and T5 and two capacitors C1 and C2, which allows the pixel circuit PXd to have a small area and a high PPI.

[0120] Fig. 16 is a timing diagram showing an example of operation of the pixel circuit PXd of Fig. 5. Fig. 17 is a circuit diagram showing an example of operation of the pixel circuit PXd of Fig. 15 in the first interval DU1 of Fig. 16. Fig. 18 is a circuit diagram showing an example of operation of the pixel circuit PXd of Fig. 15 in the second interval DU2 of Fig. 16. Fig. 19 is a circuit diagram showing an example of operation of the pixel circuit PXd of Fig. 15 in the third interval DU3 of Fig. 16. Fig. 20 is a circuit diagram showing an example of operation of the pixel circuit PXd of Fig. 15 in the fourth interval DU4 of Fig. 16.

[0121] 16 and 17, in a first interval DU1, the first power supply voltage ELVDD has the low level L, the second power supply voltage ELVSS has the high level H, the compensation gate signal GC has the high level H, the second compensation gate signal GC2 has the high level H, the initialization gate signal GI has the high level H, the data write gate signal GW[N] has the low level L, and the data line DL transmits the reference voltage VREF. The first power supply voltage ELVDD, the second power supply voltage ELVSS, the compensation gate signal GC, the second compensation gate signal GC2, the initialization gate signal GI, and the data write gate signal GW[N] may be simultaneously applied to the pixel circuit PXd.

[0122] The fifth transistor T5 is turned on in response to the initialization gate signal GI having the high level H to provide the initialization voltage VINT to the second node N2, so that the voltage of the second node N2 has the initialization voltage VINT.

[0123] The fourth transistor T4 is turned on in response to the second compensation gate signal GC2 having the high level H, and provides the voltage of the second node N2 to the first node N1, so that the voltage of the first node N1 has the initialization voltage VINT.

[0124] As described above, in the first period DU1, the voltage of the first node N1 and the voltage of the second node N2 are initialized to the initialization voltage VINT, and therefore the first period DU1 is referred to as an initialization period.

[0125] 16 and 18, in the second interval DU2, the first power supply voltage ELVDD has the high level H, the second power supply voltage ELVSS has the high level H, the compensation gate signal GC has the high level H, the second compensation gate signal GC2 has the high level H, the initialization gate signal GI has the low level L, the data write gate signal GW[N] has the low level L, and the data line DL transmits the reference voltage VREF. The first power supply voltage ELVDD, the second power supply voltage ELVSS, the compensation gate signal GC, the second compensation gate signal GC2, the initialization gate signal GI, and the data write gate signal GW[N] may be simultaneously applied to the pixel circuit PXd.

[0126] The third transistor T3 is turned on in response to the compensation gate signal GC having the high level H to provide the reference voltage VREF to the third node N3, so that the voltage of the third node N3 has the reference voltage VREF.

[0127] When the first power supply voltage ELVDD is changed from the low level L to the high level H, the fourth transistor T4 is turned on in response to the second compensation gate signal GC2 having the high level H, and the first transistor T1 is turned on. As a result, the first transistor T1 is diode-connected and the threshold voltage of the first transistor T1 is compensated.

[0128] In this way, the threshold voltage of the first transistor T1 is compensated in the second section DU2, and therefore the second section DU2 is referred to as a compensation section.

[0129] 16 and 19, in the third interval DU3, the first power supply voltage ELVDD has the low level L, the second power supply voltage ELVSS has the high level H, the compensation gate signal GC has the low level L, the second compensation gate signal GC2 has the low level L, the initialization gate signal GI has the high level H, the data write gate signal GW[N] has the high level H, and the data line DL transmits the data voltage VDATA. The first power supply voltage ELVDD, the second power supply voltage ELVSS, the compensation gate signal GC, the second compensation gate signal GC2, and the initialization gate signal GI are simultaneously applied to the pixel circuit PXd, and the data write gate signal GW[N] is sequentially applied to the pixel circuit PXd.

[0130] The second transistor T2 is turned on in response to the data write gate signal GW[N] having the high level H to connect the data line DL transmitting the data voltage VDATA to the first node N1, so that the second transistor T2 provides the data voltage VDATA to the first node N1, and the voltage of the first node N1 has the data voltage VDATA.

[0131] The fifth transistor T5 is turned on in response to the initialization gate signal GI having the high level H to provide the initialization voltage VINT to the second node N2, so that the voltage at the second node N2 has the initialization voltage VINT.

[0132] In this manner, the data voltage VDATA is applied to the pixel circuit PXd in the third section DU3, and therefore the third section DU3 is referred to as a data write section.

[0133] 16 and 20, in the fourth interval DU4, the first power supply voltage ELVDD has the high level H, the second power supply voltage ELVSS has the low level L, the compensation gate signal GC has the low level L, the second compensation gate signal GC2 has the low level L, the initialization gate signal GI has the low level L, the data write gate signal GW[N] has the low level L, and the data line DL transmits the reference voltage VREF. The first power supply voltage ELVDD, the second power supply voltage ELVSS, the compensation gate signal GC, the second compensation gate signal GC2, the initialization gate signal GI, and the data write gate signal GW[N] may be simultaneously applied to the pixel circuit PXd.

[0134] When the first power supply voltage ELVDD has the high level H and the second power supply voltage ELVSS has the low level L, the first transistor T1 generates the driving current based on the voltage of the first node N1 and the voltage of the second node N2 and provides it to the light-emitting element EL. The light-emitting element EL emits light based on the driving current. The luminance of the light-emitting element EL is determined based on the strength of the driving current, and the strength of the driving current is determined based on the level of the data voltage VDATA. That is, the luminance of the light-emitting element EL is determined based on the level of the data voltage VDATA.

[0135] In this manner, the light emitting element EL emits light in the fourth section DU4, and therefore the fourth section DU4 is referred to as a light emitting section.

[0136] FIG. 21 is a circuit diagram showing an example PXe of the pixel circuit PX of FIG.

[0137] 1 and 21, the pixel circuit PXe includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a first capacitor C1, a second capacitor C2, and a light-emitting element EL. In one embodiment, the first to fourth transistors T1 to T4 are NMOS transistors. In another embodiment, the first transistor T1 is the NMOS transistor, and the second to fourth transistors T2 to T4 are PMOS transistors.

[0138] The NMOS transistor is turned on in response to a gate signal having a high level and turned off in response to a gate signal having a low level, and the PMOS transistor is turned on in response to a gate signal having the low level and turned off in response to a gate signal having the high level.

[0139] The first transistor T1 includes a first gate electrode connected to a first node N1, a first electrode receiving a first power supply voltage ELVDD, a second electrode connected to a second node N2, and a second gate electrode connected to the second node N2. In one embodiment, the first gate electrode of the first transistor T1 is a gate electrode, and the second gate electrode of the first transistor T1 is a back gate electrode. The first transistor T1 generates a driving current based on the voltage of the first node N1 and the voltage of the second node N2, and provides the driving current to the light-emitting element EL.

[0140] The second transistor T2 connects a data line DL and a third node N3 in response to a data write gate signal GW[N]. The data line DL transmits a reference voltage VREF or a data voltage VDATA. The second transistor T2 includes a gate electrode that receives the data write gate signal GW[N], a first electrode connected to the data line DL, and a second electrode connected to the third node N3.

[0141] The third transistor T3 provides the reference voltage VREF to the first node N1 in response to a compensation gate signal GC. The third transistor T3 includes a gate electrode receiving the compensation gate signal GC, a first electrode receiving the reference voltage VREF, and a second electrode connected to the first node N1. However, the present invention is not limited thereto. In another embodiment, the reference voltage VREF received by the first electrode of the third transistor T3 is different from the reference voltage VREF transmitted by the data line DL.

[0142] The fourth transistor T4 connects the second node N2 and the third node N3 in response to the compensation gate signal GC, and includes a gate electrode receiving the compensation gate signal GC, a first electrode connected to the second node N2, and a second electrode connected to the third node N3.

[0143] The first capacitor C1 includes a first electrode connected to the first node N1 and a second electrode connected to the third node N3.

[0144] The second capacitor C2 includes a first electrode connected to the second node N2 and a second electrode connected to the third node N3.

[0145] Thus, the pixel circuit PXe includes four transistors T1, T2, T3, and T4 and two capacitors C1 and C2, which allows the pixel circuit PXe to have a small area and a high PPI.

[0146] Fig. 22 is a timing diagram showing an example of operation of the pixel circuit PXe of Fig. 21. Fig. 23 is a circuit diagram showing an example of operation of the pixel circuit PXe of Fig. 21 in the first interval DU1 of Fig. 22. Fig. 24 is a circuit diagram showing an example of operation of the pixel circuit PXe of Fig. 21 in the second interval DU2 of Fig. 22. Fig. 25 is a circuit diagram showing an example of operation of the pixel circuit PXe of Fig. 21 in the third interval DU3 of Fig. 22. Fig. 26 is a circuit diagram showing an example of operation of the pixel circuit PXe of Fig. 21 in the fourth interval DU4 of Fig. 22.

[0147] 22 and 23, in a first period DU1, the first power supply voltage ELVDD has the low level L, the second power supply voltage ELVSS has the high level H, the compensation gate signal GC has the high level H, the data write gate signal GW[N] has the low level L, and the data line DL transmits the reference voltage VREF. The first power supply voltage ELVDD, the second power supply voltage ELVSS, the compensation gate signal GC, and the data write gate signal GW[N] may be simultaneously applied to the pixel circuit PXe.

[0148] The third transistor T3 is turned on in response to the compensation gate signal GC having the high level H to provide the reference voltage VREF to the first node N1, so that the voltage of the first node N1 has the reference voltage VREF.

[0149] The fourth transistor T4 is turned on in response to the compensation gate signal GC having the high level H.

[0150] In this manner, in the first period DU1, the voltage of the first node N1 is initialized to the reference voltage VREF, and therefore the first period DU1 is referred to as an initialization period.

[0151] 22 and 24, in the second interval DU2, the first power supply voltage ELVDD has the high level H, the second power supply voltage ELVSS has the high level H, the compensation gate signal GC has the high level H, the data write gate signal GW[N] has the low level L, and the data line DL transmits the reference voltage VREF. The first power supply voltage ELVDD, the second power supply voltage ELVSS, the compensation gate signal GC, and the data write gate signal GW[N] may be simultaneously applied to the pixel circuit PXe.

[0152] The third transistor T3 is turned on in response to the compensation gate signal GC having the high level H to provide the reference voltage VREF to the first node N1, so that the voltage at the first node N1 has the reference voltage VREF.

[0153] When the first power supply voltage ELVDD changes from the low level L to the high level H, the fourth transistor T4 turns on in response to the compensation gate signal GC having the high level H, thereby turning on the first transistor T1. As a result, the voltage of the third node N3 changes to a value obtained by subtracting the threshold voltage of the first transistor T1 from the reference voltage VREF. As a result, the first capacitor C1 stores the threshold voltage of the first transistor T1, and the threshold voltage of the first transistor T1 is compensated.

[0154] In this way, the threshold voltage of the first transistor T1 is compensated in the second section DU2, and therefore the second section DU2 is referred to as a compensation section.

[0155] 22 and 25, in the third interval DU3, the first power supply voltage ELVDD has the low level L, the second power supply voltage ELVSS has the high level H, the compensation gate signal GC has the low level L, the data write gate signal GW[N] has the high level H, and the data line DL transmits the data voltage VDATA. The first power supply voltage ELVDD, the second power supply voltage ELVSS, and the compensation gate signal GC are simultaneously applied to the pixel circuit PXe, and the data write gate signal GW[N] is sequentially applied to the pixel circuit PXe.

[0156] The second transistor T2 is turned on in response to the data write gate signal GW[N] having the high level H to connect the data line DL transmitting the data voltage VDATA to the third node N3, so that the second transistor T2 provides the data voltage VDATA to the third node N3, and the voltage of the third node N3 has the data voltage VDATA.

[0157] In this manner, the data voltage VDATA is applied to the pixel circuit PXe in the third interval DU3, and therefore the third interval DU3 is referred to as a data write interval.

[0158] 22 and 26, in the fourth interval DU4, the first power supply voltage ELVDD has the high level H, the second power supply voltage ELVSS has the low level L, the compensation gate signal GC has the low level L, the data write gate signal GW[N] has the low level L, and the data line DL transmits the reference voltage VREF. The first power supply voltage ELVDD, the second power supply voltage ELVSS, the compensation gate signal GC, and the data write gate signal GW[N] may be simultaneously applied to the pixel circuit PXe.

[0159] When the first power supply voltage ELVDD has the high level H and the second power supply voltage ELVSS has the low level L, the first transistor T1 generates the driving current based on the voltage at the first node N1 and the voltage at the second node N2 and provides the driving current to the light-emitting element EL. The light-emitting element EL emits light based on the driving current. The luminance of the light-emitting element EL is determined based on the strength of the driving current, and the strength of the driving current is determined based on the level of the data voltage VDATA. That is, the luminance of the light-emitting element EL is determined based on the level of the data voltage VDATA.

[0160] In this manner, the light emitting element EL emits light in the fourth section DU4, and therefore the fourth section DU4 is referred to as a light emitting section.

[0161] Fig. 27 is a block diagram illustrating an electronic device 1000 according to an embodiment of the present invention. Fig. 28 is a diagram illustrating an example in which the electronic device 1000 of Fig. 27 is implemented as a VR device.

[0162] 27, the electronic device 1000 includes a processor 1010, a memory device 1020, a storage device 1030, an input / output device 1040, a power supply 1050, and a display device 1060. Here, the display device 1060 is the display device in FIG. 1. The electronic device 1000 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a USB device, etc., or for communicating with other systems.

[0163] 28, the electronic device 1000 may be implemented as a VR device. However, this is merely an example, and the electronic device 1000 is not limited thereto. For example, the electronic device 1000 may be implemented as a mobile phone, a video phone, a smart pad, a smart watch, a tablet PC, a vehicle navigation system, a computer monitor, a laptop computer, a head-mounted display device, etc.

[0164] The processor 1010 may perform a specific calculation or task. Depending on the embodiment, the processor 1010 may be a microprocessor, a central processing unit, an application processor, etc. The processor 1010 may be connected to other components via an address bus, a control bus, a data bus, etc. Depending on the embodiment, the processor 1010 may also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus.

[0165] The processor 1010 can output the input image data IMG and the input control signal CONT to the driving control unit 200 of FIG.

[0166] The memory device 1020 may store data necessary for the operation of the electronic device 1000. For example, the memory device 1020 may include a non-volatile memory device such as an erasable programmable read-only memory (ERPOM) device, an electrically erasable programmable read-only memory (EERPOM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistance random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM) device, etc., and / or a volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM), a mobile DRAM device, etc.

[0167] The storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, etc. The input / output device 1040 may include input means such as a keyboard, a keypad, a touchpad, a touch screen, a mouse, etc., and output means such as a speaker, a printer, etc. According to an embodiment, the display device 1060 may also be included in the input / output device 1040. The power supply 1050 may supply power necessary for operation of the electronic device 1000. The display device 1060 may be connected to other components via the bus or other communication links.

[0168] Fig. 29 is a block diagram illustrating an electronic device 10 according to an embodiment of the present invention. Fig. 30 is a schematic diagram of the electronic device 10 of Fig. 29.

[0169] As shown in FIG. 29, an electronic device 10 according to one embodiment includes a display module 11, a processor 12, a memory 13, and a power module 14.

[0170] The display device according to the embodiment of the present invention can be applied to various electronic devices.

[0171] In one embodiment, the electronic device 10 includes the display device of Fig. 1. That is, the operation of the display device included in the electronic device 10 is similar to the operation of the display device described with reference to Figs. 1 to 26. In addition to the display device, the electronic device 10 may further include modules or devices having other additional functions.

[0172] The processor 12 includes at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0173] In one embodiment, the processor 12 provides the input control signal CONT of FIG. 1 and the input image data IMG of FIG. 1 to a drive control unit 200 included in the display device of FIG.

[0174] In one embodiment, the processor 12 may be divided into two or more parts in terms of functionality or structure. For example, the processor 12 may include a main processor in the form of a first driver chip including a central processing unit, and a secondary processor in the form of a second driver chip including a controller that receives image signals from the main processor and processes the image signals to conform to the interface specifications of the display module 11. For example, the secondary processor may include the drive control unit 200 included in the display device of FIG. 1. The main processor then provides the input control signal CONT of FIG. 1 and the input image data IMG of FIG. 1 to the secondary processor. The secondary processor processes the image signals based on the input control signal CONT and the input image data IMG.

[0175] The memory 13 includes at least one of a non-volatile memory and a volatile memory. The memory 13 stores data information required for the operation of the processor 12 and the display module 11. When the processor 12 executes an application stored in the memory 13, the input control signal CONT and / or the input image data IMG are transmitted to the display module 11, and the display module 11 processes the provided input control signal CONT and / or the input image data IMG and outputs image information through a display screen.

[0176] The power supply module 14 includes a power supply module such as a power adapter or a battery device, and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 10.

[0177] At least one of the components of the electronic device 10 is included in the display device according to an embodiment of the present invention. Furthermore, some of the individual modules functionally included in one module may be included in the display device, while other modules may be provided separately from the display device. For example, the display device may include the display module 11, and the processor 12, the memory 13, and the power supply module 14 may be provided in the form of other devices within the electronic device 10, rather than the display device.

[0178] 30, various electronic devices to which the display device according to the present embodiment is applied include not only electronic devices for displaying images such as a smartphone 10_1a, a tablet PC 10_1b, a laptop 10_1c, a TV 10_1d, and a desk monitor 10_1e, but also wearable electronic devices including a display module such as smart glasses 10_2a, a head-mounted display 10_2b, and a smart watch 10_2c, and vehicular electronic devices 10_3 including a display module such as a CID (Center Information Display) and a Room Mirror Display disposed on an instrument panel, center fascia, or dashboard of an automobile. The electronic devices 10 are not limited to electronic devices for displaying images, wearable electronic devices, and vehicular electronic devices 10_3. [Industrial Applicability]

[0179] The present invention can be applied to pixel circuits and display devices and electronic devices including the same, such as mobile phones, smartphones, tablet computers, TVs, digital TVs, 3D TVs, PCs, home electronic devices, notebook computers, PDAs, PMPs, digital cameras, music players, portable game consoles, and navigation systems.

[0180] Although the present invention has been described with reference to the embodiments, it will be understood by those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit and scope of the present invention as defined in the claims. [Explanation of symbols]

[0181] 100: Display panel 200: Drive control unit 300: Gate driver 400: Gamma reference voltage generator 500: Data Drive

Claims

1. a first transistor including a first gate electrode connected to a first node, a first electrode receiving a first power supply voltage, a second electrode connected to a second node, and a third gate electrode connected to a third node; a second transistor connecting the data line and the first node in response to a data write gate signal; a third transistor responsive to a compensating gate signal to provide a reference voltage to the third node; a first capacitor including a first electrode connected to the first node and a second electrode connected to the second node; a second capacitor including a first electrode connected to the second node and a second electrode connected to the third node; a light-emitting element including an anode electrode connected to the second node and a cathode electrode receiving a second power supply voltage.

2. 2. The pixel circuit according to claim 1, wherein the first to third transistors are NMOS transistors.

3. 2. The pixel circuit of claim 1, wherein the second transistor includes a gate electrode that receives the data write gate signal, a first electrode that is connected to the data line, and a second electrode that is connected to the first node.

4. 2. The pixel circuit of claim 1, wherein the third transistor includes a gate electrode that receives the compensation gate signal, a first electrode that receives the reference voltage, and a second electrode that is connected to the third node.

5. 2. The pixel circuit according to claim 1, wherein the first gate electrode of the first transistor is a gate electrode, and the second gate electrode of the first transistor is a back gate electrode.

6. 2. The pixel circuit according to claim 1, wherein the first gate electrode of the first transistor is a back gate electrode, and the second gate electrode of the first transistor is a gate electrode.

7. 2. The pixel circuit of claim 1, further comprising a fourth transistor connecting the first node and the second node in response to a second compensation gate signal.

8. 8. The pixel circuit of claim 7, wherein the fourth transistor includes a gate electrode that receives the second compensation gate signal, a first electrode that is connected to the first node, and a second electrode that is connected to the second node.

9. 8. The pixel circuit of claim 7, further comprising a fifth transistor responsive to an initialization gate signal to provide an initialization voltage to the second node.

10. 10. The pixel circuit of claim 9, wherein the fifth transistor includes a gate electrode that receives the initialization gate signal, a first electrode that receives the initialization voltage, and a second electrode that is connected to the second node.

11. a first transistor including a first gate electrode connected to a first node, a first electrode receiving a first power supply voltage, a second electrode connected to a second node, and a second gate electrode connected to the second node; a first capacitor including a first electrode connected to the first node and a second electrode connected to a third node; a second transistor connecting the data line and the third node in response to a data write gate signal; a third transistor responsive to a compensating gate signal to provide a reference voltage to the first node; a fourth transistor connecting the second node and the third node in response to the compensation gate signal; a second capacitor including a first electrode connected to the second node and a second electrode connected to the third node; a light-emitting element including an anode electrode connected to the second node and a cathode electrode receiving a second power supply voltage.

12. 12. The pixel circuit according to claim 11, wherein the first to fourth transistors are NMOS transistors.

13. 12. The pixel circuit of claim 11, wherein the second transistor includes a gate electrode that receives the data write gate signal, a first electrode that is connected to the data line, and a second electrode that is connected to the third node.

14. 12. The pixel circuit of claim 11, wherein the third transistor includes a gate electrode that receives the compensation gate signal, a first electrode that receives the reference voltage, and a second electrode that is connected to the first node.

15. 12. The pixel circuit of claim 11, wherein the fourth transistor includes a gate electrode that receives the compensation gate signal, a first electrode that is connected to the second node, and a second electrode that is connected to the third node.

16. a display panel including pixel circuits; a gate driver for providing a gate signal to the pixel circuit; a data driver for providing a data voltage to the pixel circuit; a driving control unit for controlling the gate driver and the data driver, The pixel circuit a first transistor including a first gate electrode connected to a first node, a first electrode receiving a first power supply voltage, a second electrode connected to a second node, and a third gate electrode connected to a third node; a second transistor connecting the data line and the first node in response to a data write gate signal; a third transistor responsive to a compensating gate signal to provide a reference voltage to the third node; a first capacitor including a first electrode connected to the first node and a second electrode connected to the second node; a second capacitor including a first electrode connected to the second node and a second electrode connected to the third node; a light-emitting element including an anode electrode connected to the second node and a cathode electrode receiving a second power supply voltage.

17. 17. The display device according to claim 16, wherein the first to third transistors are NMOS transistors.

18. 17. The display device of claim 16, wherein the second transistor includes a gate electrode that receives the data write gate signal, a first electrode that is connected to the data line, and a second electrode that is connected to the first node.

19. 17. The display device of claim 16, wherein the third transistor includes a gate electrode that receives the compensation gate signal, a first electrode that receives the reference voltage, and a second electrode that is connected to the third node.

20. 17. The display device according to claim 16, wherein the first gate electrode of the first transistor is a gate electrode, and the second gate electrode of the first transistor is a back gate electrode.

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