Support substrate, electronic device, and module

Abstract

To provide a support substrate, an electronic device, and a module which are applied to a frequency band of 3.5 GHz or more for effectively reducing the energy of longitudinal wave transmission, effectively reducing spurious reflection, and realizing normal filtering.SOLUTION: In the polycrystalline material which is the material of the support substrate of the present invention, the number of small-angle grain boundaries having a misorientation angle of 2 to 15 ° in the support substrate accounts for 1 to 5% of the total number of grain boundaries. Accordingly, the support substrate having the specific occupancy of the small-angle grain boundaries is able to effectively reduce or prevent spurious responses to ensure normal filtering.SELECTED DRAWING: None

Description

[Technical Field]

[0001] The present invention relates to the field of electronic device processing and manufacturing technology, and more particularly to a support substrate, an electronic device, and a module. [Background technology]

[0002] In recent years, technological advances have led to demands for ever-increasing performance in acoustic wave devices, such as surface acoustic wave (SAW) devices. Some SAW devices, such as temperature-compensated SAW (TC-SAW), require the use of composite substrates obtained by bonding a piezoelectric layer substrate to a support substrate. Therefore, the design of support substrates remains an important research topic in SAW device-related processes, and identifying suitable materials for support substrates has become a key industry focus. For example, single-crystal sapphire has excellent thermal conductivity and is widely used in the LED industry. However, due to the properties of its single crystal, TC-SAWs fabricated using single-crystal sapphire are always susceptible to spurious signals, preventing proper filtering. Therefore, the design of support substrates that can reduce spurious signals and achieve proper filtering remains a key challenge. Summary of the Invention [Problem to be solved by the invention]

[0003] An object of the present invention is to provide a support substrate, an electronic device, and a module that can reduce spurious emissions. [Means for solving the problem]

[0004] One embodiment of the present invention provides a support substrate, the material of the support substrate is a polycrystalline material, and the number of small-angle grain boundaries in the support substrate, with misorientation angles of 2 to 15°, accounts for 1 to 5% of the total number of grain boundaries.

[0005] One embodiment of the present invention provides a support substrate, the material of the support substrate is a polycrystalline material, and the number of small-angle grain boundaries with a misorientation angle of 2 to 15° is 5 or more in any one metric region on any one surface of the support substrate, and the metric region is an area with a length of 150 micrometers and a width of 150 micrometers.

[0006] One embodiment of the present invention provides an electronic device including any one of the support substrates described above, and further including a piezoelectric layer disposed on the support substrate, and an IDT electrode located on a main surface of the piezoelectric layer opposite the support substrate.

[0007] One embodiment of the present invention provides a module including a wiring substrate, a plurality of external connection terminals, an integrated circuit member, an inductor, a sealing portion, and the electronic device described above. [Effects of the Invention]

[0008] The above-described embodiment of the present invention has at least one or more of the following beneficial effects: The support substrate with a special grain boundary occupancy can effectively reduce the energy of longitudinal wave transmission, and further effectively reduce spurious reflection, achieve normal filtering, and be applicable to frequency bands above 3.5 GHz. [Brief explanation of the drawings]

[0009] Hereinafter, specific embodiments of the present invention will be described in detail with reference to the drawings. [Figure 1] 1 is a structural schematic diagram of a support substrate provided in an embodiment of the present invention; [Figure 2] FIG. 2 is a microstructure diagram of one metric region of one support substrate provided in an embodiment of the present invention. [Figure 3] This is the IPF coloring diagram of Figure 2. [Figure 4] FIG. 3 is a distribution diagram of misorientation angles of the grain boundaries in FIG. 2. [Figure 5] FIG. 10 is a microstructure diagram within one metric region of another support substrate provided in an embodiment of the present invention. [Figure 6] This is an IPF coloring diagram of Figure 5. [Figure 7] FIG. 6 is a distribution diagram of misorientation angles of the grain boundaries in FIG. 5. [Figure 8] FIG. 10 is a microstructure diagram within one metric region of another support substrate provided in an embodiment of the present invention. [Figure 9] This is an IPF coloring diagram of Figure 8. [Figure 10] FIG. 9 is a distribution diagram of misorientation angles of the grain boundaries in FIG. 8. [Figure 11] 10A and 10B are diagrams comparing the effects of support substrates provided in different embodiments of the present invention on suppressing spurious signals. [Figure 12] 1 is a structural schematic diagram of one composite substrate provided in an embodiment of the present invention. [Figure 13] 1 is a structural schematic diagram of an electronic device provided in an embodiment of the present invention; [Figure 14] FIG. 2 is a structural schematic diagram of another electronic device provided in an embodiment of the present invention. [Figure 15] FIG. 2 is a structural schematic diagram of another electronic device provided in an embodiment of the present invention. [Figure 16] FIG. 2 is a structural schematic diagram of yet another electronic device provided in an embodiment of the present invention. [Figure 17] FIG. 2 is a structural schematic diagram of one module provided in an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] As shown in Figure 1, one embodiment of the present invention provides a support substrate 11. The material of the support substrate 11 is a polycrystalline material, and a plurality of crystal grains in the support substrate 11 have different crystal orientations and are connected to each other by grain boundaries, which are the interfaces between the crystal grains. The included angle between the crystal orientations of any two adjacent crystal grains is the misorientation angle, and depending on the value of the misorientation angle, the corresponding grain boundaries can be classified as low-angle grain boundaries and non-low-angle grain boundaries. Here, grain boundaries with misorientation angles of 2° to 15° are called low-angle grain boundaries, and grain boundaries with misorientation angles greater than 15° and grain boundaries with misorientation angles less than 2° are collectively called non-low-angle grain boundaries. In the support substrate 11 provided in the embodiment of the present invention, the ratio of the number of low-angle grain boundaries to the total number of grain boundaries (abbreviated as the occupancy rate of low-angle grain boundaries) is 1 to 5%, and may be, for example, 1%, 2%, 3%, 4%, etc., and the ratio of the number of corresponding non-low-angle grain boundaries (including those with misorientation angles less than 2° or greater than 15°) to the total number of grain boundaries (abbreviated as the occupancy rate of non-low-angle grain boundaries) is 95 to 99%. For example, the occupancy rate of low-angle grain boundaries is 2%, and the occupancy rate of non-low-angle grain boundaries is 98%. For example, the occupancy rate of low-angle grain boundaries is 3%, and the occupancy rate of non-low-angle grain boundaries is 97%. Naturally, the above is merely an illustrative example, and the embodiment is not limited thereto.

[0011] However, the polycrystalline material is, for example, any one of polycrystalline magnesium aluminum spinel, polycrystalline sapphire, polycrystalline aluminum nitride, polycrystalline magnesium oxide, and polycrystalline quartz.

[0012] However, the value of the misorientation angle of the grain boundaries and the number of grain boundaries in the support substrate 11 can be determined by obtaining a microstructure diagram on the support substrate 11 using electron backscatter diffraction (EBSD) technology and then performing IPF coloring (Inverse Pole Figure coloring) on ​​the microstructure on the support substrate 11. IPF coloring is a method for characterizing crystal orientation in materials science. It displays crystal orientation information in the form of color on a polar coordinate diagram, allowing the observer to intuitively recognize the texture characteristics of the crystal.

[0013] Experiments have shown that the support substrate 11 having such a special grain boundary ratio provided in the embodiment of the present invention can effectively reduce the energy of longitudinal wave transmission, and further effectively reduce spurious reflection, achieve normal filtering, and be applicable to frequency bands above 3.5 GHz.

[0014] 1, the support substrate 11 has, for example, a main support surface 111, a back surface 112 opposite the main support surface 111, and a side surface 113 located between the main support surface 111 and the back surface 112. The main support surface 111 can be used to support the piezoelectric layer.

[0015] Specifically, in some embodiments, the number of low-angle grain boundaries in a lateral cross section or lateral surface of support substrate 11 accounts for 1 to 5% of the total number of grain boundaries. More specifically, the occupancy rate of low-angle grain boundaries in a lateral cross section or lateral surface of support substrate 11 may be 3 to 4%. However, the lateral cross section may be any one of the cross sections parallel to major support surface 111 of support substrate 11. The lateral surface may be major support surface 111 or another surface parallel to major support surface 111. For example, back surface 112 may be parallel to major support surface 111, and the lateral surface may be back surface 112. That is, in some embodiments, the occupancy rate of low-angle grain boundaries on major support surface 111 of support substrate 11 is 1 to 5%. In some embodiments, the occupancy rate of low-angle grain boundaries on back surface 112 of support substrate 11 is 1 to 5%. In some embodiments, the occupancy rate of low-angle grain boundaries in any one of the cross sections parallel to major support surface 111 of support substrate 11 is 1 to 5%.

[0016] In some embodiments, the number of low-angle grain boundaries on any one surface of support substrate 11 (i.e., any one of main support surface 111, back surface 112, and side surface 113) accounts for 1 to 5% of the total number of grain boundaries. That is, when observing the grain boundaries on any one surface of support substrate 11, the proportion of the number of low-angle grain boundaries is 1 to 5%.

[0017] More specifically, the number of low-angle grain boundaries on any one surface of the support substrate 11 accounts for 3 to 4% of the total number of grain boundaries, achieving a better spurious reduction effect. Referring to Figure 11, spurious responses for a single crystal sapphire substrate and the support substrate 11 of the present application are compared. In Figure 11, #1 is a sapphire substrate, and #2, #3, and #4 are support substrates 11 provided in the present application. The grain size in #2 is 20 to 30 μm, and the occupancy rate of low-angle grain boundaries is 3.2%. The grain size in #3 is 15 to 20 μm, and the occupancy rate of low-angle grain boundaries is 3.5%. The grain size in #4 is 5 to 10 μm, and the occupancy rate of low-angle grain boundaries is 3.7%. In Figure 11, the horizontal axis is frequency (MHz) and the vertical axis is admittance (dB), with the gray dashed arrow indicating the frequency boundary of 1600 MHz. As can be seen from Figure 11, when the occupancy rate of the low-angle grain boundaries is between 3.2% and 3.7%, the spurious emissions meet the requirements for use, and when the occupancy rate of the low-angle grain boundaries is 3.7%, the effect of suppressing spurious emissions is greatest.

[0018] In some embodiments, the number of low-angle grain boundaries is five or more in any one measurement region on any one surface of the support substrate 11, where the measurement region is a region having a length of 150 μm (micrometers) and a width of 150 μm. That is, when a 150 μm*150 μm region is randomly selected and observed on any one surface of the support substrate 11, the number of low-angle grain boundaries observed is five or more.

[0019] As shown in Figures 2 and 3, Figure 2 is an image of the microstructure of one metric region on a lateral surface of the support substrate 11 (made of polycrystalline magnesium aluminum spinel) provided in this example, and Figure 3 is an image obtained by applying IPF coloring to Figure 2. In Figure 3, the colored areas (displayed in different grayscales in the figure) represent crystal grains, and the outlines of the crystal grains represent grain boundaries. In Figure 3, the closer the colors of two adjacent crystal grains are, the smaller the misorientation angle corresponding to the grain boundary between the two crystal grains. In Figure 2, for clearer illustration, low-angle grain boundaries are surrounded by elliptical dashed lines, and as shown in Figure 2, there are six low-angle grain boundaries.

[0020] In some embodiments, the grain size of the crystal grains in the support substrate 11 is 1 to 100 micrometers. Specifically, in the graphs shown in Figures 2 and 3, the grain size of the crystal grains is 10 to 100 micrometers, and for example, the support substrate 11 has crystal grains with different grain sizes, such as 10 micrometers, 25 micrometers, 40 micrometers, 50 micrometers, 60 micrometers, and 100 micrometers, and the grain size of the smallest crystal grain is 10 micrometers or more (≧10 μm) and the grain size of the largest crystal grain is 100 μm or less (≦100 μm).

[0021] In a further embodiment, the grain size of the crystal grains in support substrate 11 is 5 to 60 micrometers, and for example, support substrate 11 contains crystal grains of different sizes, such as 5 micrometers, 10 micrometers, 20 micrometers, 25 micrometers, 40 micrometers, and 60 micrometers, and the smallest crystal grains have a grain size of 5 micrometers or more (≧5 μm) and the largest crystal grains have a grain size of 60 micrometers or less (≦60 μm), and the number of low-angle grain boundaries in any one measurement region on any one surface of support substrate 11 is 25 or more. That is, when any one 150 micrometer x 150 micrometer region is selected and observed in support substrate 11 with a grain size of 5 to 60 micrometers, the number of low-angle grain boundaries is observed to be 25 or more. 5 and 6, Fig. 5 is an image of the microstructure of a 150 micrometer x 150 micrometer region within a lateral surface of a support substrate 11 (made of polycrystalline magnesium aluminum spinel) with a crystal grain size of 5 to 60 micrometers. Fig. 6 is an image processed by the IPF coloring method using the region in Fig. 5. The closer the colors of two adjacent crystal grains in Fig. 6, the smaller the misorientation angle corresponding to the grain boundary between the two adjacent crystal grains. Some low-angle grain boundaries in Fig. 5 are surrounded by circular dashed lines, and Fig. 5 clearly shows that there are 25 or more low-angle grain boundaries.

[0022] In another embodiment, the crystal grain size in support substrate 11 is 1 to 5 micrometers, and for example, support substrate 11 contains crystal grains of different sizes, such as 1 micrometer, 2 micrometers, 3 micrometers, and 5 micrometers, and the smallest crystal grain has a grain size of 5 micrometers or more (≧5 μm) and the largest crystal grain has a grain size of 60 micrometers or less (≦60 μm), and the number of low-angle grain boundaries in any one measurement region on any one surface of support substrate 11 is 40 or more. That is, when any one region of 150 micrometers x 150 micrometers on any one surface of support substrate 11 is selected and observed, the number of low-angle grain boundaries observed is 40 or more. 8 and 9, Fig. 8 is an image of the microstructure of a 150 x 150 micrometer region within a lateral surface of a support substrate 11 (made of polycrystalline magnesium aluminum spinel) with a crystal grain size of 1 to 5 micrometers, and Fig. 9 is an image of the region in Fig. 8 processed by the IPF coloring method. In Fig. 9, the closer the colors of two adjacent crystal grains, the smaller the misorientation angle corresponding to the grain boundary between the two adjacent crystal grains. In Fig. 8, some low-angle grain boundaries are surrounded by circular dashed lines, and Fig. 8 clearly shows that there are 40 or more low-angle grain boundaries.

[0023] In some embodiments, the number of low-angle grain boundaries in any one measurement region on any one surface of the support substrate 11 accounts for 1 to 5% of the total number of grain boundaries. That is, when a 150-micrometer × 150-micrometer region on any one surface of the support substrate 11 is randomly selected and observed, the occupancy rate of the low-angle grain boundaries is always within the range of 1 to 5%. That is, not only is there a specific occupancy rate of low-angle grain boundaries within the support substrate 11, but the distribution of the low-angle grain boundaries is also uniform, resulting in better spurious suppression. More specifically, the number of low-angle grain boundaries in any one measurement region on any one surface of the support substrate 11 accounts for 3 to 4% of the total number of grain boundaries. For example, the occupancy rate of low-angle grain boundaries actually measured from FIGS. 2 and 3 is 3.2%, and the occupancy rate of non-low-angle grain boundaries is 96.8%. The occupancy rate of low-angle grain boundaries actually measured from FIGS. 5 and 6 is 3.45%, and the occupancy rate of non-low-angle grain boundaries is 96.55%. 8 and 9, the occupancy rate of low-angle grain boundaries was 3.7%, and the occupancy rate of non-low-angle grain boundaries was 96.3%. In the above examples, the occupancy rates of low-angle grain boundaries were all within the range of 3 to 4%.

[0024] In some embodiments, the misorientation angle distribution peak in the support substrate 11 is 30 to 60°. In more specific embodiments, the misorientation angle distribution peak is 40 to 50°. The misorientation angle distribution peak means that the number of misorientation angles at the distribution peak occupies the largest proportion of the total number of grain boundaries in the support substrate 11. For example, if the proportion of grain boundaries with a misorientation angle of 45° at the total number of grain boundaries in the support substrate 11 is the largest, the misorientation angle distribution peak is 35°. FIG. 4 is a diagram showing the distribution data of misorientation angles in the measurement regions shown in FIGS. 2 and 3, and FIG. 7 is a diagram showing the distribution data of misorientation angles in the measurement regions shown in FIGS. 5 and 6. FIG. 10 is a diagram showing the distribution data of misorientation angles in the measurement regions shown in FIGS. 8 and 9. In Figures 4, 7, and 10, the horizontal axis represents the misorientation angle value, and the vertical axis represents the relative frequency of the misorientation angle corresponding to the horizontal axis value. The relative frequency is the percentage of the grain boundary with that misorientation angle in the total number of grain boundaries. The higher the value on the vertical axis for a given coordinate point, the more grain boundaries there are with a misorientation angle corresponding to that horizontal axis value. In Figure 4, the misorientation angle value corresponding to the peak is approximately 46°, indicating that the most common grain boundaries have a misorientation angle of approximately 46° within the measurement region shown in Figures 2 and 3. In Figure 7, the misorientation angle value corresponding to the peak is approximately 45°, indicating that the most common grain boundaries have a misorientation angle of approximately 45° within the measurement region shown in Figures 2 and 3. In Figure 10, the misorientation angle value corresponding to the peak is approximately 45°, indicating that the most common grain boundaries have a misorientation angle of approximately 45° within the measurement region shown in Figures 2 and 3.

[0025] Hereinafter, a method for manufacturing the support substrate 11 provided in the embodiment of the present invention will be described using magnesium aluminum spinel as an example. In S1, a magnesium aluminum spinel powder is selected and subjected to particle size screening to select a powder having a target particle size; In S2, cold isostatic pressing (CIP) is further performed to press the powder into a semi-finished product. In S3, the magnesium aluminum spinel semi-finished product is subjected to HIP (hot isostatic pressing), and a magnesium aluminum spinel crystal ingot formed after HIP (at this time, the grain boundary ratio is already constant) is obtained. In S4, the magnesium aluminum spinel crystal ingot is subjected to multi-wire cutting to obtain a cut spinel substrate, and the substrate is subjected to a polishing treatment; In S5, the spinel polished substrate produced in S4 is polished to obtain a support substrate 11.

[0026] The target particle size in step S1 is, for example, 0.1 μm to 100 μm. In step S2, the CIP temperature is 1400 to 1500°C, and the pressing pressure is 10,000 to 100,000 Psi (pounds per square inch). In step S3, the HIP temperature is 1650 to 1850°C, and the environmental pressure is 150 to 250 MPa. In step S4, the thickness of the cut substrate is, for example, 250 to 350 μm, and it is polished with silicon carbide or boron carbide powder, preferably with a particle size of 1200 to 1500# (mesh). In step S5, the polished surface is the surface for bonding to the piezoelectric layer. The roughness of the support substrate surface (i.e., main support surface 111) obtained in step S5 is Sa≦0.6 nm, TTV≦2 μm, and the thickness of the final spinel substrate (i.e., support substrate 11) is 200 to 250 μm.

[0027] Referring to FIG. 12 , an embodiment of the present invention further provides a composite substrate 10, which includes a piezoelectric layer 12 and a support substrate 11 described in the previous embodiments, with the piezoelectric layer 12 disposed on the support substrate 11. In some embodiments, the piezoelectric layer 12 and the support substrate 11 are bonded to each other, specifically, the piezoelectric layer 12 is bonded to the major support surface 111 of the support substrate 11. The two may be directly bonded together by van der Waals forces. However, the piezoelectric layer 12 may be made of, for example, lithium tantalate or lithium niobate. The composite substrate 10 utilizes the support substrate 11 described above and has at least the same spurious suppression effect as the support substrate. Referring to FIG. 13 , an embodiment of the present invention further provides an electronic device 100 including the support substrate 11 described in the previous embodiments or the composite substrate 10 described in the previous embodiments. In the composite substrate 10, the piezoelectric layer 12 includes, for example, a main surface 121 facing the support substrate 11, and the electronic device 100 further includes, for example, an electrode 20 disposed on the main surface 121, the electrode 20 including, for example, an IDT electrode 21, where the IDT is an interdigital transducer, and the electronic device 100 is, for example, a SAW device. The electronic device 100 includes the support substrate 11 in the above-described embodiment and has the same spurious suppression effect as the support substrate 11.

[0028] 14, an electronic device 100 (composite substrate 10) in another embodiment of the present invention further includes an intermediate layer 13, which is located between the piezoelectric layer 12 and the support substrate 11. However, the acoustic velocity of the intermediate layer 13 is lower than that of the piezoelectric layer 12. That is, the acoustic velocity of the bulk wave in the intermediate layer 13 is lower than that of the bulk wave propagating through the piezoelectric layer 12. In this embodiment, by providing the intermediate layer 13 with a low acoustic velocity, the acoustic velocity of the elastic wave can be reduced and the energy of the elastic wave can be concentrated in the medium with a low acoustic velocity (i.e., the intermediate layer 13), thereby reducing loss and improving the Q value.

[0029] However, the material of the intermediate layer 13 is any one of silicon oxide, silicon oxynitride, tantalum oxide, or a material containing these materials as a main component. In some embodiments, the intermediate layer is made of silicon oxide, and the material of the piezoelectric layer 12 is lithium tantalate. The elastic constant of lithium tantalate has a negative temperature coefficient, while silicon dioxide has a positive temperature coefficient, thereby reducing the absolute value of the TCF (temperature coefficient) of the acoustic wave device. Furthermore, the specific acoustic impedance of silicon oxide is smaller than that of lithium tantalate, thereby increasing the electromechanical coupling coefficient of the electronic element.

[0030] In some embodiments, the thickness of the intermediate layer 13 is 0.5λ or more, where λ is the wavelength of the acoustic wave determined by the electrode period of the IDT electrode 21. Specifically, the thickness of the intermediate layer 13 can be 0.6 to 0.8λ. In some embodiments, the thickness of the piezoelectric layer 12 is 2λ or less. Specifically, the thickness of the piezoelectric layer 12 can be less than 1λ. In one specific embodiment, λ is 2.25 micrometers, the thickness of the piezoelectric layer 12 is 0.1λ to 1λ, and the thickness of the intermediate layer 13 is 0.6λ.

[0031] The electronic device 100 provided in this embodiment can use a CSP package (Chip Scale Package) or a WLP package (Wafer Level Package).

[0032] 15, which is a structural schematic diagram of an electronic device 100 using a CSP package. The electronic device 100 includes an element (including a composite substrate 10 and electrodes 20), a package substrate 30, a first sealing structure 41, and a first external terminal electrode 53. The package substrate 30 is disposed opposite the surface of the element on which the electrodes 20 are located (i.e., the main surface 121 of the piezoelectric layer 12), and a gap 60 is formed between the package substrate 30 and the main surface 121. The first sealing structure 41 is disposed on the side of the package substrate 30 facing the element, and covers the side surface of the element and the surface facing away from the package substrate 30, thereby sealing the gap 60 and encapsulating the element. The electrode 20 includes an electrode pad 22 electrically connected to the IDT electrode 21, and the electrode pad 22 is electrically connected to a first conductive portion 52 in the wiring pattern on the package substrate 30 via a bump 51. The first conductive portion 52 is electrically connected to a first external terminal electrode 53 on the side of the package substrate 30 facing away from the element, thereby enabling electrical connection between the electronic device 100 and an external device via the first external terminal electrode 53.

[0033] However, the materials of the package substrate 30 and the first sealing structure 41 can refer to the substrate materials and sealing materials commonly found in conventional CSP packages, and the electrode pads 22, bumps 51, first conductive parts 52 and first external terminal electrodes 53 are all made of materials with excellent conductivity, and this embodiment is not limited to the above examples.

[0034] FIG. 16 is a structural schematic diagram of an electronic device 100 using a CSP package. The electronic device 100 includes an element (including a composite substrate 10 and an electrode 20), a lid 70, a second sealing structure 42, and a second external terminal electrode. The lid 70 is disposed opposite the surface of the element on which the electrode 20 is disposed (i.e., the main surface 121 of the piezoelectric layer 12), and a gap 60 is formed between the lid 70 and the main surface 121. The electrode 20 includes an electrode pad 22 electrically connected to an IDT electrode 21. The area of ​​the main surface 121 where the IDT electrode 21 is disposed is called an active area. The second sealing structure 42 is disposed between the lid 70 and the element and surrounds the active area. The second sealing structure 42 surrounds the electrode pad 22 to seal the element. The second external terminal electrode 55, which is installed on the surface of the lid body 70 facing away from the element, is connected to the electrode pad 22 via the second conductive portion 54 that penetrates the lid body 70 and the second sealing structure 42, thereby allowing the electronic device 100 to be electrically connected to an external device via the second external terminal electrode 55.

[0035] However, the materials of the lid 70 and the second sealing structure 42 may refer to the lid material and sealing material used in conventional WLP packages, and the electrode pad 22, the second conductive portion 54, and the second external terminal electrode 55 are all made of materials with excellent conductivity, and are not limited to this embodiment. Referring to FIG. 17 , the present invention further provides a module 1000 including a wiring substrate 700, a plurality of external connection terminals 701, an integrated circuit member 600, an electronic device 100 (including a composite substrate 10), an inductor 400, and a sealing portion 500. The plurality of external connection terminals 701 are formed on one surface of the wiring substrate 700, and the plurality of external connection terminals 701 are attached to a motherboard of a predetermined mobile communication terminal. The integrated circuit member 600 (which may also be referred to as an IC) is attached inside the wiring substrate 700. The integrated circuit member 600 includes a switch circuit and a noise amplifier. The electronic device 100 is attached to the main surface of the wiring substrate 700. The inductor 400 is used for impedance matching, and is, for example, an integrated passive device (IPD). The sealing unit 500 is used to seal a plurality of electronic components including the electronic device 100 on the wiring substrate 700.

[0036] The module 1000 provided in this embodiment includes the electronic device 100, that is, the support substrate 11, and has the same spurious suppression effect as the support substrate 11, and the description thereof will be omitted here. [Explanation of symbols]

[0037] 10 composite substrate, 100 electronic devices, 11 Support substrate, 111 Main support surface, 112 Back side, 113 side, 12 piezoelectric layers, 121: the main surface of the piezoelectric layer 12; 13 middle class, 20 element electrodes, 21 IDT electrodes, 22 electrode pads, 30 package substrate, 400 inductor, 41 first sealing structure, 42 second sealing structure, 500 sealing part, 52 first conductive part, 53 first external terminal electrode, 54 second conductive part, 55 second external terminal electrode, 60 gap, 600 Integrated circuit components, 70 lid body, 700 wiring board, 701 external connection terminal, 1000 modules.

Claims

1. A support substrate, wherein the material of the support substrate is a polycrystalline material, and the number of small-angle grain boundaries in the support substrate, each having a misorientation angle of 2 to 15 degrees, accounts for 1 to 5% of the total number of grain boundaries.

2. The support substrate of claim 1, wherein the support substrate has a major support surface, the number of the small-angle grain boundaries in a lateral cross section or a lateral surface in the support substrate accounts for 1 to 5% of the total number of grain boundaries, the lateral surface is the major support surface or is parallel to the major support surface, and the lateral cross section is parallel to the major support surface.

3. The support substrate according to claim 1, characterized in that the number of small-angle grain boundaries is five or more within any one metric region on any one surface of the support substrate, and the metric region is an area having a length of 150 micrometers and a width of 150 micrometers.

4. The support substrate according to claim 3, characterized in that the grain size of the crystal grains in the support substrate is 5 to 60 micrometers, and the number of the small-angle grain boundaries in any one of the metric regions on any one surface of the support substrate is 25 or more.

5. The support substrate according to claim 3, characterized in that the grain size of the crystal grains in the support substrate is 1 to 5 micrometers, and the number of the small-angle grain boundaries in any one of the metric regions on any one surface of the support substrate is 40 or more.

6. 2. The support substrate according to claim 1, wherein the distribution peak of the misorientation angle in the support substrate is 30 to 60 degrees.

7. The support substrate according to any one of claims 1 to 6, characterized in that the polycrystalline material is one of polycrystalline magnesium aluminum spinel, polycrystalline sapphire, polycrystalline aluminum nitride, polycrystalline magnesium oxide, and polycrystalline quartz.

8. The support substrate according to any one of claims 1 to 6, further comprising: a piezoelectric layer disposed on the support substrate; an IDT electrode located on a main surface of the piezoelectric layer opposite the support substrate.

9. The electronic device according to claim 8 , further comprising an intermediate layer located between the piezoelectric layer and the support substrate, wherein the acoustic velocity of the intermediate layer is lower than the acoustic velocity of the piezoelectric layer.

10. 10. The electronic device according to claim 9, wherein the thickness of the intermediate layer is 0.5λ or more, where λ is the wavelength of an acoustic wave determined by the electrode period of the IDT electrode.

11. 9. The electronic device according to claim 8, wherein the thickness of the piezoelectric layer is 2λ or less, where λ is the wavelength of an acoustic wave determined by the electrode period of the IDT electrodes.

12. A module comprising a wiring substrate, a plurality of external connection terminals, an integrated circuit member, an inductor, a sealing portion, and the electronic device according to any one of claims 8 to 11.

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