Electronic device

Abstract

To provide an electronic device capable of suppressing deterioration of radiation noise.SOLUTION: The electronic device 100 includes a main board 20, a semiconductor package 30, a shield cover 60, and a ground conduction portion 70. A main ground pattern 27 is formed on the main substrate 20. The semiconductor package 30 is mounted on the main board 20, and includes a semiconductor chip 40, a package substrate 50 on which the semiconductor chip 40 is mounted, and a package ground pattern 57 formed around the semiconductor chip 40 on the package substrate 50. The shield cover 60 is used to dissipate heat from the semiconductor chip 40 and includes a shield portion 62. The shield portion 62 is formed of a conductive material and is disposed so as to cover the semiconductor chip 40. The ground conductive portion 70 electrically connects the shield portion 62 to the package ground pattern 57.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] TECHNICAL FIELD This disclosure relates to electronic devices. [Background technology]

[0002] Patent Document 1 discloses an electronic device including a printed circuit board on which circuit components are mounted and a shield cover electrically connected to a ground pattern formed on the printed circuit board. The shield cover has heat dissipation fins and is connected to the circuit components directly or via a heat conductor. The adoption of such a shield structure makes it possible to provide electromagnetic shielding while ensuring heat dissipation. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-314286 Summary of the Invention [Problem to be solved by the invention]

[0004] In recent years, electronic devices have increasingly adopted semiconductor packages that include a semiconductor chip and a package substrate on which the semiconductor chip is mounted. When the shielding structure disclosed in Patent Document 1 is adopted in such electronic devices in which a semiconductor package is mounted on a main substrate, the shield cover is connected to the ground pattern of the main substrate outside the package substrate, avoiding the package substrate. As a result, the path of noise current becomes longer, which can cause the shield cover, which has heat dissipation properties, to function as an antenna, particularly in high frequency bands, raising concerns about worsening radiated noise.

[0005] The present disclosure aims to provide an electronic device that can suppress the deterioration of radiation noise. [Means for solving the problem]

[0006] In order to achieve the above object, one disclosed embodiment is an electronic device comprising: a main substrate (20) on which a main ground pattern (27) is formed; a semiconductor package (30) having a semiconductor chip (40), a package substrate (50) on which the semiconductor chip is mounted, and a package ground pattern (57) formed around the semiconductor chip on the package substrate, and mounted on the main substrate; a heat dissipation member (60) having a shielding portion (62) formed of a conductive material and arranged to cover the semiconductor chip, and used to dissipate heat from the semiconductor chip; and a ground conductive portion (70) that electrically connects the shielding portion to the package ground pattern.

[0007] In this embodiment, the shield portion disposed to cover the semiconductor chip of the semiconductor package is electrically connected to a package ground pattern formed around the semiconductor chip on the package substrate by the ground conductive portion. This configuration can shorten the path of noise current, making it less likely that the heat dissipation component will function as an antenna. As a result, it is possible to suppress the deterioration of radiated noise.

[0008] It should be noted that the reference numbers in parentheses in the above and claims merely indicate an example of the correspondence with the specific configurations in the embodiments described below, and do not limit the technical scope in any way. Furthermore, claims not explicitly stated in the claims may be combined together if no particular problems arise in the combination. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view showing a configuration of an electronic device according to a first embodiment of the present disclosure. [Figure 2] FIG. 2 is a plan view showing the shape of a ground pattern of a package substrate. [Figure 3] FIG. 4 is an enlarged view for explaining details of the heat dissipation function and the noise suppression function. [Figure 4] FIG. 10 is a cross-sectional view showing the configuration of an electronic device according to a second embodiment. [Figure 5]FIG. 10 is a cross-sectional view showing the configuration of an electronic device according to a third embodiment. [Figure 6] 10A and 10B are plan views showing the shapes of a package ground pattern and a cylindrical filling wall. [Figure 7] FIG. 10 is a plan view showing the shape of a ground pattern of a package substrate according to Modification 1. [Figure 8] FIG. 10 is a plan view showing the shape of a ground pattern of a package substrate according to Modification 2. [Figure 9] FIG. 11 is a plan view showing the shape of a ground pattern of a package substrate according to Modification 3. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, several embodiments will be described with reference to the drawings. Note that corresponding components in each embodiment are given the same reference numerals, and redundant description may be omitted. When only a portion of the configuration is described in each embodiment, the configuration of another embodiment described previously can be applied to the remaining portion of the configuration. Furthermore, in addition to the combinations of configurations explicitly stated in the description of each embodiment, configurations of several embodiments can also be partially combined together even if not explicitly stated, as long as there is no particular problem with the combination.

[0011] (First embodiment) An electronic device 100 according to the first embodiment of the present disclosure shown in FIG. 1 is a vehicle ECU (Electronic Control Unit) used in a vehicle. As an example, the electronic device 100 is a meter device that provides the driver with vehicle information for understanding the vehicle's status, etc. The electronic device 100 may also be another display-related ECU, a communication-related ECU, a body-related ECU, or an engine control-related ECU. Furthermore, the electronic device 100 may be a zone ECU that integrally manages multiple functions of a specific zone in the vehicle.

[0012] The electronic device 100 is composed of a main substrate 20, a semiconductor package 30, a shield cover 60, a thermal conductor 80, and the like. Here, the up-down direction, width direction Hb, and depth direction Ok in the present disclosure are defined with respect to the main substrate 20. Specifically, the up-down direction (upper Ue and lower Si) is defined along the thickness direction of the main substrate 20 and is a direction perpendicular to the main substrate 20. The width direction Hb and depth direction Ok are defined along the surface direction of the main substrate 20. As an example, the width direction Hb is defined along the longitudinal direction of the main substrate 20, and the depth direction Ok is defined along the lateral direction of the main substrate 20. Note that for simplicity of description, the symbols indicating the respective directions may be omitted in the following description.

[0013] The main substrate 20 is a multilayer printed wiring board formed by laminating a composite insulating material that combines glass fiber and epoxy resin. The main substrate 20 is formed in a rectangular plate shape. Of the two surfaces of the main substrate 20, one facing upward Ue is a main mounting surface 21, and the other facing downward Si is a back surface 22. A large number of electronic components, including at least one semiconductor package 30, are mounted on the main mounting surface 21. The electronic components include a microcontroller, a power supply IC (Integrated Circuit), a memory element, a connector, and the like. Some of the electronic components may be mounted on the back surface 22.

[0014] Conductive patterns are formed on the main mounting surface 21, the back surface 22, and between each layer of the main board 20. The conductive patterns are formed of copper foil or the like. The conductive patterns include a circuit pattern 26 and a ground pattern (hereinafter referred to as the main ground pattern 27). The circuit pattern 26 is a conductive pattern for electrically connecting a large number of electronic components to each other to form an electronic circuit on the main board 20. A portion of the circuit pattern 26 forms a conductive land on the main mounting surface 21 for connection with each electronic component. The main ground pattern 27 is a conductive pattern for supplying a reference potential (ground potential) of the electronic circuit to the electronic components, etc. A portion of the main ground pattern 27 forms a ground land on the main mounting surface 21 for connection with each electronic component and the shield cover 60. A green mask layer (solder resist layer) is provided on the main mounting surface 21 and the back surface 22 so as to cover the areas other than the conductive lands and ground lands.

[0015] 1 and 2 is mounted in the center of the main mounting surface 21 of the main substrate 20. The semiconductor package 30 is, for example, an FC-BGA (Flip-Chip Ball Grid Array). The semiconductor package 30 is composed of a semiconductor chip 40, a package substrate 50, etc.

[0016] The semiconductor chip 40 is formed in a flat rectangular parallelepiped shape. The semiconductor chip 40 is, for example, an MPU (Micro Processor Unit). The MPU has a calculation function for processing digital data and executes instructions based on a program. The semiconductor chip 40 is mounted on a package substrate 50. The semiconductor chip 40 is flipped upside down using flip-chip technology and is arranged so that the connection terminals are in direct contact with the package substrate. The connection terminals of the semiconductor chip 40 are joined to the conductor pattern of the package substrate 50 by fine solder bumps, beads, or the like.

[0017] Here, the semiconductor chip 40 may be a semiconductor element different from an MPU. For example, a GPU, an FPGA, an ASIC, an SoC, a chiplet assembly, a DRAM, a flash memory, a communication IC, a power supply IC, or the like may be mounted on the package substrate 50 as the semiconductor chip 40. Furthermore, multiple semiconductor chips 40 may be mounted on the package substrate 50.

[0018] The package substrate 50 is a glass epoxy substrate made of a composite insulating material that combines glass fiber and epoxy resin. The package substrate 50 is formed in the shape of a rectangular plate. The area of ​​the package substrate 50 is larger than that of the semiconductor chip 40 but smaller than that of the main substrate 20. Of the two surfaces of the package substrate 50, one facing upward Ue is a chip mounting surface 51, and the other facing downward Si is a bottom surface 52.

[0019] At least one semiconductor chip 40 is mounted in the center of the chip mounting surface 51. The semiconductor chip 40 is attached to the chip mounting surface 51 with its longitudinal direction aligned with the longitudinal direction of the package substrate 50 and the width direction Hb of the electronic device 100. The bottom surface 52 faces the main mounting surface 21 in the vertical direction. A large number of solder connection portions 53 arranged in an array are provided on the bottom surface 52. The solder connection portions 53 are electrically connected by solder bonding to the circuit pattern 26 or the main ground pattern 27 exposed on the main mounting surface 21, in other words, to the conductive lands or ground lands.

[0020] The conductor patterns formed on the package substrate 50 include a circuit pattern (hereinafter referred to as package circuit pattern) and a ground pattern (hereinafter referred to as package ground pattern 57). The package circuit pattern is a conductor pattern for electrically connecting the semiconductor chip 40 to the circuit pattern 26 of the main substrate 20 via the solder connection parts 53. The package ground pattern 57 is a conductor pattern for supplying a reference potential of the electronic circuit to the semiconductor chip 40. The package ground pattern 57 is electrically connected to the main ground pattern 27 via the solder connection parts 53.

[0021] The package substrate 50 is provided with a package ground pattern 57 that is formed around the semiconductor chip 40 and exposed on the chip mounting surface 51. The package ground pattern 57 is formed in a rectangular ring shape that continuously surrounds the entire periphery of the semiconductor chip 40. A green mask layer that protects the chip mounting surface 51 is provided so as to cover the entire surface except for the annular exposed package ground pattern 57. The longitudinal direction of the package ground pattern 57 is the longitudinal direction of the semiconductor chip 40 and the package substrate 50, and is aligned with the width direction Hb of the electronic device 100. The lateral direction of the package ground pattern 57 is aligned with the depth direction Ok of the electronic device 100. The semiconductor chip 40 is located in the center of the area surrounded by the package ground pattern 57.

[0022] The shield cover 60 is formed in the shape of a flat container with a bottom, from a metal material (such as aluminum or copper) that has high conductivity and magnetism. The shield cover 60 is attached to the main board 20 with the opening facing downward Si so as to cover the main mounting surface 21. The shield cover 60 performs both a noise suppression function that blocks electromagnetic noise generated by semiconductor elements including the semiconductor chip 40, conductor patterns, etc., and a heat dissipation function that dissipates heat generated from the semiconductor elements, conductor patterns, etc.

[0023] The shield cover 60 is formed with a main body bottom wall 61, four side walls 66, and a flange portion 67. The main body bottom wall 61 is the bottom portion of the container-shaped shield cover 60. The main body bottom wall 61 is formed in the shape of a rectangular plate overall. The main body bottom wall 61 is positioned along the main board 20 and is located above Ue the main mounting surface 21. The side walls 66 are arranged so as to surround the main mounting surface 21 on all four sides. Each side wall 66 extends downward Si from the outer edge of the main body bottom wall 61 toward the main board 20.

[0024] The flange portion 67 is a brim-shaped portion that protrudes from the end of each side wall 66 toward the outer periphery. Mounting holes 68 are formed in the flange portion 67. The flange portion 67 is held to the main board 20 by fastening screws 69 that are inserted through the mounting holes 68. The end face of the flange portion 67 facing downward Si (hereinafter referred to as the flange end face 67a) is pressed against the main ground pattern 27 (grounding land) provided on the outer edge portion of the main mounting surface 21 by the axial force of the screws 69 that fasten the main board 20. The flange portion 67 electrically connects the shield cover 60 to the flange portion 67.

[0025] The shield cover 60 includes a shield portion 62 and a ground conductive portion 70. The shield portion 62 and the ground conductive portion 70 are formed in the center portion of the main body bottom wall 61 that faces the semiconductor package 30 in the vertical direction.

[0026] The shield portion 62 is formed by recessing the central portion of the bottom wall 61 of the main body downward. The shield portion 62 is made of the above-mentioned conductive material and is arranged to cover the semiconductor chip 40. A heat sink portion 63 is provided on the outer surface of the shield portion 62. The heat sink portion 63 is formed integrally with the shield portion 62. The heat sink portion 63 has a large number of heat dissipation fins 64. Each heat dissipation fin 64 is formed in a thin plate shape, increasing the contact area between the shield portion 62 and the air. The heat dissipation fins 64 efficiently dissipate heat from the shield portion 62 into the air.

[0027] The ground conductive section 70 is provided between the shield section 62 and the semiconductor package 30 in the vertical direction. The ground conductive section 70 has four vertical partition walls arranged to surround the semiconductor package 30 on all four sides. Each vertical partition wall is formed integrally with the shield section 62 (shield cover 60). Each vertical partition wall extends downward Si from the shield section 62 toward the chip mounting surface 51. A tip surface 71 of each vertical partition wall is pressed against the package ground pattern 57. The tip surface 71 and the package ground pattern 57 are in surface contact with each other over the entire periphery surrounding the semiconductor chip 40.

[0028] The ground conductive portion 70 electrically connects the shield portion 62 to the package ground pattern 57. When the shield cover 60 is attached to the main board 20, it biases the ground conductive portion 70 toward the package ground pattern 57. The ground conductive portion 70 has high rigidity due to a configuration in which four vertical partition walls are connected, and supports the shield portion 62 relative to the package substrate 50. The ground conductive portion 70, together with the package substrate 50 and the shield portion 62, defines a filled space 72.

[0029] The thermal conductor 80 is formed of a material with high thermal conductivity, flexibility, and electrical insulation. The thermal conductor 80 is located between the semiconductor chip 40 and the shield portion 62 and is in contact with both the semiconductor chip 40 and the shield portion 62 over a wide area. The thermal conductor 80 conducts heat from the semiconductor chip 40 to the shield portion 62. As an example, a heat dissipation gel 81 made of silicone gel or the like is used as the thermal conductor 80. The silicone gel may contain a filler (thermally conductive filler) that enhances thermal conductivity. The heat dissipation gel 81 fills the filling space 72 (see the dotted area in Figure 1). The heat dissipation gel 81 is filled into this filling space 72 so as to reach every corner of the filling space 72. The heat dissipation gel 81 is a fluid gel and is in close contact with the chip mounting surface 51 and the outer surface of the semiconductor chip 40.

[0030] <Explanation of heat dissipation and noise shielding functions> Next, the heat dissipation function and noise suppression function of the electronic device 100 will be further described in detail with reference to FIG.

[0031] The amount of heat generated by the semiconductor chip 40 increases with the increasing speed, functionality, and integration of MPUs. Therefore, a heat dissipation structure for cooling the semiconductor chip 40 is essential. In the electronic device 100, a heat dissipation gel 81, which acts as an easily deformable insulator, is sandwiched between the semiconductor chip 40 and the shield 62, which has heat dissipation fins 64. If a heat dissipation structure were to be directly contacted with the semiconductor chip 40, stress would be easily applied to the solder joints 53, raising concerns about cracking and breakage of the solder joints 53. On the other hand, if the heat dissipation gel 81 is sandwiched between the shield 62 and the semiconductor chip 40, stress applied to the solder joints 53 is alleviated, making damage to the solder joints 53 less likely. Heat generated by the semiconductor chip 40 is conducted to the shield 62 via the heat dissipation gel 81 and then released into the atmosphere from the heat dissipation fins 64.

[0032] In addition, as MPU speeds increase, the frequency of noise generated by the semiconductor chip 40 increases. In particular, when the noise frequency is in the GHz range, the shield cover 60 is more likely to function as an antenna. More specifically, if the wavelength of the noise is λ, the shield cover 60 must be grounded at a distance sufficiently smaller than λ / 4. If the speed of light is c (3×10^8 m / s), the dielectric constant of the substrate is ε, and the noise frequency is f (Hz), the noise wavelength λ (m) is defined as in the following equation (1): λ=c / (√ε×f) Formula (1)

[0033] As an example, if the noise frequency f is 3 GHz, the wavelength λ is 5 cm, and λ / 4 is 1.25 cm. If the ground conduction part 70 and the package ground pattern 57 were not provided, the noise current NC caused by noise propagating from the noise generation source 40a of the semiconductor chip 40 would flow to the main ground pattern 27 via the body bottom wall 61 and side wall 66. In this configuration, it would be difficult to shorten the path length of the noise current NC to less than λ / 4. As a result, the shield cover 60 would act as an antenna, which could worsen the radiated noise.

[0034] In order to shorten the path length of the noise current NC, it is also possible to consider a configuration in which an on-board connector that connects the main body bottom wall 61 to the main ground pattern 27 is provided on the main mounting surface 21, and a configuration in which a separate outer case is further provided to cover the shield cover 60. However, these configurations may result in increased costs and weight.

[0035] In contrast, in a configuration in which the ground conductive portion 70 formed integrally with the shield portion 62 is in contact with the package ground pattern 57, it is possible to shorten the path of the noise current NC caused by the noise source 40a (see the dashed arrow in FIG. 3). Specifically, the path of the noise current NC from the semiconductor chip 40 through the shield portion 62, the ground conductive portion 70, and the package ground pattern 57 is made shorter than λ / 4, which is based on the noise frequency f. As a result, the shield cover 60 can be prevented from acting as an antenna.

[0036] Furthermore, a parasitic capacitance SC occurs in the heat dissipation gel 81 disposed between the shield part 62 and the semiconductor chip 40. The parasitic capacitance SC occurring in the heat dissipation gel 81 varies depending on the distance between the shield part 62 and the semiconductor chip 40, and on slight misalignment of the heat dissipation gel 81 with respect to the semiconductor chip 40. As a result, variations in EMC performance occur.

[0037] Therefore, in the electronic device 100, the ground conduction portion 70 supports the shield portion 62 relative to the package substrate 50. Therefore, by appropriately managing the dimensions of each portion of the shield cover 60, it is possible to maintain a constant distance between the shield portion 62 and the semiconductor chip 40. In addition, if the ground conduction portion 70 defines a filling space 72 and the filling space 72 is filled with a heat dissipation gel 81, it is possible to prevent the heat dissipation gel 81 from shifting in position relative to the semiconductor chip 40. As a result, variation in the parasitic capacitance SC, and therefore variation in EMC performance, is reduced.

[0038] (Summary of the first embodiment) In the first embodiment described so far, the shield part 62 arranged to cover the semiconductor chip 40 is electrically connected by the ground conductive part 70 to the package ground pattern 57 formed around the semiconductor chip 40 on the package substrate 50. With this configuration, the noise current NC flows only through the shield part 62 located directly above the semiconductor chip 40 in the body bottom wall 61. As a result, the path of the noise current NC can be shortened, making it less likely that the shield cover 60 will function as an antenna. As a result, it is possible to suppress deterioration of radiated noise.

[0039] Additionally, in the first embodiment, the thermal conductor 80 is positioned between the semiconductor chip 40 and the shield portion 62 and conducts heat from the semiconductor chip 40 to the shield portion 62. Furthermore, the ground conduction portion 70 supports the shield portion 62 relative to the package substrate 50. This configuration enables highly accurate control of the distance from the semiconductor chip 40 to the shield portion 62. For example, the distance from the semiconductor chip 40 to the shield portion 62 can be controlled to an accuracy of approximately 0.1 mm. As a result, variation in the parasitic capacitance SC occurring in the thermal conductor 80 disposed between the semiconductor chip 40 and the shield portion 62 is suppressed. As a result, deterioration of EMC performance due to the bottom wall 61 of the main body acting as an antenna is suppressed, and a heat dissipation structure capable of stabilizing EMC performance can also be realized.

[0040] Furthermore, in the first embodiment, a filled space 72 is defined by the ground conductive portion 70, the shield portion 62, and the package substrate 50. This filled space 72 is filled with a heat dissipating gel 81 as a thermal conductor 80. With this configuration, even if the heat dissipating gel 81 has the property of being easily deformed, the position of the heat dissipating gel 81 relative to the semiconductor chip 40 can be fixed. By suppressing misalignment of the heat dissipating gel 81 in this way, it is possible to achieve both high levels of heat dissipation performance and EMC performance.

[0041] Furthermore, in the first embodiment, the package ground pattern 57 is formed in a shape that surrounds the entire periphery of the semiconductor chip 40. With this configuration, a sufficiently wide path width of the noise current NC from the shield part 62 to the package ground pattern 57 via the ground conductive part 70 is ensured. As a result, the impedance of the noise current NC can be reduced, and the EMC performance of the electronic device 100 can be further improved.

[0042] Additionally, in the first embodiment, the shield cover 60 biases the ground conductive portion 70 toward the package ground pattern 57. Therefore, the tip surface 71 of the ground conductive portion 70 can be reliably brought into contact with the package ground pattern 57, which makes it possible to more reliably form a short path for the noise current NC to flow.

[0043] Furthermore, in the first embodiment, the ground conductive portion 70 is formed integrally with the shield cover 60. With this configuration, the shield portion 62 and the ground conductive portion 70 are reliably electrically connected, which more reliably shortens the path of the noise current NC. In addition, the dimension from the shield portion 62 to the tip surface 71 of the ground conductive portion 70, and therefore the distance from the shield portion 62 to the semiconductor chip 40, can be controlled with high precision. As a result, variations in EMC performance can be suppressed.

[0044] Furthermore, the semiconductor package 30 of the first embodiment further has a large number of solder connections 53 electrically connected to the circuit pattern 26 of the main substrate 20. The solder connections 53 are formed in a ball shape and arranged in an array on the bottom surface 52 of the package substrate 50. As described above, by employing a BGA structure for the package substrate 50, it is possible to reduce the package dimensions of the semiconductor package 30 even when the package substrate 50 includes a high-performance semiconductor chip 40. As a result, it is also possible to shorten the path of the noise current NC, which can improve EMC performance.

[0045] In the first embodiment, the shield cover 60 corresponds to the “heat dissipation member.” In the present disclosure, the expression “connected” may mean being directly connected to another element, or being indirectly connected via an intervening element.

[0046] Second Embodiment An electronic device 200 according to a second embodiment of the present disclosure shown in FIG. 4 is a modified example of the first embodiment. The electronic device 200 of the second embodiment further includes a plurality of conductive buffer sections 90. The conductive buffer sections 90 are flexible and made of a conductive material. The conductive buffer sections 90 are disposed on a package ground pattern 57 formed in an annular shape on the chip mounting surface 51. The conductive buffer sections 90 are electrically connected to the package ground pattern 57. The plurality of conductive buffer sections 90 are arranged at intervals from one another along the package ground pattern 57.

[0047] As an example, a gasket 91 is used for the conductive buffer section 90. The gasket 91 is formed of a polyurethane sponge core material and a metal-plated polyimide film or the like. The gasket 91 has a sponge core material covered with a film, and as such has high flexibility and excellent electrical properties.

[0048] The conductive buffer portion 90 is located between the ground conductive portion 70 and the package substrate 50. When the shield cover 60 is attached to the main substrate 20, the ground conductive portion 70 is biased toward the conductive buffer portion 90. The conductive buffer portion 90 is pressed downward Si by the ground conductive portion 70. As a result, the tip surface 71 of the ground conductive portion 70 is in surface contact with each of the upper end surfaces 90a of the multiple conductive buffer portions 90.

[0049] Here, an on-board clip or an on-board contact may be used as the conductive buffer portion 90 instead of the gasket 91. The on-board clip or the on-board contact is formed of a thin plate-like material with high conductivity that is copper-plated or the like. Like the gasket 91, a plurality of on-board clips or on-board contacts are provided on the chip mounting surface 51, arranged along the package ground pattern 57. The on-board clip physically sandwiches the vertical bulkhead of the ground conductive portion 70, thereby forming an electrical connection between the ground conductive portion 70 and the package ground pattern 57. The on-board contact is pressed downward into the Si by the tip surface 71 of the ground conductive portion 70, thereby forming an electrical connection between the ground conductive portion 70 and the package ground pattern 57.

[0050] The second embodiment described so far also has the same effects as the first embodiment, and the configuration in which the ground conductive portion 70 is electrically connected to the package ground pattern 57 makes it difficult for the shield cover 60 to function as an antenna, thereby making it possible to suppress deterioration of radiation noise.

[0051] Additionally, the second embodiment is provided with a flexible conductive buffer portion 90. The conductive buffer portion 90 is electrically connected to the package ground pattern 57 and is located between the ground conductive portion 70 and the package substrate 50. In this manner, the ground conductive portion 70 and the package substrate 50 are not in direct contact with each other, and the structure in which the conductive buffer portion 90 is sandwiched between them can reduce stress acting on the solder connection portion 53.

[0052] (Third embodiment) An electronic device 300 according to a third embodiment of the present disclosure, shown in FIGS. 5 and 6 , is another modified example of the first embodiment. The electronic device 300 of the third embodiment further includes a cylindrical filling wall 370. The cylindrical filling wall 370 is formed in the shield cover 60 together with the ground conductive portion 70. The cylindrical filling wall 370 is provided between the shield portion 62 and the semiconductor package 30, on the inner circumferential side of the ground conductive portion 70. The cylindrical filling wall 370 is formed integrally with the shield portion 62 and extends downward from the shield portion 62 toward the chip mounting surface 51. The semiconductor chip 40 is formed with a first region 41 including the noise generation source 40a and a second region 42 excluding the first region 41. The cylindrical filling wall 370 is formed in a cylindrical shape surrounding the second region 42 while avoiding the first region 41. The cylindrical filling wall 370, together with the shield portion 62 and the second region 42, defines a filling space 372. The filled space 372 is filled with the heat dissipation gel 81 (see the dotted area in FIG. 5). On the other hand, the space defined between the cylindrical filling wall 370 and the ground conductive portion 70 is an unfilled space that is not filled with the heat dissipation gel 81.

[0053] In the electronic device 300 described above, heat generated in the semiconductor chip 40 is conducted from the second region 42 to the shield portion 62 via the heat dissipation gel 81. The heat conducted to the shield portion 62 is then released into the atmosphere from the heat dissipation fins 64 of the heat sink portion 63. Meanwhile, the first region 41 including the noise generation source 40a does not include the heat dissipation gel 81, and therefore no parasitic capacitance SC (see FIG. 3) is generated. Therefore, a noise current NC1 (see the thin dashed arrow in FIG. 5) associated with the first region 41 is not formed. As a result, the noise radiated from the heat dissipation fins 64 can be further reduced while still ensuring heat dissipation.

[0054] The third embodiment described so far also has the same effects as the first embodiment, and the configuration in which the ground conductive portion 70 is electrically connected to the package ground pattern 57 can shorten the path of the noise current NC2 (see the thick dashed arrow in FIG. 5) associated with the second region 42. As a result, the shield cover 60 is less likely to function as an antenna, making it possible to suppress deterioration of radiated noise.

[0055] Additionally, the semiconductor chip 40 of the third embodiment is formed with a first region 41 including the noise generating source 40a and a second region 42 excluding the first region 41. A cylindrical filling wall 370 is formed in a cylindrical shape surrounding the second region 42 while avoiding the first region 41. The cylindrical filling wall 370 defines a filling space 372 filled with a heat dissipation gel 81 together with the shielding portion 62 and the second region 42. With this configuration, it is possible to achieve both high levels of heat dissipation performance and EMC performance.

[0056] (Other embodiments) Although multiple embodiments of the present disclosure have been described above, the present disclosure should not be construed as being limited to the above-described embodiments, and can be applied to various embodiments and combinations within the scope that does not deviate from the gist of the present disclosure.

[0057] In the first to third modifications of the above embodiment, the package ground pattern 57 includes a plurality of divided pattern portions 58 extending to surround the periphery of the semiconductor chip 40 .

[0058] 7 includes two divided pattern portions 58a extending along the width direction Hb and two divided pattern portions 58b extending along the depth direction Ok. The four divided pattern portions 58a, 58b form the rectangular package ground pattern 57. Ground slits 59, which form gaps in the package ground pattern 57, are formed between each divided pattern portion 58a and each divided pattern portion 58b.

[0059] 8 includes four L-shaped divided pattern portions 58. The four divided pattern portions 58 form a rectangular package ground pattern 57 as a whole. Ground slits 59 are formed between the divided pattern portions 58.

[0060] 9 includes four divided pattern portions 58 extending in a strip shape. The two divided pattern portions 58a are located on either side of the semiconductor chip 40 in the depth direction Ok and extend along the width direction Hb. The two divided pattern portions 58b are located on either side of the semiconductor chip 40 in the width direction Hb and extend along the depth direction Ok. A ground slit 59 is formed between the divided pattern portions 58a and 58b.

[0061] As in the above-described first to third modifications, if the package ground pattern 57 is configured to be divided into a plurality of divided pattern portions 58, it becomes possible to form a package circuit pattern in the area that becomes the ground slit 59 on the chip mounting surface 51. As a result, it is possible to avoid a situation in which the addition of the package ground pattern 57 makes it difficult to form the package circuit pattern.

[0062] In the fourth modification of the above embodiment, the shield cover 60 and the ground conductive portion 70 are formed as separate bodies. The ground conductive portion 70 is formed in a rectangular tubular shape from a conductive material. The ground conductive portion 70 is disposed between the shield portion 62 and the chip mounting surface 51 with its axial direction aligned in the up-down direction. Of both end faces of the ground conductive portion 70, one facing upward Ue is in contact with the shield portion 62, and the other facing downward Si is in contact with the package ground pattern 57. The ground conductive portion 70 electrically connects the shield portion 62 to the package ground pattern 57.

[0063] The semiconductor package 30 of the above embodiment is a BGA package in which the package substrate 50 is electrically connected to the main substrate 20 by two-dimensionally arranged ball-shaped solder connection portions 53. In contrast, the semiconductor package 30 of Modification 5 of the above embodiment is a PGA (Pin Grid Array) package in which the package substrate 50 is electrically connected to the main substrate 20 by two-dimensionally arranged pin-shaped solder connection portions. Furthermore, the semiconductor package 30 of Modification 6 of the above embodiment is an LGA (Land Grid Array) package in which the package substrate 50 is electrically connected to the main substrate 20 by land-shaped solder connection portions arranged in a grid pattern. As in Modifications 5 and 6 above, the form of the semiconductor package 30 may be modified as appropriate.

[0064] In the seventh modification of the above embodiment, a heat dissipation sheet is used as the thermal conductor 80 that conducts heat from the semiconductor package 30 to the shield portion 62, instead of the heat dissipation gel 81. The heat dissipation sheet is formed into a thin plate shape using silicone or the like. The heat dissipation sheet is disposed between the semiconductor chip 40 and the shield portion 62 in a slightly crushed state.

[0065] In an eighth modification of the above embodiment, the four vertical partition walls constituting the ground conduction portion 70 are discontinuously formed. Moreover, in a ninth modification of the above embodiment, instead of the four vertical partition walls, one or more pillar portions are provided on the main body bottom wall 61 as the ground conduction portion 70. As in the eighth and ninth modifications, the form of the ground conduction portion 70 may be modified as appropriate.

[0066] In a tenth modification of the above embodiment, a heat pipe, a cooling fan, a liquid cooling system, and the like are attached to the shield part 62 instead of or together with the heat sink part 63. As in the tenth modification, the heat dissipation structure provided in the shield cover 60 may be changed as appropriate.

[0067] In an eleventh modification of the above embodiment, a plurality of semiconductor chips 40 are mounted on the chip mounting surface 51 of the package substrate 50. In this eleventh modification, a package ground pattern 57 and a ground conductive portion 70 are formed so as to surround the plurality of semiconductor chips 40. In addition, a thermal conductor 80 is disposed so as to be in contact with all of the semiconductor chips 40, and can dissipate heat from each semiconductor chip 40 to the shield portion 62.

[0068] Vehicles equipped with an electronic device according to the present disclosure are not limited to POVs (Personally Owned Vehicles) that are generally owned by individuals. The electronic device may be installed in rental cars, manned taxis, ride-sharing vehicles, freight vehicles, buses, and the like. Furthermore, the electronic device may be installed in unmanned vehicles used for mobility services, construction machinery, agricultural machinery, railroad cars, trams, DMVs (Dual Mode Vehicles), and the like. Furthermore, the electronic device may be installed as a mobility control device in ships and electric aircraft such as drones and eVTOLs. [Explanation of symbols]

[0069] 20 main board, 26 circuit pattern, 27 main ground pattern, 30 semiconductor package, 40 semiconductor chip, 40a noise source, 41 first area, 42 second area, 50 package substrate, 52 bottom surface, 53 solder connection portion, 57 package ground pattern, 58, 58a, 58b divided pattern portion, 60 shield cover (heat dissipation member), 62 shield portion, 70 ground conduction portion, 370 cylindrical filling wall, 72, 372 filling space, 80 heat conductor, 81 heat dissipation gel, 90 conductive buffer portion, 100, 200, 300 electronic device

Claims

1. a main substrate (20) on which a main ground pattern (27) is formed; a semiconductor package (30) that is mounted on the main substrate and that has a semiconductor chip (40), a package substrate (50) on which the semiconductor chip is mounted, and a package ground pattern (57) that is formed around the semiconductor chip on the package substrate; a heat dissipation member (60) that has a shield portion (62) formed of a conductive material and arranged to cover the semiconductor chip, and is used to dissipate heat from the semiconductor chip; and a ground conductor (70) that electrically connects the shielding portion to the package ground pattern.

2. a thermal conductor (80) positioned between the semiconductor chip and the shielding portion and conducting heat from the semiconductor chip to the shielding portion, The electronic device according to claim 1 , wherein the ground conduction portion supports the shield portion relative to the package substrate.

3. The electronic device according to claim 2 , wherein the ground conductive portion, together with the shield portion and the package substrate, defines a filling space (72) filled with a heat dissipation gel (81) serving as the thermal conductor.

4. The semiconductor chip is formed with a first region (41) including a noise generating source (40a) and a second region (42) excluding the first region, The electronic device of claim 2, further comprising a cylindrical filling wall (370) that is formed in a cylindrical shape surrounding the second region while avoiding the first region, and that defines a filling space (372) filled with a heat dissipation gel as the thermal conductor together with the shield portion and the second region.

5. 5. The electronic device according to claim 1, wherein the package ground pattern is formed in a shape that surrounds the entire periphery of the semiconductor chip.

6. 5. The electronic device according to claim 1, wherein the package ground pattern includes a plurality of divided pattern portions (58) extending so as to surround the periphery of the semiconductor chip.

7. 5. The electronic device according to claim 1, wherein the heat dissipation member biases the ground conduction portion toward the package ground pattern.

8. The electronic device according to any one of claims 1 to 4, further comprising a conductive buffer portion (90) that is flexible, electrically connected to the package ground pattern, and positioned between the ground conduction portion and the package substrate.

9. 5. The electronic device according to claim 1, wherein the ground conductive portion is integrally formed with the heat dissipation member.

10. A circuit pattern (26) is further formed on the main substrate, The electronic device according to any one of claims 1 to 4, wherein the semiconductor package is formed in a ball shape and further comprises a number of solder connection portions (53) arranged in an array on a bottom surface (52) of the package substrate that faces the main substrate and is electrically connected to the circuit pattern.

Images